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/llvm-project/llvm/test/ObjectYAML/MachO/
H A Dlazy_bind_opcode.yaml65 - Opcode: BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB
69 - Opcode: BIND_OPCODE_SET_DYLIB_ORDINAL_IMM
71 - Opcode: BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM
74 - Opcode: BIND_OPCODE_DO_BIND
76 - Opcode: BIND_OPCODE_DONE
78 - Opcode: BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB
82 - Opcode: BIND_OPCODE_SET_DYLIB_ORDINAL_IMM
84 - Opcode: BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM
87 - Opcode: BIND_OPCODE_DO_BIND
89 - Opcode: BIND_OPCODE_DONE
[all …]
H A Dbind_opcode.yaml65 - Opcode: BIND_OPCODE_SET_DYLIB_ORDINAL_IMM
67 - Opcode: BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM
70 - Opcode: BIND_OPCODE_SET_TYPE_IMM
72 - Opcode: BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB
76 - Opcode: BIND_OPCODE_DO_BIND
78 - Opcode: BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM
81 - Opcode: BIND_OPCODE_DO_BIND
83 - Opcode: BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM
86 - Opcode: BIND_OPCODE_DO_BIND
88 - Opcode: BIND_OPCODE_SET_DYLIB_ORDINAL_IMM
[all …]
H A Dweak_bind_opcode.yaml65 - Opcode: BIND_OPCODE_SET_DYLIB_ORDINAL_IMM
67 - Opcode: BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM
70 - Opcode: BIND_OPCODE_SET_TYPE_IMM
72 - Opcode: BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB
76 - Opcode: BIND_OPCODE_DO_BIND
78 - Opcode: BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM
81 - Opcode: BIND_OPCODE_DO_BIND
83 - Opcode: BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM
86 - Opcode: BIND_OPCODE_DO_BIND
88 - Opcode: BIND_OPCODE_SET_DYLIB_ORDINAL_IMM
[all …]
H A Dout_of_order_linkedit.yaml143 - Opcode: REBASE_OPCODE_SET_TYPE_IMM
145 - Opcode: REBASE_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB
149 - Opcode: REBASE_OPCODE_DO_REBASE_ULEB_TIMES
153 - Opcode: REBASE_OPCODE_DONE
156 - Opcode: BIND_OPCODE_SET_DYLIB_ORDINAL_IMM
159 - Opcode: BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM
162 - Opcode: BIND_OPCODE_SET_TYPE_IMM
165 - Opcode: BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB
170 - Opcode: BIND_OPCODE_DO_BIND
173 - Opcode: BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM
[all …]
/llvm-project/clang/test/InstallAPI/Inputs/Simple/
H A DSimple.yaml328 - Opcode: REBASE_OPCODE_SET_TYPE_IMM
330 - Opcode: REBASE_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB
333 - Opcode: REBASE_OPCODE_DO_REBASE_ULEB_TIMES_SKIPPING_ULEB
336 - Opcode: REBASE_OPCODE_DO_REBASE_ADD_ADDR_ULEB
339 - Opcode: REBASE_OPCODE_DO_REBASE_IMM_TIMES
341 - Opcode: REBASE_OPCODE_ADD_ADDR_IMM_SCALED
343 - Opcode: REBASE_OPCODE_DO_REBASE_ADD_ADDR_ULEB
346 - Opcode: REBASE_OPCODE_DO_REBASE_ADD_ADDR_ULEB
349 - Opcode: REBASE_OPCODE_DO_REBASE_IMM_TIMES
351 - Opcode: REBASE_OPCODE_ADD_ADDR_IMM_SCALED
[all …]
/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.h128 bool SetInstruction(const Opcode &insn_opcode, const Address &inst_addr,
145 bool ConditionPassed(const uint32_t opcode);
147 uint32_t CurrentCond(const uint32_t opcode);
301 const uint32_t opcode,
310 static ARMOpcode *GetARMOpcodeForInstruction(const uint32_t opcode,
313 static ARMOpcode *GetThumbOpcodeForInstruction(const uint32_t opcode,
317 bool EmulatePUSH(const uint32_t opcode, const ARMEncoding encoding);
320 bool EmulatePOP(const uint32_t opcode, const ARMEncoding encoding);
323 bool EmulateADDRdSPImm(const uint32_t opcode, const ARMEncoding encoding);
326 bool EmulateMOVRdSP(const uint32_t opcode, const ARMEncoding encoding);
[all …]
H A DEmulateInstructionARM.cpp891 bool EmulateInstructionARM::EmulatePUSH(const uint32_t opcode, in EmulatePUSH() argument
921 if (ConditionPassed(opcode)) { in EmulatePUSH()
930 registers = Bits32(opcode, 7, 0); in EmulatePUSH()
932 if (Bit32(opcode, 8)) in EmulatePUSH()
940 registers = Bits32(opcode, 15, 0) & ~0xa000; in EmulatePUSH()
946 Rt = Bits32(opcode, 15, 12); in EmulatePUSH()
953 registers = Bits32(opcode, 15, 0); in EmulatePUSH()
959 Rt = Bits32(opcode, 15, 12); in EmulatePUSH()
1014 bool EmulateInstructionARM::EmulatePOP(const uint32_t opcode, in EmulatePOP() argument
1037 if (ConditionPassed(opcode)) { in EmulatePOP()
[all …]
/llvm-project/llvm/test/tools/llvm-lipo/Inputs/
H A Darmv7-slice-big.yaml388 - Opcode: REBASE_OPCODE_SET_TYPE_IMM
390 - Opcode: REBASE_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB
394 - Opcode: REBASE_OPCODE_DO_REBASE_IMM_TIMES
396 - Opcode: REBASE_OPCODE_ADD_ADDR_IMM_SCALED
398 - Opcode: REBASE_OPCODE_DO_REBASE_ADD_ADDR_ULEB
402 - Opcode: REBASE_OPCODE_DO_REBASE_IMM_TIMES
404 - Opcode: REBASE_OPCODE_ADD_ADDR_IMM_SCALED
406 - Opcode: REBASE_OPCODE_DO_REBASE_ULEB_TIMES_SKIPPING_ULEB
411 - Opcode: REBASE_OPCODE_DO_REBASE_IMM_TIMES
413 - Opcode: REBASE_OPCODE_DONE
[all …]
/llvm-project/llvm/test/tools/llvm-readtapi/
H A Dstubify-ehtypes.test419 - Opcode: REBASE_OPCODE_SET_TYPE_IMM
421 - Opcode: REBASE_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB
424 - Opcode: REBASE_OPCODE_DO_REBASE_ADD_ADDR_ULEB
427 - Opcode: REBASE_OPCODE_DO_REBASE_ADD_ADDR_ULEB
430 - Opcode: REBASE_OPCODE_DO_REBASE_ULEB_TIMES_SKIPPING_ULEB
433 - Opcode: REBASE_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB
436 - Opcode: REBASE_OPCODE_DO_REBASE_IMM_TIMES
438 - Opcode: REBASE_OPCODE_ADD_ADDR_IMM_SCALED
440 - Opcode: REBASE_OPCODE_DO_REBASE_ADD_ADDR_ULEB
443 - Opcode: REBASE_OPCODE_DO_REBASE_IMM_TIMES
[all …]
/llvm-project/lldb/unittests/Symbol/Inputs/
H A Dinlined-functions.yaml720 - Opcode: DW_LNS_extended_op
724 - Opcode: 0x17
726 - Opcode: DW_LNS_set_column
728 - Opcode: DW_LNS_set_prologue_end
730 - Opcode: 0xC9
732 - Opcode: DW_LNS_set_column
734 - Opcode: DW_LNS_negate_stmt
736 - Opcode: 0x3C
738 - Opcode: DW_LNS_set_column
740 - Opcode: 0x3C
[all …]
/llvm-project/lldb/include/lldb/Core/
H A DOpcode.h1 //===-- Opcode.h ------------------------------------------------*- C++ -*-===//
29 class Opcode {
41 Opcode() = default;
43 Opcode(uint8_t inst, lldb::ByteOrder order) in Opcode() function
48 Opcode(uint16_t inst, lldb::ByteOrder order) in Opcode() function
53 Opcode(uint32_t inst, lldb::ByteOrder order) in Opcode() function
58 Opcode(uint64_t inst, lldb::ByteOrder order) in Opcode() function
63 Opcode(uint8_t *bytes, size_t length) in Opcode() function
70 m_type = Opcode::eTypeInvalid; in Clear()
73 Opcode::Type GetType() const { return m_type; } in GetType()
[all …]
/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h106 static BranchPredicate getBranchPredicate(unsigned Opcode);
135 unsigned Opcode) const;
138 unsigned Opcode) const;
141 unsigned Opcode, bool Swap = false) const;
144 unsigned Opcode,
160 unsigned Opcode,
304 // Splits a V_MOV_B64_DPP_PSEUDO opcode into a pair of v_mov_b32_dpp
312 // Returns an opcode that can be used to move a value to a \p DstRC
421 bool isSALU(uint16_t Opcode) const { in isVALU()
422 return get(Opcode) in isVALU()
412 isSALU(uint16_t Opcode) isSALU() argument
420 isVALU(uint16_t Opcode) isVALU() argument
428 isImage(uint16_t Opcode) isImage() argument
436 isVMEM(uint16_t Opcode) isVMEM() argument
444 isSOP1(uint16_t Opcode) isSOP1() argument
452 isSOP2(uint16_t Opcode) isSOP2() argument
460 isSOPC(uint16_t Opcode) isSOPC() argument
468 isSOPK(uint16_t Opcode) isSOPK() argument
476 isSOPP(uint16_t Opcode) isSOPP() argument
484 isPacked(uint16_t Opcode) isPacked() argument
492 isVOP1(uint16_t Opcode) isVOP1() argument
500 isVOP2(uint16_t Opcode) isVOP2() argument
508 isVOP3(uint16_t Opcode) isVOP3() argument
516 isSDWA(uint16_t Opcode) isSDWA() argument
524 isVOPC(uint16_t Opcode) isVOPC() argument
532 isMUBUF(uint16_t Opcode) isMUBUF() argument
540 isMTBUF(uint16_t Opcode) isMTBUF() argument
548 isSMRD(uint16_t Opcode) isSMRD() argument
558 isDS(uint16_t Opcode) isDS() argument
566 isLDSDMA(uint16_t Opcode) isLDSDMA() argument
574 isGWS(uint16_t Opcode) isGWS() argument
584 isMIMG(uint16_t Opcode) isMIMG() argument
592 isVIMAGE(uint16_t Opcode) isVIMAGE() argument
600 isVSAMPLE(uint16_t Opcode) isVSAMPLE() argument
608 isGather4(uint16_t Opcode) isGather4() argument
623 isSegmentSpecificFLAT(uint16_t Opcode) isSegmentSpecificFLAT() argument
632 isFLATGlobal(uint16_t Opcode) isFLATGlobal() argument
640 isFLATScratch(uint16_t Opcode) isFLATScratch() argument
645 isFLAT(uint16_t Opcode) isFLAT() argument
661 isEXP(uint16_t Opcode) isEXP() argument
669 isAtomicNoRet(uint16_t Opcode) isAtomicNoRet() argument
677 isAtomicRet(uint16_t Opcode) isAtomicRet() argument
686 isAtomic(uint16_t Opcode) isAtomic() argument
699 isWQM(uint16_t Opcode) isWQM() argument
707 isDisableWQM(uint16_t Opcode) isDisableWQM() argument
722 isVGPRSpill(uint16_t Opcode) isVGPRSpill() argument
734 isSGPRSpill(uint16_t Opcode) isSGPRSpill() argument
740 isSpill(uint16_t Opcode) isSpill() argument
748 isWWMRegSpillOpcode(uint16_t Opcode) isWWMRegSpillOpcode() argument
755 isChainCallOpcode(uint64_t Opcode) isChainCallOpcode() argument
764 isDPP(uint16_t Opcode) isDPP() argument
772 isTRANS(uint16_t Opcode) isTRANS() argument
780 isVOP3P(uint16_t Opcode) isVOP3P() argument
788 isVINTRP(uint16_t Opcode) isVINTRP() argument
796 isMAI(uint16_t Opcode) isMAI() argument
813 isWMMA(uint16_t Opcode) isWMMA() argument
825 isSWMMAC(uint16_t Opcode) isSWMMAC() argument
829 isDOT(uint16_t Opcode) isDOT() argument
837 isLDSDIR(uint16_t Opcode) isLDSDIR() argument
845 isVINTERP(uint16_t Opcode) isVINTERP() argument
863 sopkIsZext(unsigned Opcode) sopkIsZext() argument
876 isScalarStore(uint16_t Opcode) isScalarStore() argument
884 isFixedSize(uint16_t Opcode) isFixedSize() argument
892 hasFPClamp(uint16_t Opcode) hasFPClamp() argument
912 usesFPDPRounding(uint16_t Opcode) usesFPDPRounding() argument
920 isFPAtomic(uint16_t Opcode) isFPAtomic() argument
931 isBarrierStart(unsigned Opcode) isBarrierStart() argument
943 doesNotReadTiedSource(uint16_t Opcode) doesNotReadTiedSource() argument
947 getNonSoftWaitcntOpcode(unsigned Opcode) getNonSoftWaitcntOpcode() argument
1105 getOpSize(uint16_t Opcode,unsigned OpNo) getOpSize() argument
1246 getMCOpcodeFromPseudo(unsigned Opcode) getMCOpcodeFromPseudo() argument
[all...]
/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dlegalizer-info-validation.mir17 # DEBUG: G_ADD (opcode [[ADD_OPC:[0-9]+]]): 1 type index, 0 imm indices
21 # DEBUG-NEXT: G_SUB (opcode [[SUB_OPC:[0-9]+]]): 1 type index, 0 imm indices
22 # DEBUG-NEXT: .. opcode [[SUB_OPC]] is aliased to [[ADD_OPC]]
26 # DEBUG-NEXT: G_MUL (opcode {{[0-9]+}}): 1 type index, 0 imm indices
30 # DEBUG-NEXT: G_SDIV (opcode {{[0-9]+}}): 1 type index, 0 imm indices
34 # DEBUG-NEXT: G_UDIV (opcode {{[0-9]+}}): 1 type index, 0 imm indices
35 # DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
39 # DEBUG-NEXT: G_SREM (opcode {{[0-9]+}}): 1 type index, 0 imm indices
43 # DEBUG-NEXT: G_UREM (opcode {{[0-9]+}}): 1 type index, 0 imm indices
44 # DEBUG-NEXT: .. opcode {{[
[all...]
/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430InstrFormats.td46 class IForm<bits<4> opcode, DestMode ad, bit bw, SourceMode as, int size,
54 let Inst{15-12} = opcode;
63 class IForm8<bits<4> opcode, DestMode dest, SourceMode src, int size,
65 : IForm<opcode, dest, 1, src, size, outs, ins, asmstr, pattern>;
67 class I8rr<bits<4> opcode,
69 : IForm8<opcode, DstReg, SrcReg, 2, outs, ins, asmstr, pattern> {
73 class I8ri<bits<4> opcode,
75 : IForm8<opcode, DstReg, SrcImm, 4, outs, ins, asmstr, pattern> {
82 class I8rc<bits<4> opcode,
91 let Inst{15-12} = opcode;
[all …]
/llvm-project/llvm/test/MC/X86/
H A Dx86_64-asm-match.s5 // CHECK: Trying to match opcode MMX_PSHUFBrr
6 …deSize=64,BaseReg=rip,Scale=1,Disp=CPI1_0): Opcode result: multiple operand mismatches, ignoring t…
7 // CHECK: Trying to match opcode PSHUFBrr
8 …deSize=64,BaseReg=rip,Scale=1,Disp=CPI1_0): Opcode result: multiple operand mismatches, ignoring t…
9 // CHECK: Trying to match opcode PSHUFBrm
13 // CHECK: Opcode result: complete match, selecting this opcode
15 // CHECK: Trying to match opcode SHA1RNDS4rri
20 // CHECK: Opcode result: complete match, selecting this opcode
22 // CHECK: Trying to match opcode MMX_PINSRWrr
25 …ainst actual operand at index 3 (Reg:xmm5): Opcode result: multiple operand mismatches, ignoring t…
[all …]
/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td13 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
22 let Inst{0-5} = opcode;
129 class IXFormMemOp<bits<6> opcode, dag OOL, dag IOL, string asmstr,
131 :I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp;
134 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
136 : I<opcode, OOL, IOL, asmstr, itin> {
146 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
147 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
163 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
165 : BForm<opcode, a
[all...]
/llvm-project/llvm/test/tools/llvm-readtapi/Inputs/
H A Dobjc.yaml341 - Opcode: REBASE_OPCODE_SET_TYPE_IMM
343 - Opcode: REBASE_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB
346 - Opcode: REBASE_OPCODE_DO_REBASE_IMM_TIMES
348 - Opcode: REBASE_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB
351 - Opcode: REBASE_OPCODE_DO_REBASE_ULEB_TIMES_SKIPPING_ULEB
354 - Opcode: REBASE_OPCODE_ADD_ADDR_IMM_SCALED
356 - Opcode: REBASE_OPCODE_DO_REBASE_IMM_TIMES
358 - Opcode: REBASE_OPCODE_ADD_ADDR_IMM_SCALED
360 - Opcode: REBASE_OPCODE_DO_REBASE_IMM_TIMES
362 - Opcode: REBASE_OPCODE_ADD_ADDR_IMM_SCALED
[all …]
/llvm-project/llvm/unittests/MC/
H A DDwarfLineTables.cpp72 // Minimal line offset expressible through extended opcode, 0 addr delta in TEST()
73 const uint8_t Encoding0[] = {13}; // Special opcode Addr += 0, Line += -5 in TEST()
76 // Maximal line offset expressible through extended opcode, in TEST()
77 const uint8_t Encoding1[] = {26}; // Special opcode Addr += 0, Line += +8 in TEST()
81 const uint8_t Encoding2[] = {146}; // Special opcode Addr += 9, Line += 2 in TEST()
84 // Minimal line offset expressible through extended opcode, max addr delta in TEST()
85 const uint8_t Encoding3[] = {251}; // Special opcode Addr += 17, Line += -5 in TEST()
88 // Biggest special opcode in TEST()
89 const uint8_t Encoding4[] = {255}; // Special opcode Addr += 17, Line += -1 in TEST()
92 // Line delta outside of the special opcode range, address delta in range in TEST()
[all …]
/llvm-project/lldb/test/API/functionalities/module_cache/debug_index/
H A Dexe.yaml731 - Opcode: DW_LNS_extended_op
735 - Opcode: 0x17
737 - Opcode: DW_LNS_set_column
739 - Opcode: DW_LNS_set_prologue_end
741 - Opcode: 0x83
743 - Opcode: DW_LNS_set_column
745 - Opcode: DW_LNS_negate_stmt
747 - Opcode: DW_LNS_advance_line
750 - Opcode: 0x4A
752 - Opcode: DW_LNS_set_column
[all …]
/llvm-project/lldb/source/Core/
H A DOpcode.cpp1 //===-- Opcode.cpp --------------------------------------------------------===//
9 #include "lldb/Core/Opcode.h"
24 int Opcode::Dump(Stream *s, uint32_t min_byte_width) { in Dump()
27 case Opcode::eTypeInvalid: in Dump()
30 case Opcode::eType8: in Dump()
33 case Opcode::eType16: in Dump()
36 case Opcode::eType16_2: in Dump()
37 case Opcode::eType32: in Dump()
41 case Opcode::eType64: in Dump()
45 case Opcode::eTypeBytes: in Dump()
[all …]
/llvm-project/mlir/lib/Target/SPIRV/Deserialization/
H A DDeserializeOps.cpp33 /// Extracts the opcode from the given first word of a SPIR-V instruction.
34 static inline spirv::Opcode extractOpcode(uint32_t word) { in extractOpcode()
35 return static_cast<spirv::Opcode>(word & 0xffff); in extractOpcode()
78 spirv::Opcode &opcode, ArrayRef<uint32_t> &operands, in sliceInstruction() argument
79 std::optional<spirv::Opcode> expectedOpcode) { in sliceInstruction()
100 opcode = extractOpcode(binary[curOffset]); in sliceInstruction()
107 spirv::Opcode opcode, ArrayRef<uint32_t> operands, bool deferInstructions) { in processInstruction() argument
109 << spirv::stringifyOpcode(opcode) << "\ in processInstruction()
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/llvm-project/llvm/lib/Target/BPF/
H A DBPFMISimplifyPatchable.cpp63 bool isLoadInst(unsigned Opcode);
77 unsigned Opcode);
97 static bool isST(unsigned Opcode) { in isST() argument
98 return Opcode == BPF::STB_imm || Opcode == BPF::STH_imm || in isST()
99 Opcode == BPF::STW_imm || Opcode == BPF::STD_imm; in isST()
102 static bool isSTX32(unsigned Opcode) { in isSTX32() argument
103 return Opcode == BPF::STB32 || Opcode == BPF::STH32 || Opcode == BPF::STW32; in isSTX32()
106 static bool isSTX64(unsigned Opcode) { in isSTX64() argument
107 return Opcode == BPF::STB || Opcode == BPF::STH || Opcode == BPF::STW || in isSTX64()
108 Opcode == BPF::STD; in isSTX64()
[all …]
/llvm-project/llvm/test/MC/SystemZ/
H A Dasm-match.s7 // CHECK: Trying to match opcode SLLG
12 // CHECK: Opcode result: complete match, selecting this opcode
14 // CHECK: Trying to match opcode LLILL
18 // CHECK: Opcode result: complete match, selecting this opcode
20 // CHECK: Trying to match opcode LGR
24 // CHECK: Opcode result: complete match, selecting this opcode
26 // CHECK: Trying to match opcode L
[all...]
/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrFormats.td41 // MemKey identifies a targe reg-mem opcode, while MemType can be either
43 // its corresponding target opcode. See comment at MemFoldPseudo.
2332 class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
2334 : InstRRE<opcode, (outs cls:$R1), (ins),
2340 class InherentDualRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
2341 : InstRRE<opcode, (outs cls:$R1, cls:$R2), (ins),
2344 class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value>
2345 : InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> {
2350 class StoreInherentS<string mnemonic, bits<16> opcode,
2352 : InstS<opcode, (out
[all...]
/llvm-project/clang/lib/AST/Interp/
H A DOpcodes.td

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