Lines Matching full:opcode
106 static BranchPredicate getBranchPredicate(unsigned Opcode);
135 unsigned Opcode) const;
138 unsigned Opcode) const;
141 unsigned Opcode, bool Swap = false) const;
144 unsigned Opcode,
160 unsigned Opcode,
304 // Splits a V_MOV_B64_DPP_PSEUDO opcode into a pair of v_mov_b32_dpp
312 // Returns an opcode that can be used to move a value to a \p DstRC
421 bool isSALU(uint16_t Opcode) const {
422 return get(Opcode).TSFlags & SIInstrFlags::SALU;
429 bool isVALU(uint16_t Opcode) const {
430 return get(Opcode).TSFlags & SIInstrFlags::VALU;
437 bool isImage(uint16_t Opcode) const {
438 return isMIMG(Opcode) || isVSAMPLE(Opcode) || isVIMAGE(Opcode);
445 bool isVMEM(uint16_t Opcode) const {
446 return isMUBUF(Opcode) || isMTBUF(Opcode) || isImage(Opcode);
453 bool isSOP1(uint16_t Opcode) const {
454 return get(Opcode).TSFlags & SIInstrFlags::SOP1;
461 bool isSOP2(uint16_t Opcode) const {
462 return get(Opcode).TSFlags & SIInstrFlags::SOP2;
469 bool isSOPC(uint16_t Opcode) const {
470 return get(Opcode).TSFlags & SIInstrFlags::SOPC;
477 bool isSOPK(uint16_t Opcode) const {
478 return get(Opcode).TSFlags & SIInstrFlags::SOPK;
485 bool isSOPP(uint16_t Opcode) const {
486 return get(Opcode).TSFlags & SIInstrFlags::SOPP;
493 bool isPacked(uint16_t Opcode) const {
494 return get(Opcode).TSFlags & SIInstrFlags::IsPacked;
501 bool isVOP1(uint16_t Opcode) const {
502 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
509 bool isVOP2(uint16_t Opcode) const {
510 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
517 bool isVOP3(uint16_t Opcode) const {
518 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
525 bool isSDWA(uint16_t Opcode) const {
526 return get(Opcode).TSFlags & SIInstrFlags::SDWA;
533 bool isVOPC(uint16_t Opcode) const {
534 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
541 bool isMUBUF(uint16_t Opcode) const {
542 return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
549 bool isMTBUF(uint16_t Opcode) const {
550 return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
557 bool isSMRD(uint16_t Opcode) const {
558 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
567 bool isDS(uint16_t Opcode) const {
568 return get(Opcode).TSFlags & SIInstrFlags::DS;
575 bool isLDSDMA(uint16_t Opcode) {
576 return isVALU(Opcode) && (isMUBUF(Opcode) || isFLAT(Opcode));
583 bool isGWS(uint16_t Opcode) const {
584 return get(Opcode).TSFlags & SIInstrFlags::GWS;
587 bool isAlwaysGDS(uint16_t Opcode) const;
593 bool isMIMG(uint16_t Opcode) const {
594 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
601 bool isVIMAGE(uint16_t Opcode) const {
602 return get(Opcode).TSFlags & SIInstrFlags::VIMAGE;
609 bool isVSAMPLE(uint16_t Opcode) const {
610 return get(Opcode).TSFlags & SIInstrFlags::VSAMPLE;
617 bool isGather4(uint16_t Opcode) const {
618 return get(Opcode).TSFlags & SIInstrFlags::Gather4;
632 bool isSegmentSpecificFLAT(uint16_t Opcode) const {
633 auto Flags = get(Opcode).TSFlags;
641 bool isFLATGlobal(uint16_t Opcode) const {
642 return get(Opcode).TSFlags & SIInstrFlags::FlatGlobal;
649 bool isFLATScratch(uint16_t Opcode) const {
650 return get(Opcode).TSFlags & SIInstrFlags::FlatScratch;
654 bool isFLAT(uint16_t Opcode) const {
655 return get(Opcode).TSFlags & SIInstrFlags::FLAT;
670 bool isEXP(uint16_t Opcode) const {
671 return get(Opcode).TSFlags & SIInstrFlags::EXP;
678 bool isAtomicNoRet(uint16_t Opcode) const {
679 return get(Opcode).TSFlags & SIInstrFlags::IsAtomicNoRet;
686 bool isAtomicRet(uint16_t Opcode) const {
687 return get(Opcode).TSFlags & SIInstrFlags::IsAtomicRet;
695 bool isAtomic(uint16_t Opcode) const {
696 return get(Opcode).TSFlags & (SIInstrFlags::IsAtomicRet |
708 bool isWQM(uint16_t Opcode) const {
709 return get(Opcode).TSFlags & SIInstrFlags::WQM;
716 bool isDisableWQM(uint16_t Opcode) const {
717 return get(Opcode).TSFlags & SIInstrFlags::DisableWQM;
731 bool isVGPRSpill(uint16_t Opcode) const {
732 return Opcode != AMDGPU::SI_SPILL_S32_TO_VGPR &&
733 Opcode != AMDGPU::SI_RESTORE_S32_FROM_VGPR &&
734 (isSpill(Opcode) && isVALU(Opcode));
743 bool isSGPRSpill(uint16_t Opcode) const {
744 return Opcode == AMDGPU::SI_SPILL_S32_TO_VGPR ||
745 Opcode == AMDGPU::SI_RESTORE_S32_FROM_VGPR ||
746 (isSpill(Opcode) && isSALU(Opcode));
749 bool isSpill(uint16_t Opcode) const {
750 return get(Opcode).TSFlags & SIInstrFlags::Spill;
757 static bool isWWMRegSpillOpcode(uint16_t Opcode) {
758 return Opcode == AMDGPU::SI_SPILL_WWM_V32_SAVE ||
759 Opcode == AMDGPU::SI_SPILL_WWM_AV32_SAVE ||
760 Opcode == AMDGPU::SI_SPILL_WWM_V32_RESTORE ||
761 Opcode == AMDGPU::SI_SPILL_WWM_AV32_RESTORE;
764 static bool isChainCallOpcode(uint64_t Opcode) {
765 return Opcode == AMDGPU::SI_CS_CHAIN_TC_W32 ||
766 Opcode == AMDGPU::SI_CS_CHAIN_TC_W64;
773 bool isDPP(uint16_t Opcode) const {
774 return get(Opcode).TSFlags & SIInstrFlags::DPP;
781 bool isTRANS(uint16_t Opcode) const {
782 return get(Opcode).TSFlags & SIInstrFlags::TRANS;
789 bool isVOP3P(uint16_t Opcode) const {
790 return get(Opcode).TSFlags & SIInstrFlags::VOP3P;
797 bool isVINTRP(uint16_t Opcode) const {
798 return get(Opcode).TSFlags & SIInstrFlags::VINTRP;
805 bool isMAI(uint16_t Opcode) const {
806 return get(Opcode).TSFlags & SIInstrFlags::IsMAI;
822 bool isWMMA(uint16_t Opcode) const {
823 return get(Opcode).TSFlags & SIInstrFlags::IsWMMA;
834 bool isSWMMAC(uint16_t Opcode) const {
835 return get(Opcode).TSFlags & SIInstrFlags::IsSWMMAC;
838 bool isDOT(uint16_t Opcode) const {
839 return get(Opcode).TSFlags & SIInstrFlags::IsDOT;
846 bool isLDSDIR(uint16_t Opcode) const {
847 return get(Opcode).TSFlags & SIInstrFlags::LDSDIR;
854 bool isVINTERP(uint16_t Opcode) const {
855 return get(Opcode).TSFlags & SIInstrFlags::VINTERP;
872 static bool sopkIsZext(unsigned Opcode) {
873 return Opcode == AMDGPU::S_CMPK_EQ_U32 || Opcode == AMDGPU::S_CMPK_LG_U32 ||
874 Opcode == AMDGPU::S_CMPK_GT_U32 || Opcode == AMDGPU::S_CMPK_GE_U32 ||
875 Opcode == AMDGPU::S_CMPK_LT_U32 || Opcode == AMDGPU::S_CMPK_LE_U32 ||
876 Opcode == AMDGPU::S_GETREG_B32;
885 bool isScalarStore(uint16_t Opcode) const {
886 return get(Opcode).TSFlags & SIInstrFlags::SCALAR_STORE;
893 bool isFixedSize(uint16_t Opcode) const {
894 return get(Opcode).TSFlags & SIInstrFlags::FIXED_SIZE;
901 bool hasFPClamp(uint16_t Opcode) const {
902 return get(Opcode).TSFlags & SIInstrFlags::FPClamp;
921 bool usesFPDPRounding(uint16_t Opcode) const {
922 return get(Opcode).TSFlags & SIInstrFlags::FPDPRounding;
929 bool isFPAtomic(uint16_t Opcode) const {
930 return get(Opcode).TSFlags & SIInstrFlags::FPAtomic;
937 // Check to see if opcode is for a barrier start. Pre gfx12 this is just the
940 bool isBarrierStart(unsigned Opcode) const {
941 return Opcode == AMDGPU::S_BARRIER ||
942 Opcode == AMDGPU::S_BARRIER_SIGNAL_M0 ||
943 Opcode == AMDGPU::S_BARRIER_SIGNAL_ISFIRST_M0 ||
944 Opcode == AMDGPU::S_BARRIER_SIGNAL_IMM ||
945 Opcode == AMDGPU::S_BARRIER_SIGNAL_ISFIRST_IMM;
948 bool isBarrier(unsigned Opcode) const {
949 return isBarrierStart(Opcode) || Opcode == AMDGPU::S_BARRIER_WAIT ||
950 Opcode == AMDGPU::S_BARRIER_INIT_M0 ||
951 Opcode == AMDGPU::S_BARRIER_INIT_IMM ||
952 Opcode == AMDGPU::S_BARRIER_JOIN_IMM ||
953 Opcode == AMDGPU::S_BARRIER_LEAVE ||
954 Opcode == AMDGPU::S_BARRIER_LEAVE_IMM ||
955 Opcode == AMDGPU::DS_GWS_INIT || Opcode == AMDGPU::DS_GWS_BARRIER;
958 static bool isF16PseudoScalarTrans(unsigned Opcode) {
959 return Opcode == AMDGPU::V_S_EXP_F16_e64 ||
960 Opcode == AMDGPU::V_S_LOG_F16_e64 ||
961 Opcode == AMDGPU::V_S_RCP_F16_e64 ||
962 Opcode == AMDGPU::V_S_RSQ_F16_e64 ||
963 Opcode == AMDGPU::V_S_SQRT_F16_e64;
970 bool doesNotReadTiedSource(uint16_t Opcode) const {
971 return get(Opcode).TSFlags & SIInstrFlags::TiedSourceNotRead;
974 bool isIGLP(unsigned Opcode) const {
975 return Opcode == AMDGPU::SCHED_BARRIER ||
976 Opcode == AMDGPU::SCHED_GROUP_BARRIER || Opcode == AMDGPU::IGLP_OPT;
981 static unsigned getNonSoftWaitcntOpcode(unsigned Opcode) {
982 switch (Opcode) {
1000 return Opcode;
1004 bool isWaitcnt(unsigned Opcode) const {
1005 switch (getNonSoftWaitcntOpcode(Opcode)) {
1123 bool hasVALU32BitEncoding(unsigned Opcode) const;
1138 bool hasModifiers(unsigned Opcode) const;
1173 // instruction opcode.
1174 unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
1175 const MCOperandInfo &OpInfo = get(Opcode).operands()[OpNo];
1265 /// Replace the instructions opcode with the equivalent VALU
1266 /// opcode. This function will also move the users of MachineInstruntions
1318 /// that corresponds to the specified pseudo or native opcode.
1319 const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const {
1320 return get(pseudoToMCOpcode(Opcode));
1393 static bool isKillTerminator(unsigned Opcode);
1394 const MCInstrDesc &getKillTerminatorFromPseudo(unsigned Opcode) const;
1418 /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
1419 /// Return -1 if the target-specific opcode for the pseudo instruction does
1420 /// not exist. If Opcode is not a pseudo instruction, this is identity.
1421 int pseudoToMCOpcode(int Opcode) const;
1424 /// Return true if this opcode should not be used by codegen.
1513 int getVOPe64(uint16_t Opcode);
1516 int getVOPe32(uint16_t Opcode);
1519 int getSDWAOp(uint16_t Opcode);
1522 int getDPPOp32(uint16_t Opcode);
1525 int getDPPOp64(uint16_t Opcode);
1528 int getBasicFromSDWAOp(uint16_t Opcode);
1531 int getCommuteRev(uint16_t Opcode);
1534 int getCommuteOrig(uint16_t Opcode);
1537 int getAddr64Inst(uint16_t Opcode);
1539 /// Check if \p Opcode is an Addr64 opcode.
1541 /// \returns \p Opcode if it is an Addr64 opcode, otherwise -1.
1543 int getIfAddr64Inst(uint16_t Opcode);
1546 int getSOPKOp(uint16_t Opcode);
1548 /// \returns SADDR form of a FLAT Global instruction given an \p Opcode
1551 int getGlobalSaddrOp(uint16_t Opcode);
1553 /// \returns VADDR form of a FLAT Global instruction given an \p Opcode
1556 int getGlobalVaddrOp(uint16_t Opcode);
1559 int getVCMPXNoSDstOp(uint16_t Opcode);
1562 /// given an \p Opcode of an SS (SADDR) form.
1564 int getFlatScratchInstSTfromSS(uint16_t Opcode);
1566 /// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode
1569 int getFlatScratchInstSVfromSVS(uint16_t Opcode);
1571 /// \returns SS (SADDR) form of a FLAT Scratch instruction given an \p Opcode
1574 int getFlatScratchInstSSfromSV(uint16_t Opcode);
1576 /// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode
1579 int getFlatScratchInstSVfromSS(uint16_t Opcode);
1583 int getMFMAEarlyClobberOp(uint16_t Opcode);
1586 /// vdst, given an \p Opcode of an MFMA which uses VGPRs for srcC/vdst.
1588 int getMFMASrcCVDstAGPROp(uint16_t Opcode);
1592 int getVCMPXOpFromVCMP(uint16_t Opcode);