Lines Matching full:opcode

41   // MemKey identifies a targe reg-mem opcode, while MemType can be either
43   // its corresponding target opcode. See comment at MemFoldPseudo.
2332 class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
2334   : InstRRE<opcode, (outs cls:$R1), (ins),
2340 class InherentDualRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
2341   : InstRRE<opcode, (outs cls:$R1, cls:$R2), (ins),
2344 class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value>
2345   : InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> {
2350 class StoreInherentS<string mnemonic, bits<16> opcode,
2352   : InstS<opcode, (outs), (ins (bdaddr12only $B2, $D2):$BD2),
2358 class SideEffectInherentE<string mnemonic, bits<16>opcode>
2359   : InstE<opcode, (outs), (ins), mnemonic, []>;
2361 class SideEffectInherentS<string mnemonic, bits<16> opcode,
2363   : InstS<opcode, (outs), (ins), mnemonic, [(operator)]> {
2368 class SideEffectInherentRRE<string mnemonic, bits<16> opcode>
2369   : InstRRE<opcode, (outs), (ins), mnemonic, []> {
2375 class CallRI<string mnemonic, bits<12> opcode>
2376   : InstRIb<opcode, (outs), (ins GR64:$R1, brtarget16tls:$RI2),
2380 class CallRIL<string mnemonic, bits<12> opcode>
2381   : InstRILb<opcode, (outs), (ins GR64:$R1, brtarget32tls:$RI2),
2384 class CallRR<string mnemonic, bits<8> opcode>
2385   : InstRR<opcode, (outs), (ins GR64:$R1, ADDR64:$R2),
2388 class CallRX<string mnemonic, bits<8> opcode>
2389   : InstRXa<opcode, (outs), (ins GR64:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
2392 class CondBranchRI<string mnemonic, bits<12> opcode,
2394   : InstRIc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget16:$RI2),
2400 class AsmCondBranchRI<string mnemonic, bits<12> opcode>
2401   : InstRIc<opcode, (outs), (ins imm32zx4:$M1, brtarget16:$RI2),
2404 class NeverCondBranchRI<string mnemonic, bits<12> opcode>
2405   : InstRIc<opcode, (outs), (ins brtarget16:$RI2),
2410 class FixedCondBranchRI<CondVariant V, string mnemonic, bits<12> opcode,
2412   : InstRIc<opcode, (outs), (ins brtarget16:$RI2),
2419 class CondBranchRIL<string mnemonic, bits<12> opcode>
2420   : InstRILc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget32:$RI2),
2425 class AsmCondBranchRIL<string mnemonic, bits<12> opcode>
2426   : InstRILc<opcode, (outs), (ins imm32zx4:$M1, brtarget32:$RI2),
2429 class NeverCondBranchRIL<string mnemonic, bits<12> opcode>
2430   : InstRILc<opcode, (outs), (ins brtarget32:$RI2),
2435 class FixedCondBranchRIL<CondVariant V, string mnemonic, bits<12> opcode>
2436   : InstRILc<opcode, (outs), (ins brtarget32:$RI2),
2443 class CondBranchRR<string mnemonic, bits<8> opcode>
2444   : InstRR<opcode, (outs), (ins cond4:$valid, cond4:$R1, GR64:$R2),
2449 class AsmCondBranchRR<string mnemonic, bits<8> opcode>
2450   : InstRR<opcode, (outs), (ins imm32zx4:$R1, GR64:$R2),
2453 multiclass NeverCondBranchRR<string mnemonic, bits<8> opcode> {
2455   def "" : InstRR<opcode, (outs), (ins GR64:$R2),
2459   def Opt : InstRR<opcode, (outs), (ins), mnemonic, []> {
2465 class FixedCondBranchRR<CondVariant V, string mnemonic, bits<8> opcode,
2467   : InstRR<opcode, (outs), (ins ADDR64:$R2),
2474 class CondBranchRX<string mnemonic, bits<8> opcode>
2475   : InstRXb<opcode, (outs),
2481 class AsmCondBranchRX<string mnemonic, bits<8> opcode>
2482   : InstRXb<opcode, (outs),
2486 multiclass NeverCondBranchRX<string mnemonic, bits<8> opcode> {
2488   def "" : InstRXb<opcode, (outs),
2493   def Opt : InstRXb<opcode, (outs), (ins), mnemonic, []> {
2501 class FixedCondBranchRX<CondVariant V, string mnemonic, bits<8> opcode>
2502   : InstRXb<opcode, (outs), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
2509 class CondBranchRXY<string mnemonic, bits<16> opcode>
2510   : InstRXYb<opcode, (outs), (ins cond4:$valid, cond4:$M1,
2517 class AsmCondBranchRXY<string mnemonic, bits<16> opcode>
2518   : InstRXYb<opcode, (outs),
2524 class FixedCondBranchRXY<CondVariant V, string mnemonic, bits<16> opcode,
2526   : InstRXYb<opcode, (outs), (ins (bdxaddr20only $B2, $D2, $X2):$XBD2),
2535 class CmpBranchRIEa<string mnemonic, bits<16> opcode,
2537   : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, cond4:$M3),
2540 class AsmCmpBranchRIEa<string mnemonic, bits<16> opcode,
2542   : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, imm32zx4:$M3),
2545 class FixedCmpBranchRIEa<CondVariant V, string mnemonic, bits<16> opcode,
2547   : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2),
2554 multiclass CmpBranchRIEaPair<string mnemonic, bits<16> opcode,
2557     def "" : CmpBranchRIEa<mnemonic, opcode, cls, imm>;
2558   def Asm : AsmCmpBranchRIEa<mnemonic, opcode, cls, imm>;
2561 class CmpBranchRIEb<string mnemonic, bits<16> opcode,
2563   : InstRIEb<opcode, (outs),
2567 class AsmCmpBranchRIEb<string mnemonic, bits<16> opcode,
2569   : InstRIEb<opcode, (outs),
2573 class FixedCmpBranchRIEb<CondVariant V, string mnemonic, bits<16> opcode,
2575   : InstRIEb<opcode, (outs), (ins cls:$R1, cls:$R2, brtarget16:$RI4),
2582 multiclass CmpBranchRIEbPair<string mnemonic, bits<16> opcode,
2585     def "" : CmpBranchRIEb<mnemonic, opcode, cls>;
2586   def Asm : AsmCmpBranchRIEb<mnemonic, opcode, cls>;
2589 class CmpBranchRIEc<string mnemonic, bits<16> opcode,
2591   : InstRIEc<opcode, (outs),
2595 class AsmCmpBranchRIEc<string mnemonic, bits<16> opcode,
2597   : InstRIEc<opcode, (outs),
2601 class FixedCmpBranchRIEc<CondVariant V, string mnemonic, bits<16> opcode,
2603   : InstRIEc<opcode, (outs), (ins cls:$R1, imm:$I2, brtarget16:$RI4),
2610 multiclass CmpBranchRIEcPair<string mnemonic, bits<16> opcode,
2613     def "" : CmpBranchRIEc<mnemonic, opcode, cls, imm>;
2614   def Asm : AsmCmpBranchRIEc<mnemonic, opcode, cls, imm>;
2617 class CmpBranchRRFc<string mnemonic, bits<16> opcode,
2619   : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, cond4:$M3),
2622 class AsmCmpBranchRRFc<string mnemonic, bits<16> opcode,
2624   : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, imm32zx4:$M3),
2627 multiclass CmpBranchRRFcPair<string mnemonic, bits<16> opcode,
2630     def "" : CmpBranchRRFc<mnemonic, opcode, cls>;
2631   def Asm : AsmCmpBranchRRFc<mnemonic, opcode, cls>;
2634 class FixedCmpBranchRRFc<CondVariant V, string mnemonic, bits<16> opcode,
2636   : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2),
2643 class CmpBranchRRS<string mnemonic, bits<16> opcode,
2645   : InstRRS<opcode, (outs),
2649 class AsmCmpBranchRRS<string mnemonic, bits<16> opcode,
2651   : InstRRS<opcode, (outs),
2655 class FixedCmpBranchRRS<CondVariant V, string mnemonic, bits<16> opcode,
2657   : InstRRS<opcode, (outs),
2665 multiclass CmpBranchRRSPair<string mnemonic, bits<16> opcode,
2668     def "" : CmpBranchRRS<mnemonic, opcode, cls>;
2669   def Asm : AsmCmpBranchRRS<mnemonic, opcode, cls>;
2672 class CmpBranchRIS<string mnemonic, bits<16> opcode,
2674   : InstRIS<opcode, (outs),
2678 class AsmCmpBranchRIS<string mnemonic, bits<16> opcode,
2680   : InstRIS<opcode, (outs),
2684 class FixedCmpBranchRIS<CondVariant V, string mnemonic, bits<16> opcode,
2686   : InstRIS<opcode, (outs),
2694 multiclass CmpBranchRISPair<string mnemonic, bits<16> opcode,
2697     def "" : CmpBranchRIS<mnemonic, opcode, cls, imm>;
2698   def Asm : AsmCmpBranchRIS<mnemonic, opcode, cls, imm>;
2701 class CmpBranchRSYb<string mnemonic, bits<16> opcode,
2703   : InstRSYb<opcode, (outs),
2707 class AsmCmpBranchRSYb<string mnemonic, bits<16> opcode,
2709   : InstRSYb<opcode, (outs),
2713 multiclass CmpBranchRSYbPair<string mnemonic, bits<16> opcode,
2716     def "" : CmpBranchRSYb<mnemonic, opcode, cls>;
2717   def Asm : AsmCmpBranchRSYb<mnemonic, opcode, cls>;
2720 class FixedCmpBranchRSYb<CondVariant V, string mnemonic, bits<16> opcode,
2722   : InstRSYb<opcode, (outs), (ins cls:$R1, (bdaddr20only $B2, $D2):$BD2),
2729 class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls>
2730   : InstRIb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$RI2),
2736 class BranchUnaryRIL<string mnemonic, bits<12> opcode, RegisterOperand cls>
2737   : InstRILb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget32:$RI2),
2743 class BranchUnaryRR<string mnemonic, bits<8> opcode, RegisterOperand cls>
2744   : InstRR<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2),
2750 class BranchUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
2751   : InstRRE<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2),
2757 class BranchUnaryRX<string mnemonic, bits<8> opcode, RegisterOperand cls>
2758   : InstRXa<opcode, (outs cls:$R1),
2765 class BranchUnaryRXY<string mnemonic, bits<16> opcode, RegisterOperand cls>
2766   : InstRXYa<opcode, (outs cls:$R1),
2773 class BranchBinaryRSI<string mnemonic, bits<8> opcode, RegisterOperand cls>
2774   : InstRSI<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, brtarget16:$RI2),
2780 class BranchBinaryRIEe<string mnemonic, bits<16> opcode, RegisterOperand cls>
2781   : InstRIEe<opcode, (outs cls:$R1),
2788 class BranchBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls>
2789   : InstRSa<opcode, (outs cls:$R1),
2796 class BranchBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
2797   : InstRSYa<opcode,
2805 class LoadMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
2807   : InstRSa<opcode, (outs cls:$R1, cls:$R3), (ins (mode $B2, $D2):$BD2),
2812 class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
2814   : InstRSYa<opcode, (outs cls:$R1, cls:$R3), (ins (mode $B2, $D2):$BD2),
2829 class LoadMultipleSSe<string mnemonic, bits<8> opcode, RegisterOperand cls>
2830   : InstSSe<opcode, (outs cls:$R1, cls:$R3),
2836 multiclass LoadMultipleVRSaAlign<string mnemonic, bits<16> opcode> {
2838     def Align : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3),
2842       def "" : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3),
2848 class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2850   : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
2860 class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2863   : InstRXa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
2872 class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2875   : InstRXYa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
2896 class StoreVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2898   : InstVRX<opcode, (outs),
2907 class StoreVRXGeneric<string mnemonic, bits<16> opcode>
2908   : InstVRX<opcode, (outs),
2914 multiclass StoreVRXAlign<string mnemonic, bits<16> opcode> {
2916     def Align : InstVRX<opcode, (outs),
2921       def "" : InstVRX<opcode, (outs),
2927 class StoreLengthVRSb<string mnemonic, bits<16> opcode,
2929   : InstVRSb<opcode, (outs),
2938 class StoreLengthVRSd<string mnemonic, bits<16> opcode,
2940   : InstVRSd<opcode, (outs),
2948 class StoreLengthVSI<string mnemonic, bits<16> opcode,
2950   : InstVSI<opcode, (outs),
2958 class StoreMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
2960   : InstRSa<opcode, (outs), (ins cls:$R1, cls:$R3, (mode $B2, $D2):$BD2),
2965 class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
2967   : InstRSYa<opcode, (outs), (ins cls:$R1, cls:$R3, (mode $B2, $D2):$BD2),
2982 multiclass StoreMultipleVRSaAlign<string mnemonic, bits<16> opcode> {
2984     def Align : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3,
2989       def "" : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3,
3001 class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3003   : InstSI<opcode, (outs), (ins (mviaddr12pair $B1, $D1):$BD1, imm:$I2),
3009 class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3011   : InstSIY<opcode, (outs), (ins (mviaddr20pair $B1, $D1):$BD1, imm:$I2),
3017 class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3019   : InstSIL<opcode, (outs), (ins (mviaddr12pair $B1, $D1):$BD1, imm:$I2),
3035 class StoreSSE<string mnemonic, bits<16> opcode>
3036   : InstSSE<opcode, (outs),
3042 class CondStoreRSY<string mnemonic, bits<16> opcode,
3045   : InstRSYb<opcode, (outs),
3055 class AsmCondStoreRSY<string mnemonic, bits<16> opcode,
3058   : InstRSYb<opcode, (outs), (ins cls:$R1, (mode $B2, $D2):$BD2, imm32zx4:$M3),
3065 class FixedCondStoreRSY<CondVariant V, string mnemonic, bits<16> opcode,
3068   : InstRSYb<opcode, (outs), (ins cls:$R1, (mode $B2, $D2):$BD2),
3077 multiclass CondStoreRSYPair<string mnemonic, bits<16> opcode,
3081     def "" : CondStoreRSY<mnemonic, opcode, cls, bytes, mode>;
3082   def Asm : AsmCondStoreRSY<mnemonic, opcode, cls, bytes, mode>;
3085 class SideEffectUnaryI<string mnemonic, bits<8> opcode, ImmOpWithPattern imm>
3086   : InstI<opcode, (outs), (ins imm:$I1),
3089 class SideEffectUnaryRR<string mnemonic, bits<8>opcode, RegisterOperand cls>
3090   : InstRR<opcode, (outs), (ins cls:$R1),
3095 class SideEffectUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
3097   : InstRRE<opcode, (outs), (ins cls:$R1),
3102 class SideEffectUnaryS<string mnemonic, bits<16> opcode,
3105   : InstS<opcode, (outs), (ins (mode $B2, $D2):$BD2),
3111 class SideEffectUnarySIY<string mnemonic, bits<16> opcode,
3114   : InstSIY<opcode, (outs), (ins (mode $B1, $D1):$BD1),
3121 class SideEffectAddressS<string mnemonic, bits<16> opcode,
3124   : InstS<opcode, (outs), (ins (mode $B2, $D2):$BD2),
3127 class LoadAddressRX<string mnemonic, bits<8> opcode,
3129   : InstRXa<opcode, (outs GR64:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
3133 class LoadAddressRXY<string mnemonic, bits<16> opcode,
3135   : InstRXYa<opcode, (outs GR64:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
3149 class LoadAddressRIL<string mnemonic, bits<12> opcode,
3151   : InstRILb<opcode, (outs GR64:$R1), (ins pcrel32:$RI2),
3155 multiclass LoadIndexedAddressRXY<string mnemonic, bits<16> opcode,
3158   def "" : InstRXYa<opcode, (outs GR64:$R1),
3181 class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3183   : InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2),
3190 class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3192   : InstRRE<opcode, (outs cls1:$R1), (ins cls2:$R2),
3199 class UnaryTiedRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
3200   : InstRRE<opcode, (outs cls:$R1), (ins cls:$R1src),
3207 class UnaryMemRRFc<string mnemonic, bits<16> opcode,
3209   : InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src),
3216 class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3218   : InstRIa<opcode, (outs cls:$R1), (ins imm:$I2),
3222 class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3224   : InstRILa<opcode, (outs cls:$R1), (ins imm:$I2),
3228 class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3230   : InstRILb<opcode, (outs cls:$R1), (ins pcrel32:$RI2),
3240 class CondUnaryRSY<string mnemonic, bits<16> opcode,
3243   : InstRSYb<opcode, (outs cls:$R1),
3262 class AsmCondUnaryRSY<string mnemonic, bits<16> opcode,
3265   : InstRSYb<opcode, (outs cls:$R1),
3275 class FixedCondUnaryRSY<CondVariant V, string mnemonic, bits<16> opcode,
3278   : InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, (mode $B2, $D2):$BD2),
3289 multiclass CondUnaryRSYPair<string mnemonic, bits<16> opcode,
3294     def "" : CondUnaryRSY<mnemonic, opcode, operator, cls, bytes, mode>;
3295   def Asm : AsmCondUnaryRSY<mnemonic, opcode, cls, bytes, mode>;
3298 class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3301   : InstRXa<opcode, (outs cls:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
3310 class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3312   : InstRXE<opcode, (outs cls:$R1), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
3322 class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3325   : InstRXYa<opcode, (outs cls:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
3346 class UnaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3348   : InstVRIa<opcode, (outs tr.op:$V1), (ins imm:$I2),
3354 class UnaryVRIaGeneric<string mnemonic, bits<16> opcode, ImmOpWithPattern imm>
3355   : InstVRIa<opcode, (outs VR128:$V1), (ins imm:$I2, imm32zx4:$M3),
3358 class UnaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3361   : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2),
3371 class UnaryVRRaGeneric<string mnemonic, bits<16> opcode, bits<4> m4 = 0,
3373   : InstVRRa<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
3379 class UnaryVRRaFloatGeneric<string mnemonic, bits<16> opcode, bits<4> m5 = 0>
3380   : InstVRRa<opcode, (outs VR128:$V1),
3390 multiclass UnaryExtraVRRaSPair<string mnemonic, bits<16> opcode,
3395     def "" : InstVRRa<opcode, (outs tr1.op:$V1),
3403     def S : UnaryVRRa<mnemonic#"s", opcode, operator_cc, tr1, tr2,
3407 multiclass UnaryExtraVRRaSPairGeneric<string mnemonic, bits<16> opcode> {
3409     def "" : InstVRRa<opcode, (outs VR128:$V1),
3417 class UnaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3419   : InstVRX<opcode, (outs tr.op:$V1), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
3427 class UnaryVRXGeneric<string mnemonic, bits<16> opcode>
3428   : InstVRX<opcode, (outs VR128:$V1),
3434 multiclass UnaryVRXAlign<string mnemonic, bits<16> opcode> {
3436     def Align : InstVRX<opcode, (outs VR128:$V1),
3440       def "" : InstVRX<opcode, (outs VR128:$V1),
3446 class SideEffectBinaryRX<string mnemonic, bits<8> opcode,
3448   : InstRXa<opcode, (outs), (ins cls:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
3451 class SideEffectBinaryRXY<string mnemonic, bits<16> opcode,
3453   : InstRXYa<opcode, (outs), (ins cls:$R1, (bdxaddr20only $B2, $D2, $X2):$XBD2),
3456 class SideEffectBinaryRILPC<string mnemonic, bits<12> opcode,
3458   : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
3466 class SideEffectBinaryRRE<string mnemonic, bits<16> opcode,
3468   : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
3471 class SideEffectBinaryRRFa<string mnemonic, bits<16> opcode,
3473   : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2),
3479 class SideEffectBinaryRRFc<string mnemonic, bits<16> opcode,
3481   : InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2),
3486 class SideEffectBinaryIE<string mnemonic, bits<16> opcode,
3488   : InstIE<opcode, (outs), (ins imm1:$I1, imm2:$I2),
3491 class SideEffectBinarySI<string mnemonic, bits<8> opcode, Operand imm>
3492   : InstSI<opcode, (outs), (ins (bdaddr12only $B1, $D1):$BD1, imm:$I2),
3495 class SideEffectBinarySIL<string mnemonic, bits<16> opcode,
3497   : InstSIL<opcode, (outs), (ins (bdaddr12only $B1, $D1):$BD1, imm:$I2),
3500 class SideEffectBinarySSa<string mnemonic, bits<8> opcode>
3501   : InstSSa<opcode, (outs), (ins (bdladdr12onlylen8 $B1, $D1, $L1):$BDL1,
3505 class SideEffectBinarySSb<string mnemonic, bits<8> opcode>
3506   : InstSSb<opcode,
3511 class SideEffectBinarySSf<string mnemonic, bits<8> opcode>
3512   : InstSSf<opcode, (outs), (ins (bdaddr12only $B1, $D1):$BD1,
3516 class SideEffectBinarySSE<string mnemonic, bits<16> opcode>
3517   : InstSSE<opcode, (outs),
3521 class SideEffectBinaryMemMemRR<string mnemonic, bits<8> opcode,
3523   : InstRR<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
3529 class SideEffectBinaryMemRRE<string mnemonic, bits<16> opcode,
3531   : InstRRE<opcode, (outs cls2:$R2), (ins cls1:$R1, cls2:$R2src),
3537 class SideEffectBinaryMemMemRRE<string mnemonic, bits<16> opcode,
3539   : InstRRE<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
3545 class SideEffectBinaryMemMemRRFc<string mnemonic, bits<16> opcode,
3547   : InstRRFc<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
3554 class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3556   : InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
3565 class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3567   : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
3576 class BinaryRRD<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3578   : InstRRD<opcode, (outs cls1:$R1), (ins cls2:$R3, cls2:$R2),
3585 class BinaryRRFa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3588   : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3),
3597 class UnaryRRFa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3599   : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls2:$R3),
3633 class BinaryRRFb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3636   : InstRRFb<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3),
3642 class BinaryRRFc<string mnemonic, bits<16> opcode,
3644   : InstRRFc<opcode, (outs cls1:$R1), (ins cls2:$R2, imm32zx4:$M3),
3647 class BinaryMemRRFc<string mnemonic, bits<16> opcode,
3649   : InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src, imm:$M3),
3655 multiclass BinaryMemRRFcOpt<string mnemonic, bits<16> opcode,
3657   def "" : BinaryMemRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>;
3658   def Opt : UnaryMemRRFc<mnemonic, opcode, cls1, cls2>;
3661 class BinaryRRFd<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3663   : InstRRFd<opcode, (outs cls1:$R1), (ins cls2:$R2, imm32zx4:$M4),
3666 class BinaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3668   : InstRRFe<opcode, (outs cls1:$R1), (ins imm32zx4:$M3, cls2:$R2),
3673 class CondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3675   : InstRRFc<opcode, (outs cls1:$R1),
3691 class AsmCondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3693   : InstRRFc<opcode, (outs cls1:$R1),
3701 class FixedCondBinaryRRF<CondVariant V, string mnemonic, bits<16> opcode,
3703   : InstRRFc<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
3712 multiclass CondBinaryRRFPair<string mnemonic, bits<16> opcode,
3715     def "" : CondBinaryRRF<mnemonic, opcode, cls1, cls2>;
3716   def Asm : AsmCondBinaryRRF<mnemonic, opcode, cls1, cls2>;
3719 class CondBinaryRRFa<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3721   : InstRRFa<opcode, (outs cls1:$R1),
3735 class AsmCondBinaryRRFa<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3737   : InstRRFa<opcode, (outs cls1:$R1), (ins cls3:$R3, cls2:$R2, imm32zx4:$M4),
3741 class FixedCondBinaryRRFa<CondVariant V, string mnemonic, bits<16> opcode,
3744   : InstRRFa<opcode, (outs cls1:$R1), (ins cls3:$R3, cls2:$R2),
3751 multiclass CondBinaryRRFaPair<string mnemonic, bits<16> opcode,
3755     def "" : CondBinaryRRFa<mnemonic, opcode, cls1, cls2, cls3>;
3756   def Asm : AsmCondBinaryRRFa<mnemonic, opcode, cls1, cls2, cls3>;
3759 class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3761   : InstRIa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
3768 class BinaryRIE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3770   : InstRIEd<opcode, (outs cls:$R1), (ins cls:$R3, imm:$I2),
3786 class CondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
3788   : InstRIEg<opcode, (outs cls:$R1),
3800 class AsmCondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
3802   : InstRIEg<opcode, (outs cls:$R1),
3810 class FixedCondBinaryRIE<CondVariant V, string mnemonic, bits<16> opcode,
3812   : InstRIEg<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
3821 multiclass CondBinaryRIEPair<string mnemonic, bits<16> opcode,
3824     def "" : CondBinaryRIE<mnemonic, opcode, cls, imm>;
3825   def Asm : AsmCondBinaryRIE<mnemonic, opcode, cls, imm>;
3828 class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3830   : InstRILa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
3837 class BinaryRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3839   : InstRSa<opcode, (outs cls:$R1),
3848 class BinaryRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3850   : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, (shift20only $B2, $D2):$BD2),
3865 class BinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls>
3866   : InstRSLb<opcode, (outs cls:$R1),
3872 class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3875   : InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, (mode $B2, $D2, $X2):$XBD2),
3886 class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3888   : InstRXE<opcode, (outs cls:$R1),
3902 class BinaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3905   : InstRXF<opcode, (outs cls1:$R1),
3915 class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3918   : InstRXYa<opcode, (outs cls:$R1),
3943 class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3945   : InstSI<opcode, (outs), (ins (mode $B1, $D1):$BD1, imm:$I2),
3952 class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3954   : InstSIY<opcode, (outs), (ins (mode $B1, $D1):$BD1, imm:$I2),
3972 class BinarySSF<string mnemonic, bits<12> opcode, RegisterOperand cls>
3973   : InstSSF<opcode, (outs cls:$R3),
3979 class BinaryVRIb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3981   : InstVRIb<opcode, (outs tr.op:$V1), (ins imm32zx8:$I2, imm32zx8:$I3),
3987 class BinaryVRIbGeneric<string mnemonic, bits<16> opcode>
3988   : InstVRIb<opcode, (outs VR128:$V1),
3992 class BinaryVRIc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3994   : InstVRIc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, imm32zx16:$I2),
4001 class BinaryVRIcGeneric<string mnemonic, bits<16> opcode>
4002   : InstVRIc<opcode, (outs VR128:$V1),
4006 class BinaryVRIe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4008   : InstVRIe<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx12:$I3),
4016 class BinaryVRIeFloatGeneric<string mnemonic, bits<16> opcode>
4017   : InstVRIe<opcode, (outs VR128:$V1),
4021 class BinaryVRIh<string mnemonic, bits<16> opcode>
4022   : InstVRIh<opcode, (outs VR128:$V1),
4026 class BinaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4028   : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx4:$M5),
4036 class BinaryVRRaFloatGeneric<string mnemonic, bits<16> opcode>
4037   : InstVRRa<opcode, (outs VR128:$V1),
4041 class BinaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4044   : InstVRRb<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
4052 class BinaryExtraVRRb<string mnemonic, bits<16> opcode, bits<4> type = 0>
4053   : InstVRRb<opcode, (outs VR128:$V1), (ins VR128:$V2, VR128:$V3, imm32zx4:$M5),
4058 class BinaryExtraVRRbGeneric<string mnemonic, bits<16> opcode>
4059   : InstVRRb<opcode, (outs VR128:$V1),
4065 multiclass BinaryVRRbSPair<string mnemonic, bits<16> opcode,
4069   def "" : BinaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
4072     def S : BinaryVRRb<mnemonic#"s", opcode, operator_cc, tr1, tr2, type,
4076 class BinaryVRRbSPairGeneric<string mnemonic, bits<16> opcode>
4077   : InstVRRb<opcode, (outs VR128:$V1),
4087 multiclass BinaryExtraVRRbSPair<string mnemonic, bits<16> opcode,
4092     def "" : InstVRRb<opcode, (outs tr1.op:$V1),
4101     def S : BinaryVRRb<mnemonic#"s", opcode, operator_cc, tr1, tr2, type, 1>;
4104 multiclass BinaryExtraVRRbSPairGeneric<string mnemonic, bits<16> opcode> {
4106     def "" : InstVRRb<opcode, (outs VR128:$V1),
4114 class BinaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4117   : InstVRRc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
4128 class BinaryVRRcGeneric<string mnemonic, bits<16> opcode, bits<4> m5 = 0,
4130   : InstVRRc<opcode, (outs VR128:$V1),
4137 class BinaryVRRcFloatGeneric<string mnemonic, bits<16> opcode, bits<4> m6 = 0>
4138   : InstVRRc<opcode, (outs VR128:$V1),
4146 multiclass BinaryVRRcSPair<string mnemonic, bits<16> opcode,
4151   def "" : BinaryVRRc<mnemonic, opcode, operator, tr1, tr2, type,
4154     def S : BinaryVRRc<mnemonic#"s", opcode, operator_cc, tr1, tr2, type,
4158 class BinaryVRRcSPairFloatGeneric<string mnemonic, bits<16> opcode>
4159   : InstVRRc<opcode, (outs VR128:$V1),
4164 class BinaryVRRf<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4166   : InstVRRf<opcode, (outs tr.op:$V1), (ins GR64:$R2, GR64:$R3),
4170 class BinaryVRRi<string mnemonic, bits<16> opcode, RegisterOperand cls>
4171   : InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2, imm32zx4:$M3),
4176 class BinaryVRRk<string mnemonic, bits<16> opcode>
4177   : InstVRRk<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
4180 class BinaryVRSa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4182   : InstVRSa<opcode, (outs tr1.op:$V1),
4190 class BinaryVRSaGeneric<string mnemonic, bits<16> opcode>
4191   : InstVRSa<opcode, (outs VR128:$V1),
4195 class BinaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4197   : InstVRSb<opcode, (outs VR128:$V1),
4206 class BinaryVRSc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4208   : InstVRSc<opcode, (outs GR64:$R1),
4215 class BinaryVRScGeneric<string mnemonic, bits<16> opcode>
4216   : InstVRSc<opcode, (outs GR64:$R1),
4220 class BinaryVRSd<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4222   : InstVRSd<opcode, (outs VR128:$V1),
4230 class BinaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4232   : InstVRX<opcode, (outs VR128:$V1),
4241 class StoreBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
4243   : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4249 class StoreBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
4251   : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4269 class StoreBinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls>
4270   : InstRSLb<opcode, (outs),
4277 class BinaryVSI<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4279   : InstVSI<opcode, (outs VR128:$V1),
4287 class StoreBinaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
4289   : InstVRV<opcode, (outs),
4296 class StoreBinaryVRX<string mnemonic, bits<16> opcode,
4299   : InstVRX<opcode, (outs),
4307 class MemoryBinarySSd<string mnemonic, bits<8> opcode,
4309   : InstSSd<opcode, (outs),
4314 class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
4316   : InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2),
4324 class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4326   : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
4334 class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
4336   : InstRIa<opcode, (outs), (ins cls:$R1, imm:$I2),
4342 class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
4344   : InstRILa<opcode, (outs), (ins cls:$R1, imm:$I2),
4350 class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
4352   : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
4363 class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
4366   : InstRXa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
4376 class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4378   : InstRXE<opcode, (outs), (ins cls:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
4389 class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4392   : InstRXYa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
4415 class CompareRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
4417   : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4423 class CompareRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
4425   : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4441 class CompareSSb<string mnemonic, bits<8> opcode>
4442   : InstSSb<opcode,
4450 class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
4453   : InstSI<opcode, (outs), (ins (mode $B1, $D1):$BD1, imm:$I2),
4460 class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4462   : InstSIL<opcode, (outs), (ins (bdaddr12only $B1, $D1):$BD1, imm:$I2),
4469 class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4472   : InstSIY<opcode, (outs), (ins (mode $B1, $D1):$BD1, imm:$I2),
4491 class CompareVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4493   : InstVRRa<opcode, (outs), (ins tr.op:$V1, tr.op:$V2),
4504 class CompareVRRaGeneric<string mnemonic, bits<16> opcode>
4505   : InstVRRa<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3),
4512 class CompareVRRaFloatGeneric<string mnemonic, bits<16> opcode>
4513   : InstVRRa<opcode, (outs),
4520 class CompareVRRh<string mnemonic, bits<16> opcode>
4521   : InstVRRh<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3),
4526 class TestInherentS<string mnemonic, bits<16> opcode,
4528   : InstS<opcode, (outs), (ins), mnemonic, [(set CC, (operator))]> {
4533 class TestRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4535   : InstRXE<opcode, (outs), (ins cls:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
4541 class TestBinarySIL<string mnemonic, bits<16> opcode,
4543   : InstSIL<opcode, (outs), (ins (bdaddr12only $B1, $D1):$BD1, imm:$I2),
4547 class TestRSL<string mnemonic, bits<16> opcode>
4548   : InstRSLa<opcode, (outs), (ins (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1),
4553 class TestVRRg<string mnemonic, bits<16> opcode>
4554   : InstVRRg<opcode, (outs), (ins VR128:$V1),
4559 class TestExtraVRRg<string mnemonic, bits<16> opcode>
4560   : InstVRRg<opcode, (outs), (ins VR128:$V1, imm32zx16:$I2),
4563 class TestExtraVRIl<string mnemonic, bits<16> opcode>
4564   : InstVRIl<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx16:$I3),
4567 class SideEffectTernarySSc<string mnemonic, bits<8> opcode>
4568   : InstSSc<opcode, (outs), (ins (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1,
4572 class SideEffectTernaryRRFa<string mnemonic, bits<16> opcode,
4575   : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3),
4580 class SideEffectTernaryMemMemRRFa<string mnemonic, bits<16> opcode,
4583   : InstRRFa<opcode, (outs cls1:$R1, cls2:$R2),
4591 class SideEffectTernaryRRFb<string mnemonic, bits<16> opcode,
4594   : InstRRFb<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3),
4599 class SideEffectTernaryMemMemMemRRFb<string mnemonic, bits<16> opcode,
4603   : InstRRFb<opcode, (outs cls1:$R1, cls2:$R2, cls3:$R3),
4611 class SideEffectTernaryRRFc<string mnemonic, bits<16> opcode,
4614   : InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2, imm:$M3),
4617 multiclass SideEffectTernaryRRFcOpt<string mnemonic, bits<16> opcode,
4620   def "" : SideEffectTernaryRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>;
4621   def Opt : SideEffectBinaryRRFc<mnemonic, opcode, cls1, cls2>;
4624 class SideEffectTernaryMemMemRRFc<string mnemonic, bits<16> opcode,
4627   : InstRRFc<opcode, (outs cls1:$R1, cls2:$R2),
4634 multiclass SideEffectTernaryMemMemRRFcOpt<string mnemonic, bits<16> opcode,
4637   def "" : SideEffectTernaryMemMemRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>;
4638   def Opt : SideEffectBinaryMemMemRRFc<mnemonic, opcode, cls1, cls2>;
4641 class SideEffectTernarySSF<string mnemonic, bits<12> opcode,
4643   : InstSSF<opcode, (outs),
4648 class TernaryRRFa<string mnemonic, bits<16> opcode,
4651   : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3, imm32zx4:$M4),
4654 class TernaryRRFb<string mnemonic, bits<16> opcode,
4657   : InstRRFb<opcode, (outs cls1:$R1, cls3:$R3),
4664 class TernaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1,
4666   : InstRRFe<opcode, (outs cls1:$R1),
4670 class TernaryRRD<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4672   : InstRRD<opcode, (outs cls1:$R1), (ins cls2:$R1src, cls2:$R3, cls2:$R2),
4681 class TernaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
4683   : InstRSb<opcode, (outs cls:$R1),
4693 class TernaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
4695   : InstRSYb<opcode, (outs cls:$R1),
4715 class SideEffectTernaryRS<string mnemonic, bits<8> opcode,
4717   : InstRSa<opcode, (outs),
4721 class SideEffectTernaryRSY<string mnemonic, bits<16> opcode,
4723   : InstRSYa<opcode, (outs),
4727 class SideEffectTernaryMemMemRS<string mnemonic, bits<8> opcode,
4729   : InstRSa<opcode, (outs cls1:$R1, cls2:$R3),
4736 class SideEffectTernaryMemMemRSY<string mnemonic, bits<16> opcode,
4738   : InstRSYa<opcode, (outs cls1:$R1, cls2:$R3),
4745 class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4748   : InstRXF<opcode, (outs cls1:$R1),
4761 class TernaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4763   : InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3),
4771 class TernaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4773   : InstVRId<opcode, (outs tr1.op:$V1),
4782 class TernaryVRIi<string mnemonic, bits<16> opcode, RegisterOperand cls>
4783   : InstVRIi<opcode, (outs VR128:$V1),
4787 class TernaryVRIj<string mnemonic, bits<16> opcode>
4788   : InstVRIj<opcode, (outs VR128:$V1),
4792 class TernaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4794   : InstVRRa<opcode, (outs tr1.op:$V1),
4804 class TernaryVRRaFloatGeneric<string mnemonic, bits<16> opcode>
4805   : InstVRRa<opcode, (outs VR128:$V1),
4809 class TernaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4812   : InstVRRb<opcode, (outs tr1.op:$V1),
4825 multiclass TernaryOptVRRbSPair<string mnemonic, bits<16> opcode,
4830   def "" : TernaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
4836     def S : TernaryVRRb<mnemonic#"s", opcode, operator_cc, tr1, tr2, type,
4843 multiclass TernaryOptVRRbSPairGeneric<string mnemonic, bits<16> opcode> {
4845     def "" : InstVRRb<opcode, (outs VR128:$V1),
4853 class TernaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4855   : InstVRRc<opcode, (outs tr1.op:$V1),
4865 class TernaryVRRcInt<string mnemonic, bits<16> opcode,
4868   : InstVRRc<opcode, (outs tr1.op:$V1),
4878 class TernaryVRRcIntGeneric<string mnemonic, bits<16> opcode>
4879   : InstVRRc<opcode, (outs VR128:$V1),
4885 class TernaryVRRcFloat<string mnemonic, bits<16> opcode,
4888   : InstVRRc<opcode, (outs tr1.op:$V1),
4898 class TernaryVRRcFloatGeneric<string mnemonic, bits<16> opcode>
4899   : InstVRRc<opcode, (outs VR128:$V1),
4904 class TernaryVRRd<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4906   : InstVRRd<opcode, (outs tr1.op:$V1),
4916 class TernaryVRRdGeneric<string mnemonic, bits<16> opcode>
4917   : InstVRRd<opcode, (outs VR128:$V1),
4925 multiclass TernaryExtraVRRd<string mnemonic, bits<16> opcode,
4929     def "" : InstVRRd<opcode, (outs tr1.op:$V1),
4940 multiclass TernaryExtraVRRdGeneric<string mnemonic, bits<16> opcode> {
4942     def "" : InstVRRd<opcode, (outs VR128:$V1),
4951 class TernaryVRRe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4954   : InstVRRe<opcode, (outs tr1.op:$V1),
4966 class TernaryVRReFloatGeneric<string mnemonic, bits<16> opcode>
4967   : InstVRRe<opcode, (outs VR128:$V1),
4971 class TernaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4973   : InstVRSb<opcode, (outs tr1.op:$V1),
4984 class TernaryVRRi<string mnemonic, bits<16> opcode, RegisterOperand cls>
4985   : InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2,
4989 class TernaryVRRj<string mnemonic, bits<16> opcode>
4990   : InstVRRj<opcode, (outs VR128:$V1), (ins VR128:$V2,
4994 class TernaryVRSbGeneric<string mnemonic, bits<16> opcode>
4995   : InstVRSb<opcode, (outs VR128:$V1),
5003 class TernaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
5005   : InstVRV<opcode, (outs VR128:$V1),
5014 class TernaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
5016   : InstVRX<opcode, (outs tr1.op:$V1),
5028 class QuaternaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
5030   : InstVRId<opcode, (outs tr1.op:$V1),
5042 class QuaternaryVRIdGeneric<string mnemonic, bits<16> opcode>
5043   : InstVRId<opcode, (outs VR128:$V1),
5051 class QuaternaryVRIf<string mnemonic, bits<16> opcode>
5052   : InstVRIf<opcode, (outs VR128:$V1),
5057 class QuaternaryVRIg<string mnemonic, bits<16> opcode>
5058   : InstVRIg<opcode, (outs VR128:$V1),
5063 class QuaternaryVRIk<string mnemonic, bits<16> opcode,
5065   : InstVRIk<opcode, (outs VR128:$V1),
5073 class QuaternaryVRRd<string mnemonic, bits<16> opcode,
5077   : InstVRRd<opcode, (outs tr1.op:$V1),
5088 class QuaternaryVRRdGeneric<string mnemonic, bits<16> opcode>
5089   : InstVRRd<opcode, (outs VR128:$V1),
5096 multiclass QuaternaryOptVRRdSPair<string mnemonic, bits<16> opcode,
5101   def "" : QuaternaryVRRd<mnemonic, opcode, operator,
5108     def S : QuaternaryVRRd<mnemonic#"s", opcode, operator_cc,
5116 multiclass QuaternaryOptVRRdSPairGeneric<string mnemonic, bits<16> opcode> {
5118     def "" : QuaternaryVRRdGeneric<mnemonic, opcode>;
5124 class SideEffectQuaternaryRRFa<string mnemonic, bits<16> opcode,
5127   : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3, imm32zx4:$M4),
5130 multiclass SideEffectQuaternaryRRFaOptOpt<string mnemonic, bits<16> opcode,
5134   def "" : SideEffectQuaternaryRRFa<mnemonic, opcode, cls1, cls2, cls3>;
5135   def Opt : SideEffectTernaryRRFa<mnemonic, opcode, cls1, cls2, cls3>;
5136   def OptOpt : SideEffectBinaryRRFa<mnemonic, opcode, cls1, cls2>;
5139 class SideEffectQuaternaryRRFb<string mnemonic, bits<16> opcode,
5142   : InstRRFb<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3, imm32zx4:$M4),
5145 multiclass SideEffectQuaternaryRRFbOpt<string mnemonic, bits<16> opcode,
5149   def "" : SideEffectQuaternaryRRFb<mnemonic, opcode, cls1, cls2, cls3>;
5150   def Opt : SideEffectTernaryRRFb<mnemonic, opcode, cls1, cls2, cls3>;
5153 class SideEffectQuaternarySSe<string mnemonic, bits<8> opcode,
5155   : InstSSe<opcode, (outs),
5160 class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
5162   : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, (mode $B2, $D2):$BD2),
5169 class CmpSwapRRE<string mnemonic, bits<16> opcode,
5171   : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
5179 class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
5181   : InstRSa<opcode, (outs cls:$R1),
5191 class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
5193   : InstRSYa<opcode, (outs cls:$R1),
5213 class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
5215   : InstRIEf<opcode, (outs cls1:$R1),
5223 class PrefetchRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator>
5224   : InstRXYb<opcode, (outs),
5229 class PrefetchRILPC<string mnemonic, bits<12> opcode,
5231   : InstRILc<opcode, (outs), (ins imm32zx4_timm:$M1, pcrel32:$RI2),
5240 class BranchPreloadSMI<string mnemonic, bits<8> opcode>
5241   : InstSMI<opcode, (outs),
5246 class BranchPreloadMII<string mnemonic, bits<8> opcode>
5247   : InstMII<opcode, (outs),
5633 multiclass BinaryRXYAndPseudo<string mnemonic, bits<16> opcode,
5637   def "" : BinaryRXY<mnemonic, opcode, operator, cls, load, bytes, mode> {
5663 multiclass BinaryRXEAndPseudo<string mnemonic, bits<16> opcode,
5666   def "" : BinaryRXE<mnemonic, opcode, operator, cls, load, bytes> {
5673 multiclass TernaryRXFAndPseudo<string mnemonic, bits<16> opcode,
5677   def "" : TernaryRXF<mnemonic, opcode, operator, cls1, cls2, load, bytes> {
5684 multiclass CondUnaryRSYPairAndMemFold<string mnemonic, bits<16> opcode,
5688   defm "" : CondUnaryRSYPair<mnemonic, opcode, operator, cls, bytes, mode>;
5706 multiclass MemorySS<string mnemonic, bits<8> opcode, SDPatternOperator memop> {
5707   def "" : SideEffectBinarySSa<mnemonic, opcode>;
5721 multiclass CompareMemorySS<string mnemonic, bits<8> opcode,
5723   def "" : SideEffectBinarySSa<mnemonic, opcode>;
5741 multiclass StringRRE<string mnemonic, bits<16> opcode,
5744     def "" : SideEffectBinaryMemMemRRE<mnemonic, opcode, GR64, GR64>;