1//===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// 11// PowerPC instruction formats 12 13class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> 14 : Instruction { 15 field bits<32> Inst; 16 field bits<32> SoftFail = 0; 17 let Size = 4; 18 19 bit PPC64 = 0; // Default value, override with isPPC64 20 21 let Namespace = "PPC"; 22 let Inst{0-5} = opcode; 23 let OutOperandList = OOL; 24 let InOperandList = IOL; 25 let AsmString = asmstr; 26 let Itinerary = itin; 27 28 bits<1> PPC970_First = 0; 29 bits<1> PPC970_Single = 0; 30 bits<1> PPC970_Cracked = 0; 31 bits<3> PPC970_Unit = 0; 32 33 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 34 /// these must be reflected there! See comments there for what these are. 35 let TSFlags{0} = PPC970_First; 36 let TSFlags{1} = PPC970_Single; 37 let TSFlags{2} = PPC970_Cracked; 38 let TSFlags{5-3} = PPC970_Unit; 39 40 // Indicate that this instruction is of type X-Form Load or Store 41 bits<1> XFormMemOp = 0; 42 let TSFlags{6} = XFormMemOp; 43 44 // Indicate that this instruction is prefixed. 45 bits<1> Prefixed = 0; 46 let TSFlags{7} = Prefixed; 47 48 // Indicate that this instruction produces a result that is sign extended from 49 // 32 bits to 64 bits. 50 bits<1> SExt32To64 = 0; 51 let TSFlags{8} = SExt32To64; 52 53 // Indicate that this instruction produces a result that is zero extended from 54 // 32 bits to 64 bits. 55 bits<1> ZExt32To64 = 0; 56 let TSFlags{9} = ZExt32To64; 57 58 // Indicate that this instruction takes a register+immediate memory operand. 59 bits<1> MemriOp = 0; 60 let TSFlags{10} = MemriOp; 61 62 // Fields used for relation models. 63 string BaseName = ""; 64 65 // For cases where multiple instruction definitions really represent the 66 // same underlying instruction but with one definition for 64-bit arguments 67 // and one for 32-bit arguments, this bit breaks the degeneracy between 68 // the two forms and allows TableGen to generate mapping tables. 69 bit Interpretation64Bit = 0; 70} 71 72class PPC970_DGroup_First { bits<1> PPC970_First = 1; } 73class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; } 74class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; } 75class PPC970_MicroCode; 76 77class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; } 78class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; } 79class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; } 80class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; } 81class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; } 82class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; } 83class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; } 84class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; } 85 86class XFormMemOp { bits<1> XFormMemOp = 1; } 87class SExt32To64 { bits<1> SExt32To64 = 1; } 88class ZExt32To64 { bits<1> ZExt32To64 = 1; } 89class MemriOp { bits<1> MemriOp = 1; } 90 91// Two joined instructions; used to emit two adjacent instructions as one. 92// The itinerary from the first instruction is used for scheduling and 93// classification. 94class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr, 95 InstrItinClass itin> 96 : Instruction { 97 field bits<64> Inst; 98 field bits<64> SoftFail = 0; 99 let Size = 8; 100 101 bit PPC64 = 0; // Default value, override with isPPC64 102 103 let Namespace = "PPC"; 104 let Inst{0-5} = opcode1; 105 let Inst{32-37} = opcode2; 106 let OutOperandList = OOL; 107 let InOperandList = IOL; 108 let AsmString = asmstr; 109 let Itinerary = itin; 110 111 bits<1> PPC970_First = 0; 112 bits<1> PPC970_Single = 0; 113 bits<1> PPC970_Cracked = 0; 114 bits<3> PPC970_Unit = 0; 115 116 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 117 /// these must be reflected there! See comments there for what these are. 118 let TSFlags{0} = PPC970_First; 119 let TSFlags{1} = PPC970_Single; 120 let TSFlags{2} = PPC970_Cracked; 121 let TSFlags{5-3} = PPC970_Unit; 122 123 // Fields used for relation models. 124 string BaseName = ""; 125 bit Interpretation64Bit = 0; 126} 127 128// Base class for all X-Form memory instructions 129class IXFormMemOp<bits<6> opcode, dag OOL, dag IOL, string asmstr, 130 InstrItinClass itin> 131 :I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp; 132 133// 1.7.1 I-Form 134class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr, 135 InstrItinClass itin, list<dag> pattern> 136 : I<opcode, OOL, IOL, asmstr, itin> { 137 let Pattern = pattern; 138 bits<24> LI; 139 140 let Inst{6-29} = LI; 141 let Inst{30} = aa; 142 let Inst{31} = lk; 143} 144 145// 1.7.2 B-Form 146class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr> 147 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 148 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 149 bits<3> CR; 150 bits<14> BD; 151 152 bits<5> BI; 153 let BI{0-1} = BIBO{5-6}; 154 let BI{2-4} = CR{0-2}; 155 156 let Inst{6-10} = BIBO{4-0}; 157 let Inst{11-15} = BI; 158 let Inst{16-29} = BD; 159 let Inst{30} = aa; 160 let Inst{31} = lk; 161} 162 163class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL, 164 string asmstr> 165 : BForm<opcode, aa, lk, OOL, IOL, asmstr> { 166 let BIBO{4-0} = bo; 167 let BIBO{6-5} = 0; 168 let CR = 0; 169} 170 171class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk, 172 dag OOL, dag IOL, string asmstr> 173 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 174 bits<14> BD; 175 176 let Inst{6-10} = bo; 177 let Inst{11-15} = bi; 178 let Inst{16-29} = BD; 179 let Inst{30} = aa; 180 let Inst{31} = lk; 181} 182 183class BForm_3<bits<6> opcode, bit aa, bit lk, 184 dag OOL, dag IOL, string asmstr> 185 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 186 bits<5> BO; 187 bits<5> BI; 188 bits<14> BD; 189 190 let Inst{6-10} = BO; 191 let Inst{11-15} = BI; 192 let Inst{16-29} = BD; 193 let Inst{30} = aa; 194 let Inst{31} = lk; 195} 196 197class BForm_3_at<bits<6> opcode, bit aa, bit lk, 198 dag OOL, dag IOL, string asmstr> 199 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 200 bits<5> BO; 201 bits<2> at; 202 bits<5> BI; 203 bits<14> BD; 204 205 let Inst{6-8} = BO{4-2}; 206 let Inst{9-10} = at; 207 let Inst{11-15} = BI; 208 let Inst{16-29} = BD; 209 let Inst{30} = aa; 210 let Inst{31} = lk; 211} 212 213class 214BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk, 215 dag OOL, dag IOL, string asmstr> 216 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 217 bits<5> BI; 218 bits<14> BD; 219 220 let Inst{6-10} = bo; 221 let Inst{11-15} = BI; 222 let Inst{16-29} = BD; 223 let Inst{30} = aa; 224 let Inst{31} = lk; 225} 226 227// 1.7.3 SC-Form 228class SCForm<bits<6> opcode, bits<1> xo1, bits<1> xo2, 229 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 230 list<dag> pattern> 231 : I<opcode, OOL, IOL, asmstr, itin> { 232 bits<7> LEV; 233 234 let Pattern = pattern; 235 236 let Inst{20-26} = LEV; 237 let Inst{30} = xo1; 238 let Inst{31} = xo2; 239} 240 241// 1.7.4 D-Form 242class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr, 243 InstrItinClass itin, list<dag> pattern> 244 : I<opcode, OOL, IOL, asmstr, itin> { 245 bits<5> RST; 246 bits<5> RA; 247 bits<16> D; 248 249 let Pattern = pattern; 250 251 let Inst{6-10} = RST; 252 let Inst{11-15} = RA; 253 let Inst{16-31} = D; 254} 255 256class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 257 InstrItinClass itin, list<dag> pattern> 258 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern>, MemriOp { 259} 260 261class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 262 InstrItinClass itin, list<dag> pattern> 263 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> { 264 265 // Even though ADDIC_rec does not really have an RC bit, provide 266 // the declaration of one here so that isRecordForm has something to set. 267 bit RC = 0; 268} 269 270class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr, 271 InstrItinClass itin, list<dag> pattern> 272 : I<opcode, OOL, IOL, asmstr, itin> { 273 bits<5> RST; 274 bits<16> D; 275 276 let Pattern = pattern; 277 278 let Inst{6-10} = RST; 279 let Inst{11-15} = 0; 280 let Inst{16-31} = D; 281} 282 283class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr, 284 InstrItinClass itin, list<dag> pattern> 285 : I<opcode, OOL, IOL, asmstr, itin> { 286 bits<5> RA; 287 bits<5> RST; 288 bits<16> D; 289 290 let Pattern = pattern; 291 292 let Inst{6-10} = RST; 293 let Inst{11-15} = RA; 294 let Inst{16-31} = D; 295} 296 297class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr, 298 InstrItinClass itin, list<dag> pattern> 299 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 300 let RST = 0; 301 let RA = 0; 302 let D = 0; 303 let MemriOp = 0; 304} 305 306class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL, 307 string asmstr, InstrItinClass itin, 308 list<dag> pattern> 309 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> { 310 let RST = R; 311 let RA = R; 312 let D = 0; 313} 314 315class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 316 dag OOL, dag IOL, string asmstr, 317 InstrItinClass itin, list<dag> pattern> 318 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 319 bits<5> RST; 320 bits<5> RA; 321 bits<16> D; 322 323 let Pattern = pattern; 324 bits<24> LI; 325 326 let Inst{6-29} = LI; 327 let Inst{30} = aa; 328 let Inst{31} = lk; 329 330 let Inst{38-42} = RST; 331 let Inst{43-47} = RA; 332 let Inst{48-63} = D; 333} 334 335// This is used to emit BL8+NOP. 336class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 337 dag OOL, dag IOL, string asmstr, 338 InstrItinClass itin, list<dag> pattern> 339 : IForm_and_DForm_1<opcode1, aa, lk, opcode2, 340 OOL, IOL, asmstr, itin, pattern> { 341 let RST = 0; 342 let RA = 0; 343 let D = 0; 344} 345 346class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 347 InstrItinClass itin> 348 : I<opcode, OOL, IOL, asmstr, itin> { 349 bits<3> BF; 350 bits<1> L; 351 bits<5> RA; 352 bits<16> D; 353 354 let Inst{6-8} = BF; 355 let Inst{9} = 0; 356 let Inst{10} = L; 357 let Inst{11-15} = RA; 358 let Inst{16-31} = D; 359} 360 361class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 362 InstrItinClass itin> 363 : DForm_5<opcode, OOL, IOL, asmstr, itin> { 364 let L = PPC64; 365} 366 367class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr, 368 InstrItinClass itin> 369 : DForm_5<opcode, OOL, IOL, asmstr, itin>; 370 371class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 372 InstrItinClass itin> 373 : DForm_6<opcode, OOL, IOL, asmstr, itin> { 374 let L = PPC64; 375} 376 377 378// 1.7.5 DS-Form 379class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 380 InstrItinClass itin, list<dag> pattern> 381 : I<opcode, OOL, IOL, asmstr, itin>, MemriOp { 382 bits<5> RST; 383 bits<5> RA; 384 bits<14> D; 385 386 let Pattern = pattern; 387 388 let Inst{6-10} = RST; 389 let Inst{11-15} = RA; 390 let Inst{16-29} = D; 391 let Inst{30-31} = xo; 392} 393 394// ISA V3.0B 1.6.6 DX-Form 395class DXForm<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 396 InstrItinClass itin, list<dag> pattern> 397 : I<opcode, OOL, IOL, asmstr, itin> { 398 bits<5> RT; 399 bits<16> D; 400 401 let Pattern = pattern; 402 403 let Inst{6-10} = RT; 404 let Inst{11-15} = D{5-1}; // d1 405 let Inst{16-25} = D{15-6}; // d0 406 let Inst{26-30} = xo; 407 let Inst{31} = D{0}; // d2 408} 409 410// DQ-Form: [PO T RA DQ TX XO] or [PO S RA DQ SX XO] 411class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 412 string asmstr, InstrItinClass itin, list<dag> pattern> 413 : I<opcode, OOL, IOL, asmstr, itin>, MemriOp { 414 bits<6> XT; 415 bits<5> RA; 416 bits<12> DQ; 417 418 let Pattern = pattern; 419 420 let Inst{6-10} = XT{4-0}; 421 let Inst{11-15} = RA; 422 let Inst{16-27} = DQ; 423 let Inst{28} = XT{5}; 424 let Inst{29-31} = xo; 425} 426 427class DQForm_RTp5_RA17_MEM<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 428 string asmstr, InstrItinClass itin, 429 list<dag> pattern> 430 : I<opcode, OOL, IOL, asmstr, itin>, MemriOp { 431 bits<5> RTp; 432 bits<5> RA; 433 bits<12> DQ; 434 let Pattern = pattern; 435 436 let Inst{6-10} = RTp{4-0}; 437 let Inst{11-15} = RA; 438 let Inst{16-27} = DQ; 439 let Inst{28-31} = xo; 440} 441 442// 1.7.6 X-Form 443class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 444 InstrItinClass itin, list<dag> pattern> 445 : I<opcode, OOL, IOL, asmstr, itin> { 446 bits<5> RST; 447 bits<5> RA; 448 bits<5> RB; 449 450 let Pattern = pattern; 451 452 bit RC = 0; // set by isRecordForm 453 454 let Inst{6-10} = RST; 455 let Inst{11-15} = RA; 456 let Inst{16-20} = RB; 457 let Inst{21-30} = xo; 458 let Inst{31} = RC; 459} 460 461class XForm_base_r3xo_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 462 string asmstr, InstrItinClass itin, 463 list<dag> pattern> 464 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>, XFormMemOp; 465 466class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr, 467 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> { 468 let RST = 0; 469} 470 471class XForm_tlbilx<bits<10> xo, dag OOL, dag IOL, string asmstr, 472 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> { 473 bits<5> T; 474 let RST = T; 475} 476 477class XForm_attn<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 478 InstrItinClass itin> 479 : I<opcode, OOL, IOL, asmstr, itin> { 480 let Inst{21-30} = xo; 481} 482 483// This is the same as XForm_base_r3xo, but the first two operands are swapped 484// when code is emitted. 485class XForm_base_r3xo_swapped 486 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 487 InstrItinClass itin> 488 : I<opcode, OOL, IOL, asmstr, itin> { 489 bits<5> RA; 490 bits<5> RST; 491 bits<5> RB; 492 493 bit RC = 0; // set by isRecordForm 494 495 let Inst{6-10} = RST; 496 let Inst{11-15} = RA; 497 let Inst{16-20} = RB; 498 let Inst{21-30} = xo; 499 let Inst{31} = RC; 500} 501 502 503class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 504 InstrItinClass itin, list<dag> pattern> 505 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 506 507class XForm_1_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 508 InstrItinClass itin, list<dag> pattern> 509 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 510 511class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 512 InstrItinClass itin, list<dag> pattern> 513 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 514 let RST = 0; 515} 516 517class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 518 InstrItinClass itin, list<dag> pattern> 519 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 520 let RA = 0; 521 let RB = 0; 522} 523 524class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 525 InstrItinClass itin, list<dag> pattern> 526 : I<opcode, OOL, IOL, asmstr, itin> { 527 bits<5> RST; 528 bits<5> RA; 529 bits<1> WS; 530 531 let Pattern = pattern; 532 533 let Inst{6-10} = RST; 534 let Inst{11-15} = RA; 535 let Inst{20} = WS; 536 let Inst{21-30} = xo; 537 let Inst{31} = 0; 538} 539 540class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 541 InstrItinClass itin, list<dag> pattern> 542 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 543 let Pattern = pattern; 544} 545 546class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 547 InstrItinClass itin, list<dag> pattern> 548 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 549 550class XForm_8_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 551 InstrItinClass itin, list<dag> pattern> 552 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 553 554class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 555 InstrItinClass itin, list<dag> pattern> 556 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 557 let Pattern = pattern; 558} 559 560class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 561 InstrItinClass itin, list<dag> pattern> 562 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 563 let RB = 0; 564 let Pattern = pattern; 565} 566 567class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 568 InstrItinClass itin> 569 : I<opcode, OOL, IOL, asmstr, itin> { 570 bits<3> BF; 571 bits<1> L; 572 bits<5> RA; 573 bits<5> RB; 574 575 let Inst{6-8} = BF; 576 let Inst{9} = 0; 577 let Inst{10} = L; 578 let Inst{11-15} = RA; 579 let Inst{16-20} = RB; 580 let Inst{21-30} = xo; 581 let Inst{31} = 0; 582} 583 584class XForm_icbt<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 585 InstrItinClass itin> 586 : I<opcode, OOL, IOL, asmstr, itin> { 587 bits<4> CT; 588 bits<5> RA; 589 bits<5> RB; 590 591 let Inst{6} = 0; 592 let Inst{7-10} = CT; 593 let Inst{11-15} = RA; 594 let Inst{16-20} = RB; 595 let Inst{21-30} = xo; 596 let Inst{31} = 0; 597} 598 599class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 600 InstrItinClass itin> 601 : I<opcode, OOL, IOL, asmstr, itin> { 602 bits<5> RS; 603 bits<4> SR; 604 605 let Inst{6-10} = RS; 606 let Inst{12-15} = SR; 607 let Inst{21-30} = xo; 608} 609 610class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 611 InstrItinClass itin> 612 : I<opcode, OOL, IOL, asmstr, itin> { 613 bits<5> MO; 614 615 let Inst{6-10} = MO; 616 let Inst{21-30} = xo; 617} 618 619class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 620 InstrItinClass itin> 621 : I<opcode, OOL, IOL, asmstr, itin> { 622 bits<5> RS; 623 bits<5> RB; 624 625 let Inst{6-10} = RS; 626 let Inst{16-20} = RB; 627 let Inst{21-30} = xo; 628} 629 630class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 631 InstrItinClass itin> 632 : I<opcode, OOL, IOL, asmstr, itin> { 633 bits<5> RS; 634 bits<1> L; 635 636 let Inst{6-10} = RS; 637 let Inst{15} = L; 638 let Inst{21-30} = xo; 639} 640 641class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 642 InstrItinClass itin> 643 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 644 let L = PPC64; 645} 646 647class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 648 InstrItinClass itin> 649 : I<opcode, OOL, IOL, asmstr, itin> { 650 bits<3> BF; 651 bits<5> RA; 652 bits<5> RB; 653 654 let Inst{6-8} = BF; 655 let Inst{9-10} = 0; 656 let Inst{11-15} = RA; 657 let Inst{16-20} = RB; 658 let Inst{21-30} = xo; 659 let Inst{31} = 0; 660} 661 662class XForm_17a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 663 InstrItinClass itin, list<dag> pattern> 664 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin > { 665 let RA = 0; 666 let Pattern = pattern; 667} 668 669class XForm_18<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 670 InstrItinClass itin, list<dag> pattern> 671 : I<opcode, OOL, IOL, asmstr, itin> { 672 bits<5> FRT; 673 bits<5> FRA; 674 bits<5> FRB; 675 676 let Pattern = pattern; 677 678 let Inst{6-10} = FRT; 679 let Inst{11-15} = FRA; 680 let Inst{16-20} = FRB; 681 let Inst{21-30} = xo; 682 let Inst{31} = 0; 683} 684 685class XForm_19<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 686 InstrItinClass itin, list<dag> pattern> 687 : XForm_18<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 688 let FRA = 0; 689} 690 691class XForm_20<bits<6> opcode, bits<6> xo, dag OOL, dag IOL, string asmstr, 692 InstrItinClass itin, list<dag> pattern> 693 : I<opcode, OOL, IOL, asmstr, itin> { 694 bits<5> FRT; 695 bits<5> FRA; 696 bits<5> FRB; 697 bits<4> tttt; 698 699 let Pattern = pattern; 700 701 let Inst{6-10} = FRT; 702 let Inst{11-15} = FRA; 703 let Inst{16-20} = FRB; 704 let Inst{21-24} = tttt; 705 let Inst{25-30} = xo; 706 let Inst{31} = 0; 707} 708 709class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 710 InstrItinClass itin, list<dag> pattern> 711 : I<opcode, OOL, IOL, asmstr, itin> { 712 let Pattern = pattern; 713 let Inst{6-10} = 31; 714 let Inst{11-15} = 0; 715 let Inst{16-20} = 0; 716 let Inst{21-30} = xo; 717 let Inst{31} = 0; 718} 719 720class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 721 string asmstr, InstrItinClass itin, list<dag> pattern> 722 : I<opcode, OOL, IOL, asmstr, itin> { 723 bits<2> L; 724 725 let Pattern = pattern; 726 let Inst{6-8} = 0; 727 let Inst{9-10} = L; 728 let Inst{11-15} = 0; 729 let Inst{16-20} = 0; 730 let Inst{21-30} = xo; 731 let Inst{31} = 0; 732} 733 734class XForm_IMM2_IMM2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 735 string asmstr, InstrItinClass itin, list<dag> pattern> 736 : I<opcode, OOL, IOL, asmstr, itin> { 737 bits<2> L; 738 bits<2> PL; 739 740 let Pattern = pattern; 741 let Inst{6-8} = 0; 742 let Inst{9-10} = L; 743 let Inst{11-13} = 0; 744 let Inst{14-15} = PL; 745 let Inst{16-20} = 0; 746 let Inst{21-30} = xo; 747 let Inst{31} = 0; 748} 749 750class XForm_IMM3_IMM2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 751 string asmstr, InstrItinClass itin, list<dag> pattern> 752 : I<opcode, OOL, IOL, asmstr, itin> { 753 bits<3> L; 754 bits<2> SC; 755 756 let Pattern = pattern; 757 let Inst{6-7} = 0; 758 let Inst{8-10} = L; 759 let Inst{11-13} = 0; 760 let Inst{14-15} = SC; 761 let Inst{16-20} = 0; 762 let Inst{21-30} = xo; 763 let Inst{31} = 0; 764} 765 766class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 767 string asmstr, InstrItinClass itin, list<dag> pattern> 768 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 769 let L = 0; 770} 771 772class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 773 InstrItinClass itin, list<dag> pattern> 774 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 775} 776 777class XForm_25_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 778 string asmstr, InstrItinClass itin, list<dag> pattern> 779 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 780} 781 782// [PO RT /// RB XO RC] 783class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 784 InstrItinClass itin, list<dag> pattern> 785 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 786 let RA = 0; 787} 788 789class XForm_28_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 790 string asmstr, InstrItinClass itin, list<dag> pattern> 791 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 792} 793 794class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 795 InstrItinClass itin, list<dag> pattern> 796 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 797} 798 799// This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of 800// numbers presumably relates to some document, but I haven't found it. 801class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 802 InstrItinClass itin, list<dag> pattern> 803 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 804 let Pattern = pattern; 805 806 bit RC = 0; // set by isRecordForm 807 808 let Inst{6-10} = RST; 809 let Inst{11-20} = 0; 810 let Inst{21-30} = xo; 811 let Inst{31} = RC; 812} 813class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 814 InstrItinClass itin, list<dag> pattern> 815 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 816 let Pattern = pattern; 817 bits<5> FM; 818 819 bit RC = 0; // set by isRecordForm 820 821 let Inst{6-10} = FM; 822 let Inst{11-20} = 0; 823 let Inst{21-30} = xo; 824 let Inst{31} = RC; 825} 826 827class XForm_44<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 828 InstrItinClass itin> 829 : I<opcode, OOL, IOL, asmstr, itin> { 830 bits<5> RT; 831 bits<3> BFA; 832 833 let Inst{6-10} = RT; 834 let Inst{11-13} = BFA; 835 let Inst{14-15} = 0; 836 let Inst{16-20} = 0; 837 let Inst{21-30} = xo; 838 let Inst{31} = 0; 839} 840 841class XForm_45<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 842 InstrItinClass itin> 843 : I<opcode, OOL, IOL, asmstr, itin> { 844 bits<5> RT; 845 bits<2> L; 846 847 let Inst{6-10} = RT; 848 let Inst{11-13} = 0; 849 let Inst{14-15} = L; 850 let Inst{16-20} = 0; 851 let Inst{21-30} = xo; 852 let Inst{31} = 0; 853} 854 855class X_FRT5_XO2_XO3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, bits<10> xo, 856 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 857 list<dag> pattern> 858 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 859 let Pattern = pattern; 860 861 let Inst{6-10} = RST; 862 let Inst{11-12} = xo1; 863 let Inst{13-15} = xo2; 864 let Inst{16-20} = 0; 865 let Inst{21-30} = xo; 866 let Inst{31} = 0; 867} 868 869class X_FRT5_XO2_XO3_FRB5_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 870 bits<10> xo, dag OOL, dag IOL, string asmstr, 871 InstrItinClass itin, list<dag> pattern> 872 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 873 let Pattern = pattern; 874 bits<5> FRB; 875 876 let Inst{6-10} = RST; 877 let Inst{11-12} = xo1; 878 let Inst{13-15} = xo2; 879 let Inst{16-20} = FRB; 880 let Inst{21-30} = xo; 881 let Inst{31} = 0; 882} 883 884class X_FRT5_XO2_XO3_DRM3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 885 bits<10> xo, dag OOL, dag IOL, string asmstr, 886 InstrItinClass itin, list<dag> pattern> 887 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 888 let Pattern = pattern; 889 bits<3> DRM; 890 891 let Inst{6-10} = RST; 892 let Inst{11-12} = xo1; 893 let Inst{13-15} = xo2; 894 let Inst{16-17} = 0; 895 let Inst{18-20} = DRM; 896 let Inst{21-30} = xo; 897 let Inst{31} = 0; 898} 899 900class X_FRT5_XO2_XO3_RM2_X10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 901 bits<10> xo, dag OOL, dag IOL, string asmstr, 902 InstrItinClass itin, list<dag> pattern> 903 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 904 let Pattern = pattern; 905 bits<2> RM; 906 907 let Inst{6-10} = RST; 908 let Inst{11-12} = xo1; 909 let Inst{13-15} = xo2; 910 let Inst{16-18} = 0; 911 let Inst{19-20} = RM; 912 let Inst{21-30} = xo; 913 let Inst{31} = 0; 914} 915 916 917class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 918 InstrItinClass itin, list<dag> pattern> 919 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 920 let RST = 0; 921 let RA = 0; 922 let RB = 0; 923} 924 925class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 926 InstrItinClass itin, list<dag> pattern> 927 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 928 let RST = 0; 929 let RA = 0; 930} 931 932class XForm_htm0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 933 string asmstr, InstrItinClass itin> 934 : I<opcode, OOL, IOL, asmstr, itin> { 935 bit R; 936 937 bit RC = 1; 938 939 let Inst{6-9} = 0; 940 let Inst{10} = R; 941 let Inst{11-20} = 0; 942 let Inst{21-30} = xo; 943 let Inst{31} = RC; 944} 945 946class XForm_htm1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 947 string asmstr, InstrItinClass itin> 948 : I<opcode, OOL, IOL, asmstr, itin> { 949 bit A; 950 951 bit RC = 1; 952 953 let Inst{6} = A; 954 let Inst{7-20} = 0; 955 let Inst{21-30} = xo; 956 let Inst{31} = RC; 957} 958 959class XForm_htm2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 960 InstrItinClass itin> 961 : I<opcode, OOL, IOL, asmstr, itin> { 962 bit L; 963 964 bit RC = 0; // set by isRecordForm 965 966 let Inst{7-9} = 0; 967 let Inst{10} = L; 968 let Inst{11-20} = 0; 969 let Inst{21-30} = xo; 970 let Inst{31} = RC; 971} 972 973class XForm_htm3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 974 InstrItinClass itin> 975 : I<opcode, OOL, IOL, asmstr, itin> { 976 bits<3> BF; 977 978 bit RC = 0; 979 980 let Inst{6-8} = BF; 981 let Inst{9-20} = 0; 982 let Inst{21-30} = xo; 983 let Inst{31} = RC; 984} 985 986// [PO RT RA RB XO /] 987class X_BF3_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 988 string asmstr, InstrItinClass itin, list<dag> pattern> 989 : I<opcode, OOL, IOL, asmstr, itin> { 990 bits<3> BF; 991 bits<1> L; 992 bits<5> RA; 993 bits<5> RB; 994 995 let Pattern = pattern; 996 997 let Inst{6-8} = BF; 998 let Inst{9} = 0; 999 let Inst{10} = L; 1000 let Inst{11-15} = RA; 1001 let Inst{16-20} = RB; 1002 let Inst{21-30} = xo; 1003 let Inst{31} = 0; 1004} 1005 1006// Same as XForm_17 but with GPR's and new naming convention 1007class X_BF3_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1008 string asmstr, InstrItinClass itin, list<dag> pattern> 1009 : I<opcode, OOL, IOL, asmstr, itin> { 1010 bits<3> BF; 1011 bits<5> RA; 1012 bits<5> RB; 1013 1014 let Pattern = pattern; 1015 1016 let Inst{6-8} = BF; 1017 let Inst{9-10} = 0; 1018 let Inst{11-15} = RA; 1019 let Inst{16-20} = RB; 1020 let Inst{21-30} = xo; 1021 let Inst{31} = 0; 1022} 1023 1024// e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RO] 1025class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL, 1026 string asmstr, InstrItinClass itin, list<dag> pattern> 1027 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1028 let RA = xo2; 1029} 1030 1031class X_BF3_DCMX7_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1032 string asmstr, InstrItinClass itin, list<dag> pattern> 1033 : I<opcode, OOL, IOL, asmstr, itin> { 1034 bits<3> BF; 1035 bits<7> DCMX; 1036 bits<5> VB; 1037 1038 let Pattern = pattern; 1039 1040 let Inst{6-8} = BF; 1041 let Inst{9-15} = DCMX; 1042 let Inst{16-20} = VB; 1043 let Inst{21-30} = xo; 1044 let Inst{31} = 0; 1045} 1046 1047class X_RD6_IMM8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1048 string asmstr, InstrItinClass itin, list<dag> pattern> 1049 : I<opcode, OOL, IOL, asmstr, itin> { 1050 bits<6> XT; 1051 bits<8> IMM8; 1052 1053 let Pattern = pattern; 1054 1055 let Inst{6-10} = XT{4-0}; 1056 let Inst{11-12} = 0; 1057 let Inst{13-20} = IMM8; 1058 let Inst{21-30} = xo; 1059 let Inst{31} = XT{5}; 1060} 1061 1062// XForm_base_r3xo for instructions such as P9 atomics where we don't want 1063// to specify an SDAG pattern for matching. 1064class X_RD5_RS5_IM5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1065 string asmstr, InstrItinClass itin> 1066 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, []> { 1067} 1068 1069class X_BF3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1070 InstrItinClass itin> 1071 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin> { 1072 let RA = 0; 1073 let RB = 0; 1074} 1075 1076// [PO /// L RA RB XO /] 1077class X_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1078 string asmstr, InstrItinClass itin, list<dag> pattern> 1079 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 1080 let BF = 0; 1081 let Pattern = pattern; 1082 1083 bit RC = 0; 1084 let Inst{31} = RC; 1085} 1086 1087// XX*-Form (VSX) 1088class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1089 InstrItinClass itin, list<dag> pattern> 1090 : I<opcode, OOL, IOL, asmstr, itin> { 1091 bits<6> XT; 1092 bits<5> RA; 1093 bits<5> RB; 1094 1095 let Pattern = pattern; 1096 1097 let Inst{6-10} = XT{4-0}; 1098 let Inst{11-15} = RA; 1099 let Inst{16-20} = RB; 1100 let Inst{21-30} = xo; 1101 let Inst{31} = XT{5}; 1102} 1103 1104class XX1Form_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1105 string asmstr, InstrItinClass itin, list<dag> pattern> 1106 : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern>, XFormMemOp; 1107 1108class XX1_RS6_RD5_XO<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1109 string asmstr, InstrItinClass itin, list<dag> pattern> 1110 : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1111 let RB = 0; 1112} 1113 1114class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1115 InstrItinClass itin, list<dag> pattern> 1116 : I<opcode, OOL, IOL, asmstr, itin> { 1117 bits<6> XT; 1118 bits<6> XB; 1119 1120 let Pattern = pattern; 1121 1122 let Inst{6-10} = XT{4-0}; 1123 let Inst{11-15} = 0; 1124 let Inst{16-20} = XB{4-0}; 1125 let Inst{21-29} = xo; 1126 let Inst{30} = XB{5}; 1127 let Inst{31} = XT{5}; 1128} 1129 1130class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1131 InstrItinClass itin, list<dag> pattern> 1132 : I<opcode, OOL, IOL, asmstr, itin> { 1133 bits<3> CR; 1134 bits<6> XB; 1135 1136 let Pattern = pattern; 1137 1138 let Inst{6-8} = CR; 1139 let Inst{9-15} = 0; 1140 let Inst{16-20} = XB{4-0}; 1141 let Inst{21-29} = xo; 1142 let Inst{30} = XB{5}; 1143 let Inst{31} = 0; 1144} 1145 1146class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1147 InstrItinClass itin, list<dag> pattern> 1148 : I<opcode, OOL, IOL, asmstr, itin> { 1149 bits<6> XT; 1150 bits<6> XB; 1151 bits<2> D; 1152 1153 let Pattern = pattern; 1154 1155 let Inst{6-10} = XT{4-0}; 1156 let Inst{11-13} = 0; 1157 let Inst{14-15} = D; 1158 let Inst{16-20} = XB{4-0}; 1159 let Inst{21-29} = xo; 1160 let Inst{30} = XB{5}; 1161 let Inst{31} = XT{5}; 1162} 1163 1164class XX2_RD6_UIM5_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1165 string asmstr, InstrItinClass itin, list<dag> pattern> 1166 : I<opcode, OOL, IOL, asmstr, itin> { 1167 bits<6> XT; 1168 bits<6> XB; 1169 bits<5> UIM5; 1170 1171 let Pattern = pattern; 1172 1173 let Inst{6-10} = XT{4-0}; 1174 let Inst{11-15} = UIM5; 1175 let Inst{16-20} = XB{4-0}; 1176 let Inst{21-29} = xo; 1177 let Inst{30} = XB{5}; 1178 let Inst{31} = XT{5}; 1179} 1180 1181// [PO T XO B XO BX /] 1182class XX2_RD5_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL, 1183 string asmstr, InstrItinClass itin, list<dag> pattern> 1184 : I<opcode, OOL, IOL, asmstr, itin> { 1185 bits<5> RT; 1186 bits<6> XB; 1187 1188 let Pattern = pattern; 1189 1190 let Inst{6-10} = RT; 1191 let Inst{11-15} = xo2; 1192 let Inst{16-20} = XB{4-0}; 1193 let Inst{21-29} = xo; 1194 let Inst{30} = XB{5}; 1195 let Inst{31} = 0; 1196} 1197 1198// [PO T XO B XO BX TX] 1199class XX2_RD6_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL, 1200 string asmstr, InstrItinClass itin, list<dag> pattern> 1201 : I<opcode, OOL, IOL, asmstr, itin> { 1202 bits<6> XT; 1203 bits<6> XB; 1204 1205 let Pattern = pattern; 1206 1207 let Inst{6-10} = XT{4-0}; 1208 let Inst{11-15} = xo2; 1209 let Inst{16-20} = XB{4-0}; 1210 let Inst{21-29} = xo; 1211 let Inst{30} = XB{5}; 1212 let Inst{31} = XT{5}; 1213} 1214 1215class XX2_BF3_DCMX7_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1216 string asmstr, InstrItinClass itin, list<dag> pattern> 1217 : I<opcode, OOL, IOL, asmstr, itin> { 1218 bits<3> BF; 1219 bits<7> DCMX; 1220 bits<6> XB; 1221 1222 let Pattern = pattern; 1223 1224 let Inst{6-8} = BF; 1225 let Inst{9-15} = DCMX; 1226 let Inst{16-20} = XB{4-0}; 1227 let Inst{21-29} = xo; 1228 let Inst{30} = XB{5}; 1229 let Inst{31} = 0; 1230} 1231 1232class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2, 1233 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 1234 list<dag> pattern> 1235 : I<opcode, OOL, IOL, asmstr, itin> { 1236 bits<6> XT; 1237 bits<7> DCMX; 1238 bits<6> XB; 1239 1240 let Pattern = pattern; 1241 1242 let Inst{6-10} = XT{4-0}; 1243 let Inst{11-15} = DCMX{4-0}; 1244 let Inst{16-20} = XB{4-0}; 1245 let Inst{21-24} = xo1; 1246 let Inst{25} = DCMX{6}; 1247 let Inst{26-28} = xo2; 1248 let Inst{29} = DCMX{5}; 1249 let Inst{30} = XB{5}; 1250 let Inst{31} = XT{5}; 1251} 1252 1253class XForm_XD6_RA5_RB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1254 string asmstr, InstrItinClass itin, list<dag> pattern> 1255 : I<opcode, OOL, IOL, asmstr, itin>, MemriOp { 1256 bits<5> RA; 1257 bits<6> D; 1258 bits<5> RB; 1259 1260 let Pattern = pattern; 1261 1262 let Inst{6-10} = D{4-0}; // D 1263 let Inst{11-15} = RA; 1264 let Inst{16-20} = RB; 1265 let Inst{21-30} = xo; 1266 let Inst{31} = D{5}; // DX 1267} 1268 1269class XForm_BF3_UIM6_FRB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1270 string asmstr, InstrItinClass itin, list<dag> pattern> 1271 : I<opcode, OOL, IOL, asmstr, itin> { 1272 bits<3> BF; 1273 bits<6> UIM; 1274 bits<5> FRB; 1275 1276 let Pattern = pattern; 1277 1278 let Inst{6-8} = BF; 1279 let Inst{9} = 0; 1280 let Inst{10-15} = UIM; 1281 let Inst{16-20} = FRB; 1282 let Inst{21-30} = xo; 1283 let Inst{31} = 0; 1284} 1285 1286class XForm_SP2_FRTB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1287 list<dag> pattern, InstrItinClass itin> 1288 : I<opcode, OOL, IOL, asmstr, itin> { 1289 bits<2> SP; 1290 bits<5> FRT; 1291 bits<5> FRB; 1292 1293 let Pattern = pattern; 1294 1295 bit RC = 0; // set by isRecordForm 1296 1297 let Inst{6 - 10} = FRT; 1298 let Inst{11 - 12} = SP; 1299 let Inst{13 - 15} = 0; 1300 let Inst{16 - 20} = FRB; 1301 let Inst{21 - 30} = xo; 1302 let Inst{31} = RC; 1303} 1304 1305class XForm_S1_FRTB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1306 string asmstr, list<dag> pattern, InstrItinClass itin> 1307 : I<opcode, OOL, IOL, asmstr, itin> { 1308 bit S; 1309 bits<5> FRT; 1310 bits<5> FRB; 1311 1312 let Pattern = pattern; 1313 1314 bit RC = 0; // set by isRecordForm 1315 1316 let Inst{6 - 10} = FRT; 1317 let Inst{11} = S; 1318 let Inst{12 - 15} = 0; 1319 let Inst{16 - 20} = FRB; 1320 let Inst{21 - 30} = xo; 1321 let Inst{31} = RC; 1322} 1323 1324class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1325 InstrItinClass itin, list<dag> pattern> 1326 : I<opcode, OOL, IOL, asmstr, itin> { 1327 bits<6> XT; 1328 bits<6> XA; 1329 bits<6> XB; 1330 1331 let Pattern = pattern; 1332 1333 let Inst{6-10} = XT{4-0}; 1334 let Inst{11-15} = XA{4-0}; 1335 let Inst{16-20} = XB{4-0}; 1336 let Inst{21-28} = xo; 1337 let Inst{29} = XA{5}; 1338 let Inst{30} = XB{5}; 1339 let Inst{31} = XT{5}; 1340} 1341 1342class XX3Form_SameOp<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1343 InstrItinClass itin, list<dag> pattern> 1344 : XX3Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1345 let XA = XT; 1346 let XB = XT; 1347} 1348 1349class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1350 InstrItinClass itin, list<dag> pattern> 1351 : I<opcode, OOL, IOL, asmstr, itin> { 1352 bits<3> CR; 1353 bits<6> XA; 1354 bits<6> XB; 1355 1356 let Pattern = pattern; 1357 1358 let Inst{6-8} = CR; 1359 let Inst{9-10} = 0; 1360 let Inst{11-15} = XA{4-0}; 1361 let Inst{16-20} = XB{4-0}; 1362 let Inst{21-28} = xo; 1363 let Inst{29} = XA{5}; 1364 let Inst{30} = XB{5}; 1365 let Inst{31} = 0; 1366} 1367 1368class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1369 InstrItinClass itin, list<dag> pattern> 1370 : I<opcode, OOL, IOL, asmstr, itin> { 1371 bits<6> XT; 1372 bits<6> XA; 1373 bits<6> XB; 1374 bits<2> D; 1375 1376 let Pattern = pattern; 1377 1378 let Inst{6-10} = XT{4-0}; 1379 let Inst{11-15} = XA{4-0}; 1380 let Inst{16-20} = XB{4-0}; 1381 let Inst{21} = 0; 1382 let Inst{22-23} = D; 1383 let Inst{24-28} = xo; 1384 let Inst{29} = XA{5}; 1385 let Inst{30} = XB{5}; 1386 let Inst{31} = XT{5}; 1387} 1388 1389class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr, 1390 InstrItinClass itin, list<dag> pattern> 1391 : I<opcode, OOL, IOL, asmstr, itin> { 1392 bits<6> XT; 1393 bits<6> XA; 1394 bits<6> XB; 1395 1396 let Pattern = pattern; 1397 1398 bit RC = 0; // set by isRecordForm 1399 1400 let Inst{6-10} = XT{4-0}; 1401 let Inst{11-15} = XA{4-0}; 1402 let Inst{16-20} = XB{4-0}; 1403 let Inst{21} = RC; 1404 let Inst{22-28} = xo; 1405 let Inst{29} = XA{5}; 1406 let Inst{30} = XB{5}; 1407 let Inst{31} = XT{5}; 1408} 1409 1410class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 1411 InstrItinClass itin, list<dag> pattern> 1412 : I<opcode, OOL, IOL, asmstr, itin> { 1413 bits<6> XT; 1414 bits<6> XA; 1415 bits<6> XB; 1416 bits<6> XC; 1417 1418 let Pattern = pattern; 1419 1420 let Inst{6-10} = XT{4-0}; 1421 let Inst{11-15} = XA{4-0}; 1422 let Inst{16-20} = XB{4-0}; 1423 let Inst{21-25} = XC{4-0}; 1424 let Inst{26-27} = xo; 1425 let Inst{28} = XC{5}; 1426 let Inst{29} = XA{5}; 1427 let Inst{30} = XB{5}; 1428 let Inst{31} = XT{5}; 1429} 1430 1431// DCB_Form - Form X instruction, used for dcb* instructions. 1432class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, 1433 InstrItinClass itin, list<dag> pattern> 1434 : I<31, OOL, IOL, asmstr, itin> { 1435 bits<5> RA; 1436 bits<5> RB; 1437 1438 let Pattern = pattern; 1439 1440 let Inst{6-10} = immfield; 1441 let Inst{11-15} = RA; 1442 let Inst{16-20} = RB; 1443 let Inst{21-30} = xo; 1444 let Inst{31} = 0; 1445} 1446 1447class DCB_Form_hint<bits<10> xo, dag OOL, dag IOL, string asmstr, 1448 InstrItinClass itin, list<dag> pattern> 1449 : I<31, OOL, IOL, asmstr, itin> { 1450 bits<5> TH; 1451 bits<5> RA; 1452 bits<5> RB; 1453 1454 let Pattern = pattern; 1455 1456 let Inst{6-10} = TH; 1457 let Inst{11-15} = RA; 1458 let Inst{16-20} = RB; 1459 let Inst{21-30} = xo; 1460 let Inst{31} = 0; 1461} 1462 1463// DSS_Form - Form X instruction, used for altivec dss* instructions. 1464class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr, 1465 InstrItinClass itin, list<dag> pattern> 1466 : I<31, OOL, IOL, asmstr, itin> { 1467 bits<2> STRM; 1468 bits<5> RA; 1469 bits<5> RB; 1470 1471 let Pattern = pattern; 1472 1473 let Inst{6} = T; 1474 let Inst{7-8} = 0; 1475 let Inst{9-10} = STRM; 1476 let Inst{11-15} = RA; 1477 let Inst{16-20} = RB; 1478 let Inst{21-30} = xo; 1479 let Inst{31} = 0; 1480} 1481 1482// 1.7.7 XL-Form 1483class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1484 InstrItinClass itin, list<dag> pattern> 1485 : I<opcode, OOL, IOL, asmstr, itin> { 1486 bits<5> CRD; 1487 bits<5> CRA; 1488 bits<5> CRB; 1489 1490 let Pattern = pattern; 1491 1492 let Inst{6-10} = CRD; 1493 let Inst{11-15} = CRA; 1494 let Inst{16-20} = CRB; 1495 let Inst{21-30} = xo; 1496 let Inst{31} = 0; 1497} 1498 1499// XL-Form for unary alias for CRNOR (CRNOT) 1500class XLForm_1s<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1501 InstrItinClass itin, list<dag> pattern> 1502 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1503 let CRB = CRA; 1504} 1505 1506class XLForm_1_np<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1507 InstrItinClass itin, list<dag> pattern> 1508 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1509 let CRD = 0; 1510 let CRA = 0; 1511 let CRB = 0; 1512} 1513 1514class XLForm_1_gen<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1515 InstrItinClass itin, list<dag> pattern> 1516 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1517 bits<5> RT; 1518 bits<5> RB; 1519 1520 let CRD = RT; 1521 let CRA = 0; 1522 let CRB = RB; 1523} 1524 1525class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1526 InstrItinClass itin, list<dag> pattern> 1527 : I<opcode, OOL, IOL, asmstr, itin> { 1528 bits<5> CRD; 1529 1530 let Pattern = pattern; 1531 1532 let Inst{6-10} = CRD; 1533 let Inst{11-15} = CRD; 1534 let Inst{16-20} = CRD; 1535 let Inst{21-30} = xo; 1536 let Inst{31} = 0; 1537} 1538 1539class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr, 1540 InstrItinClass itin, list<dag> pattern> 1541 : I<opcode, OOL, IOL, asmstr, itin> { 1542 bits<5> BO; 1543 bits<5> BI; 1544 bits<2> BH; 1545 1546 let Pattern = pattern; 1547 1548 let Inst{6-10} = BO; 1549 let Inst{11-15} = BI; 1550 let Inst{16-18} = 0; 1551 let Inst{19-20} = BH; 1552 let Inst{21-30} = xo; 1553 let Inst{31} = lk; 1554} 1555 1556class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, 1557 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1558 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1559 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 1560 bits<3> CR; 1561 1562 let BO = BIBO{4-0}; 1563 let BI{0-1} = BIBO{5-6}; 1564 let BI{2-4} = CR{0-2}; 1565 let BH = 0; 1566} 1567 1568class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk, 1569 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1570 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1571 let BO = bo; 1572 let BH = 0; 1573} 1574 1575class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk, 1576 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1577 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1578 let BO = bo; 1579 let BI = bi; 1580 let BH = 0; 1581} 1582 1583class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1584 InstrItinClass itin> 1585 : I<opcode, OOL, IOL, asmstr, itin> { 1586 bits<3> BF; 1587 bits<3> BFA; 1588 1589 let Inst{6-8} = BF; 1590 let Inst{9-10} = 0; 1591 let Inst{11-13} = BFA; 1592 let Inst{14-15} = 0; 1593 let Inst{16-20} = 0; 1594 let Inst{21-30} = xo; 1595 let Inst{31} = 0; 1596} 1597 1598class XLForm_4<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1599 InstrItinClass itin> 1600 : I<opcode, OOL, IOL, asmstr, itin> { 1601 bits<3> BF; 1602 bit W; 1603 bits<4> U; 1604 1605 bit RC = 0; 1606 1607 let Inst{6-8} = BF; 1608 let Inst{9-10} = 0; 1609 let Inst{11-14} = 0; 1610 let Inst{15} = W; 1611 let Inst{16-19} = U; 1612 let Inst{20} = 0; 1613 let Inst{21-30} = xo; 1614 let Inst{31} = RC; 1615} 1616 1617class XLForm_S<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1618 InstrItinClass itin, list<dag> pattern> 1619 : I<opcode, OOL, IOL, asmstr, itin> { 1620 bits<1> S; 1621 1622 let Pattern = pattern; 1623 1624 let Inst{6-19} = 0; 1625 let Inst{20} = S; 1626 let Inst{21-30} = xo; 1627 let Inst{31} = 0; 1628} 1629 1630class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk, 1631 bits<6> opcode2, bits<2> xo2, 1632 dag OOL, dag IOL, string asmstr, 1633 InstrItinClass itin, list<dag> pattern> 1634 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 1635 bits<5> BO; 1636 bits<5> BI; 1637 bits<2> BH; 1638 1639 bits<5> RST; 1640 bits<5> RA; 1641 bits<14> D; 1642 1643 let Pattern = pattern; 1644 1645 let Inst{6-10} = BO; 1646 let Inst{11-15} = BI; 1647 let Inst{16-18} = 0; 1648 let Inst{19-20} = BH; 1649 let Inst{21-30} = xo1; 1650 let Inst{31} = lk; 1651 1652 let Inst{38-42} = RST; 1653 let Inst{43-47} = RA; 1654 let Inst{48-61} = D; 1655 let Inst{62-63} = xo2; 1656} 1657 1658class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1, 1659 bits<5> bo, bits<5> bi, bit lk, 1660 bits<6> opcode2, bits<2> xo2, 1661 dag OOL, dag IOL, string asmstr, 1662 InstrItinClass itin, list<dag> pattern> 1663 : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2, 1664 OOL, IOL, asmstr, itin, pattern> { 1665 let BO = bo; 1666 let BI = bi; 1667 let BH = 0; 1668} 1669 1670class XLForm_2_ext_and_DForm_1<bits<6> opcode1, bits<10> xo1, bits<5> bo, 1671 bits<5> bi, bit lk, bits<6> opcode2, dag OOL, 1672 dag IOL, string asmstr, InstrItinClass itin, 1673 list<dag> pattern> 1674 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 1675 1676 bits<5> RST; 1677 bits<5> RA; 1678 bits<16> D; 1679 1680 let Pattern = pattern; 1681 1682 let Inst{6-10} = bo; 1683 let Inst{11-15} = bi; 1684 let Inst{16-18} = 0; 1685 let Inst{19-20} = 0; // Unused (BH) 1686 let Inst{21-30} = xo1; 1687 let Inst{31} = lk; 1688 1689 let Inst{38-42} = RST; 1690 let Inst{43-47} = RA; 1691 let Inst{48-63} = D; 1692} 1693 1694// 1.7.8 XFX-Form 1695class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1696 InstrItinClass itin> 1697 : I<opcode, OOL, IOL, asmstr, itin> { 1698 bits<5> RST; 1699 bits<10> SPR; 1700 1701 let Inst{6-10} = RST; 1702 let Inst{11} = SPR{4}; 1703 let Inst{12} = SPR{3}; 1704 let Inst{13} = SPR{2}; 1705 let Inst{14} = SPR{1}; 1706 let Inst{15} = SPR{0}; 1707 let Inst{16} = SPR{9}; 1708 let Inst{17} = SPR{8}; 1709 let Inst{18} = SPR{7}; 1710 let Inst{19} = SPR{6}; 1711 let Inst{20} = SPR{5}; 1712 let Inst{21-30} = xo; 1713 let Inst{31} = 0; 1714} 1715 1716class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 1717 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1718 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> { 1719 let SPR = spr; 1720} 1721 1722class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1723 InstrItinClass itin> 1724 : I<opcode, OOL, IOL, asmstr, itin> { 1725 bits<5> RT; 1726 1727 let Inst{6-10} = RT; 1728 let Inst{11-20} = 0; 1729 let Inst{21-30} = xo; 1730 let Inst{31} = 0; 1731} 1732 1733class XFXForm_3p<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1734 InstrItinClass itin, list<dag> pattern> 1735 : I<opcode, OOL, IOL, asmstr, itin> { 1736 bits<5> RT; 1737 bits<10> imm; 1738 let Pattern = pattern; 1739 1740 let Inst{6-10} = RT; 1741 let Inst{11-20} = imm; 1742 let Inst{21-30} = xo; 1743 let Inst{31} = 0; 1744} 1745 1746class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1747 InstrItinClass itin> 1748 : I<opcode, OOL, IOL, asmstr, itin> { 1749 bits<8> FXM; 1750 bits<5> RST; 1751 1752 let Inst{6-10} = RST; 1753 let Inst{11} = 0; 1754 let Inst{12-19} = FXM; 1755 let Inst{20} = 0; 1756 let Inst{21-30} = xo; 1757 let Inst{31} = 0; 1758} 1759 1760class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1761 InstrItinClass itin> 1762 : I<opcode, OOL, IOL, asmstr, itin> { 1763 bits<5> RST; 1764 bits<8> FXM; 1765 1766 let Inst{6-10} = RST; 1767 let Inst{11} = 1; 1768 let Inst{12-19} = FXM; 1769 let Inst{20} = 0; 1770 let Inst{21-30} = xo; 1771 let Inst{31} = 0; 1772} 1773 1774// XFL-Form - MTFSF 1775// This is probably 1.7.9, but I don't have the reference that uses this 1776// numbering scheme... 1777class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1778 InstrItinClass itin, list<dag>pattern> 1779 : I<opcode, OOL, IOL, asmstr, itin> { 1780 bits<8> FM; 1781 bits<5> RT; 1782 1783 bit RC = 0; // set by isRecordForm 1784 let Pattern = pattern; 1785 1786 let Inst{6} = 0; 1787 let Inst{7-14} = FM; 1788 let Inst{15} = 0; 1789 let Inst{16-20} = RT; 1790 let Inst{21-30} = xo; 1791 let Inst{31} = RC; 1792} 1793 1794class XFLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1795 InstrItinClass itin, list<dag>pattern> 1796 : I<opcode, OOL, IOL, asmstr, itin> { 1797 bit L; 1798 bits<8> FLM; 1799 bit W; 1800 bits<5> FRB; 1801 1802 bit RC = 0; // set by isRecordForm 1803 let Pattern = pattern; 1804 1805 let Inst{6} = L; 1806 let Inst{7-14} = FLM; 1807 let Inst{15} = W; 1808 let Inst{16-20} = FRB; 1809 let Inst{21-30} = xo; 1810 let Inst{31} = RC; 1811} 1812 1813// 1.7.10 XS-Form - SRADI. 1814class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1815 InstrItinClass itin, list<dag> pattern> 1816 : I<opcode, OOL, IOL, asmstr, itin> { 1817 bits<5> RA; 1818 bits<5> RS; 1819 bits<6> SH; 1820 1821 bit RC = 0; // set by isRecordForm 1822 let Pattern = pattern; 1823 1824 let Inst{6-10} = RS; 1825 let Inst{11-15} = RA; 1826 let Inst{16-20} = SH{4,3,2,1,0}; 1827 let Inst{21-29} = xo; 1828 let Inst{30} = SH{5}; 1829 let Inst{31} = RC; 1830} 1831 1832// 1.7.11 XO-Form 1833class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr, 1834 InstrItinClass itin, list<dag> pattern> 1835 : I<opcode, OOL, IOL, asmstr, itin> { 1836 bits<5> RT; 1837 bits<5> RA; 1838 bits<5> RB; 1839 1840 let Pattern = pattern; 1841 1842 bit RC = 0; // set by isRecordForm 1843 1844 let Inst{6-10} = RT; 1845 let Inst{11-15} = RA; 1846 let Inst{16-20} = RB; 1847 let Inst{21} = oe; 1848 let Inst{22-30} = xo; 1849 let Inst{31} = RC; 1850} 1851 1852class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, 1853 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1854 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> { 1855 let RB = 0; 1856} 1857 1858// 1.7.12 A-Form 1859class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1860 InstrItinClass itin, list<dag> pattern> 1861 : I<opcode, OOL, IOL, asmstr, itin> { 1862 bits<5> FRT; 1863 bits<5> FRA; 1864 bits<5> FRC; 1865 bits<5> FRB; 1866 1867 let Pattern = pattern; 1868 1869 bit RC = 0; // set by isRecordForm 1870 1871 let Inst{6-10} = FRT; 1872 let Inst{11-15} = FRA; 1873 let Inst{16-20} = FRB; 1874 let Inst{21-25} = FRC; 1875 let Inst{26-30} = xo; 1876 let Inst{31} = RC; 1877} 1878 1879class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1880 InstrItinClass itin, list<dag> pattern> 1881 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1882 let FRC = 0; 1883} 1884 1885class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1886 InstrItinClass itin, list<dag> pattern> 1887 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1888 let FRB = 0; 1889} 1890 1891class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1892 InstrItinClass itin, list<dag> pattern> 1893 : I<opcode, OOL, IOL, asmstr, itin> { 1894 bits<5> RT; 1895 bits<5> RA; 1896 bits<5> RB; 1897 bits<5> COND; 1898 1899 let Pattern = pattern; 1900 1901 let Inst{6-10} = RT; 1902 let Inst{11-15} = RA; 1903 let Inst{16-20} = RB; 1904 let Inst{21-25} = COND; 1905 let Inst{26-30} = xo; 1906 let Inst{31} = 0; 1907} 1908 1909// 1.7.13 M-Form 1910class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1911 InstrItinClass itin, list<dag> pattern> 1912 : I<opcode, OOL, IOL, asmstr, itin> { 1913 bits<5> RA; 1914 bits<5> RS; 1915 bits<5> RB; 1916 bits<5> MB; 1917 bits<5> ME; 1918 1919 let Pattern = pattern; 1920 1921 bit RC = 0; // set by isRecordForm 1922 1923 let Inst{6-10} = RS; 1924 let Inst{11-15} = RA; 1925 let Inst{16-20} = RB; 1926 let Inst{21-25} = MB; 1927 let Inst{26-30} = ME; 1928 let Inst{31} = RC; 1929} 1930 1931class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1932 InstrItinClass itin, list<dag> pattern> 1933 : I<opcode, OOL, IOL, asmstr, itin> { 1934 bits<5> RA; 1935 bits<5> RS; 1936 bits<5> SH; 1937 bits<5> MB; 1938 bits<5> ME; 1939 1940 let Pattern = pattern; 1941 1942 bit RC = 0; // set by isRecordForm 1943 1944 let Inst{6-10} = RS; 1945 let Inst{11-15} = RA; 1946 let Inst{16-20} = SH; 1947 let Inst{21-25} = MB; 1948 let Inst{26-30} = ME; 1949 let Inst{31} = RC; 1950} 1951 1952// 1.7.14 MD-Form 1953class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr, 1954 InstrItinClass itin, list<dag> pattern> 1955 : I<opcode, OOL, IOL, asmstr, itin> { 1956 bits<5> RA; 1957 bits<5> RS; 1958 bits<6> SH; 1959 bits<6> MBE; 1960 1961 let Pattern = pattern; 1962 1963 bit RC = 0; // set by isRecordForm 1964 1965 let Inst{6-10} = RS; 1966 let Inst{11-15} = RA; 1967 let Inst{16-20} = SH{4,3,2,1,0}; 1968 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1969 let Inst{27-29} = xo; 1970 let Inst{30} = SH{5}; 1971 let Inst{31} = RC; 1972} 1973 1974class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr, 1975 InstrItinClass itin, list<dag> pattern> 1976 : I<opcode, OOL, IOL, asmstr, itin> { 1977 bits<5> RA; 1978 bits<5> RS; 1979 bits<5> RB; 1980 bits<6> MBE; 1981 1982 let Pattern = pattern; 1983 1984 bit RC = 0; // set by isRecordForm 1985 1986 let Inst{6-10} = RS; 1987 let Inst{11-15} = RA; 1988 let Inst{16-20} = RB; 1989 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1990 let Inst{27-30} = xo; 1991 let Inst{31} = RC; 1992} 1993 1994 1995// E-1 VA-Form 1996 1997// VAForm_1 - DACB ordering. 1998class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr, 1999 InstrItinClass itin, list<dag> pattern> 2000 : I<4, OOL, IOL, asmstr, itin> { 2001 bits<5> RT; 2002 bits<5> RA; 2003 bits<5> RC; 2004 bits<5> RB; 2005 2006 let Pattern = pattern; 2007 2008 let Inst{6-10} = RT; 2009 let Inst{11-15} = RA; 2010 let Inst{16-20} = RB; 2011 let Inst{21-25} = RC; 2012 let Inst{26-31} = xo; 2013} 2014 2015// VAForm_1a - DABC ordering. 2016class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr, 2017 InstrItinClass itin, list<dag> pattern> 2018 : I<4, OOL, IOL, asmstr, itin> { 2019 bits<5> RT; 2020 bits<5> RA; 2021 bits<5> RB; 2022 bits<5> RC; 2023 2024 let Pattern = pattern; 2025 2026 let Inst{6-10} = RT; 2027 let Inst{11-15} = RA; 2028 let Inst{16-20} = RB; 2029 let Inst{21-25} = RC; 2030 let Inst{26-31} = xo; 2031} 2032 2033class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr, 2034 InstrItinClass itin, list<dag> pattern> 2035 : I<4, OOL, IOL, asmstr, itin> { 2036 bits<5> RT; 2037 bits<5> RA; 2038 bits<5> RB; 2039 bits<4> SH; 2040 2041 let Pattern = pattern; 2042 2043 let Inst{6-10} = RT; 2044 let Inst{11-15} = RA; 2045 let Inst{16-20} = RB; 2046 let Inst{21} = 0; 2047 let Inst{22-25} = SH; 2048 let Inst{26-31} = xo; 2049} 2050 2051// E-2 VX-Form 2052class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr, 2053 InstrItinClass itin, list<dag> pattern> 2054 : I<4, OOL, IOL, asmstr, itin> { 2055 bits<5> VD; 2056 bits<5> VA; 2057 bits<5> VB; 2058 2059 let Pattern = pattern; 2060 2061 let Inst{6-10} = VD; 2062 let Inst{11-15} = VA; 2063 let Inst{16-20} = VB; 2064 let Inst{21-31} = xo; 2065} 2066 2067class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr, 2068 InstrItinClass itin, list<dag> pattern> 2069 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> { 2070 let VA = VD; 2071 let VB = VD; 2072} 2073 2074 2075class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr, 2076 InstrItinClass itin, list<dag> pattern> 2077 : I<4, OOL, IOL, asmstr, itin> { 2078 bits<5> VD; 2079 bits<5> VB; 2080 2081 let Pattern = pattern; 2082 2083 let Inst{6-10} = VD; 2084 let Inst{11-15} = 0; 2085 let Inst{16-20} = VB; 2086 let Inst{21-31} = xo; 2087} 2088 2089class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr, 2090 InstrItinClass itin, list<dag> pattern> 2091 : I<4, OOL, IOL, asmstr, itin> { 2092 bits<5> VD; 2093 bits<5> IMM; 2094 2095 let Pattern = pattern; 2096 2097 let Inst{6-10} = VD; 2098 let Inst{11-15} = IMM; 2099 let Inst{16-20} = 0; 2100 let Inst{21-31} = xo; 2101} 2102 2103/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr. 2104class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr, 2105 InstrItinClass itin, list<dag> pattern> 2106 : I<4, OOL, IOL, asmstr, itin> { 2107 bits<5> VD; 2108 2109 let Pattern = pattern; 2110 2111 let Inst{6-10} = VD; 2112 let Inst{11-15} = 0; 2113 let Inst{16-20} = 0; 2114 let Inst{21-31} = xo; 2115} 2116 2117/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr. 2118class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr, 2119 InstrItinClass itin, list<dag> pattern> 2120 : I<4, OOL, IOL, asmstr, itin> { 2121 bits<5> VB; 2122 2123 let Pattern = pattern; 2124 2125 let Inst{6-10} = 0; 2126 let Inst{11-15} = 0; 2127 let Inst{16-20} = VB; 2128 let Inst{21-31} = xo; 2129} 2130 2131// e.g. [PO VRT EO VRB XO] 2132class VXForm_RD5_XO5_RS5<bits<11> xo, bits<5> eo, dag OOL, dag IOL, 2133 string asmstr, InstrItinClass itin, list<dag> pattern> 2134 : I<4, OOL, IOL, asmstr, itin> { 2135 bits<5> VD; 2136 bits<5> VB; 2137 2138 let Pattern = pattern; 2139 2140 let Inst{6-10} = VD; 2141 let Inst{11-15} = eo; 2142 let Inst{16-20} = VB; 2143 let Inst{21-31} = xo; 2144} 2145 2146/// VXForm_CR - VX crypto instructions with "VRT, VRA, ST, SIX" 2147class VXForm_CR<bits<11> xo, dag OOL, dag IOL, string asmstr, 2148 InstrItinClass itin, list<dag> pattern> 2149 : I<4, OOL, IOL, asmstr, itin> { 2150 bits<5> VD; 2151 bits<5> VA; 2152 bits<1> ST; 2153 bits<4> SIX; 2154 2155 let Pattern = pattern; 2156 2157 let Inst{6-10} = VD; 2158 let Inst{11-15} = VA; 2159 let Inst{16} = ST; 2160 let Inst{17-20} = SIX; 2161 let Inst{21-31} = xo; 2162} 2163 2164/// VXForm_BX - VX crypto instructions with "VRT, VRA, 0 - like vsbox" 2165class VXForm_BX<bits<11> xo, dag OOL, dag IOL, string asmstr, 2166 InstrItinClass itin, list<dag> pattern> 2167 : I<4, OOL, IOL, asmstr, itin> { 2168 bits<5> VD; 2169 bits<5> VA; 2170 2171 let Pattern = pattern; 2172 2173 let Inst{6-10} = VD; 2174 let Inst{11-15} = VA; 2175 let Inst{16-20} = 0; 2176 let Inst{21-31} = xo; 2177} 2178 2179// E-4 VXR-Form 2180class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr, 2181 InstrItinClass itin, list<dag> pattern> 2182 : I<4, OOL, IOL, asmstr, itin> { 2183 bits<5> VD; 2184 bits<5> VA; 2185 bits<5> VB; 2186 bit RC = 0; 2187 2188 let Pattern = pattern; 2189 2190 let Inst{6-10} = VD; 2191 let Inst{11-15} = VA; 2192 let Inst{16-20} = VB; 2193 let Inst{21} = RC; 2194 let Inst{22-31} = xo; 2195} 2196 2197// VX-Form: [PO VRT EO VRB 1 PS XO] 2198class VX_RD5_EO5_RS5_PS1_XO9<bits<5> eo, bits<9> xo, 2199 dag OOL, dag IOL, string asmstr, 2200 InstrItinClass itin, list<dag> pattern> 2201 : I<4, OOL, IOL, asmstr, itin> { 2202 bits<5> VD; 2203 bits<5> VB; 2204 bit PS; 2205 2206 let Pattern = pattern; 2207 2208 let Inst{6-10} = VD; 2209 let Inst{11-15} = eo; 2210 let Inst{16-20} = VB; 2211 let Inst{21} = 1; 2212 let Inst{22} = PS; 2213 let Inst{23-31} = xo; 2214} 2215 2216// VX-Form: [PO VRT VRA VRB 1 PS XO] or [PO VRT VRA VRB 1 / XO] 2217class VX_RD5_RSp5_PS1_XO9<bits<9> xo, dag OOL, dag IOL, string asmstr, 2218 InstrItinClass itin, list<dag> pattern> 2219 : I<4, OOL, IOL, asmstr, itin> { 2220 bits<5> VD; 2221 bits<5> VA; 2222 bits<5> VB; 2223 bit PS; 2224 2225 let Pattern = pattern; 2226 2227 let Inst{6-10} = VD; 2228 let Inst{11-15} = VA; 2229 let Inst{16-20} = VB; 2230 let Inst{21} = 1; 2231 let Inst{22} = PS; 2232 let Inst{23-31} = xo; 2233} 2234 2235class Z22Form_BF3_FRA5_DCM6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 2236 string asmstr, InstrItinClass itin, 2237 list<dag> pattern> 2238 : I<opcode, OOL, IOL, asmstr, itin> { 2239 bits<3> BF; 2240 bits<5> FRA; 2241 bits<6> DCM; 2242 2243 let Pattern = pattern; 2244 2245 let Inst{6-8} = BF; 2246 let Inst{9-10} = 0; 2247 let Inst{11-15} = FRA; 2248 let Inst{16-21} = DCM; 2249 let Inst{22-30} = xo; 2250 let Inst{31} = 0; 2251} 2252 2253class Z22Form_FRTA5_SH6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 2254 string asmstr, list<dag> pattern, InstrItinClass itin> 2255 : I<opcode, OOL, IOL, asmstr, itin> { 2256 2257 bits<5> FRT; 2258 bits<5> FRA; 2259 bits<6> SH; 2260 2261 let Pattern = pattern; 2262 2263 bit RC = 0; // set by isRecordForm 2264 2265 let Inst{6 - 10} = FRT; 2266 let Inst{11 - 15} = FRA; 2267 let Inst{16 - 21} = SH; 2268 let Inst{22 - 30} = xo; 2269 let Inst{31} = RC; 2270} 2271 2272class Z23Form_8<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 2273 InstrItinClass itin, list<dag> pattern> 2274 : I<opcode, OOL, IOL, asmstr, itin> { 2275 bits<5> VRT; 2276 bit R; 2277 bits<5> VRB; 2278 bits<2> idx; 2279 2280 let Pattern = pattern; 2281 2282 bit RC = 0; // set by isRecordForm 2283 2284 let Inst{6-10} = VRT; 2285 let Inst{11-14} = 0; 2286 let Inst{15} = R; 2287 let Inst{16-20} = VRB; 2288 let Inst{21-22} = idx; 2289 let Inst{23-30} = xo; 2290 let Inst{31} = RC; 2291} 2292 2293class Z23Form_RTAB5_CY2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 2294 string asmstr, InstrItinClass itin, list<dag> pattern> 2295 : I<opcode, OOL, IOL, asmstr, itin> { 2296 bits<5> RT; 2297 bits<5> RA; 2298 bits<5> RB; 2299 bits<2> CY; 2300 2301 let Pattern = pattern; 2302 2303 let Inst{6-10} = RT; 2304 let Inst{11-15} = RA; 2305 let Inst{16-20} = RB; 2306 let Inst{21-22} = CY; 2307 let Inst{23-30} = xo; 2308 let Inst{31} = 0; 2309} 2310 2311class Z23Form_FRTAB5_RMC2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 2312 string asmstr, list<dag> pattern> 2313 : I<opcode, OOL, IOL, asmstr, NoItinerary> { 2314 bits<5> FRT; 2315 bits<5> FRA; 2316 bits<5> FRB; 2317 bits<2> RMC; 2318 2319 let Pattern = pattern; 2320 2321 bit RC = 0; // set by isRecordForm 2322 2323 let Inst{6 - 10} = FRT; 2324 let Inst{11 - 15} = FRA; 2325 let Inst{16 - 20} = FRB; 2326 let Inst{21 - 22} = RMC; 2327 let Inst{23 - 30} = xo; 2328 let Inst{31} = RC; 2329} 2330 2331class Z23Form_TE5_FRTB5_RMC2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 2332 string asmstr, list<dag> pattern> 2333 : Z23Form_FRTAB5_RMC2<opcode, xo, OOL, IOL, asmstr, pattern> { 2334 bits<5> TE; 2335 let FRA = TE; 2336} 2337 2338class Z23Form_FRTB5_R1_RMC2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 2339 string asmstr, list<dag> pattern> 2340 : I<opcode, OOL, IOL, asmstr, NoItinerary> { 2341 bits<5> FRT; 2342 bits<1> R; 2343 bits<5> FRB; 2344 bits<2> RMC; 2345 2346 let Pattern = pattern; 2347 2348 bit RC = 0; // set by isRecordForm 2349 2350 let Inst{6 - 10} = FRT; 2351 let Inst{11 - 14} = 0; 2352 let Inst{15} = R; 2353 let Inst{16 - 20} = FRB; 2354 let Inst{21 - 22} = RMC; 2355 let Inst{23 - 30} = xo; 2356 let Inst{31} = RC; 2357} 2358 2359//===----------------------------------------------------------------------===// 2360// EmitTimePseudo won't have encoding information for the [MC]CodeEmitter 2361// stuff 2362class PPCEmitTimePseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2363 : I<0, OOL, IOL, asmstr, NoItinerary> { 2364 let isCodeGenOnly = 1; 2365 let PPC64 = 0; 2366 let Pattern = pattern; 2367 let Inst{31-0} = 0; 2368 let hasNoSchedulingInfo = 1; 2369} 2370 2371// Instruction that require custom insertion support 2372// a.k.a. ISelPseudos, however, these won't have isPseudo set 2373class PPCCustomInserterPseudo<dag OOL, dag IOL, string asmstr, 2374 list<dag> pattern> 2375 : PPCEmitTimePseudo<OOL, IOL, asmstr, pattern> { 2376 let usesCustomInserter = 1; 2377} 2378 2379// PostRAPseudo will be expanded in expandPostRAPseudo, isPseudo flag in td 2380// files is set only for PostRAPseudo 2381class PPCPostRAExpPseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2382 : PPCEmitTimePseudo<OOL, IOL, asmstr, pattern> { 2383 let isPseudo = 1; 2384} 2385 2386class PseudoXFormMemOp<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2387 : PPCPostRAExpPseudo<OOL, IOL, asmstr, pattern>, XFormMemOp; 2388 2389