Lines Matching full:opcode
891 bool EmulateInstructionARM::EmulatePUSH(const uint32_t opcode, in EmulatePUSH() argument
921 if (ConditionPassed(opcode)) { in EmulatePUSH()
930 registers = Bits32(opcode, 7, 0); in EmulatePUSH()
932 if (Bit32(opcode, 8)) in EmulatePUSH()
940 registers = Bits32(opcode, 15, 0) & ~0xa000; in EmulatePUSH()
946 Rt = Bits32(opcode, 15, 12); in EmulatePUSH()
953 registers = Bits32(opcode, 15, 0); in EmulatePUSH()
959 Rt = Bits32(opcode, 15, 12); in EmulatePUSH()
1014 bool EmulateInstructionARM::EmulatePOP(const uint32_t opcode, in EmulatePOP() argument
1037 if (ConditionPassed(opcode)) { in EmulatePOP()
1046 registers = Bits32(opcode, 7, 0); in EmulatePOP()
1048 if (Bit32(opcode, 8)) in EmulatePOP()
1056 registers = Bits32(opcode, 15, 0) & ~0x2000; in EmulatePOP()
1059 if (BitCount(registers) < 2 || (Bit32(opcode, 15) && Bit32(opcode, 14))) in EmulatePOP()
1067 Rt = Bits32(opcode, 15, 12); in EmulatePOP()
1077 registers = Bits32(opcode, 15, 0); in EmulatePOP()
1083 if (BitIsSet(opcode, 13) && ArchVersion() >= ARMv7) in EmulatePOP()
1087 Rt = Bits32(opcode, 15, 12); in EmulatePOP()
1142 bool EmulateInstructionARM::EmulateADDRdSPImm(const uint32_t opcode, in EmulateADDRdSPImm() argument
1164 if (ConditionPassed(opcode)) { in EmulateADDRdSPImm()
1173 imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32) in EmulateADDRdSPImm()
1176 Rd = Bits32(opcode, 15, 12); in EmulateADDRdSPImm()
1177 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateADDRdSPImm()
1203 bool EmulateInstructionARM::EmulateMOVRdSP(const uint32_t opcode, in EmulateMOVRdSP() argument
1225 if (ConditionPassed(opcode)) { in EmulateMOVRdSP()
1258 bool EmulateInstructionARM::EmulateMOVLowHigh(const uint32_t opcode, in EmulateMOVLowHigh() argument
1260 return EmulateMOVRdRm(opcode, encoding); in EmulateMOVLowHigh()
1265 bool EmulateInstructionARM::EmulateMOVRdRm(const uint32_t opcode, in EmulateMOVRdRm() argument
1287 if (ConditionPassed(opcode)) { in EmulateMOVRdRm()
1293 Rd = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0); in EmulateMOVRdRm()
1294 Rm = Bits32(opcode, 6, 3); in EmulateMOVRdRm()
1300 Rd = Bits32(opcode, 2, 0); in EmulateMOVRdRm()
1301 Rm = Bits32(opcode, 5, 3); in EmulateMOVRdRm()
1307 Rd = Bits32(opcode, 11, 8); in EmulateMOVRdRm()
1308 Rm = Bits32(opcode, 3, 0); in EmulateMOVRdRm()
1309 setflags = BitIsSet(opcode, 20); in EmulateMOVRdRm()
1319 Rd = Bits32(opcode, 15, 12); in EmulateMOVRdRm()
1320 Rm = Bits32(opcode, 3, 0); in EmulateMOVRdRm()
1321 setflags = BitIsSet(opcode, 20); in EmulateMOVRdRm()
1326 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateMOVRdRm()
1356 bool EmulateInstructionARM::EmulateMOVRdImm(const uint32_t opcode, in EmulateMOVRdImm() argument
1376 if (ConditionPassed(opcode)) { in EmulateMOVRdImm()
1386 Rd = Bits32(opcode, 10, 8); in EmulateMOVRdImm()
1388 imm32 = Bits32(opcode, 7, 0); // imm32 = ZeroExtend(imm8, 32) in EmulateMOVRdImm()
1394 Rd = Bits32(opcode, 11, 8); in EmulateMOVRdImm()
1395 setflags = BitIsSet(opcode, 20); in EmulateMOVRdImm()
1396 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); in EmulateMOVRdImm()
1405 Rd = Bits32(opcode, 11, 8); in EmulateMOVRdImm()
1407 uint32_t imm4 = Bits32(opcode, 19, 16); in EmulateMOVRdImm()
1408 uint32_t imm3 = Bits32(opcode, 14, 12); in EmulateMOVRdImm()
1409 uint32_t i = Bit32(opcode, 26); in EmulateMOVRdImm()
1410 uint32_t imm8 = Bits32(opcode, 7, 0); in EmulateMOVRdImm()
1421 Rd = Bits32(opcode, 15, 12); in EmulateMOVRdImm()
1422 setflags = BitIsSet(opcode, 20); in EmulateMOVRdImm()
1423 imm32 = ARMExpandImm_C(opcode, APSR_C, carry); in EmulateMOVRdImm()
1428 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateMOVRdImm()
1434 Rd = Bits32(opcode, 15, 12); in EmulateMOVRdImm()
1436 uint32_t imm4 = Bits32(opcode, 19, 16); in EmulateMOVRdImm()
1437 uint32_t imm12 = Bits32(opcode, 11, 0); in EmulateMOVRdImm()
1469 bool EmulateInstructionARM::EmulateMUL(const uint32_t opcode, in EmulateMUL() argument
1487 if (ConditionPassed(opcode)) { in EmulateMUL()
1497 d = Bits32(opcode, 2, 0); in EmulateMUL()
1498 n = Bits32(opcode, 5, 3); in EmulateMUL()
1499 m = Bits32(opcode, 2, 0); in EmulateMUL()
1510 d = Bits32(opcode, 11, 8); in EmulateMUL()
1511 n = Bits32(opcode, 19, 16); in EmulateMUL()
1512 m = Bits32(opcode, 3, 0); in EmulateMUL()
1523 d = Bits32(opcode, 19, 16); in EmulateMUL()
1524 n = Bits32(opcode, 3, 0); in EmulateMUL()
1525 m = Bits32(opcode, 11, 8); in EmulateMUL()
1526 setflags = BitIsSet(opcode, 20); in EmulateMUL()
1598 bool EmulateInstructionARM::EmulateMVNImm(const uint32_t opcode, in EmulateMVNImm() argument
1618 if (ConditionPassed(opcode)) { in EmulateMVNImm()
1625 Rd = Bits32(opcode, 11, 8); in EmulateMVNImm()
1626 setflags = BitIsSet(opcode, 20); in EmulateMVNImm()
1627 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); in EmulateMVNImm()
1630 Rd = Bits32(opcode, 15, 12); in EmulateMVNImm()
1631 setflags = BitIsSet(opcode, 20); in EmulateMVNImm()
1632 imm32 = ARMExpandImm_C(opcode, APSR_C, carry); in EmulateMVNImm()
1637 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateMVNImm()
1658 bool EmulateInstructionARM::EmulateMVNReg(const uint32_t opcode, in EmulateMVNReg() argument
1679 if (ConditionPassed(opcode)) { in EmulateMVNReg()
1688 Rd = Bits32(opcode, 2, 0); in EmulateMVNReg()
1689 Rm = Bits32(opcode, 5, 3); in EmulateMVNReg()
1697 Rd = Bits32(opcode, 11, 8); in EmulateMVNReg()
1698 Rm = Bits32(opcode, 3, 0); in EmulateMVNReg()
1699 setflags = BitIsSet(opcode, 20); in EmulateMVNReg()
1700 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateMVNReg()
1706 Rd = Bits32(opcode, 15, 12); in EmulateMVNReg()
1707 Rm = Bits32(opcode, 3, 0); in EmulateMVNReg()
1708 setflags = BitIsSet(opcode, 20); in EmulateMVNReg()
1709 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateMVNReg()
1739 bool EmulateInstructionARM::EmulateLDRRtPCRelative(const uint32_t opcode, in EmulateLDRRtPCRelative() argument
1761 if (ConditionPassed(opcode)) { in EmulateLDRRtPCRelative()
1782 Rt = Bits32(opcode, 10, 8); in EmulateLDRRtPCRelative()
1783 imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32); in EmulateLDRRtPCRelative()
1787 Rt = Bits32(opcode, 15, 12); in EmulateLDRRtPCRelative()
1788 imm32 = Bits32(opcode, 11, 0) << 2; // imm32 = ZeroExtend(imm12, 32); in EmulateLDRRtPCRelative()
1789 add = BitIsSet(opcode, 23); in EmulateLDRRtPCRelative()
1827 bool EmulateInstructionARM::EmulateADDSPImm(const uint32_t opcode, in EmulateADDSPImm() argument
1849 if (ConditionPassed(opcode)) { in EmulateADDSPImm()
1859 d = Bits32(opcode, 10, 8); in EmulateADDSPImm()
1860 imm32 = (Bits32(opcode, 7, 0) << 2); in EmulateADDSPImm()
1867 imm32 = ThumbImm7Scaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32) in EmulateADDSPImm()
1874 d = Bits32(opcode, 11, 8); in EmulateADDSPImm()
1875 imm32 = ThumbExpandImm(opcode); in EmulateADDSPImm()
1876 setflags = Bit32(opcode, 20); in EmulateADDSPImm()
1890 d = Bits32(opcode, 11, 8); in EmulateADDSPImm()
1892 uint32_t i = Bit32(opcode, 26); in EmulateADDSPImm()
1893 uint32_t imm3 = Bits32(opcode, 14, 12); in EmulateADDSPImm()
1894 uint32_t imm8 = Bits32(opcode, 7, 0); in EmulateADDSPImm()
1938 bool EmulateInstructionARM::EmulateADDSPRm(const uint32_t opcode, in EmulateADDSPRm() argument
1961 if (ConditionPassed(opcode)) { in EmulateADDSPRm()
1968 Rm = Bits32(opcode, 6, 3); in EmulateADDSPRm()
1998 bool EmulateInstructionARM::EmulateBLXImmediate(const uint32_t opcode, in EmulateBLXImmediate() argument
2020 if (ConditionPassed(opcode)) { in EmulateBLXImmediate()
2032 uint32_t S = Bit32(opcode, 26); in EmulateBLXImmediate()
2033 uint32_t imm10 = Bits32(opcode, 25, 16); in EmulateBLXImmediate()
2034 uint32_t J1 = Bit32(opcode, 13); in EmulateBLXImmediate()
2035 uint32_t J2 = Bit32(opcode, 11); in EmulateBLXImmediate()
2036 uint32_t imm11 = Bits32(opcode, 10, 0); in EmulateBLXImmediate()
2051 uint32_t S = Bit32(opcode, 26); in EmulateBLXImmediate()
2052 uint32_t imm10H = Bits32(opcode, 25, 16); in EmulateBLXImmediate()
2053 uint32_t J1 = Bit32(opcode, 13); in EmulateBLXImmediate()
2054 uint32_t J2 = Bit32(opcode, 11); in EmulateBLXImmediate()
2055 uint32_t imm10L = Bits32(opcode, 10, 1); in EmulateBLXImmediate()
2070 imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2); in EmulateBLXImmediate()
2077 imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2 | in EmulateBLXImmediate()
2078 Bits32(opcode, 24, 24) << 1); in EmulateBLXImmediate()
2102 bool EmulateInstructionARM::EmulateBLXRm(const uint32_t opcode, in EmulateBLXRm() argument
2122 if (ConditionPassed(opcode)) { in EmulateBLXRm()
2133 Rm = Bits32(opcode, 6, 3); in EmulateBLXRm()
2142 Rm = Bits32(opcode, 3, 0); in EmulateBLXRm()
2167 bool EmulateInstructionARM::EmulateBXRm(const uint32_t opcode, in EmulateBXRm() argument
2178 if (ConditionPassed(opcode)) { in EmulateBXRm()
2184 Rm = Bits32(opcode, 6, 3); in EmulateBXRm()
2189 Rm = Bits32(opcode, 3, 0); in EmulateBXRm()
2215 bool EmulateInstructionARM::EmulateBXJRm(const uint32_t opcode, in EmulateBXJRm() argument
2232 if (ConditionPassed(opcode)) { in EmulateBXJRm()
2238 Rm = Bits32(opcode, 19, 16); in EmulateBXJRm()
2245 Rm = Bits32(opcode, 3, 0); in EmulateBXJRm()
2268 bool EmulateInstructionARM::EmulateSUBR7IPImm(const uint32_t opcode, in EmulateSUBR7IPImm() argument
2288 if (ConditionPassed(opcode)) { in EmulateSUBR7IPImm()
2296 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateSUBR7IPImm()
2318 bool EmulateInstructionARM::EmulateSUBIPSPImm(const uint32_t opcode, in EmulateSUBIPSPImm() argument
2338 if (ConditionPassed(opcode)) { in EmulateSUBIPSPImm()
2346 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateSUBIPSPImm()
2371 bool EmulateInstructionARM::EmulateSUBSPImm(const uint32_t opcode, in EmulateSUBSPImm() argument
2392 if (ConditionPassed(opcode)) { in EmulateSUBSPImm()
2404 imm32 = ThumbImm7Scaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32) in EmulateSUBSPImm()
2407 Rd = Bits32(opcode, 11, 8); in EmulateSUBSPImm()
2408 setflags = BitIsSet(opcode, 20); in EmulateSUBSPImm()
2409 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) in EmulateSUBSPImm()
2411 return EmulateCMPImm(opcode, eEncodingT2); in EmulateSUBSPImm()
2416 Rd = Bits32(opcode, 11, 8); in EmulateSUBSPImm()
2418 imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32) in EmulateSUBSPImm()
2423 Rd = Bits32(opcode, 15, 12); in EmulateSUBSPImm()
2424 setflags = BitIsSet(opcode, 20); in EmulateSUBSPImm()
2425 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateSUBSPImm()
2430 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateSUBSPImm()
2457 bool EmulateInstructionARM::EmulateSTRRtSP(const uint32_t opcode, in EmulateSTRRtSP() argument
2472 if (ConditionPassed(opcode)) { in EmulateSTRRtSP()
2487 Rt = Bits32(opcode, 15, 12); in EmulateSTRRtSP()
2488 imm12 = Bits32(opcode, 11, 0); in EmulateSTRRtSP()
2489 Rn = Bits32(opcode, 19, 16); in EmulateSTRRtSP()
2494 index = BitIsSet(opcode, 24); in EmulateSTRRtSP()
2495 add = BitIsSet(opcode, 23); in EmulateSTRRtSP()
2496 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21)); in EmulateSTRRtSP()
2551 bool EmulateInstructionARM::EmulateVPUSH(const uint32_t opcode, in EmulateVPUSH() argument
2574 if (ConditionPassed(opcode)) { in EmulateVPUSH()
2587 d = Bit32(opcode, 22) << 4 | Bits32(opcode, 15, 12); in EmulateVPUSH()
2588 imm32 = Bits32(opcode, 7, 0) * addr_byte_size; in EmulateVPUSH()
2590 regs = Bits32(opcode, 7, 0) / 2; in EmulateVPUSH()
2598 d = Bits32(opcode, 15, 12) << 1 | Bit32(opcode, 22); in EmulateVPUSH()
2599 imm32 = Bits32(opcode, 7, 0) * addr_byte_size; in EmulateVPUSH()
2600 regs = Bits32(opcode, 7, 0); in EmulateVPUSH()
2644 bool EmulateInstructionARM::EmulateVPOP(const uint32_t opcode, in EmulateVPOP() argument
2666 if (ConditionPassed(opcode)) { in EmulateVPOP()
2679 d = Bit32(opcode, 22) << 4 | Bits32(opcode, 15, 12); in EmulateVPOP()
2680 imm32 = Bits32(opcode, 7, 0) * addr_byte_size; in EmulateVPOP()
2682 regs = Bits32(opcode, 7, 0) / 2; in EmulateVPOP()
2690 d = Bits32(opcode, 15, 12) << 1 | Bit32(opcode, 22); in EmulateVPOP()
2691 imm32 = Bits32(opcode, 7, 0) * addr_byte_size; in EmulateVPOP()
2692 regs = Bits32(opcode, 7, 0); in EmulateVPOP()
2733 bool EmulateInstructionARM::EmulateSVC(const uint32_t opcode, in EmulateSVC() argument
2746 if (ConditionPassed(opcode)) { in EmulateSVC()
2756 imm32 = Bits32(opcode, 7, 0); in EmulateSVC()
2761 imm32 = Bits32(opcode, 23, 0); in EmulateSVC()
2779 bool EmulateInstructionARM::EmulateIT(const uint32_t opcode, in EmulateIT() argument
2787 m_it_session.InitIT(Bits32(opcode, 7, 0)); in EmulateIT()
2791 bool EmulateInstructionARM::EmulateNop(const uint32_t opcode, in EmulateNop() argument
2798 bool EmulateInstructionARM::EmulateB(const uint32_t opcode, in EmulateB() argument
2811 if (ConditionPassed(opcode)) { in EmulateB()
2822 imm32 = llvm::SignExtend32<9>(Bits32(opcode, 7, 0) << 1); in EmulateB()
2827 imm32 = llvm::SignExtend32<12>(Bits32(opcode, 10, 0) << 1); in EmulateB()
2834 if (Bits32(opcode, 25, 23) == 7) in EmulateB()
2838 uint32_t S = Bit32(opcode, 26); in EmulateB()
2839 uint32_t imm6 = Bits32(opcode, 21, 16); in EmulateB()
2840 uint32_t J1 = Bit32(opcode, 13); in EmulateB()
2841 uint32_t J2 = Bit32(opcode, 11); in EmulateB()
2842 uint32_t imm11 = Bits32(opcode, 10, 0); in EmulateB()
2851 uint32_t S = Bit32(opcode, 26); in EmulateB()
2852 uint32_t imm10 = Bits32(opcode, 25, 16); in EmulateB()
2853 uint32_t J1 = Bit32(opcode, 13); in EmulateB()
2854 uint32_t J2 = Bit32(opcode, 11); in EmulateB()
2855 uint32_t imm11 = Bits32(opcode, 10, 0); in EmulateB()
2866 imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2); in EmulateB()
2882 bool EmulateInstructionARM::EmulateCB(const uint32_t opcode, in EmulateCB() argument
2894 uint32_t reg_val = ReadCoreReg(Bits32(opcode, 2, 0), &success); in EmulateCB()
2909 imm32 = Bit32(opcode, 9) << 6 | Bits32(opcode, 7, 3) << 1; in EmulateCB()
2910 nonzero = BitIsSet(opcode, 11); in EmulateCB()
2936 bool EmulateInstructionARM::EmulateTB(const uint32_t opcode, in EmulateTB() argument
2950 if (ConditionPassed(opcode)) { in EmulateTB()
2958 Rn = Bits32(opcode, 19, 16); in EmulateTB()
2959 Rm = Bits32(opcode, 3, 0); in EmulateTB()
2960 is_tbh = BitIsSet(opcode, 4); in EmulateTB()
3010 bool EmulateInstructionARM::EmulateADDImmThumb(const uint32_t opcode, in EmulateADDImmThumb() argument
3026 if (ConditionPassed(opcode)) { in EmulateADDImmThumb()
3038 d = Bits32(opcode, 2, 0); in EmulateADDImmThumb()
3039 n = Bits32(opcode, 5, 3); in EmulateADDImmThumb()
3041 imm32 = Bits32(opcode, 8, 6); in EmulateADDImmThumb()
3048 d = Bits32(opcode, 10, 8); in EmulateADDImmThumb()
3049 n = Bits32(opcode, 10, 8); in EmulateADDImmThumb()
3051 imm32 = Bits32(opcode, 7, 0); in EmulateADDImmThumb()
3059 d = Bits32(opcode, 11, 8); in EmulateADDImmThumb()
3060 n = Bits32(opcode, 19, 16); in EmulateADDImmThumb()
3061 setflags = BitIsSet(opcode, 20); in EmulateADDImmThumb()
3062 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry_out); in EmulateADDImmThumb()
3066 return EmulateADDSPImm(opcode, eEncodingT3); in EmulateADDImmThumb()
3078 d = Bits32(opcode, 11, 8); in EmulateADDImmThumb()
3079 n = Bits32(opcode, 19, 16); in EmulateADDImmThumb()
3081 uint32_t i = Bit32(opcode, 26); in EmulateADDImmThumb()
3082 uint32_t imm3 = Bits32(opcode, 14, 12); in EmulateADDImmThumb()
3083 uint32_t imm8 = Bits32(opcode, 7, 0); in EmulateADDImmThumb()
3088 return EmulateADDSPImm(opcode, eEncodingT4); in EmulateADDImmThumb()
3131 bool EmulateInstructionARM::EmulateADDImmARM(const uint32_t opcode, in EmulateADDImmARM() argument
3151 if (ConditionPassed(opcode)) { in EmulateADDImmARM()
3158 Rd = Bits32(opcode, 15, 12); in EmulateADDImmARM()
3159 Rn = Bits32(opcode, 19, 16); in EmulateADDImmARM()
3160 setflags = BitIsSet(opcode, 20); in EmulateADDImmARM()
3161 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateADDImmARM()
3196 bool EmulateInstructionARM::EmulateADDReg(const uint32_t opcode, in EmulateADDReg() argument
3217 if (ConditionPassed(opcode)) { in EmulateADDReg()
3224 Rd = Bits32(opcode, 2, 0); in EmulateADDReg()
3225 Rn = Bits32(opcode, 5, 3); in EmulateADDReg()
3226 Rm = Bits32(opcode, 8, 6); in EmulateADDReg()
3232 Rd = Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0); in EmulateADDReg()
3233 Rm = Bits32(opcode, 6, 3); in EmulateADDReg()
3243 Rd = Bits32(opcode, 15, 12); in EmulateADDReg()
3244 Rn = Bits32(opcode, 19, 16); in EmulateADDReg()
3245 Rm = Bits32(opcode, 3, 0); in EmulateADDReg()
3246 setflags = BitIsSet(opcode, 20); in EmulateADDReg()
3247 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateADDReg()
3285 bool EmulateInstructionARM::EmulateCMNImm(const uint32_t opcode, in EmulateCMNImm() argument
3304 Rn = Bits32(opcode, 19, 16); in EmulateCMNImm()
3305 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) in EmulateCMNImm()
3310 Rn = Bits32(opcode, 19, 16); in EmulateCMNImm()
3311 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateCMNImm()
3332 bool EmulateInstructionARM::EmulateCMNReg(const uint32_t opcode, in EmulateCMNReg() argument
3354 Rn = Bits32(opcode, 2, 0); in EmulateCMNReg()
3355 Rm = Bits32(opcode, 5, 3); in EmulateCMNReg()
3360 Rn = Bits32(opcode, 19, 16); in EmulateCMNReg()
3361 Rm = Bits32(opcode, 3, 0); in EmulateCMNReg()
3362 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateCMNReg()
3368 Rn = Bits32(opcode, 19, 16); in EmulateCMNReg()
3369 Rm = Bits32(opcode, 3, 0); in EmulateCMNReg()
3370 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateCMNReg()
3398 bool EmulateInstructionARM::EmulateCMPImm(const uint32_t opcode, in EmulateCMPImm() argument
3417 Rn = Bits32(opcode, 10, 8); in EmulateCMPImm()
3418 imm32 = Bits32(opcode, 7, 0); in EmulateCMPImm()
3421 Rn = Bits32(opcode, 19, 16); in EmulateCMPImm()
3422 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) in EmulateCMPImm()
3427 Rn = Bits32(opcode, 19, 16); in EmulateCMPImm()
3428 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateCMPImm()
3449 bool EmulateInstructionARM::EmulateCMPReg(const uint32_t opcode, in EmulateCMPReg() argument
3471 Rn = Bits32(opcode, 2, 0); in EmulateCMPReg()
3472 Rm = Bits32(opcode, 5, 3); in EmulateCMPReg()
3477 Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0); in EmulateCMPReg()
3478 Rm = Bits32(opcode, 6, 3); in EmulateCMPReg()
3487 Rn = Bits32(opcode, 19, 16); in EmulateCMPReg()
3488 Rm = Bits32(opcode, 3, 0); in EmulateCMPReg()
3489 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateCMPReg()
3494 Rn = Bits32(opcode, 19, 16); in EmulateCMPReg()
3495 Rm = Bits32(opcode, 3, 0); in EmulateCMPReg()
3496 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateCMPReg()
3526 bool EmulateInstructionARM::EmulateASRImm(const uint32_t opcode, in EmulateASRImm() argument
3544 return EmulateShiftImm(opcode, encoding, SRType_ASR); in EmulateASRImm()
3552 bool EmulateInstructionARM::EmulateASRReg(const uint32_t opcode, in EmulateASRReg() argument
3568 return EmulateShiftReg(opcode, encoding, SRType_ASR); in EmulateASRReg()
3574 bool EmulateInstructionARM::EmulateLSLImm(const uint32_t opcode, in EmulateLSLImm() argument
3592 return EmulateShiftImm(opcode, encoding, SRType_LSL); in EmulateLSLImm()
3599 bool EmulateInstructionARM::EmulateLSLReg(const uint32_t opcode, in EmulateLSLReg() argument
3615 return EmulateShiftReg(opcode, encoding, SRType_LSL); in EmulateLSLReg()
3622 bool EmulateInstructionARM::EmulateLSRImm(const uint32_t opcode, in EmulateLSRImm() argument
3640 return EmulateShiftImm(opcode, encoding, SRType_LSR); in EmulateLSRImm()
3647 bool EmulateInstructionARM::EmulateLSRReg(const uint32_t opcode, in EmulateLSRReg() argument
3663 return EmulateShiftReg(opcode, encoding, SRType_LSR); in EmulateLSRReg()
3670 bool EmulateInstructionARM::EmulateRORImm(const uint32_t opcode, in EmulateRORImm() argument
3688 return EmulateShiftImm(opcode, encoding, SRType_ROR); in EmulateRORImm()
3696 bool EmulateInstructionARM::EmulateRORReg(const uint32_t opcode, in EmulateRORReg() argument
3712 return EmulateShiftReg(opcode, encoding, SRType_ROR); in EmulateRORReg()
3720 bool EmulateInstructionARM::EmulateRRX(const uint32_t opcode, in EmulateRRX() argument
3738 return EmulateShiftImm(opcode, encoding, SRType_RRX); in EmulateRRX()
3741 bool EmulateInstructionARM::EmulateShiftImm(const uint32_t opcode, in EmulateShiftImm() argument
3752 if (ConditionPassed(opcode)) { in EmulateShiftImm()
3771 Rd = Bits32(opcode, 2, 0); in EmulateShiftImm()
3772 Rm = Bits32(opcode, 5, 3); in EmulateShiftImm()
3774 imm5 = Bits32(opcode, 10, 6); in EmulateShiftImm()
3782 Rd = Bits32(opcode, 11, 8); in EmulateShiftImm()
3783 Rm = Bits32(opcode, 3, 0); in EmulateShiftImm()
3784 setflags = BitIsSet(opcode, 20); in EmulateShiftImm()
3785 imm5 = Bits32(opcode, 14, 12) << 2 | Bits32(opcode, 7, 6); in EmulateShiftImm()
3790 Rd = Bits32(opcode, 15, 12); in EmulateShiftImm()
3791 Rm = Bits32(opcode, 3, 0); in EmulateShiftImm()
3792 setflags = BitIsSet(opcode, 20); in EmulateShiftImm()
3793 imm5 = Bits32(opcode, 11, 7); in EmulateShiftImm()
3827 bool EmulateInstructionARM::EmulateShiftReg(const uint32_t opcode, in EmulateShiftReg() argument
3837 if (ConditionPassed(opcode)) { in EmulateShiftReg()
3846 Rd = Bits32(opcode, 2, 0); in EmulateShiftReg()
3848 Rm = Bits32(opcode, 5, 3); in EmulateShiftReg()
3852 Rd = Bits32(opcode, 11, 8); in EmulateShiftReg()
3853 Rn = Bits32(opcode, 19, 16); in EmulateShiftReg()
3854 Rm = Bits32(opcode, 3, 0); in EmulateShiftReg()
3855 setflags = BitIsSet(opcode, 20); in EmulateShiftReg()
3860 Rd = Bits32(opcode, 15, 12); in EmulateShiftReg()
3861 Rn = Bits32(opcode, 3, 0); in EmulateShiftReg()
3862 Rm = Bits32(opcode, 11, 8); in EmulateShiftReg()
3863 setflags = BitIsSet(opcode, 20); in EmulateShiftReg()
3901 bool EmulateInstructionARM::EmulateLDM(const uint32_t opcode, in EmulateLDM() argument
3921 if (ConditionPassed(opcode)) { in EmulateLDM()
3930 n = Bits32(opcode, 10, 8); in EmulateLDM()
3931 registers = Bits32(opcode, 7, 0); in EmulateLDM()
3941 n = Bits32(opcode, 19, 16); in EmulateLDM()
3942 registers = Bits32(opcode, 15, 0); in EmulateLDM()
3944 wback = BitIsSet(opcode, 21); in EmulateLDM()
3949 (BitIsSet(opcode, 14) && BitIsSet(opcode, 15))) in EmulateLDM()
3963 n = Bits32(opcode, 19, 16); in EmulateLDM()
3964 registers = Bits32(opcode, 15, 0); in EmulateLDM()
3965 wback = BitIsSet(opcode, 21); in EmulateLDM()
4044 bool EmulateInstructionARM::EmulateLDMDA(const uint32_t opcode, in EmulateLDMDA() argument
4065 if (ConditionPassed(opcode)) { in EmulateLDMDA()
4075 n = Bits32(opcode, 19, 16); in EmulateLDMDA()
4076 registers = Bits32(opcode, 15, 0); in EmulateLDMDA()
4077 wback = BitIsSet(opcode, 21); in EmulateLDMDA()
4159 bool EmulateInstructionARM::EmulateLDMDB(const uint32_t opcode, in EmulateLDMDB() argument
4179 if (ConditionPassed(opcode)) { in EmulateLDMDB()
4187 n = Bits32(opcode, 19, 16); in EmulateLDMDB()
4188 registers = Bits32(opcode, 15, 0); in EmulateLDMDB()
4190 wback = BitIsSet(opcode, 21); in EmulateLDMDB()
4195 (BitIsSet(opcode, 14) && BitIsSet(opcode, 15))) in EmulateLDMDB()
4211 n = Bits32(opcode, 19, 16); in EmulateLDMDB()
4212 registers = Bits32(opcode, 15, 0); in EmulateLDMDB()
4213 wback = BitIsSet(opcode, 21); in EmulateLDMDB()
4296 bool EmulateInstructionARM::EmulateLDMIB(const uint32_t opcode, in EmulateLDMIB() argument
4315 if (ConditionPassed(opcode)) { in EmulateLDMIB()
4323 n = Bits32(opcode, 19, 16); in EmulateLDMIB()
4324 registers = Bits32(opcode, 15, 0); in EmulateLDMIB()
4325 wback = BitIsSet(opcode, 21); in EmulateLDMIB()
4406 bool EmulateInstructionARM::EmulateLDRRtRnImm(const uint32_t opcode, in EmulateLDRRtRnImm() argument
4427 if (ConditionPassed(opcode)) { in EmulateLDRRtRnImm()
4437 Rt = Bits32(opcode, 2, 0); in EmulateLDRRtRnImm()
4438 Rn = Bits32(opcode, 5, 3); in EmulateLDRRtRnImm()
4439 imm32 = Bits32(opcode, 10, 6) << 2; // imm32 = ZeroExtend(imm5:'00', 32); in EmulateLDRRtRnImm()
4449 Rt = Bits32(opcode, 10, 8); in EmulateLDRRtRnImm()
4451 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateLDRRtRnImm()
4463 Rt = Bits32(opcode, 15, 12); in EmulateLDRRtRnImm()
4464 Rn = Bits32(opcode, 19, 16); in EmulateLDRRtRnImm()
4465 imm32 = Bits32(opcode, 11, 0); in EmulateLDRRtRnImm()
4484 if (BitIsClear(opcode, 10) && BitIsClear(opcode, 8)) in EmulateLDRRtRnImm()
4488 Rt = Bits32(opcode, 15, 12); in EmulateLDRRtRnImm()
4489 Rn = Bits32(opcode, 19, 16); in EmulateLDRRtRnImm()
4490 imm32 = Bits32(opcode, 7, 0); in EmulateLDRRtRnImm()
4493 index = BitIsSet(opcode, 10); in EmulateLDRRtRnImm()
4494 add = BitIsSet(opcode, 9); in EmulateLDRRtRnImm()
4495 wback = BitIsSet(opcode, 8); in EmulateLDRRtRnImm()
4569 bool EmulateInstructionARM::EmulateSTM(const uint32_t opcode, in EmulateSTM() argument
4591 if (ConditionPassed(opcode)) { in EmulateSTM()
4601 n = Bits32(opcode, 10, 8); in EmulateSTM()
4602 registers = Bits32(opcode, 7, 0); in EmulateSTM()
4614 n = Bits32(opcode, 19, 16); in EmulateSTM()
4615 registers = Bits32(opcode, 15, 0); in EmulateSTM()
4617 wback = BitIsSet(opcode, 21); in EmulateSTM()
4631 n = Bits32(opcode, 19, 16); in EmulateSTM()
4632 registers = Bits32(opcode, 15, 0); in EmulateSTM()
4633 wback = BitIsSet(opcode, 21); in EmulateSTM()
4721 bool EmulateInstructionARM::EmulateSTMDA(const uint32_t opcode, in EmulateSTMDA() argument
4744 if (ConditionPassed(opcode)) { in EmulateSTMDA()
4754 n = Bits32(opcode, 19, 16); in EmulateSTMDA()
4755 registers = Bits32(opcode, 15, 0); in EmulateSTMDA()
4756 wback = BitIsSet(opcode, 21); in EmulateSTMDA()
4843 bool EmulateInstructionARM::EmulateSTMDB(const uint32_t opcode, in EmulateSTMDB() argument
4866 if (ConditionPassed(opcode)) { in EmulateSTMDB()
4876 if ((BitIsSet(opcode, 21)) && (Bits32(opcode, 19, 16) == 13)) { in EmulateSTMDB()
4880 n = Bits32(opcode, 19, 16); in EmulateSTMDB()
4881 registers = Bits32(opcode, 15, 0); in EmulateSTMDB()
4883 wback = BitIsSet(opcode, 21); in EmulateSTMDB()
4895 if (BitIsSet(opcode, 21) && (Bits32(opcode, 19, 16) == 13) && in EmulateSTMDB()
4896 BitCount(Bits32(opcode, 15, 0)) >= 2) { in EmulateSTMDB()
4900 n = Bits32(opcode, 19, 16); in EmulateSTMDB()
4901 registers = Bits32(opcode, 15, 0); in EmulateSTMDB()
4902 wback = BitIsSet(opcode, 21); in EmulateSTMDB()
4992 bool EmulateInstructionARM::EmulateSTMIB(const uint32_t opcode, in EmulateSTMIB() argument
5015 if (ConditionPassed(opcode)) { in EmulateSTMIB()
5025 n = Bits32(opcode, 19, 16); in EmulateSTMIB()
5026 registers = Bits32(opcode, 15, 0); in EmulateSTMIB()
5027 wback = BitIsSet(opcode, 21); in EmulateSTMIB()
5114 bool EmulateInstructionARM::EmulateSTRThumb(const uint32_t opcode, in EmulateSTRThumb() argument
5130 if (ConditionPassed(opcode)) { in EmulateSTRThumb()
5143 t = Bits32(opcode, 2, 0); in EmulateSTRThumb()
5144 n = Bits32(opcode, 5, 3); in EmulateSTRThumb()
5145 imm32 = Bits32(opcode, 10, 6) << 2; in EmulateSTRThumb()
5155 t = Bits32(opcode, 10, 8); in EmulateSTRThumb()
5157 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateSTRThumb()
5167 if (Bits32(opcode, 19, 16) == 15) in EmulateSTRThumb()
5171 t = Bits32(opcode, 15, 12); in EmulateSTRThumb()
5172 n = Bits32(opcode, 19, 16); in EmulateSTRThumb()
5173 imm32 = Bits32(opcode, 11, 0); in EmulateSTRThumb()
5190 if ((Bits32(opcode, 19, 16) == 15) || in EmulateSTRThumb()
5191 (BitIsClear(opcode, 10) && BitIsClear(opcode, 8))) in EmulateSTRThumb()
5195 t = Bits32(opcode, 15, 12); in EmulateSTRThumb()
5196 n = Bits32(opcode, 19, 16); in EmulateSTRThumb()
5197 imm32 = Bits32(opcode, 7, 0); in EmulateSTRThumb()
5200 index = BitIsSet(opcode, 10); in EmulateSTRThumb()
5201 add = BitIsSet(opcode, 9); in EmulateSTRThumb()
5202 wback = BitIsSet(opcode, 8); in EmulateSTRThumb()
5281 bool EmulateInstructionARM::EmulateSTRRegister(const uint32_t opcode, in EmulateSTRRegister() argument
5302 if (ConditionPassed(opcode)) { in EmulateSTRRegister()
5320 t = Bits32(opcode, 2, 0); in EmulateSTRRegister()
5321 n = Bits32(opcode, 5, 3); in EmulateSTRRegister()
5322 m = Bits32(opcode, 8, 6); in EmulateSTRRegister()
5336 if (Bits32(opcode, 19, 16) == 15) in EmulateSTRRegister()
5340 t = Bits32(opcode, 15, 12); in EmulateSTRRegister()
5341 n = Bits32(opcode, 19, 16); in EmulateSTRRegister()
5342 m = Bits32(opcode, 3, 0); in EmulateSTRRegister()
5351 shift_n = Bits32(opcode, 5, 4); in EmulateSTRRegister()
5361 t = Bits32(opcode, 15, 12); in EmulateSTRRegister()
5362 n = Bits32(opcode, 19, 16); in EmulateSTRRegister()
5363 m = Bits32(opcode, 3, 0); in EmulateSTRRegister()
5367 index = BitIsSet(opcode, 24); in EmulateSTRRegister()
5368 add = BitIsSet(opcode, 23); in EmulateSTRRegister()
5369 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21)); in EmulateSTRRegister()
5372 uint32_t typ = Bits32(opcode, 6, 5); in EmulateSTRRegister()
5373 uint32_t imm5 = Bits32(opcode, 11, 7); in EmulateSTRRegister()
5470 bool EmulateInstructionARM::EmulateSTRBThumb(const uint32_t opcode, in EmulateSTRBThumb() argument
5483 if (ConditionPassed(opcode)) { in EmulateSTRBThumb()
5494 t = Bits32(opcode, 2, 0); in EmulateSTRBThumb()
5495 n = Bits32(opcode, 5, 3); in EmulateSTRBThumb()
5496 imm32 = Bits32(opcode, 10, 6); in EmulateSTRBThumb()
5506 if (Bits32(opcode, 19, 16) == 15) in EmulateSTRBThumb()
5510 t = Bits32(opcode, 15, 12); in EmulateSTRBThumb()
5511 n = Bits32(opcode, 19, 16); in EmulateSTRBThumb()
5512 imm32 = Bits32(opcode, 11, 0); in EmulateSTRBThumb()
5527 if (Bits32(opcode, 19, 16) == 15) in EmulateSTRBThumb()
5531 t = Bits32(opcode, 15, 12); in EmulateSTRBThumb()
5532 n = Bits32(opcode, 19, 16); in EmulateSTRBThumb()
5533 imm32 = Bits32(opcode, 7, 0); in EmulateSTRBThumb()
5536 index = BitIsSet(opcode, 10); in EmulateSTRBThumb()
5537 add = BitIsSet(opcode, 9); in EmulateSTRBThumb()
5538 wback = BitIsSet(opcode, 8); in EmulateSTRBThumb()
5606 bool EmulateInstructionARM::EmulateSTRHRegister(const uint32_t opcode, in EmulateSTRHRegister() argument
5623 if (ConditionPassed(opcode)) { in EmulateSTRHRegister()
5639 t = Bits32(opcode, 2, 0); in EmulateSTRHRegister()
5640 n = Bits32(opcode, 5, 3); in EmulateSTRHRegister()
5641 m = Bits32(opcode, 8, 6); in EmulateSTRHRegister()
5657 t = Bits32(opcode, 15, 12); in EmulateSTRHRegister()
5658 n = Bits32(opcode, 19, 16); in EmulateSTRHRegister()
5659 m = Bits32(opcode, 3, 0); in EmulateSTRHRegister()
5670 shift_n = Bits32(opcode, 5, 4); in EmulateSTRHRegister()
5681 t = Bits32(opcode, 15, 12); in EmulateSTRHRegister()
5682 n = Bits32(opcode, 19, 16); in EmulateSTRHRegister()
5683 m = Bits32(opcode, 3, 0); in EmulateSTRHRegister()
5687 index = BitIsSet(opcode, 24); in EmulateSTRHRegister()
5688 add = BitIsSet(opcode, 23); in EmulateSTRHRegister()
5689 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21)); in EmulateSTRHRegister()
5780 bool EmulateInstructionARM::EmulateADCImm(const uint32_t opcode, in EmulateADCImm() argument
5800 if (ConditionPassed(opcode)) { in EmulateADCImm()
5807 Rd = Bits32(opcode, 11, 8); in EmulateADCImm()
5808 Rn = Bits32(opcode, 19, 16); in EmulateADCImm()
5809 setflags = BitIsSet(opcode, 20); in EmulateADCImm()
5810 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) in EmulateADCImm()
5815 Rd = Bits32(opcode, 15, 12); in EmulateADCImm()
5816 Rn = Bits32(opcode, 19, 16); in EmulateADCImm()
5817 setflags = BitIsSet(opcode, 20); in EmulateADCImm()
5818 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateADCImm()
5821 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateADCImm()
5849 bool EmulateInstructionARM::EmulateADCReg(const uint32_t opcode, in EmulateADCReg() argument
5870 if (ConditionPassed(opcode)) { in EmulateADCReg()
5877 Rd = Rn = Bits32(opcode, 2, 0); in EmulateADCReg()
5878 Rm = Bits32(opcode, 5, 3); in EmulateADCReg()
5884 Rd = Bits32(opcode, 11, 8); in EmulateADCReg()
5885 Rn = Bits32(opcode, 19, 16); in EmulateADCReg()
5886 Rm = Bits32(opcode, 3, 0); in EmulateADCReg()
5887 setflags = BitIsSet(opcode, 20); in EmulateADCReg()
5888 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateADCReg()
5893 Rd = Bits32(opcode, 15, 12); in EmulateADCReg()
5894 Rn = Bits32(opcode, 19, 16); in EmulateADCReg()
5895 Rm = Bits32(opcode, 3, 0); in EmulateADCReg()
5896 setflags = BitIsSet(opcode, 20); in EmulateADCReg()
5897 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateADCReg()
5900 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateADCReg()
5934 bool EmulateInstructionARM::EmulateADR(const uint32_t opcode, in EmulateADR() argument
5949 if (ConditionPassed(opcode)) { in EmulateADR()
5955 Rd = Bits32(opcode, 10, 8); in EmulateADR()
5956 imm32 = ThumbImm8Scaled(opcode); // imm32 = ZeroExtend(imm8:'00', 32) in EmulateADR()
5961 Rd = Bits32(opcode, 11, 8); in EmulateADR()
5962 imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32) in EmulateADR()
5963 add = (Bits32(opcode, 24, 21) == 0); // 0b0000 => ADD; 0b0101 => SUB in EmulateADR()
5969 Rd = Bits32(opcode, 15, 12); in EmulateADR()
5970 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateADR()
5971 add = (Bits32(opcode, 24, 21) == 0x4); // 0b0100 => ADD; 0b0010 => SUB in EmulateADR()
5997 bool EmulateInstructionARM::EmulateANDImm(const uint32_t opcode, in EmulateANDImm() argument
6017 if (ConditionPassed(opcode)) { in EmulateANDImm()
6025 Rd = Bits32(opcode, 11, 8); in EmulateANDImm()
6026 Rn = Bits32(opcode, 19, 16); in EmulateANDImm()
6027 setflags = BitIsSet(opcode, 20); in EmulateANDImm()
6029 opcode, APSR_C, in EmulateANDImm()
6033 return EmulateTSTImm(opcode, eEncodingT1); in EmulateANDImm()
6038 Rd = Bits32(opcode, 15, 12); in EmulateANDImm()
6039 Rn = Bits32(opcode, 19, 16); in EmulateANDImm()
6040 setflags = BitIsSet(opcode, 20); in EmulateANDImm()
6042 ARMExpandImm_C(opcode, APSR_C, in EmulateANDImm()
6046 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateANDImm()
6072 bool EmulateInstructionARM::EmulateANDReg(const uint32_t opcode, in EmulateANDReg() argument
6093 if (ConditionPassed(opcode)) { in EmulateANDReg()
6101 Rd = Rn = Bits32(opcode, 2, 0); in EmulateANDReg()
6102 Rm = Bits32(opcode, 5, 3); in EmulateANDReg()
6108 Rd = Bits32(opcode, 11, 8); in EmulateANDReg()
6109 Rn = Bits32(opcode, 19, 16); in EmulateANDReg()
6110 Rm = Bits32(opcode, 3, 0); in EmulateANDReg()
6111 setflags = BitIsSet(opcode, 20); in EmulateANDReg()
6112 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateANDReg()
6115 return EmulateTSTReg(opcode, eEncodingT2); in EmulateANDReg()
6120 Rd = Bits32(opcode, 15, 12); in EmulateANDReg()
6121 Rn = Bits32(opcode, 19, 16); in EmulateANDReg()
6122 Rm = Bits32(opcode, 3, 0); in EmulateANDReg()
6123 setflags = BitIsSet(opcode, 20); in EmulateANDReg()
6124 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateANDReg()
6127 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateANDReg()
6162 bool EmulateInstructionARM::EmulateBICImm(const uint32_t opcode, in EmulateBICImm() argument
6182 if (ConditionPassed(opcode)) { in EmulateBICImm()
6190 Rd = Bits32(opcode, 11, 8); in EmulateBICImm()
6191 Rn = Bits32(opcode, 19, 16); in EmulateBICImm()
6192 setflags = BitIsSet(opcode, 20); in EmulateBICImm()
6194 opcode, APSR_C, in EmulateBICImm()
6200 Rd = Bits32(opcode, 15, 12); in EmulateBICImm()
6201 Rn = Bits32(opcode, 19, 16); in EmulateBICImm()
6202 setflags = BitIsSet(opcode, 20); in EmulateBICImm()
6204 ARMExpandImm_C(opcode, APSR_C, in EmulateBICImm()
6210 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateBICImm()
6237 bool EmulateInstructionARM::EmulateBICReg(const uint32_t opcode, in EmulateBICReg() argument
6258 if (ConditionPassed(opcode)) { in EmulateBICReg()
6266 Rd = Rn = Bits32(opcode, 2, 0); in EmulateBICReg()
6267 Rm = Bits32(opcode, 5, 3); in EmulateBICReg()
6273 Rd = Bits32(opcode, 11, 8); in EmulateBICReg()
6274 Rn = Bits32(opcode, 19, 16); in EmulateBICReg()
6275 Rm = Bits32(opcode, 3, 0); in EmulateBICReg()
6276 setflags = BitIsSet(opcode, 20); in EmulateBICReg()
6277 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateBICReg()
6282 Rd = Bits32(opcode, 15, 12); in EmulateBICReg()
6283 Rn = Bits32(opcode, 19, 16); in EmulateBICReg()
6284 Rm = Bits32(opcode, 3, 0); in EmulateBICReg()
6285 setflags = BitIsSet(opcode, 20); in EmulateBICReg()
6286 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateBICReg()
6291 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateBICReg()
6326 bool EmulateInstructionARM::EmulateLDRImmediateARM(const uint32_t opcode, in EmulateLDRImmediateARM() argument
6345 if (ConditionPassed(opcode)) { in EmulateLDRImmediateARM()
6362 t = Bits32(opcode, 15, 12); in EmulateLDRImmediateARM()
6363 n = Bits32(opcode, 19, 16); in EmulateLDRImmediateARM()
6364 imm32 = Bits32(opcode, 11, 0); in EmulateLDRImmediateARM()
6368 index = BitIsSet(opcode, 24); in EmulateLDRImmediateARM()
6369 add = BitIsSet(opcode, 23); in EmulateLDRImmediateARM()
6370 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21)); in EmulateLDRImmediateARM()
6462 bool EmulateInstructionARM::EmulateLDRRegister(const uint32_t opcode, in EmulateLDRRegister() argument
6485 if (ConditionPassed(opcode)) { in EmulateLDRRegister()
6502 t = Bits32(opcode, 2, 0); in EmulateLDRRegister()
6503 n = Bits32(opcode, 5, 3); in EmulateLDRRegister()
6504 m = Bits32(opcode, 8, 6); in EmulateLDRRegister()
6520 t = Bits32(opcode, 15, 12); in EmulateLDRRegister()
6521 n = Bits32(opcode, 19, 16); in EmulateLDRRegister()
6522 m = Bits32(opcode, 3, 0); in EmulateLDRRegister()
6531 shift_n = Bits32(opcode, 5, 4); in EmulateLDRRegister()
6546 t = Bits32(opcode, 15, 12); in EmulateLDRRegister()
6547 n = Bits32(opcode, 19, 16); in EmulateLDRRegister()
6548 m = Bits32(opcode, 3, 0); in EmulateLDRRegister()
6552 index = BitIsSet(opcode, 24); in EmulateLDRRegister()
6553 add = BitIsSet(opcode, 23); in EmulateLDRRegister()
6554 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21)); in EmulateLDRRegister()
6557 uint32_t type = Bits32(opcode, 6, 5); in EmulateLDRRegister()
6558 uint32_t imm5 = Bits32(opcode, 11, 7); in EmulateLDRRegister()
6668 bool EmulateInstructionARM::EmulateLDRBImmediate(const uint32_t opcode, in EmulateLDRBImmediate() argument
6681 if (ConditionPassed(opcode)) { in EmulateLDRBImmediate()
6693 t = Bits32(opcode, 2, 0); in EmulateLDRBImmediate()
6694 n = Bits32(opcode, 5, 3); in EmulateLDRBImmediate()
6695 imm32 = Bits32(opcode, 10, 6); in EmulateLDRBImmediate()
6706 t = Bits32(opcode, 15, 12); in EmulateLDRBImmediate()
6707 n = Bits32(opcode, 19, 16); in EmulateLDRBImmediate()
6708 imm32 = Bits32(opcode, 11, 0); in EmulateLDRBImmediate()
6721 return EmulateLDRBLiteral(opcode, eEncodingT1); in EmulateLDRBImmediate()
6732 if (BitIsClear(opcode, 10) && BitIsClear(opcode, 8)) in EmulateLDRBImmediate()
6736 t = Bits32(opcode, 15, 12); in EmulateLDRBImmediate()
6737 n = Bits32(opcode, 19, 16); in EmulateLDRBImmediate()
6738 imm32 = Bits32(opcode, 7, 0); in EmulateLDRBImmediate()
6741 index = BitIsSet(opcode, 10); in EmulateLDRBImmediate()
6742 add = BitIsSet(opcode, 9); in EmulateLDRBImmediate()
6743 wback = BitIsSet(opcode, 8); in EmulateLDRBImmediate()
6751 return EmulateLDRBLiteral(opcode, eEncodingT1); in EmulateLDRBImmediate()
6815 bool EmulateInstructionARM::EmulateLDRBLiteral(const uint32_t opcode, in EmulateLDRBLiteral() argument
6827 if (ConditionPassed(opcode)) { in EmulateLDRBLiteral()
6834 t = Bits32(opcode, 15, 12); in EmulateLDRBLiteral()
6835 imm32 = Bits32(opcode, 11, 0); in EmulateLDRBLiteral()
6836 add = BitIsSet(opcode, 23); in EmulateLDRBLiteral()
6850 t = Bits32(opcode, 15, 12); in EmulateLDRBLiteral()
6851 imm32 = Bits32(opcode, 11, 0); in EmulateLDRBLiteral()
6852 add = BitIsSet(opcode, 23); in EmulateLDRBLiteral()
6896 bool EmulateInstructionARM::EmulateLDRBRegister(const uint32_t opcode, in EmulateLDRBRegister() argument
6910 if (ConditionPassed(opcode)) { in EmulateLDRBRegister()
6924 t = Bits32(opcode, 2, 0); in EmulateLDRBRegister()
6925 n = Bits32(opcode, 5, 3); in EmulateLDRBRegister()
6926 m = Bits32(opcode, 8, 6); in EmulateLDRBRegister()
6940 t = Bits32(opcode, 15, 12); in EmulateLDRBRegister()
6941 n = Bits32(opcode, 19, 16); in EmulateLDRBRegister()
6942 m = Bits32(opcode, 3, 0); in EmulateLDRBRegister()
6951 shift_n = Bits32(opcode, 5, 4); in EmulateLDRBRegister()
6959 return EmulateLDRBLiteral(opcode, eEncodingT1); in EmulateLDRBRegister()
6969 t = Bits32(opcode, 15, 12); in EmulateLDRBRegister()
6970 n = Bits32(opcode, 19, 16); in EmulateLDRBRegister()
6971 m = Bits32(opcode, 3, 0); in EmulateLDRBRegister()
6975 index = BitIsSet(opcode, 24); in EmulateLDRBRegister()
6976 add = BitIsSet(opcode, 23); in EmulateLDRBRegister()
6977 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21)); in EmulateLDRBRegister()
6980 uint32_t type = Bits32(opcode, 6, 5); in EmulateLDRBRegister()
6981 uint32_t imm5 = Bits32(opcode, 11, 7); in EmulateLDRBRegister()
7058 bool EmulateInstructionARM::EmulateLDRHImmediate(const uint32_t opcode, in EmulateLDRHImmediate() argument
7075 if (ConditionPassed(opcode)) { in EmulateLDRHImmediate()
7087 t = Bits32(opcode, 2, 0); in EmulateLDRHImmediate()
7088 n = Bits32(opcode, 5, 3); in EmulateLDRHImmediate()
7089 imm32 = Bits32(opcode, 10, 6) << 1; in EmulateLDRHImmediate()
7102 t = Bits32(opcode, 15, 12); in EmulateLDRHImmediate()
7103 n = Bits32(opcode, 19, 16); in EmulateLDRHImmediate()
7104 imm32 = Bits32(opcode, 11, 0); in EmulateLDRHImmediate()
7122 if (BitIsClear(opcode, 10) && BitIsClear(opcode, 8)) in EmulateLDRHImmediate()
7126 t = Bits32(opcode, 15, 12); in EmulateLDRHImmediate()
7127 n = Bits32(opcode, 19, 16); in EmulateLDRHImmediate()
7128 imm32 = Bits32(opcode, 7, 0); in EmulateLDRHImmediate()
7131 index = BitIsSet(opcode, 10); in EmulateLDRHImmediate()
7132 add = BitIsSet(opcode, 9); in EmulateLDRHImmediate()
7133 wback = BitIsSet(opcode, 8); in EmulateLDRHImmediate()
7205 bool EmulateInstructionARM::EmulateLDRHLiteral(const uint32_t opcode, in EmulateLDRHLiteral() argument
7221 if (ConditionPassed(opcode)) { in EmulateLDRHLiteral()
7231 t = Bits32(opcode, 15, 12); in EmulateLDRHLiteral()
7232 imm32 = Bits32(opcode, 11, 0); in EmulateLDRHLiteral()
7233 add = BitIsSet(opcode, 23); in EmulateLDRHLiteral()
7242 uint32_t imm4H = Bits32(opcode, 11, 8); in EmulateLDRHLiteral()
7243 uint32_t imm4L = Bits32(opcode, 3, 0); in EmulateLDRHLiteral()
7246 t = Bits32(opcode, 15, 12); in EmulateLDRHLiteral()
7248 add = BitIsSet(opcode, 23); in EmulateLDRHLiteral()
7309 bool EmulateInstructionARM::EmulateLDRHRegister(const uint32_t opcode, in EmulateLDRHRegister() argument
7327 if (ConditionPassed(opcode)) { in EmulateLDRHRegister()
7343 t = Bits32(opcode, 2, 0); in EmulateLDRHRegister()
7344 n = Bits32(opcode, 5, 3); in EmulateLDRHRegister()
7345 m = Bits32(opcode, 8, 6); in EmulateLDRHRegister()
7362 t = Bits32(opcode, 15, 12); in EmulateLDRHRegister()
7363 n = Bits32(opcode, 19, 16); in EmulateLDRHRegister()
7364 m = Bits32(opcode, 3, 0); in EmulateLDRHRegister()
7373 shift_n = Bits32(opcode, 5, 4); in EmulateLDRHRegister()
7383 t = Bits32(opcode, 15, 12); in EmulateLDRHRegister()
7384 n = Bits32(opcode, 19, 16); in EmulateLDRHRegister()
7385 m = Bits32(opcode, 3, 0); in EmulateLDRHRegister()
7389 index = BitIsSet(opcode, 24); in EmulateLDRHRegister()
7390 add = BitIsSet(opcode, 23); in EmulateLDRHRegister()
7391 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21)); in EmulateLDRHRegister()
7485 bool EmulateInstructionARM::EmulateLDRSBImmediate(const uint32_t opcode, in EmulateLDRSBImmediate() argument
7498 if (ConditionPassed(opcode)) { in EmulateLDRSBImmediate()
7512 t = Bits32(opcode, 15, 12); in EmulateLDRSBImmediate()
7513 n = Bits32(opcode, 19, 16); in EmulateLDRSBImmediate()
7514 imm32 = Bits32(opcode, 11, 0); in EmulateLDRSBImmediate()
7532 if (BitIsClear(opcode, 10) && BitIsClear(opcode, 8)) in EmulateLDRSBImmediate()
7536 t = Bits32(opcode, 15, 12); in EmulateLDRSBImmediate()
7537 n = Bits32(opcode, 19, 16); in EmulateLDRSBImmediate()
7538 imm32 = Bits32(opcode, 7, 0); in EmulateLDRSBImmediate()
7541 index = BitIsSet(opcode, 10); in EmulateLDRSBImmediate()
7542 add = BitIsSet(opcode, 9); in EmulateLDRSBImmediate()
7543 wback = BitIsSet(opcode, 8); in EmulateLDRSBImmediate()
7547 ((t == 15) && (BitIsClear(opcode, 10) || BitIsSet(opcode, 9) || in EmulateLDRSBImmediate()
7548 BitIsSet(opcode, 8)))) || in EmulateLDRSBImmediate()
7558 t = Bits32(opcode, 15, 12); in EmulateLDRSBImmediate()
7559 n = Bits32(opcode, 19, 16); in EmulateLDRSBImmediate()
7561 uint32_t imm4H = Bits32(opcode, 11, 8); in EmulateLDRSBImmediate()
7562 uint32_t imm4L = Bits32(opcode, 3, 0); in EmulateLDRSBImmediate()
7567 index = BitIsSet(opcode, 24); in EmulateLDRSBImmediate()
7568 add = BitIsSet(opcode, 23); in EmulateLDRSBImmediate()
7569 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21)); in EmulateLDRSBImmediate()
7634 bool EmulateInstructionARM::EmulateLDRSBLiteral(const uint32_t opcode, in EmulateLDRSBLiteral() argument
7646 if (ConditionPassed(opcode)) { in EmulateLDRSBLiteral()
7656 t = Bits32(opcode, 15, 12); in EmulateLDRSBLiteral()
7657 imm32 = Bits32(opcode, 11, 0); in EmulateLDRSBLiteral()
7658 add = BitIsSet(opcode, 23); in EmulateLDRSBLiteral()
7668 t = Bits32(opcode, 15, 12); in EmulateLDRSBLiteral()
7669 uint32_t imm4H = Bits32(opcode, 11, 8); in EmulateLDRSBLiteral()
7670 uint32_t imm4L = Bits32(opcode, 3, 0); in EmulateLDRSBLiteral()
7672 add = BitIsSet(opcode, 23); in EmulateLDRSBLiteral()
7722 bool EmulateInstructionARM::EmulateLDRSBRegister(const uint32_t opcode, in EmulateLDRSBRegister() argument
7736 if (ConditionPassed(opcode)) { in EmulateLDRSBRegister()
7750 t = Bits32(opcode, 2, 0); in EmulateLDRSBRegister()
7751 n = Bits32(opcode, 5, 3); in EmulateLDRSBRegister()
7752 m = Bits32(opcode, 8, 6); in EmulateLDRSBRegister()
7769 t = Bits32(opcode, 15, 12); in EmulateLDRSBRegister()
7770 n = Bits32(opcode, 19, 16); in EmulateLDRSBRegister()
7771 m = Bits32(opcode, 3, 0); in EmulateLDRSBRegister()
7780 shift_n = Bits32(opcode, 5, 4); in EmulateLDRSBRegister()
7790 t = Bits32(opcode, 15, 12); in EmulateLDRSBRegister()
7791 n = Bits32(opcode, 19, 16); in EmulateLDRSBRegister()
7792 m = Bits32(opcode, 3, 0); in EmulateLDRSBRegister()
7796 index = BitIsSet(opcode, 24); in EmulateLDRSBRegister()
7797 add = BitIsSet(opcode, 23); in EmulateLDRSBRegister()
7798 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21); in EmulateLDRSBRegister()
7882 bool EmulateInstructionARM::EmulateLDRSHImmediate(const uint32_t opcode, in EmulateLDRSHImmediate() argument
7899 if (ConditionPassed(opcode)) { in EmulateLDRSHImmediate()
7913 t = Bits32(opcode, 15, 12); in EmulateLDRSHImmediate()
7914 n = Bits32(opcode, 19, 16); in EmulateLDRSHImmediate()
7915 imm32 = Bits32(opcode, 11, 0); in EmulateLDRSHImmediate()
7934 if (BitIsClear(opcode, 10) && BitIsClear(opcode, 8)) in EmulateLDRSHImmediate()
7938 t = Bits32(opcode, 15, 12); in EmulateLDRSHImmediate()
7939 n = Bits32(opcode, 19, 16); in EmulateLDRSHImmediate()
7940 imm32 = Bits32(opcode, 7, 0); in EmulateLDRSHImmediate()
7943 index = BitIsSet(opcode, 10); in EmulateLDRSHImmediate()
7944 add = BitIsSet(opcode, 9); in EmulateLDRSHImmediate()
7945 wback = BitIsSet(opcode, 8); in EmulateLDRSHImmediate()
7957 t = Bits32(opcode, 15, 12); in EmulateLDRSHImmediate()
7958 n = Bits32(opcode, 19, 16); in EmulateLDRSHImmediate()
7959 uint32_t imm4H = Bits32(opcode, 11, 8); in EmulateLDRSHImmediate()
7960 uint32_t imm4L = Bits32(opcode, 3, 0); in EmulateLDRSHImmediate()
7965 index = BitIsSet(opcode, 24); in EmulateLDRSHImmediate()
7966 add = BitIsSet(opcode, 23); in EmulateLDRSHImmediate()
7967 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21); in EmulateLDRSHImmediate()
8041 bool EmulateInstructionARM::EmulateLDRSHLiteral(const uint32_t opcode, in EmulateLDRSHLiteral() argument
8057 if (ConditionPassed(opcode)) { in EmulateLDRSHLiteral()
8067 t = Bits32(opcode, 15, 12); in EmulateLDRSHLiteral()
8068 imm32 = Bits32(opcode, 11, 0); in EmulateLDRSHLiteral()
8069 add = BitIsSet(opcode, 23); in EmulateLDRSHLiteral()
8079 t = Bits32(opcode, 15, 12); in EmulateLDRSHLiteral()
8080 uint32_t imm4H = Bits32(opcode, 11, 8); in EmulateLDRSHLiteral()
8081 uint32_t imm4L = Bits32(opcode, 3, 0); in EmulateLDRSHLiteral()
8083 add = BitIsSet(opcode, 23); in EmulateLDRSHLiteral()
8142 bool EmulateInstructionARM::EmulateLDRSHRegister(const uint32_t opcode, in EmulateLDRSHRegister() argument
8160 if (ConditionPassed(opcode)) { in EmulateLDRSHRegister()
8176 t = Bits32(opcode, 2, 0); in EmulateLDRSHRegister()
8177 n = Bits32(opcode, 5, 3); in EmulateLDRSHRegister()
8178 m = Bits32(opcode, 8, 6); in EmulateLDRSHRegister()
8195 t = Bits32(opcode, 15, 12); in EmulateLDRSHRegister()
8196 n = Bits32(opcode, 19, 16); in EmulateLDRSHRegister()
8197 m = Bits32(opcode, 3, 0); in EmulateLDRSHRegister()
8206 shift_n = Bits32(opcode, 5, 4); in EmulateLDRSHRegister()
8217 t = Bits32(opcode, 15, 12); in EmulateLDRSHRegister()
8218 n = Bits32(opcode, 19, 16); in EmulateLDRSHRegister()
8219 m = Bits32(opcode, 3, 0); in EmulateLDRSHRegister()
8223 index = BitIsSet(opcode, 24); in EmulateLDRSHRegister()
8224 add = BitIsSet(opcode, 23); in EmulateLDRSHRegister()
8225 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21); in EmulateLDRSHRegister()
8321 bool EmulateInstructionARM::EmulateSXTB(const uint32_t opcode, in EmulateSXTB() argument
8332 if (ConditionPassed(opcode)) { in EmulateSXTB()
8341 d = Bits32(opcode, 2, 0); in EmulateSXTB()
8342 m = Bits32(opcode, 5, 3); in EmulateSXTB()
8349 d = Bits32(opcode, 11, 8); in EmulateSXTB()
8350 m = Bits32(opcode, 3, 0); in EmulateSXTB()
8351 rotation = Bits32(opcode, 5, 4) << 3; in EmulateSXTB()
8361 d = Bits32(opcode, 15, 12); in EmulateSXTB()
8362 m = Bits32(opcode, 3, 0); in EmulateSXTB()
8363 rotation = Bits32(opcode, 11, 10) << 3; in EmulateSXTB()
8406 bool EmulateInstructionARM::EmulateSXTH(const uint32_t opcode, in EmulateSXTH() argument
8417 if (ConditionPassed(opcode)) { in EmulateSXTH()
8426 d = Bits32(opcode, 2, 0); in EmulateSXTH()
8427 m = Bits32(opcode, 5, 3); in EmulateSXTH()
8434 d = Bits32(opcode, 11, 8); in EmulateSXTH()
8435 m = Bits32(opcode, 3, 0); in EmulateSXTH()
8436 rotation = Bits32(opcode, 5, 4) << 3; in EmulateSXTH()
8446 d = Bits32(opcode, 15, 12); in EmulateSXTH()
8447 m = Bits32(opcode, 3, 0); in EmulateSXTH()
8448 rotation = Bits32(opcode, 11, 10) << 3; in EmulateSXTH()
8491 bool EmulateInstructionARM::EmulateUXTB(const uint32_t opcode, in EmulateUXTB() argument
8502 if (ConditionPassed(opcode)) { in EmulateUXTB()
8511 d = Bits32(opcode, 2, 0); in EmulateUXTB()
8512 m = Bits32(opcode, 5, 3); in EmulateUXTB()
8519 d = Bits32(opcode, 11, 8); in EmulateUXTB()
8520 m = Bits32(opcode, 3, 0); in EmulateUXTB()
8521 rotation = Bits32(opcode, 5, 4) << 3; in EmulateUXTB()
8531 d = Bits32(opcode, 15, 12); in EmulateUXTB()
8532 m = Bits32(opcode, 3, 0); in EmulateUXTB()
8533 rotation = Bits32(opcode, 11, 10) << 3; in EmulateUXTB()
8574 bool EmulateInstructionARM::EmulateUXTH(const uint32_t opcode, in EmulateUXTH() argument
8585 if (ConditionPassed(opcode)) { in EmulateUXTH()
8593 d = Bits32(opcode, 2, 0); in EmulateUXTH()
8594 m = Bits32(opcode, 5, 3); in EmulateUXTH()
8601 d = Bits32(opcode, 11, 8); in EmulateUXTH()
8602 m = Bits32(opcode, 3, 0); in EmulateUXTH()
8603 rotation = Bits32(opcode, 5, 4) << 3; in EmulateUXTH()
8613 d = Bits32(opcode, 15, 12); in EmulateUXTH()
8614 m = Bits32(opcode, 3, 0); in EmulateUXTH()
8615 rotation = Bits32(opcode, 11, 10) << 3; in EmulateUXTH()
8655 bool EmulateInstructionARM::EmulateRFE(const uint32_t opcode, in EmulateRFE() argument
8672 if (ConditionPassed(opcode)) { in EmulateRFE()
8683 n = Bits32(opcode, 19, 16); in EmulateRFE()
8684 wback = BitIsSet(opcode, 21); in EmulateRFE()
8700 n = Bits32(opcode, 19, 16); in EmulateRFE()
8701 wback = BitIsSet(opcode, 21); in EmulateRFE()
8717 n = Bits32(opcode, 19, 16); in EmulateRFE()
8720 wback = BitIsSet(opcode, 21); in EmulateRFE()
8721 increment = BitIsSet(opcode, 23); in EmulateRFE()
8722 wordhigher = (Bit32(opcode, 24) == Bit32(opcode, 23)); in EmulateRFE()
8801 bool EmulateInstructionARM::EmulateEORImm(const uint32_t opcode, in EmulateEORImm() argument
8821 if (ConditionPassed(opcode)) { in EmulateEORImm()
8829 Rd = Bits32(opcode, 11, 8); in EmulateEORImm()
8830 Rn = Bits32(opcode, 19, 16); in EmulateEORImm()
8831 setflags = BitIsSet(opcode, 20); in EmulateEORImm()
8833 opcode, APSR_C, in EmulateEORImm()
8837 return EmulateTEQImm(opcode, eEncodingT1); in EmulateEORImm()
8842 Rd = Bits32(opcode, 15, 12); in EmulateEORImm()
8843 Rn = Bits32(opcode, 19, 16); in EmulateEORImm()
8844 setflags = BitIsSet(opcode, 20); in EmulateEORImm()
8846 ARMExpandImm_C(opcode, APSR_C, in EmulateEORImm()
8852 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateEORImm()
8879 bool EmulateInstructionARM::EmulateEORReg(const uint32_t opcode, in EmulateEORReg() argument
8900 if (ConditionPassed(opcode)) { in EmulateEORReg()
8908 Rd = Rn = Bits32(opcode, 2, 0); in EmulateEORReg()
8909 Rm = Bits32(opcode, 5, 3); in EmulateEORReg()
8915 Rd = Bits32(opcode, 11, 8); in EmulateEORReg()
8916 Rn = Bits32(opcode, 19, 16); in EmulateEORReg()
8917 Rm = Bits32(opcode, 3, 0); in EmulateEORReg()
8918 setflags = BitIsSet(opcode, 20); in EmulateEORReg()
8919 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateEORReg()
8922 return EmulateTEQReg(opcode, eEncodingT1); in EmulateEORReg()
8927 Rd = Bits32(opcode, 15, 12); in EmulateEORReg()
8928 Rn = Bits32(opcode, 19, 16); in EmulateEORReg()
8929 Rm = Bits32(opcode, 3, 0); in EmulateEORReg()
8930 setflags = BitIsSet(opcode, 20); in EmulateEORReg()
8931 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateEORReg()
8936 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateEORReg()
8970 bool EmulateInstructionARM::EmulateORRImm(const uint32_t opcode, in EmulateORRImm() argument
8990 if (ConditionPassed(opcode)) { in EmulateORRImm()
8998 Rd = Bits32(opcode, 11, 8); in EmulateORRImm()
8999 Rn = Bits32(opcode, 19, 16); in EmulateORRImm()
9000 setflags = BitIsSet(opcode, 20); in EmulateORRImm()
9002 opcode, APSR_C, in EmulateORRImm()
9006 return EmulateMOVRdImm(opcode, eEncodingT2); in EmulateORRImm()
9011 Rd = Bits32(opcode, 15, 12); in EmulateORRImm()
9012 Rn = Bits32(opcode, 19, 16); in EmulateORRImm()
9013 setflags = BitIsSet(opcode, 20); in EmulateORRImm()
9015 ARMExpandImm_C(opcode, APSR_C, in EmulateORRImm()
9019 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateORRImm()
9046 bool EmulateInstructionARM::EmulateORRReg(const uint32_t opcode, in EmulateORRReg() argument
9067 if (ConditionPassed(opcode)) { in EmulateORRReg()
9075 Rd = Rn = Bits32(opcode, 2, 0); in EmulateORRReg()
9076 Rm = Bits32(opcode, 5, 3); in EmulateORRReg()
9082 Rd = Bits32(opcode, 11, 8); in EmulateORRReg()
9083 Rn = Bits32(opcode, 19, 16); in EmulateORRReg()
9084 Rm = Bits32(opcode, 3, 0); in EmulateORRReg()
9085 setflags = BitIsSet(opcode, 20); in EmulateORRReg()
9086 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateORRReg()
9089 return EmulateMOVRdRm(opcode, eEncodingT3); in EmulateORRReg()
9094 Rd = Bits32(opcode, 15, 12); in EmulateORRReg()
9095 Rn = Bits32(opcode, 19, 16); in EmulateORRReg()
9096 Rm = Bits32(opcode, 3, 0); in EmulateORRReg()
9097 setflags = BitIsSet(opcode, 20); in EmulateORRReg()
9098 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateORRReg()
9101 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateORRReg()
9135 bool EmulateInstructionARM::EmulateRSBImm(const uint32_t opcode, in EmulateRSBImm() argument
9162 Rd = Bits32(opcode, 2, 0); in EmulateRSBImm()
9163 Rn = Bits32(opcode, 5, 3); in EmulateRSBImm()
9168 Rd = Bits32(opcode, 11, 8); in EmulateRSBImm()
9169 Rn = Bits32(opcode, 19, 16); in EmulateRSBImm()
9170 setflags = BitIsSet(opcode, 20); in EmulateRSBImm()
9171 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) in EmulateRSBImm()
9176 Rd = Bits32(opcode, 15, 12); in EmulateRSBImm()
9177 Rn = Bits32(opcode, 19, 16); in EmulateRSBImm()
9178 setflags = BitIsSet(opcode, 20); in EmulateRSBImm()
9179 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateRSBImm()
9184 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateRSBImm()
9207 bool EmulateInstructionARM::EmulateRSBReg(const uint32_t opcode, in EmulateRSBReg() argument
9236 Rd = Bits32(opcode, 11, 8); in EmulateRSBReg()
9237 Rn = Bits32(opcode, 19, 16); in EmulateRSBReg()
9238 Rm = Bits32(opcode, 3, 0); in EmulateRSBReg()
9239 setflags = BitIsSet(opcode, 20); in EmulateRSBReg()
9240 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateRSBReg()
9246 Rd = Bits32(opcode, 15, 12); in EmulateRSBReg()
9247 Rn = Bits32(opcode, 19, 16); in EmulateRSBReg()
9248 Rm = Bits32(opcode, 3, 0); in EmulateRSBReg()
9249 setflags = BitIsSet(opcode, 20); in EmulateRSBReg()
9250 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateRSBReg()
9255 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateRSBReg()
9286 bool EmulateInstructionARM::EmulateRSCImm(const uint32_t opcode, in EmulateRSCImm() argument
9313 Rd = Bits32(opcode, 15, 12); in EmulateRSCImm()
9314 Rn = Bits32(opcode, 19, 16); in EmulateRSCImm()
9315 setflags = BitIsSet(opcode, 20); in EmulateRSCImm()
9316 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateRSCImm()
9321 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateRSCImm()
9345 bool EmulateInstructionARM::EmulateRSCReg(const uint32_t opcode, in EmulateRSCReg() argument
9374 Rd = Bits32(opcode, 15, 12); in EmulateRSCReg()
9375 Rn = Bits32(opcode, 19, 16); in EmulateRSCReg()
9376 Rm = Bits32(opcode, 3, 0); in EmulateRSCReg()
9377 setflags = BitIsSet(opcode, 20); in EmulateRSCReg()
9378 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateRSCReg()
9383 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateRSCReg()
9415 bool EmulateInstructionARM::EmulateSBCImm(const uint32_t opcode, in EmulateSBCImm() argument
9442 Rd = Bits32(opcode, 11, 8); in EmulateSBCImm()
9443 Rn = Bits32(opcode, 19, 16); in EmulateSBCImm()
9444 setflags = BitIsSet(opcode, 20); in EmulateSBCImm()
9445 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) in EmulateSBCImm()
9450 Rd = Bits32(opcode, 15, 12); in EmulateSBCImm()
9451 Rn = Bits32(opcode, 19, 16); in EmulateSBCImm()
9452 setflags = BitIsSet(opcode, 20); in EmulateSBCImm()
9453 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateSBCImm()
9458 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateSBCImm()
9483 bool EmulateInstructionARM::EmulateSBCReg(const uint32_t opcode, in EmulateSBCReg() argument
9512 Rd = Rn = Bits32(opcode, 2, 0); in EmulateSBCReg()
9513 Rm = Bits32(opcode, 5, 3); in EmulateSBCReg()
9519 Rd = Bits32(opcode, 11, 8); in EmulateSBCReg()
9520 Rn = Bits32(opcode, 19, 16); in EmulateSBCReg()
9521 Rm = Bits32(opcode, 3, 0); in EmulateSBCReg()
9522 setflags = BitIsSet(opcode, 20); in EmulateSBCReg()
9523 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateSBCReg()
9528 Rd = Bits32(opcode, 15, 12); in EmulateSBCReg()
9529 Rn = Bits32(opcode, 19, 16); in EmulateSBCReg()
9530 Rm = Bits32(opcode, 3, 0); in EmulateSBCReg()
9531 setflags = BitIsSet(opcode, 20); in EmulateSBCReg()
9532 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateSBCReg()
9537 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateSBCReg()
9567 bool EmulateInstructionARM::EmulateSUBImmThumb(const uint32_t opcode, in EmulateSUBImmThumb() argument
9591 Rd = Bits32(opcode, 2, 0); in EmulateSUBImmThumb()
9592 Rn = Bits32(opcode, 5, 3); in EmulateSUBImmThumb()
9594 imm32 = Bits32(opcode, 8, 6); // imm32 = ZeroExtend(imm3, 32) in EmulateSUBImmThumb()
9597 Rd = Rn = Bits32(opcode, 10, 8); in EmulateSUBImmThumb()
9599 imm32 = Bits32(opcode, 7, 0); // imm32 = ZeroExtend(imm8, 32) in EmulateSUBImmThumb()
9602 Rd = Bits32(opcode, 11, 8); in EmulateSUBImmThumb()
9603 Rn = Bits32(opcode, 19, 16); in EmulateSUBImmThumb()
9604 setflags = BitIsSet(opcode, 20); in EmulateSUBImmThumb()
9605 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) in EmulateSUBImmThumb()
9609 return EmulateCMPImm(opcode, eEncodingT2); in EmulateSUBImmThumb()
9613 return EmulateSUBSPImm(opcode, eEncodingT2); in EmulateSUBImmThumb()
9620 Rd = Bits32(opcode, 11, 8); in EmulateSUBImmThumb()
9621 Rn = Bits32(opcode, 19, 16); in EmulateSUBImmThumb()
9622 setflags = BitIsSet(opcode, 20); in EmulateSUBImmThumb()
9623 imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32) in EmulateSUBImmThumb()
9627 return EmulateADR(opcode, eEncodingT2); in EmulateSUBImmThumb()
9631 return EmulateSUBSPImm(opcode, eEncodingT3); in EmulateSUBImmThumb()
9657 bool EmulateInstructionARM::EmulateSUBImmARM(const uint32_t opcode, in EmulateSUBImmARM() argument
9677 if (ConditionPassed(opcode)) { in EmulateSUBImmARM()
9685 Rd = Bits32(opcode, 15, 12); in EmulateSUBImmARM()
9686 Rn = Bits32(opcode, 19, 16); in EmulateSUBImmARM()
9687 setflags = BitIsSet(opcode, 20); in EmulateSUBImmARM()
9688 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateSUBImmARM()
9692 return EmulateADR(opcode, eEncodingA2); in EmulateSUBImmARM()
9696 return EmulateSUBSPImm(opcode, eEncodingA1); in EmulateSUBImmARM()
9701 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateSUBImmARM()
9734 bool EmulateInstructionARM::EmulateTEQImm(const uint32_t opcode, in EmulateTEQImm() argument
9749 if (ConditionPassed(opcode)) { in EmulateTEQImm()
9756 Rn = Bits32(opcode, 19, 16); in EmulateTEQImm()
9758 opcode, APSR_C, in EmulateTEQImm()
9764 Rn = Bits32(opcode, 19, 16); in EmulateTEQImm()
9766 ARMExpandImm_C(opcode, APSR_C, in EmulateTEQImm()
9793 bool EmulateInstructionARM::EmulateTEQReg(const uint32_t opcode, in EmulateTEQReg() argument
9809 if (ConditionPassed(opcode)) { in EmulateTEQReg()
9816 Rn = Bits32(opcode, 19, 16); in EmulateTEQReg()
9817 Rm = Bits32(opcode, 3, 0); in EmulateTEQReg()
9818 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateTEQReg()
9823 Rn = Bits32(opcode, 19, 16); in EmulateTEQReg()
9824 Rm = Bits32(opcode, 3, 0); in EmulateTEQReg()
9825 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateTEQReg()
9859 bool EmulateInstructionARM::EmulateTSTImm(const uint32_t opcode, in EmulateTSTImm() argument
9874 if (ConditionPassed(opcode)) { in EmulateTSTImm()
9881 Rn = Bits32(opcode, 19, 16); in EmulateTSTImm()
9883 opcode, APSR_C, in EmulateTSTImm()
9889 Rn = Bits32(opcode, 19, 16); in EmulateTSTImm()
9891 ARMExpandImm_C(opcode, APSR_C, in EmulateTSTImm()
9918 bool EmulateInstructionARM::EmulateTSTReg(const uint32_t opcode, in EmulateTSTReg() argument
9934 if (ConditionPassed(opcode)) { in EmulateTSTReg()
9941 Rn = Bits32(opcode, 2, 0); in EmulateTSTReg()
9942 Rm = Bits32(opcode, 5, 3); in EmulateTSTReg()
9947 Rn = Bits32(opcode, 19, 16); in EmulateTSTReg()
9948 Rm = Bits32(opcode, 3, 0); in EmulateTSTReg()
9949 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateTSTReg()
9954 Rn = Bits32(opcode, 19, 16); in EmulateTSTReg()
9955 Rm = Bits32(opcode, 3, 0); in EmulateTSTReg()
9956 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateTSTReg()
9988 bool EmulateInstructionARM::EmulateSUBSPReg(const uint32_t opcode, in EmulateSUBSPReg() argument
10008 if (ConditionPassed(opcode)) { in EmulateSUBSPReg()
10018 d = Bits32(opcode, 11, 8); in EmulateSUBSPReg()
10019 m = Bits32(opcode, 3, 0); in EmulateSUBSPReg()
10020 setflags = BitIsSet(opcode, 20); in EmulateSUBSPReg()
10023 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateSUBSPReg()
10037 d = Bits32(opcode, 15, 12); in EmulateSUBSPReg()
10038 m = Bits32(opcode, 3, 0); in EmulateSUBSPReg()
10039 setflags = BitIsSet(opcode, 20); in EmulateSUBSPReg()
10044 EmulateSUBSPcLrEtc(opcode, encoding); in EmulateSUBSPReg()
10047 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateSUBSPReg()
10086 bool EmulateInstructionARM::EmulateADDRegShift(const uint32_t opcode, in EmulateADDRegShift() argument
10104 if (ConditionPassed(opcode)) { in EmulateADDRegShift()
10115 d = Bits32(opcode, 15, 12); in EmulateADDRegShift()
10116 n = Bits32(opcode, 19, 16); in EmulateADDRegShift()
10117 m = Bits32(opcode, 3, 0); in EmulateADDRegShift()
10118 s = Bits32(opcode, 11, 8); in EmulateADDRegShift()
10121 setflags = BitIsSet(opcode, 20); in EmulateADDRegShift()
10122 shift_t = DecodeRegShift(Bits32(opcode, 6, 5)); in EmulateADDRegShift()
10182 bool EmulateInstructionARM::EmulateSUBReg(const uint32_t opcode, in EmulateSUBReg() argument
10202 if (ConditionPassed(opcode)) { in EmulateSUBReg()
10213 d = Bits32(opcode, 2, 0); in EmulateSUBReg()
10214 n = Bits32(opcode, 5, 3); in EmulateSUBReg()
10215 m = Bits32(opcode, 8, 6); in EmulateSUBReg()
10226 d = Bits32(opcode, 11, 8); in EmulateSUBReg()
10227 n = Bits32(opcode, 19, 16); in EmulateSUBReg()
10228 m = Bits32(opcode, 3, 0); in EmulateSUBReg()
10229 setflags = BitIsSet(opcode, 20); in EmulateSUBReg()
10233 return EmulateCMPImm(opcode, eEncodingT3); in EmulateSUBReg()
10237 return EmulateSUBSPReg(opcode, eEncodingT1); in EmulateSUBReg()
10240 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateSUBReg()
10244 if ((d == 13) || ((d == 15) && BitIsClear(opcode, 20)) || (n == 15) || in EmulateSUBReg()
10253 d = Bits32(opcode, 15, 12); in EmulateSUBReg()
10254 n = Bits32(opcode, 19, 16); in EmulateSUBReg()
10255 m = Bits32(opcode, 3, 0); in EmulateSUBReg()
10256 setflags = BitIsSet(opcode, 20); in EmulateSUBReg()
10261 EmulateSUBSPcLrEtc(opcode, encoding); in EmulateSUBReg()
10264 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateSUBReg()
10316 bool EmulateInstructionARM::EmulateSTREX(const uint32_t opcode, in EmulateSTREX() argument
10331 if (ConditionPassed(opcode)) { in EmulateSTREX()
10343 d = Bits32(opcode, 11, 8); in EmulateSTREX()
10344 t = Bits32(opcode, 15, 12); in EmulateSTREX()
10345 n = Bits32(opcode, 19, 16); in EmulateSTREX()
10346 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateSTREX()
10361 d = Bits32(opcode, 15, 12); in EmulateSTREX()
10362 t = Bits32(opcode, 3, 0); in EmulateSTREX()
10363 n = Bits32(opcode, 19, 16); in EmulateSTREX()
10427 bool EmulateInstructionARM::EmulateSTRBImmARM(const uint32_t opcode, in EmulateSTRBImmARM() argument
10440 if (ConditionPassed(opcode)) { in EmulateSTRBImmARM()
10452 t = Bits32(opcode, 15, 12); in EmulateSTRBImmARM()
10453 n = Bits32(opcode, 19, 16); in EmulateSTRBImmARM()
10454 imm32 = Bits32(opcode, 11, 0); in EmulateSTRBImmARM()
10457 index = BitIsSet(opcode, 24); in EmulateSTRBImmARM()
10458 add = BitIsSet(opcode, 23); in EmulateSTRBImmARM()
10459 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21); in EmulateSTRBImmARM()
10520 bool EmulateInstructionARM::EmulateSTRImmARM(const uint32_t opcode, in EmulateSTRImmARM() argument
10533 if (ConditionPassed(opcode)) { in EmulateSTRImmARM()
10549 t = Bits32(opcode, 15, 12); in EmulateSTRImmARM()
10550 n = Bits32(opcode, 19, 16); in EmulateSTRImmARM()
10551 imm32 = Bits32(opcode, 11, 0); in EmulateSTRImmARM()
10554 index = BitIsSet(opcode, 24); in EmulateSTRImmARM()
10555 add = BitIsSet(opcode, 23); in EmulateSTRImmARM()
10556 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21); in EmulateSTRImmARM()
10629 bool EmulateInstructionARM::EmulateLDRDImmediate(const uint32_t opcode, in EmulateLDRDImmediate() argument
10643 if (ConditionPassed(opcode)) { in EmulateLDRDImmediate()
10658 t = Bits32(opcode, 15, 12); in EmulateLDRDImmediate()
10659 t2 = Bits32(opcode, 11, 8); in EmulateLDRDImmediate()
10660 n = Bits32(opcode, 19, 16); in EmulateLDRDImmediate()
10661 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateLDRDImmediate()
10664 index = BitIsSet(opcode, 24); in EmulateLDRDImmediate()
10665 add = BitIsSet(opcode, 23); in EmulateLDRDImmediate()
10666 wback = BitIsSet(opcode, 21); in EmulateLDRDImmediate()
10683 t = Bits32(opcode, 15, 12); in EmulateLDRDImmediate()
10687 n = Bits32(opcode, 19, 16); in EmulateLDRDImmediate()
10688 imm32 = (Bits32(opcode, 11, 8) << 4) | Bits32(opcode, 3, 0); in EmulateLDRDImmediate()
10691 index = BitIsSet(opcode, 24); in EmulateLDRDImmediate()
10692 add = BitIsSet(opcode, 23); in EmulateLDRDImmediate()
10693 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21); in EmulateLDRDImmediate()
10696 if (BitIsClear(opcode, 24) && BitIsSet(opcode, 21)) in EmulateLDRDImmediate()
10775 bool EmulateInstructionARM::EmulateLDRDRegister(const uint32_t opcode, in EmulateLDRDRegister() argument
10789 if (ConditionPassed(opcode)) { in EmulateLDRDRegister()
10802 t = Bits32(opcode, 15, 12); in EmulateLDRDRegister()
10806 n = Bits32(opcode, 19, 16); in EmulateLDRDRegister()
10807 m = Bits32(opcode, 3, 0); in EmulateLDRDRegister()
10810 index = BitIsSet(opcode, 24); in EmulateLDRDRegister()
10811 add = BitIsSet(opcode, 23); in EmulateLDRDRegister()
10812 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21); in EmulateLDRDRegister()
10815 if (BitIsClear(opcode, 24) && BitIsSet(opcode, 21)) in EmulateLDRDRegister()
10900 bool EmulateInstructionARM::EmulateSTRDImm(const uint32_t opcode, in EmulateSTRDImm() argument
10914 if (ConditionPassed(opcode)) { in EmulateSTRDImm()
10928 t = Bits32(opcode, 15, 12); in EmulateSTRDImm()
10929 t2 = Bits32(opcode, 11, 8); in EmulateSTRDImm()
10930 n = Bits32(opcode, 19, 16); in EmulateSTRDImm()
10931 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateSTRDImm()
10934 index = BitIsSet(opcode, 24); in EmulateSTRDImm()
10935 add = BitIsSet(opcode, 23); in EmulateSTRDImm()
10936 wback = BitIsSet(opcode, 21); in EmulateSTRDImm()
10952 t = Bits32(opcode, 15, 12); in EmulateSTRDImm()
10957 n = Bits32(opcode, 19, 16); in EmulateSTRDImm()
10958 imm32 = (Bits32(opcode, 11, 8) << 4) | Bits32(opcode, 3, 0); in EmulateSTRDImm()
10961 index = BitIsSet(opcode, 24); in EmulateSTRDImm()
10962 add = BitIsSet(opcode, 23); in EmulateSTRDImm()
10963 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21); in EmulateSTRDImm()
10966 if (BitIsClear(opcode, 24) && BitIsSet(opcode, 21)) in EmulateSTRDImm()
11053 bool EmulateInstructionARM::EmulateSTRDReg(const uint32_t opcode, in EmulateSTRDReg() argument
11067 if (ConditionPassed(opcode)) { in EmulateSTRDReg()
11080 t = Bits32(opcode, 15, 12); in EmulateSTRDReg()
11085 n = Bits32(opcode, 19, 16); in EmulateSTRDReg()
11086 m = Bits32(opcode, 3, 0); in EmulateSTRDReg()
11089 index = BitIsSet(opcode, 24); in EmulateSTRDReg()
11090 add = BitIsSet(opcode, 23); in EmulateSTRDReg()
11091 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21); in EmulateSTRDReg()
11094 if (BitIsClear(opcode, 24) && BitIsSet(opcode, 21)) in EmulateSTRDReg()
11190 bool EmulateInstructionARM::EmulateVLDM(const uint32_t opcode, in EmulateVLDM() argument
11209 if (ConditionPassed(opcode)) { in EmulateVLDM()
11225 if ((Bit32(opcode, 24) == Bit32(opcode, 23)) && BitIsSet(opcode, 21)) in EmulateVLDM()
11232 add = BitIsSet(opcode, 23); in EmulateVLDM()
11233 wback = BitIsSet(opcode, 21); in EmulateVLDM()
11236 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12); in EmulateVLDM()
11237 n = Bits32(opcode, 19, 16); in EmulateVLDM()
11238 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateVLDM()
11241 regs = Bits32(opcode, 7, 0) / 2; in EmulateVLDM()
11260 if ((Bit32(opcode, 24) == Bit32(opcode, 23)) && BitIsSet(opcode, 21)) in EmulateVLDM()
11268 add = BitIsSet(opcode, 23); in EmulateVLDM()
11269 wback = BitIsSet(opcode, 21); in EmulateVLDM()
11270 d = (Bits32(opcode, 15, 12) << 1) | Bit32(opcode, 22); in EmulateVLDM()
11271 n = Bits32(opcode, 19, 16); in EmulateVLDM()
11274 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateVLDM()
11275 regs = Bits32(opcode, 7, 0); in EmulateVLDM()
11383 bool EmulateInstructionARM::EmulateVSTM(const uint32_t opcode, in EmulateVSTM() argument
11403 if (ConditionPassed(opcode)) { in EmulateVSTM()
11419 if ((Bit32(opcode, 24) == Bit32(opcode, 23)) && BitIsSet(opcode, 21)) in EmulateVSTM()
11426 add = BitIsSet(opcode, 23); in EmulateVSTM()
11427 wback = BitIsSet(opcode, 21); in EmulateVSTM()
11430 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12); in EmulateVSTM()
11431 n = Bits32(opcode, 19, 16); in EmulateVSTM()
11432 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateVSTM()
11435 regs = Bits32(opcode, 7, 0) / 2; in EmulateVSTM()
11454 if ((Bit32(opcode, 24) == Bit32(opcode, 23)) && BitIsSet(opcode, 21)) in EmulateVSTM()
11462 add = BitIsSet(opcode, 23); in EmulateVSTM()
11463 wback = BitIsSet(opcode, 21); in EmulateVSTM()
11464 d = (Bits32(opcode, 15, 12) << 1) | Bit32(opcode, 22); in EmulateVSTM()
11465 n = Bits32(opcode, 19, 16); in EmulateVSTM()
11468 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateVSTM()
11469 regs = Bits32(opcode, 7, 0); in EmulateVSTM()
11588 bool EmulateInstructionARM::EmulateVLDR(const uint32_t opcode, in EmulateVLDR() argument
11606 if (ConditionPassed(opcode)) { in EmulateVLDR()
11619 add = BitIsSet(opcode, 23); in EmulateVLDR()
11620 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateVLDR()
11623 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12); in EmulateVLDR()
11624 n = Bits32(opcode, 19, 16); in EmulateVLDR()
11632 add = BitIsSet(opcode, 23); in EmulateVLDR()
11633 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateVLDR()
11636 d = (Bits32(opcode, 15, 12) << 1) | Bit32(opcode, 22); in EmulateVLDR()
11637 n = Bits32(opcode, 19, 16); in EmulateVLDR()
11715 bool EmulateInstructionARM::EmulateVSTR(const uint32_t opcode, in EmulateVSTR() argument
11732 if (ConditionPassed(opcode)) { in EmulateVSTR()
11745 add = BitIsSet(opcode, 23); in EmulateVSTR()
11746 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateVSTR()
11749 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12); in EmulateVSTR()
11750 n = Bits32(opcode, 19, 16); in EmulateVSTR()
11762 add = BitIsSet(opcode, 23); in EmulateVSTR()
11763 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateVSTR()
11766 d = (Bits32(opcode, 15, 12) << 1) | Bit32(opcode, 22); in EmulateVSTR()
11767 n = Bits32(opcode, 19, 16); in EmulateVSTR()
11847 bool EmulateInstructionARM::EmulateVLD1Multiple(const uint32_t opcode, in EmulateVLD1Multiple() argument
11862 if (ConditionPassed(opcode)) { in EmulateVLD1Multiple()
11888 uint32_t type = Bits32(opcode, 11, 8); in EmulateVLD1Multiple()
11889 uint32_t align = Bits32(opcode, 5, 4); in EmulateVLD1Multiple()
11919 ebytes = 1 << Bits32(opcode, 7, 6); in EmulateVLD1Multiple()
11924 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12); in EmulateVLD1Multiple()
11925 n = Bits32(opcode, 19, 15); in EmulateVLD1Multiple()
11926 m = Bits32(opcode, 3, 0); in EmulateVLD1Multiple()
12005 bool EmulateInstructionARM::EmulateVLD1Single(const uint32_t opcode, in EmulateVLD1Single() argument
12017 if (ConditionPassed(opcode)) { in EmulateVLD1Single()
12031 uint32_t size = Bits32(opcode, 11, 10); in EmulateVLD1Single()
12032 uint32_t index_align = Bits32(opcode, 7, 4); in EmulateVLD1Single()
12035 return EmulateVLD1SingleAll(opcode, encoding); in EmulateVLD1Single()
12090 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12); in EmulateVLD1Single()
12091 n = Bits32(opcode, 19, 16); in EmulateVLD1Single()
12092 m = Bits32(opcode, 3, 0); in EmulateVLD1Single()
12181 bool EmulateInstructionARM::EmulateVST1Multiple(const uint32_t opcode, in EmulateVST1Multiple() argument
12196 if (ConditionPassed(opcode)) { in EmulateVST1Multiple()
12211 uint32_t type = Bits32(opcode, 11, 8); in EmulateVST1Multiple()
12212 uint32_t align = Bits32(opcode, 5, 4); in EmulateVST1Multiple()
12247 ebytes = 1 << Bits32(opcode, 7, 6); in EmulateVST1Multiple()
12252 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12); in EmulateVST1Multiple()
12253 n = Bits32(opcode, 19, 16); in EmulateVST1Multiple()
12254 m = Bits32(opcode, 3, 0); in EmulateVST1Multiple()
12337 bool EmulateInstructionARM::EmulateVST1Single(const uint32_t opcode, in EmulateVST1Single() argument
12349 if (ConditionPassed(opcode)) { in EmulateVST1Single()
12363 uint32_t size = Bits32(opcode, 11, 10); in EmulateVST1Single()
12364 uint32_t index_align = Bits32(opcode, 7, 4); in EmulateVST1Single()
12423 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12); in EmulateVST1Single()
12424 n = Bits32(opcode, 19, 16); in EmulateVST1Single()
12425 m = Bits32(opcode, 3, 0); in EmulateVST1Single()
12496 bool EmulateInstructionARM::EmulateVLD1SingleAll(const uint32_t opcode, in EmulateVLD1SingleAll() argument
12510 if (ConditionPassed(opcode)) { in EmulateVLD1SingleAll()
12525 uint32_t size = Bits32(opcode, 7, 6); in EmulateVLD1SingleAll()
12526 if ((size == 3) || ((size == 0) && BitIsSet(opcode, 4))) in EmulateVLD1SingleAll()
12533 if (BitIsClear(opcode, 5)) in EmulateVLD1SingleAll()
12539 if (BitIsClear(opcode, 4)) in EmulateVLD1SingleAll()
12545 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12); in EmulateVLD1SingleAll()
12546 n = Bits32(opcode, 19, 16); in EmulateVLD1SingleAll()
12547 m = Bits32(opcode, 3, 0); in EmulateVLD1SingleAll()
12626 bool EmulateInstructionARM::EmulateSUBSPcLrEtc(const uint32_t opcode, in EmulateSUBSPcLrEtc() argument
12634 case opcode of in EmulateSUBSPcLrEtc()
12653 if (ConditionPassed(opcode)) { in EmulateSUBSPcLrEtc()
12665 // imm32 = ZeroExtend(imm8, 32); register_form = FALSE; opcode = '0010'; in EmulateSUBSPcLrEtc()
12668 imm32 = Bits32(opcode, 7, 0); in EmulateSUBSPcLrEtc()
12680 n = Bits32(opcode, 19, 16); in EmulateSUBSPcLrEtc()
12681 imm32 = ARMExpandImm(opcode); in EmulateSUBSPcLrEtc()
12683 code = Bits32(opcode, 24, 21); in EmulateSUBSPcLrEtc()
12689 n = Bits32(opcode, 19, 16); in EmulateSUBSPcLrEtc()
12690 m = Bits32(opcode, 3, 0); in EmulateSUBSPcLrEtc()
12694 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateSUBSPcLrEtc()
12723 // case opcode of in EmulateSUBSPcLrEtc()
12810 EmulateInstructionARM::GetARMOpcodeForInstruction(const uint32_t opcode, in GetARMOpcodeForInstruction() argument
13174 if ((g_arm_opcodes[i].mask & opcode) == g_arm_opcodes[i].value && in GetARMOpcodeForInstruction()
13182 EmulateInstructionARM::GetThumbOpcodeForInstruction(const uint32_t opcode, in GetThumbOpcodeForInstruction() argument
13252 // The next 5 opcode _must_ come before the if then instruction in GetThumbOpcodeForInstruction()
13724 if ((g_thumb_opcodes[i].mask & opcode) == g_thumb_opcodes[i].value && in GetThumbOpcodeForInstruction()
13764 bool EmulateInstructionARM::SetInstruction(const Opcode &insn_opcode, in SetInstruction()
13844 bool EmulateInstructionARM::ConditionPassed(const uint32_t opcode) { in ConditionPassed() argument
13851 const uint32_t cond = CurrentCond(opcode); in ConditionPassed()
13917 uint32_t EmulateInstructionARM::CurrentCond(const uint32_t opcode) { in CurrentCond() argument
13923 return UnsignedBits(opcode, 31, 28); in CurrentCond()
13931 if (Bits32(opcode, 15, 12) == 0x0d && Bits32(opcode, 11, 8) != 0x0f) in CurrentCond()
13932 return Bits32(opcode, 11, 8); in CurrentCond()
13934 if (Bits32(opcode, 31, 27) == 0x1e && Bits32(opcode, 15, 14) == 0x02 && in CurrentCond()
13935 Bits32(opcode, 12, 12) == 0x00 && Bits32(opcode, 25, 22) <= 0x0d) { in CurrentCond()
13936 return Bits32(opcode, 25, 22); in CurrentCond()
14306 // Call the Emulate... function if we managed to decode the opcode. in EvaluateInstruction()
14356 static constexpr llvm::StringLiteral opcode_key("opcode"); in TestEmulation()
14365 out_stream.Printf("TestEmulation: Error reading opcode from test file.\n"); in TestEmulation()