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/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp92 const TargetRegisterClass &RC = *MRI.getRegClass(Reg); mask() local
123 if (const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg)) getPhysRegBitWidth() local
131 composeWithSubRegIndex(const TargetRegisterClass & RC,unsigned Idx) const composeWithSubRegIndex() argument
281 __anon356067470402(const BT::RegisterCell &RC, uint16_t RW) evaluate() argument
288 __anon356067470502(const BT::RegisterCell &RC, uint16_t RW) evaluate() argument
289 __anon356067470602(const BT::RegisterCell &RC, unsigned N) evaluate() argument
298 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW)); evaluate() local
333 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); evaluate() local
349 RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1)); evaluate() local
356 RegisterCell RC = RegisterCell::self(Reg[0].Reg, RW); evaluate() local
372 RegisterCell RC = eADD(eSXT(CW, W1), rc(2)); evaluate() local
381 RegisterCell RC = eADD(eIMM(im(1), W0), eASL(rc(2), im(3))); evaluate() local
385 RegisterCell RC = eADD(eIMM(im(1), W0), eLSR(rc(2), im(3))); evaluate() local
389 RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0))); evaluate() local
394 RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0)); evaluate() local
399 RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0)); evaluate() local
404 RegisterCell RC = eADD(rc(1), lo(M, W0)); evaluate() local
409 RegisterCell RC = eADD(rc(1), lo(M, W0)); evaluate() local
414 RegisterCell RC = eADD(rc(1), lo(M, W0)); evaluate() local
418 RegisterCell RC = eADD(rc(1), eSUB(eIMM(im(2), W0), rc(3))); evaluate() local
422 RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0))); evaluate() local
426 RegisterCell RC = eADD(rc(1), eADD(rc(2), rc(3))); evaluate() local
430 RegisterCell RC = eADD(rc(1), eSUB(rc(2), rc(3))); evaluate() local
434 RegisterCell RC = eADD(rc(1), eASL(rc(2), im(3))); evaluate() local
448 RegisterCell RC = eSUB(eIMM(im(1), W0), eASL(rc(2), im(3))); evaluate() local
452 RegisterCell RC = eSUB(eIMM(im(1), W0), eLSR(rc(2), im(3))); evaluate() local
456 RegisterCell RC = eSUB(rc(1), eADD(rc(2), eIMM(im(3), W0))); evaluate() local
460 RegisterCell RC = eSUB(rc(1), eADD(rc(2), rc(3))); evaluate() local
483 RegisterCell RC = eADD(rc(1), lo(M, W0)); evaluate() local
488 RegisterCell RC = eSUB(rc(1), lo(M, W0)); evaluate() local
493 RegisterCell RC = eADD(rc(1), lo(M, W0)); evaluate() local
498 RegisterCell RC = eSUB(rc(1), lo(M, W0)); evaluate() local
536 RegisterCell RC = eAND(eIMM(im(1), W0), eASL(rc(2), im(3))); evaluate() local
540 RegisterCell RC = eAND(eIMM(im(1), W0), eLSR(rc(2), im(3))); evaluate() local
560 RegisterCell RC = eORL(eIMM(im(1), W0), eASL(rc(2), im(3))); evaluate() local
564 RegisterCell RC = eORL(eIMM(im(1), W0), eLSR(rc(2), im(3))); evaluate() local
573 RegisterCell RC = eORL(rc(1), eAND(rc(2), eIMM(im(3), W0))); evaluate() local
577 RegisterCell RC = eORL(rc(1), eORL(rc(2), eIMM(im(3), W0))); evaluate() local
646 RegisterCell RC = eASR(eADD(eASR(XC, im(2)), eIMM(1, 2*W0)), 1); evaluate() local
655 RegisterCell RC = eLSR(eADD(eASR(XC, S-1), eIMM(1, 2*W0)), 1); evaluate() local
684 RegisterCell RC = rc(1); evaluate() local
689 RegisterCell RC = rc(1); evaluate() local
694 RegisterCell RC = rc(1); evaluate() local
710 RegisterCell RC = eINS(eINS(RZ, BF1, 0), BF2, W1); evaluate() local
726 RegisterCell RC = RegisterCell(W0).insert(Ext, BT::BitMask(0, Wd-1)); evaluate() local
765 RegisterCell RC = half(R2, LoH).cat(half(R1, HiH)); evaluate() local
773 RegisterCell RC = half(R2, 0).cat(half(R1, 0)).cat(half(R2, 1)) evaluate() local
778 RegisterCell RC = shuffle(rc(1), rc(2), 8, false); evaluate() local
782 RegisterCell RC = shuffle(rc(1), rc(2), 16, false); evaluate() local
786 RegisterCell RC = shuffle(rc(1), rc(2), 8, true); evaluate() local
790 RegisterCell RC = shuffle(rc(1), rc(2), 16, true); evaluate() local
798 RegisterCell RC(WR); evaluate() local
834 RegisterCell RC = eSXT(rc(1).cat(eIMM(0, W1)), W1); evaluate() local
894 RegisterCell RC(W0); evaluate() local
911 RegisterCell RC(W0); evaluate() local
971 RegisterCell RC = RegisterCell::self(DefR, RW); evaluate() local
[all...]
/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h198 isSGPRClass(const TargetRegisterClass * RC) isSGPRClass() argument
210 isVGPRClass(const TargetRegisterClass * RC) isVGPRClass() argument
215 isAGPRClass(const TargetRegisterClass * RC) isAGPRClass() argument
220 isVectorSuperClass(const TargetRegisterClass * RC) isVectorSuperClass() argument
225 isVSSuperClass(const TargetRegisterClass * RC) isVSSuperClass() argument
230 hasVGPRs(const TargetRegisterClass * RC) hasVGPRs() argument
235 hasAGPRs(const TargetRegisterClass * RC) hasAGPRs() argument
240 hasSGPRs(const TargetRegisterClass * RC) hasSGPRs() argument
245 hasVectorRegisters(const TargetRegisterClass * RC) hasVectorRegisters() argument
305 isDivergentRegClass(const TargetRegisterClass * RC) isDivergentRegClass() argument
435 getRegClassAlignmentNumBits(const TargetRegisterClass * RC) getRegClassAlignmentNumBits() argument
440 isRegClassAligned(const TargetRegisterClass * RC,unsigned AlignNumBits) isRegClassAligned() argument
[all...]
H A DGCNRewritePartialRegUses.cpp81 const TargetRegisterClass *RC; global() member
187 getSuperRegClassMask(const TargetRegisterClass * RC,unsigned SubRegIdx) const getSuperRegClassMask() argument
210 auto *RC = TRI->getRegClass(ClassID); getAllocatableAndAlignedRegClassMask() local
220 getRegClassWithShiftedSubregs(const TargetRegisterClass * RC,unsigned RShift,unsigned RegNumBits,unsigned CoverSubregIdx,SubRegMap & SubRegs) const getRegClassWithShiftedSubregs() argument
271 auto *RC = TRI->getRegClass(ClassID); getRegClassWithShiftedSubregs() local
294 getMinSizeReg(const TargetRegisterClass * RC,SubRegMap & SubRegs) const getMinSizeReg() argument
418 auto *RC = MRI->getRegClass(Reg); rewriteReg() local
[all...]
/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h78 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
94 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
101 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
111 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
131 uint8_t getMinCost(const TargetRegisterClass *RC) const { in getMinCost()
139 unsigned getLastCostChange(const TargetRegisterClass *RC) const { in getLastCostChange()
H A DTargetRegisterInfo.h126 return RC != this && hasSubClassEq(RC); in hasSubClass() argument
131 unsigned ID = RC->getID(); in hasSubClassEq() argument
138 return RC->hasSubClass(this); in hasSuperClass() argument
143 hasSuperClassEq(const TargetRegisterClass * RC) hasSuperClassEq() argument
297 getRegSizeInBits(const TargetRegisterClass & RC) getRegSizeInBits() argument
303 getSpillSize(const TargetRegisterClass & RC) getSpillSize() argument
309 getSpillAlign(const TargetRegisterClass & RC) getSpillAlign() argument
314 isTypeLegalForClass(const TargetRegisterClass & RC,MVT T) isTypeLegalForClass() argument
322 isTypeLegalForClass(const TargetRegisterClass & RC,LLT T) isTypeLegalForClass() argument
336 legalclasstypes_begin(const TargetRegisterClass & RC) legalclasstypes_begin() argument
340 legalclasstypes_end(const TargetRegisterClass & RC) legalclasstypes_end() argument
584 isDivergentRegClass(const TargetRegisterClass * RC) isDivergentRegClass() argument
641 getMatchingSuperReg(MCRegister Reg,unsigned SubIdx,const TargetRegisterClass * RC) getMatchingSuperReg() argument
676 getSubClassWithSubReg(const TargetRegisterClass * RC,unsigned Idx) getSubClassWithSubReg() argument
800 getRegClassInfo(const TargetRegisterClass & RC) getRegClassInfo() argument
847 getCrossCopyRegClass(const TargetRegisterClass * RC) getCrossCopyRegClass() argument
856 getLargestLegalSuperClass(const TargetRegisterClass * RC,const MachineFunction &) getLargestLegalSuperClass() argument
869 getRegPressureLimit(const TargetRegisterClass * RC,MachineFunction & MF) getRegPressureLimit() argument
1073 saveScavengerRegister(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,MachineBasicBlock::iterator & UseMI,const TargetRegisterClass * RC,Register Reg) saveScavengerRegister() argument
1206 getLargestSuperClass(const TargetRegisterClass * RC) getLargestSuperClass() argument
1219 doesRegClassHavePseudoInitUndef(const TargetRegisterClass * RC) doesRegClassHavePseudoInitUndef() argument
[all...]
/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyExplicitLocals.cpp88 static unsigned getDropOpcode(const TargetRegisterClass *RC) { in getDropOpcode() argument
109 static unsigned getLocalGetOpcode(const TargetRegisterClass *RC) { in getLocalGetOpcode() argument
130 getLocalSetOpcode(const TargetRegisterClass * RC) getLocalSetOpcode() argument
151 getLocalTeeOpcode(const TargetRegisterClass * RC) getLocalTeeOpcode() argument
172 typeForRegClass(const TargetRegisterClass * RC) typeForRegClass() argument
311 const TargetRegisterClass *RC = MRI.getRegClass(DefReg); runOnMachineFunction() local
344 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); runOnMachineFunction() local
416 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); runOnMachineFunction() local
[all...]
/llvm-project/llvm/lib/Target/XCore/
H A DXCoreMachineFunctionInfo.cpp45 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createLRSpillSlot() local
63 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createFPSpillSlot() local
76 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createEHSpillSlot() local
/llvm-project/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp74 addRegisterClass(const CodeGenRegisterClass * RC) addRegisterClass() argument
176 visitRegisterBankClasses(const CodeGenRegBank & RegisterClassHierarchy,const CodeGenRegisterClass * RC,const Twine & Kind,std::function<void (const CodeGenRegisterClass *,StringRef)> VisitFn,SmallPtrSetImpl<const CodeGenRegisterClass * > & VisitedRCs) visitRegisterBankClasses() argument
227 for (const auto &RC : Bank.register_classes()) emitBaseClassImplementation() local
235 for (const auto &RC : RCs) { emitBaseClassImplementation() local
274 const CodeGenRegisterClass &RC = *Bank.getRCWithLargestRegSize(M); emitBaseClassImplementation() local
305 for (const CodeGenRegisterClass *RC : run() local
309 __anon7f2f83e90202(const CodeGenRegisterClass *RC, StringRef Kind) run() argument
[all...]
H A DRegisterInfoEmitter.cpp148 for (const auto &RC : RegisterClasses) runEnums() local
217 for (const auto &RC : RegBank.getRegClasses()) { EmitRegUnitPressure() local
1008 for (const auto &RC : RegisterClasses) { runMCDesc() local
1044 for (const auto &RC : RegisterClasses) { runMCDesc() local
1163 __anon413b9ad90502(const auto &RC) runTargetHeader() argument
1174 for (const auto &RC : RegisterClasses) { runTargetHeader() local
1210 for (const auto &RC : RegisterClasses) { runTargetDesc() local
1223 for (const auto &RC : RegisterClasses) { runTargetDesc() local
1281 for (const auto &RC : RegisterClasses) { runTargetDesc() local
1325 for (const auto &RC : RegisterClasses) { runTargetDesc() local
1353 for (const auto &RC : RegisterClasses) { runTargetDesc() local
1368 for (const auto &RC : RegisterClasses) { runTargetDesc() local
1403 for (const auto &RC : RegisterClasses) { runTargetDesc() local
1433 for (const auto &RC : RegisterClasses) runTargetDesc() local
1511 for (const auto &RC : RegisterClasses) { runTargetDesc() local
1544 for (const auto &RC : RegisterClasses) { runTargetDesc() local
1582 for (const auto &RC : RegisterClasses) { runTargetDesc() local
1610 for (const CodeGenRegisterClass *RC : BaseClasses) { runTargetDesc() local
1734 for (const CodeGenRegisterClass *RC : Category.getClasses()) runTargetDesc() local
1748 for (const CodeGenRegisterClass *RC : Category.getClasses()) runTargetDesc() local
1762 for (const CodeGenRegisterClass *RC : Category.getClasses()) runTargetDesc() local
1831 for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) { debugDump() local
[all...]
/llvm-project/llvm/lib/Target/Mips/
H A DMipsMachineFunction.cpp79 const TargetRegisterClass *RC; in initGlobalBaseReg() local
160 const TargetRegisterClass &RC = in createEhDataRegsFI() local
175 const TargetRegisterClass &RC = Mips::GPR32RegClass; in createISRRegFI() local
202 const TargetRegisterClass *RC) { in getMoveF64ViaSpillFI()
H A DMipsSEFrameLowering.cpp173 Register VR = MRI.createVirtualRegister(RC); in expandLoadCCond() local
188 Register VR = MRI.createVirtualRegister(RC); in expandStoreCCond() local
206 Register VR0 = MRI.createVirtualRegister(RC); in expandLoadACC() local
231 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); expandStoreACC() local
264 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize); expandCopyACC() local
317 const TargetRegisterClass *RC = &Mips::GPR32RegClass; expandBuildPairF64() local
383 const TargetRegisterClass *RC = expandExtractElementF64() local
421 const TargetRegisterClass *RC = ABI.ArePtrs64bit() ? emitPrologue() local
719 const TargetRegisterClass *RC = emitEpilogue() local
834 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); spillCalleeSavedRegisters() local
895 const TargetRegisterClass &RC = STI.isGP64bit() ? determineCalleeSaves() local
911 const TargetRegisterClass &RC = determineCalleeSaves() local
[all...]
H A DMipsInstrInfo.h139 storeRegToStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,Register SrcReg,bool isKill,int FrameIndex,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI,Register VReg) storeRegToStackSlot() argument
147 loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,Register DestReg,int FrameIndex,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI,Register VReg) loadRegFromStackSlot() argument
/llvm-project/llvm/lib/CodeGen/
H A DLiveStacks.cpp54 getOrCreateInterval(int Slot,const TargetRegisterClass * RC) getOrCreateInterval() argument
79 const TargetRegisterClass *RC = getIntervalRegClass(Slot); print() local
H A DRegisterBank.cpp26 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify() local
92 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print() local
H A DSwiftErrorValueTracking.cpp36 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in getOrCreateVReg() local
58 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in getOrCreateVRegDefAt() local
126 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in createEntriesInEntryBlock() local
240 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in propagateVRegs() local
/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrInfo.cpp85 const TargetRegisterClass *RC = &Xtensa::ARRegClass; adjustStackPtr() local
121 storeRegToStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,Register SrcReg,bool isKill,int FrameIdx,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI,Register VReg) const storeRegToStackSlot() argument
134 loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,Register DestReg,int FrameIdx,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI,Register VReg) const loadRegFromStackSlot() argument
143 getLoadStoreOpcodes(const TargetRegisterClass * RC,unsigned & LoadOpcode,unsigned & StoreOpcode,int64_t offset) const getLoadStoreOpcodes() argument
159 const TargetRegisterClass *RC = &Xtensa::ARRegClass; loadImmediate() local
[all...]
/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp449 PPCEmitLoad(MVT VT,Register & ResultReg,Address & Addr,const TargetRegisterClass * RC,bool IsZExt,unsigned FP64LoadOpc) PPCEmitLoad() argument
606 const TargetRegisterClass *RC = SelectLoad() local
623 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg); PPCEmitStore() local
987 auto RC = MRI.getRegClass(SrcReg); SelectFPTrunc() local
1051 const TargetRegisterClass *RC = &PPC::F8RCRegClass; PPCMoveToFPReg() local
1130 const TargetRegisterClass *RC = &PPC::F8RCRegClass; SelectIToFP() local
1174 const TargetRegisterClass *RC = PPCMoveToIntReg() local
1225 auto RC = MRI.getRegClass(SrcReg); SelectFPToI() local
1280 const TargetRegisterClass *RC = SelectBinaryIntOp() local
1442 const TargetRegisterClass *RC = processCallArgs() local
1454 const TargetRegisterClass *RC = processCallArgs() local
1768 const TargetRegisterClass *RC = SelectRet() local
1777 const TargetRegisterClass *RC = SelectRet() local
1925 const TargetRegisterClass *RC = SelectIntExt() local
2000 const TargetRegisterClass *RC; PPCMaterializeFP() local
2061 const TargetRegisterClass *RC = &PPC::G8RC_and_G8RC_NOX0RegClass; PPCMaterializeGV() local
2123 PPCMaterialize32BitInt(int64_t Imm,const TargetRegisterClass * RC) PPCMaterialize32BitInt() argument
2155 PPCMaterialize64BitInt(int64_t Imm,const TargetRegisterClass * RC) PPCMaterialize64BitInt() argument
2225 const TargetRegisterClass *RC = PPCMaterializeInt() local
2407 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass : fastEmit_i() local
2427 fastEmitInst_ri(unsigned MachineInstOpcode,const TargetRegisterClass * RC,unsigned Op0,uint64_t Imm) fastEmitInst_ri() argument
2446 fastEmitInst_r(unsigned MachineInstOpcode,const TargetRegisterClass * RC,unsigned Op0) fastEmitInst_r() argument
2459 fastEmitInst_rr(unsigned MachineInstOpcode,const TargetRegisterClass * RC,unsigned Op0,unsigned Op1) fastEmitInst_rr() argument
[all...]
/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXRegisterInfo.cpp29 getNVPTXRegClassName(TargetRegisterClass const * RC) getNVPTXRegClassName() argument
67 getNVPTXRegClassStr(TargetRegisterClass const * RC) getNVPTXRegClassStr() argument
[all...]
/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVRegisterBankInfo.cpp28 getRegBankFromRegClass(const TargetRegisterClass & RC,LLT Ty) const getRegBankFromRegClass() argument
/llvm-project/clang/unittests/Serialization/
H A DNoCommentsTest.cpp72 const RawComment *RC = getCompletionComment(Ctx, foo); in TEST_F() local
124 const RawComment *RC = getCompletionComment(Ctx, foo); in TEST_F() local
/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp59 for (const TargetRegisterClass *RC : TRI->regclasses()) in ResourcePriorityQueue() local
359 for (const TargetRegisterClass *RC : TRI->regclasses()) in regPressureDelta() local
363 for (const TargetRegisterClass *RC : TRI->regclasses()) { in regPressureDelta() local
477 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
488 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
/llvm-project/llvm/include/llvm/IR/
H A DConstantFolder.h46 auto *RC = dyn_cast<Constant>(RHS); in FoldBinOp() local
58 auto *RC = dyn_cast<Constant>(RHS); in FoldExactBinOp() local
71 auto *RC = dyn_cast<Constant>(RHS); in FoldNoWrapBinOp() local
100 auto *RC = dyn_cast<Constant>(RHS); in FoldCmp() local
/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.h245 getLargestSuperClass(const TargetRegisterClass * RC) getLargestSuperClass() argument
258 doesRegClassHavePseudoInitUndef(const TargetRegisterClass * RC) doesRegClassHavePseudoInitUndef() argument
/llvm-project/llvm/unittests/Analysis/
H A DLazyCallGraphTest.cpp475 LazyCallGraph::RefSCC &RC = *I++; in TEST() local
560 LazyCallGraph::RefSCC &RC = *I++; in TEST() local
1241 LazyCallGraph::RefSCC &RC = *I++; TEST() local
1335 LazyCallGraph::RefSCC &RC = *I; TEST() local
1413 LazyCallGraph::RefSCC &RC = *I; TEST() local
1480 LazyCallGraph::RefSCC &RC = *I; TEST() local
1557 LazyCallGraph::RefSCC &RC = *I++; TEST() local
1650 LazyCallGraph::RefSCC &RC = *I++; TEST() local
1762 LazyCallGraph::RefSCC &RC = *I++; TEST() local
1892 LazyCallGraph::RefSCC &RC = *I++; TEST() local
2206 LazyCallGraph::RefSCC &RC = *I++; TEST() local
2263 LazyCallGraph::RefSCC &RC = *I++; TEST() local
2316 LazyCallGraph::RefSCC &RC = *I++; TEST() local
2454 LazyCallGraph::RefSCC *RC = &*I++; TEST() local
2500 LazyCallGraph::RefSCC *RC = &*I++; TEST() local
2546 LazyCallGraph::RefSCC *RC = &*I++; TEST() local
2590 LazyCallGraph::RefSCC *RC = &*I++; TEST() local
2641 LazyCallGraph::RefSCC *RC = &*I++; TEST() local
2694 LazyCallGraph::RefSCC *RC = &*I++; TEST() local
2747 LazyCallGraph::RefSCC *RC = &*I++; TEST() local
2835 LazyCallGraph::RefSCC *RC = &*I++; TEST() local
2951 LazyCallGraph::RefSCC *RC = &*I++; TEST() local
3021 LazyCallGraph::RefSCC *RC = &*I++; TEST() local
[all...]
/llvm-project/llvm/include/llvm/Analysis/
H A DTargetFolder.h57 auto *RC = dyn_cast<Constant>(RHS); in FoldBinOp() local
69 auto *RC = dyn_cast<Constant>(RHS); in FoldExactBinOp() local
82 auto *RC = dyn_cast<Constant>(RHS); in FoldNoWrapBinOp() local
104 auto *RC = dyn_cast<Constant>(RHS); in FoldCmp() local

12345678910>>...13