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Revision tags: llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5 |
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| #
46732e2a |
| 03-Nov-2023 |
Craig Topper <craig.topper@sifive.com> |
[GISel] Remove BitVector from RegBank. Use tablegen CoverageData tables directly. NFC (#71105)
RegBanks are allocated as global variables. The use of BitVector causes
a static global constructor to
[GISel] Remove BitVector from RegBank. Use tablegen CoverageData tables directly. NFC (#71105)
RegBanks are allocated as global variables. The use of BitVector causes
a static global constructor to be used. The BitVector is initialized
from a table of bits that is created by tablegen. We can keep a pointer
to that data and use it as the bit vector instead.
This does require a little bit of manual indexing and reimplementation
of BitVector::count.
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| #
d22d42ce |
| 02-Nov-2023 |
Craig Topper <craig.topper@sifive.com> |
[GISel] Remove remainder of the concept of an invalid RegisterBank. (#71118)
RegisterBank no longer has a default constructor so there's no way to
create an invalid register bank.
Remove Invalid
[GISel] Remove remainder of the concept of an invalid RegisterBank. (#71118)
RegisterBank no longer has a default constructor so there's no way to
create an invalid register bank.
Remove InvalidID and the isValid method.
Replace the one use of isValid outside of RegBank with a check that the
ID matches so there's still some check of sanity.
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Revision tags: llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6 |
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| #
aa7eace8 |
| 03-Jun-2023 |
Nitin John Raj <nitin.raj@sifive.com> |
[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes
This patch adds logic for determining RegisterBank size to RegisterBankInfo, which allows accounting for the HwMode of the ta
[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes
This patch adds logic for determining RegisterBank size to RegisterBankInfo, which allows accounting for the HwMode of the target. Individual RegisterBanks cannot be constructed with HwMode information as construction is generated by TableGen, but a RegisterBankInfo subclass can provide the HwMode as a constructor argument. The HwMode is used to select the appropriate RegisterBank size from an array relating sizes to RegisterBanks.
Targets simply need to provide the HwMode argument to the <target>GenRegisterBankInfo constructor. The RISC-V RegisterBankInfo constructor has been updated accordingly (plus an unused argument removed).
Reviewed By: simoncook, craig.topper
Differential Revision: https://reviews.llvm.org/D76007
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Revision tags: llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7, llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, working, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1, llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2 |
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| #
cb216076 |
| 15-Feb-2022 |
Mircea Trofin <mtrofin@google.com> |
[nfc][codegen] Move RegisterBank[Info].h under CodeGen
This wraps up from D119053. The 2 headers are moved as described,
fixed file headers and include guards, updated all files where the old
paths
[nfc][codegen] Move RegisterBank[Info].h under CodeGen
This wraps up from D119053. The 2 headers are moved as described,
fixed file headers and include guards, updated all files where the old
paths were detected (simple grep through the repo), and `clang-format`-ed it all.
Differential Revision: https://reviews.llvm.org/D119876
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Revision tags: llvmorg-14.0.0-rc1 |
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| #
c62eefb8 |
| 05-Feb-2022 |
Mircea Trofin <mtrofin@google.com> |
[nfc][codegen] Move RegisterBank[Info].cpp under CodeGen
Layering-wise, it seems RegisterBank stuff fits under CodeGen, like
other target abstraction.
In particular, TargetSubtargetInfo has a getReg
[nfc][codegen] Move RegisterBank[Info].cpp under CodeGen
Layering-wise, it seems RegisterBank stuff fits under CodeGen, like
other target abstraction.
In particular, TargetSubtargetInfo has a getRegBankInfo member, but
using that object requires making sure GlobalISel is linked, which is
not always the case (e.g. llvm-jitlink doesn't).
Differential Revision: https://reviews.llvm.org/D119053
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