Lines Matching defs:RC
144 for (const auto &RC : RegisterClasses)
145 OS << " " << RC.getIdName() << " = " << RC.EnumValue << ",\n";
209 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
211 for (const auto &RC : RegBank.getRegClasses()) {
212 const CodeGenRegister::Vec &Regs = RC.getMembers();
213 OS << " {" << RC.getWeight(RegBank) << ", ";
214 if (Regs.empty() || RC.Artificial)
218 RC.buildRegUnitSet(RegBank, RegUnits);
221 OS << "}, \t// " << RC.getName() << "\n";
224 << " return RCWeightTable[RC->getID()];\n"
319 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n";
326 << " return &RCSetsTable[RCSetStartTable[RC->getID()]];\n"
999 for (const auto &RC : RegisterClasses) {
1000 ArrayRef<const Record *> Order = RC.getOrder();
1003 const std::string &Name = RC.getName();
1035 for (const auto &RC : RegisterClasses) {
1036 ArrayRef<const Record *> Order = RC.getOrder();
1037 std::string RCName = Order.empty() ? "nullptr" : RC.getName();
1038 std::string RCBitsName = Order.empty() ? "nullptr" : RC.getName() + "Bits";
1040 assert(isInt<8>(RC.CopyCost) && "Copy cost too large.");
1042 if (RC.RSI.isSimple())
1043 RegSize = RC.RSI.getSimple().RegSize;
1045 << RegClassStrings.get(RC.getName()) << ", " << RC.getOrder().size()
1046 << ", " << RCBitsSize << ", " << RC.getQualifiedIdName() << ", "
1047 << RegSize << ", " << RC.CopyCost << ", "
1048 << (RC.Allocatable ? "true" : "false") << ", "
1049 << (RC.getBaseClassOrder() ? "true" : "false") << " },\n";
1127 << "const TargetRegisterClass *RC) const override;\n"
1134 << "const TargetRegisterClass *RC) const override;\n"
1141 << " bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC)"
1154 [](const auto &RC) { return RC.getBaseClassOrder(); })) {
1165 for (const auto &RC : RegisterClasses) {
1166 const std::string &Name = RC.getName();
1200 for (const auto &RC : RegisterClasses) {
1201 ArrayRef<const Record *> Order = RC.getOrder();
1203 if (RC.Allocatable)
1214 for (const auto &RC : RegisterClasses) {
1216 for (const ValueTypeByHwMode &VVT : RC.VTs)
1272 for (const auto &RC : RegisterClasses) {
1273 assert(RC.EnumValue == EV && "Unexpected order of register classes");
1276 const RegSizeInfo &RI = RC.RSI.get(M);
1280 for (const ValueTypeByHwMode &VVT : RC.VTs)
1284 << RC.getName() << '\n';
1290 // register class, RC, is the set of sub-classes, including RC itself.
1292 // If RC has super-registers, also create a list of subreg indices and bit
1296 // For all SuperReg in SuperRC: SuperReg:Idx in RC
1300 // RC->getSuperRegIndices() = SuperRegIdxSeqs + ...
1313 for (const auto &RC : RegisterClasses) {
1314 OS << "static const uint32_t " << RC.getName()
1316 printBitVectorAsHex(OS, RC.getSubClasses(), 32);
1319 // project into RC.
1320 IdxList &SRIList = SuperRegIdxLists[RC.EnumValue];
1323 RC.getSuperRegClasses(&Idx, MaskBV);
1341 for (const auto &RC : RegisterClasses) {
1342 ArrayRef<CodeGenRegisterClass *> Supers = RC.getSuperClasses();
1348 OS << "static unsigned const " << RC.getName() << "Superclasses[] = {\n";
1355 for (const auto &RC : RegisterClasses) {
1356 if (!RC.AltOrderSelect.empty()) {
1357 OS << "\nstatic inline unsigned " << RC.getName()
1358 << "AltOrderSelect(const MachineFunction &MF) {" << RC.AltOrderSelect
1360 << "static ArrayRef<MCPhysReg> " << RC.getName()
1362 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) {
1363 ArrayRef<const Record *> Elems = RC.getOrder(oi);
1372 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n"
1375 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
1376 if (RC.getOrder(oi).empty())
1380 OS << ")\n };\n const unsigned Select = " << RC.getName()
1381 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders()
1390 for (const auto &RC : RegisterClasses) {
1391 OS << " extern const TargetRegisterClass " << RC.getName()
1393 << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n "
1394 << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + "
1395 << SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n ";
1396 printMask(OS, RC.LaneMask);
1397 OS << ",\n " << (unsigned)RC.AllocationPriority << ",\n "
1398 << (RC.GlobalPriority ? "true" : "false") << ",\n "
1399 << format("0x%02x", RC.TSFlags) << ", /* TSFlags */\n "
1400 << (RC.HasDisjunctSubRegs ? "true" : "false")
1402 << (RC.CoveredBySubRegs ? "true" : "false")
1404 if (RC.getSuperClasses().empty())
1407 OS << RC.getName() << "Superclasses, ";
1408 OS << RC.getSuperClasses().size() << ",\n ";
1409 if (RC.AltOrderSelect.empty())
1412 OS << RC.getName() << "GetRawAllocationOrder\n";
1421 for (const auto &RC : RegisterClasses)
1422 OS << " &" << RC.getQualifiedName() << "RegClass,\n";
1488 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
1499 for (const auto &RC : RegisterClasses) {
1500 OS << " {\t// " << RC.getName() << "\n";
1502 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx))
1510 OS << " };\n assert(RC && \"Missing regclass\");\n"
1511 << " if (!Idx) return RC;\n --Idx;\n"
1513 << " unsigned TV = Table[RC->getID()][Idx];\n"
1518 << "::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx)"
1532 for (const auto &RC : RegisterClasses) {
1533 OS << " {\t// " << RC.getName() << '\n';
1536 MatchingSubClass = RC.getMatchingSubClassWithSubRegs(RegBank, &Idx);
1544 OS << " " << EnumValue << ",\t// " << RC.getName() << ':'
1557 OS << " };\n assert(RC && \"Missing regclass\");\n"
1558 << " if (!Idx) return RC;\n --Idx;\n"
1560 << " unsigned TV = Table[RC->getID()][Idx];\n"
1570 for (const auto &RC : RegisterClasses) {
1571 if (RC.getBaseClassOrder())
1572 BaseClasses.push_back(&RC);
1598 for (const CodeGenRegisterClass *RC : BaseClasses) {
1599 if (is_contained(RC->getMembers(), &Reg)) {
1600 BaseRC = RC;
1719 for (const CodeGenRegisterClass *RC : Category.getClasses())
1720 OS << " " << RC->getQualifiedName()
1728 << "isGeneralPurposeRegisterClass(const TargetRegisterClass *RC)"
1733 for (const CodeGenRegisterClass *RC : Category.getClasses())
1734 OS << " " << RC->getQualifiedName()
1735 << "RegClass.hasSubClassEq(RC) ||\n";
1747 for (const CodeGenRegisterClass *RC : Category.getClasses())
1748 OS << " " << RC->getQualifiedName()
1761 for (const CodeGenRegisterClass *RC : Category.getClasses())
1762 OS << " " << RC->getQualifiedName()
1829 for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) {
1830 OS << "RegisterClass " << RC.getName() << ":\n";
1833 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillSize;
1836 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillAlignment;
1837 OS << " }\n\tNumRegs: " << RC.getMembers().size() << '\n';
1838 OS << "\tLaneMask: " << PrintLaneMask(RC.LaneMask) << '\n';
1839 OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n';
1840 OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n';
1841 OS << "\tAllocatable: " << RC.Allocatable << '\n';
1842 OS << "\tAllocationPriority: " << unsigned(RC.AllocationPriority) << '\n';
1843 OS << "\tBaseClassOrder: " << RC.getBaseClassOrder() << '\n';
1845 for (const CodeGenRegister *R : RC.getMembers()) {
1850 const BitVector &SubClasses = RC.getSubClasses();
1858 for (const CodeGenRegisterClass *SRC : RC.getSuperClasses()) {