1 //===-- ARMBaseRegisterInfo.h - ARM Register Information Impl ---*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the base ARM implementation of TargetRegisterInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H 14 #define LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H 15 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/CodeGen/MachineBasicBlock.h" 18 #include "llvm/CodeGen/MachineInstr.h" 19 #include "llvm/CodeGen/TargetRegisterInfo.h" 20 #include "llvm/IR/CallingConv.h" 21 #include "llvm/MC/MCRegisterInfo.h" 22 #include <cstdint> 23 24 #define GET_REGINFO_HEADER 25 #include "ARMGenRegisterInfo.inc" 26 27 namespace llvm { 28 29 class LiveIntervals; 30 31 /// Register allocation hints. 32 namespace ARMRI { 33 34 enum { 35 // Used for LDRD register pairs 36 RegPairOdd = 1, 37 RegPairEven = 2, 38 // Used to hint for lr in t2DoLoopStart 39 RegLR = 3 40 }; 41 42 } // end namespace ARMRI 43 44 static inline bool isCalleeSavedRegister(MCRegister Reg, 45 const MCPhysReg *CSRegs) { 46 for (unsigned i = 0; CSRegs[i]; ++i) 47 if (Reg == CSRegs[i]) 48 return true; 49 return false; 50 } 51 52 class ARMBaseRegisterInfo : public ARMGenRegisterInfo { 53 protected: 54 /// BasePtr - ARM physical register used as a base ptr in complex stack 55 /// frames. I.e., when we need a 3rd base, not just SP and FP, due to 56 /// variable size stack objects. 57 unsigned BasePtr = ARM::R6; 58 59 // Can be only subclassed. 60 explicit ARMBaseRegisterInfo(); 61 62 public: 63 /// Code Generation virtual methods... 64 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override; 65 const MCPhysReg * 66 getCalleeSavedRegsViaCopy(const MachineFunction *MF) const; 67 const uint32_t *getCallPreservedMask(const MachineFunction &MF, 68 CallingConv::ID) const override; 69 const uint32_t *getNoPreservedMask() const override; 70 const uint32_t *getTLSCallPreservedMask(const MachineFunction &MF) const; 71 const uint32_t *getSjLjDispatchPreservedMask(const MachineFunction &MF) const; 72 73 /// getThisReturnPreservedMask - Returns a call preserved mask specific to the 74 /// case that 'returned' is on an i32 first argument if the calling convention 75 /// is one that can (partially) model this attribute with a preserved mask 76 /// (i.e. it is a calling convention that uses the same register for the first 77 /// i32 argument and an i32 return value) 78 /// 79 /// Should return NULL in the case that the calling convention does not have 80 /// this property 81 const uint32_t *getThisReturnPreservedMask(const MachineFunction &MF, 82 CallingConv::ID) const; 83 84 ArrayRef<MCPhysReg> 85 getIntraCallClobberedRegs(const MachineFunction *MF) const override; 86 87 BitVector getReservedRegs(const MachineFunction &MF) const override; 88 bool isAsmClobberable(const MachineFunction &MF, 89 MCRegister PhysReg) const override; 90 bool isInlineAsmReadOnlyReg(const MachineFunction &MF, 91 unsigned PhysReg) const override; 92 93 const TargetRegisterClass * 94 getPointerRegClass(const MachineFunction &MF, 95 unsigned Kind = 0) const override; 96 const TargetRegisterClass * 97 getCrossCopyRegClass(const TargetRegisterClass *RC) const override; 98 99 const TargetRegisterClass * 100 getLargestLegalSuperClass(const TargetRegisterClass *RC, 101 const MachineFunction &MF) const override; 102 103 unsigned getRegPressureLimit(const TargetRegisterClass *RC, 104 MachineFunction &MF) const override; 105 106 bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order, 107 SmallVectorImpl<MCPhysReg> &Hints, 108 const MachineFunction &MF, const VirtRegMap *VRM, 109 const LiveRegMatrix *Matrix) const override; 110 111 void updateRegAllocHint(Register Reg, Register NewReg, 112 MachineFunction &MF) const override; 113 114 bool hasBasePointer(const MachineFunction &MF) const; 115 116 bool canRealignStack(const MachineFunction &MF) const override; 117 int64_t getFrameIndexInstrOffset(const MachineInstr *MI, 118 int Idx) const override; 119 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override; 120 Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, 121 int64_t Offset) const override; 122 void resolveFrameIndex(MachineInstr &MI, Register BaseReg, 123 int64_t Offset) const override; 124 bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, 125 int64_t Offset) const override; 126 127 bool cannotEliminateFrame(const MachineFunction &MF) const; 128 129 // Debug information queries. 130 Register getFrameRegister(const MachineFunction &MF) const override; 131 Register getBaseRegister() const { return BasePtr; } 132 133 /// emitLoadConstPool - Emits a load from constpool to materialize the 134 /// specified immediate. 135 virtual void 136 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 137 const DebugLoc &dl, Register DestReg, unsigned SubIdx, 138 int Val, ARMCC::CondCodes Pred = ARMCC::AL, 139 Register PredReg = Register(), 140 unsigned MIFlags = MachineInstr::NoFlags) const; 141 142 /// Code Generation virtual methods... 143 bool requiresRegisterScavenging(const MachineFunction &MF) const override; 144 145 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override; 146 147 bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override; 148 149 bool eliminateFrameIndex(MachineBasicBlock::iterator II, 150 int SPAdj, unsigned FIOperandNum, 151 RegScavenger *RS = nullptr) const override; 152 153 /// SrcRC and DstRC will be morphed into NewRC if this returns true 154 bool shouldCoalesce(MachineInstr *MI, 155 const TargetRegisterClass *SrcRC, 156 unsigned SubReg, 157 const TargetRegisterClass *DstRC, 158 unsigned DstSubReg, 159 const TargetRegisterClass *NewRC, 160 LiveIntervals &LIS) const override; 161 162 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, 163 unsigned DefSubReg, 164 const TargetRegisterClass *SrcRC, 165 unsigned SrcSubReg) const override; 166 167 int getSEHRegNum(unsigned i) const { return getEncodingValue(i); } 168 }; 169 170 } // end namespace llvm 171 172 #endif // LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H 173