Lines Matching defs:RC
108 const TargetRegisterClass *RC,
111 const TargetRegisterClass *RC, unsigned Op0);
113 const TargetRegisterClass *RC,
138 bool isVSFRCRegClass(const TargetRegisterClass *RC) const {
139 return RC->getID() == PPC::VSFRCRegClassID;
141 bool isVSSRCRegClass(const TargetRegisterClass *RC) const {
142 return RC->getID() == PPC::VSSRCRegClassID;
156 const TargetRegisterClass *RC, bool IsZExt = true,
169 const TargetRegisterClass *RC);
171 const TargetRegisterClass *RC);
444 const TargetRegisterClass *RC,
451 // Otherwise, RC is the register class to use. If the result of the
459 (RC ? RC :
601 const TargetRegisterClass *RC =
605 if (!PPCEmitLoad(VT, ResultReg, Addr, RC, true,
618 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg);
619 bool Is32BitInt = RC->hasSuperClassEq(&PPC::GPRCRegClass);
653 bool IsVSSRC = isVSSRCRegClass(RC);
654 bool IsVSFRC = isVSFRCRegClass(RC);
982 auto RC = MRI.getRegClass(SrcReg);
988 } else if (Subtarget->hasP8Vector() && isVSFRCRegClass(RC)) {
1046 const TargetRegisterClass *RC = &PPC::F8RCRegClass;
1048 if (!PPCEmitLoad(MVT::f64, ResultReg, Addr, RC, !IsSigned, LoadOpc))
1125 const TargetRegisterClass *RC = &PPC::F8RCRegClass;
1126 Register DestReg = createResultReg(RC);
1169 const TargetRegisterClass *RC =
1173 if (!PPCEmitLoad(VT, ResultReg, Addr, RC, !IsSigned))
1220 auto RC = MRI.getRegClass(SrcReg);
1228 } else if (isVSFRCRegClass(RC)) {
1275 const TargetRegisterClass *RC =
1278 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
1294 Register ResultReg = createResultReg(RC ? RC : &PPC::G8RCRegClass);
1435 const TargetRegisterClass *RC =
1437 Register TmpReg = createResultReg(RC);
1447 const TargetRegisterClass *RC =
1449 Register TmpReg = createResultReg(RC);
1761 const TargetRegisterClass *RC =
1763 Register TmpReg = createResultReg(RC);
1770 const TargetRegisterClass *RC =
1772 Register TmpReg = createResultReg(RC);
1918 const TargetRegisterClass *RC =
1922 Register ResultReg = createResultReg(RC);
1993 const TargetRegisterClass *RC;
1995 RC = ((VT == MVT::f32) ? &PPC::GPRCRegClass : &PPC::SPERCRegClass);
1997 RC = ((VT == MVT::f32) ? &PPC::F4RCRegClass : &PPC::F8RCRegClass);
1999 Register DestReg = createResultReg(RC);
2054 const TargetRegisterClass *RC = &PPC::G8RC_and_G8RC_NOX0RegClass;
2055 Register DestReg = createResultReg(RC);
2093 Register HighPartReg = createResultReg(RC);
2116 const TargetRegisterClass *RC) {
2120 Register ResultReg = createResultReg(RC);
2121 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
2129 Register TmpReg = createResultReg(RC);
2148 const TargetRegisterClass *RC) {
2169 unsigned TmpReg1 = PPCMaterialize32BitInt(Imm, RC);
2177 TmpReg2 = createResultReg(RC);
2185 TmpReg3 = createResultReg(RC);
2192 Register ResultReg = createResultReg(RC);
2218 const TargetRegisterClass *RC =
2228 Register ImmReg = createResultReg(RC);
2236 return PPCMaterialize64BitInt(Imm, RC);
2238 return PPCMaterialize32BitInt(Imm, RC);
2400 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
2403 return PPCMaterialize64BitInt(Imm, RC);
2405 return PPCMaterialize32BitInt(Imm, RC);
2420 const TargetRegisterClass *RC,
2429 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2430 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2439 const TargetRegisterClass* RC,
2442 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2443 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2452 const TargetRegisterClass* RC,
2455 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2456 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));