| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FlagsCopyLowering.cpp | 753 CondReg = promoteCondToReg(TestMBB, TestPos, TestLoc, Cond); in getCondOrInverseInReg() local
783 unsigned &CondReg = CondRegs[Cond]; rewriteSetCC() local
826 unsigned &CondReg = CondRegs[Cond]; rewriteArithmetic() local
900 unsigned CondReg; rewriteMI() local
[all...] |
| H A D | X86FastISel.cpp | 2109 Register CondReg = getRegForValue(Cond); X86FastEmitCMoveSelect() local
2310 Register CondReg = getRegForValue(Cond); X86FastEmitPseudoSelect() local
[all...] |
| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIPreEmitPeephole.cpp | 90 const unsigned CondReg = TRI->getVCC(); optimizeVccBranch() local
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| H A D | SIOptimizeExecMaskingPreRA.cpp | 39 MCRegister CondReg; member in __anon8f09429c0111::SIOptimizeExecMaskingPreRA
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| H A D | SIInstrInfo.cpp | 3143 preserveCondRegFlags(MachineOperand & CondReg,const MachineOperand & OrigCond) preserveCondRegFlags() argument
3198 MachineOperand &CondReg = CondBr->getOperand(1); insertBranch() local
6276 Register CondReg; emitLoadScalarOpsFromVGPRLoop() local
7131 Register CondReg = Inst.getOperand(1).getReg(); moveToVALUImpl() local
7289 Register CondReg = MRI.createVirtualRegister(RI.getWaveMaskRegClass()); moveToVALUImpl() local
7548 Register CondReg = Cond.getReg(); lowerSelect() local
[all...] |
| H A D | AMDGPURegisterBankInfo.cpp | 861 Register CondReg; in executeInWaterfallLoop() local
2365 Register CondReg = MI.getOperand(0).getReg(); applyMappingImpl() local
[all...] |
| H A D | AMDGPUMachineCFGStructurizer.cpp | |
| H A D | AMDGPUISelDAGToDAG.cpp | 2484 Register CondReg = UseSCCBr ? AMDGPU::SCC : TRI->getVCC(); SelectBRCOND() local
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| H A D | AMDGPUInstructionSelector.cpp | 2840 Register CondReg = CondOp.getReg(); selectG_BRCOND() local
[all...] |
| H A D | SIISelLowering.cpp | 4463 Register CondReg = MRI.createVirtualRegister(BoolRC); emitLoadM0FromVGPRLoop() local
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| /llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFastISel.cpp | 916 unsigned CondReg = selectSelect() local
1321 unsigned CondReg = getRegForI1Value(Br->getCondition(), Br->getParent(), Not); selectBr() local
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| /llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 961 Register CondReg = getRegForValue(BI->getCondition()); selectBranch() local
1040 Register CondReg = getRegForValue(Cond); selectSelect() local
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 2476 Register CondReg = getRegForValue(BI->getCondition()); selectBranch() local
2490 Register CondReg = getRegForValue(BI->getCondition()); selectBranch() local
2712 Register CondReg = getRegForValue(Cond); selectSelect() local
2761 Register CondReg = getRegForValue(Cond); selectSelect() local
[all...] |
| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 776 auto CondReg = MIB.getReg(1); in selectSelect() local
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| H A D | ARMFastISel.cpp | 1610 Register CondReg = getRegForValue(I->getOperand(0)); SelectSelect() local
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| /llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVInstructionSelector.cpp | 444 getOperandsForBranch(Register CondReg,MachineRegisterInfo & MRI,RISCVCC::CondCode & CC,Register & LHS,Register & RHS) getOperandsForBranch() argument
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| /llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 1476 const Register CondReg = I.getOperand(0).getReg(); selectCondBranch() local
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| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 785 Register CondReg = createResultReg(&PPC::CRRCRegClass); SelectBranch() local
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| /llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 1811 Register CondReg = I.getOperand(0).getReg(); selectCompareBranch() local
3399 const Register CondReg = Sel.getCondReg(); select() local
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| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 6161 Register CondReg = MI.getOperand(1).getReg(); narrowScalarSelect() local
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