[RISCV][GISel] Support G_MERGE_VALUES/G_UNMERGE_VALUES with Zfa. (#120379)

Without Zfa we use pseudos that are lowered to a stack load/store. With
Zfa we have instructions that can move a pair of r

[RISCV][GISel] Support G_MERGE_VALUES/G_UNMERGE_VALUES with Zfa. (#120379)

Without Zfa we use pseudos that are lowered to a stack load/store. With
Zfa we have instructions that can move a pair of registers to an FPR. Or
move the high or low half of an FPR to a GPR.

I've used a GINodeEquiv to make use of 3 of the 4 tablegen patterns. The
split case with Zfa requires 2 instructions which I'm doing through
custom isel like we do in SelectionDAG.

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[RISCV] Pattern-match frameindex (#120917)

[RISCV][GISel] Port AddiPair optimization (#120463)

Check if (add r, imm) can be optimized to (ADDI (ADDI r, imm0), imm1),
in which imm = imm0 + imml and both imm0 and imm1 are simm12. We make
imm

[RISCV][GISel] Port AddiPair optimization (#120463)

Check if (add r, imm) can be optimized to (ADDI (ADDI r, imm0), imm1),
in which imm = imm0 + imml and both imm0 and imm1 are simm12. We make
imm0 as large as possible and imm1 as small as possible so that we might
be able to use c.addi for the small immediate.

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[RISCV][GISel] Port TrailingOnesMask PatLeaf. (#119427)

[RISCV][GISel] Use correct shift width for GIShiftMask32 ComplexOperandMatcher.

We should use 32 instead of XLen. This allows us to remove
'and X, 31' from the shift amount.

[RISCV][GISel] Move G_BRJT expansion to legalization (#73711)

Instead of custom selecting a bunch of instructions, we can expand to
generic MIR during legalization.

[llvm] Remove redundant control flow statements (NFC) (#115831)

Identified with readability-redundant-control-flow.

[Target] Migrate away from PointerUnion::{is,get,dyn_cast} (NFC) (#115623)

Note that PointerUnion::{is,get,dyn_cast} have been soft deprecated in
PointerUnion.h:

// FIXME: Replace the uses of

[Target] Migrate away from PointerUnion::{is,get,dyn_cast} (NFC) (#115623)

Note that PointerUnion::{is,get,dyn_cast} have been soft deprecated in
PointerUnion.h:

// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>

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[GISel][AArch64][RISCV] Allow G_SEXT_INREG patterns to be imported. (#115576)

SelectionDAG uses VTSDNode to store the extension type. GlobalISel uses
a literal constant operand.

For vectors, Sel

[GISel][AArch64][RISCV] Allow G_SEXT_INREG patterns to be imported. (#115576)

SelectionDAG uses VTSDNode to store the extension type. GlobalISel uses
a literal constant operand.

For vectors, SelectionDAG uses a type with the same number of elements
as other operand of the sext_inreg. I assume for GISel we would just use
the scalar size.

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[RISCV][GISel] Add G_ZEXT to RISCVInstructionSelector::selectZExtBits. (#115391)

[RISCV][GISel] Remove s32 input support for G_SITOFP/UITOFP on RV64. (#115236)

I plan to make i32 an illegal type for RV64 to match SelectionDAG and to
remove i32 from the GPR register class.

I'

[RISCV][GISel] Remove s32 input support for G_SITOFP/UITOFP on RV64. (#115236)

I plan to make i32 an illegal type for RV64 to match SelectionDAG and to
remove i32 from the GPR register class.

I've added a sexti32 ComplexPattern to select sext.w+fcvt.s.l as
fcvt.s.w. The recently added zexti32 handles selecting and+fcvt.s.lu as
fcvt.s.wu. There are still some regressions that suggest we should match
g_zero_extend in zexti32.

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[RISCV][GISel] Use maskedValueIsZero in RISCVInstructionSelector::selectZExtBits. (#115244)

[RISCV][GISel] Implement zexti32/zexti16 ComplexPatterns. (#115097)

[RISCV][GISEL][NFC] Add break statement to reduce diff on future changes of preISelLower

[RISCV][GISEL] instruction-select vmclr (#110782)

This is stacked on #110778. This PR adds and tests renderVLOp too, as
that is needed from vmclr.

[RISCV][GISEL][NFC] Make MRI a member in RISCVInstructionSelector (#110926)

It was requested in
https://github.com/llvm/llvm-project/pull/110782#discussion_r1784939348
that MRI be made a member of

[RISCV][GISEL][NFC] Make MRI a member in RISCVInstructionSelector (#110926)

It was requested in
https://github.com/llvm/llvm-project/pull/110782#discussion_r1784939348
that MRI be made a member of RISCVInstructionSelector.

RISCVInstructionSelector is created in the RISCVSubtarget, independent
of MachineFunction. So it cannot be passed by reference during
construction of RISCVInstructionSelector.

The MachineRegisterInfo object belongs to each MachineFunction, so
set it in setupMF.

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[RISCV][GISel] Support G_SEXT_INREG for Zbb. (#102682)

[GISel] Make create.*InstructionSelector arguments const (#98243)

The InstructionSelector objects all take these arguments in as `const`.
This function does not modify the object. Therefore we can

[GISel] Make create.*InstructionSelector arguments const (#98243)

The InstructionSelector objects all take these arguments in as `const`.
This function does not modify the object. Therefore we can mark them as
`const` here.

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[RISCV][GISel] Support fcmp and fclass for Zfh. (#96696)

[RISCV][GISel] Support G_FCONSTANT for Zfh.

[RISCV][GISel] Add calling convention support for half (#94110)

This patch adds initial support to the half type on RISC-V.

[GISel][RISCV] Add irtranslator/legalizer/selector support for G_FREEZE. (#92744)

This patch adds support for G_FREEZE on riscv. It will be selected into
a copy instruction.

The ll test is copi

[GISel][RISCV] Add irtranslator/legalizer/selector support for G_FREEZE. (#92744)

This patch adds support for G_FREEZE on riscv. It will be selected into
a copy instruction.

The ll test is copied from the AArch64 patch:
https://github.com/llvm/llvm-project/commit/665da596854bf07ee25f368855156dde43845013.

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[RISCV][GlobalISel] Fix selectShiftMask when shift mask is created from G_AND (#89602)

This patch fixes cases where G_AND creating the shift mask is eliminated
if one of its source operands is a co

[RISCV][GlobalISel] Fix selectShiftMask when shift mask is created from G_AND (#89602)

This patch fixes cases where G_AND creating the shift mask is eliminated
if one of its source operands is a constant, resulting from an incorrect
predicate.

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[GlobalISel] Introduce G_TRAP, G_DEBUGTRAP, G_UBSANTRAP (#84941)

Here we introduce three new GMIR instructions to cover a set of trap
intrinsics. The idea behind it is that generic intrinsics shoul

[GlobalISel] Introduce G_TRAP, G_DEBUGTRAP, G_UBSANTRAP (#84941)

Here we introduce three new GMIR instructions to cover a set of trap
intrinsics. The idea behind it is that generic intrinsics shouldn't be
used with G_INTRINSIC opcode.

These new instructions can match perfectly with existing trap ISD nodes.
It allows X86, AArch64, RISCV and Mips to reuse SelectionDAG patterns for
selection and avoid manual selection. However AMDGPU is an exception. It
selects traps during legalization regardless SelectionDAG or GlobalISel.

Since there are not many places where traps are used, this change
attempts to clean up all the usages of G_INTRINSIC with trap intrinsics. So,
there is no stage when both G_TRAP and
G_INTRINSIC_W_SIDE_EFFECTS(@llvm.trap) are allowed.

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[RISCV][GISel] RegBank select and instruction select for vector G_ADD, G_SUB (#74114)

RegisterBank Selection for scalable vector G_ADD and G_SUB by creating
new mappings for different types of vect

[RISCV][GISel] RegBank select and instruction select for vector G_ADD, G_SUB (#74114)

RegisterBank Selection for scalable vector G_ADD and G_SUB by creating
new mappings for different types of vector register banks.
Then implement Instruction Selection for the same operations by choosing
the correct RISC-V vector register class.

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