Lines Matching defs:CondReg

3191 static void preserveCondRegFlags(MachineOperand &CondReg,
3193   CondReg.setIsUndef(OrigCond.isUndef());
3194   CondReg.setIsKill(OrigCond.isKill());
3239   MachineOperand &CondReg = CondBr->getOperand(1);
3240   CondReg.setIsUndef(Cond[1].isUndef());
3241   CondReg.setIsKill(Cond[1].isKill());
6462   Register CondReg;
6482       if (!CondReg) // First.
6483         CondReg = NewCondReg;
6487             .addReg(CondReg)
6489         CondReg = AndReg;
6536         if (!CondReg) // First.
6537           CondReg = NewCondReg;
6541               .addReg(CondReg)
6543           CondReg = AndReg;
6566   MRI.setSimpleHint(SaveExec, CondReg);
6570       .addReg(CondReg, RegState::Kill);
7319     Register CondReg = Inst.getOperand(1).getReg();
7320     bool IsSCC = CondReg == AMDGPU::SCC;
7326         .addReg(IsSCC ? VCC : CondReg);
7463     Register CondReg = MRI.createVirtualRegister(RI.getWaveMaskRegClass());
7465         BuildMI(*MBB, Inst, Inst.getDebugLoc(), get(NewOpcode), CondReg)
7481     addSCCDefUsersToVALUWorklist(SCCOp, Inst, Worklist, CondReg);
7499     Register CondReg = MRI.createVirtualRegister(RI.getWaveMaskRegClass());
7501         BuildMI(*MBB, Inst, Inst.getDebugLoc(), get(NewOpcode), CondReg)
7520     addSCCDefUsersToVALUWorklist(SCCOp, Inst, Worklist, CondReg);
7788   Register CondReg = Cond.getReg();
7789   bool IsSCC = (CondReg == AMDGPU::SCC);
7792   // (CondReg is a source of copy to SCC), then the select is semantically
7793   // equivalent to copying CondReg. Hence, there is no need to create
7797     MRI.replaceRegWith(Dest.getReg(), CondReg);
7801   Register NewCondReg = CondReg;
7807     // replacing the CondReg with the COPY source register