Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.

llvm-svn: 137347

Continue to tighten decoding by performing more operand validation.

llvm-svn: 137340

ARM STRBT assembly parsing and encoding.

llvm-svn: 137337

Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.

llvm-svn: 137325

Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC.

llvm-svn: 137323

Improve error checking in the new ARM disassembler. Patch by James Molloy.

llvm-svn: 137320

ARM LDRT assembly parsing and encoding.

llvm-svn: 137282

Add initial support for decoding NEON instructions in Thumb2 mode.

llvm-svn: 137236

Cleanups based on Nick Lewycky's feedback.

llvm-svn: 137224

Push GPRnopc through a large number of instruction definitions to tighten operand decoding.

llvm-svn: 137189

Tighten operand checking of register-shifted-register operands.

llvm-svn: 137180

Tighten operand checking on memory barrier instructions.

llvm-svn: 137176

Tighten operand checking on CPS instructions.

llvm-svn: 137172

Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI.

llvm-svn: 137168

ARM Disassembler: sign extend branch immediates.

Not sure about BLXi, but this is what the old disassembler did.

llvm-svn: 137156

Silence an false-positive warning.

llvm-svn: 137154

Tighten Thumb1 branch predicate decoding.

llvm-svn: 137146

Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected fail

Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.

llvm-svn: 137144

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ARM refactoring assembly parsing of memory address operands.

Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory oper

ARM refactoring assembly parsing of memory address operands.

Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.

The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.

This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.

Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.

llvm-svn: 136845

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Fix typo in the comment.

llvm-svn: 129837

Adding support for printing operands symbolically to llvm's public 'C'
disassembler API. Hooked this up to the ARM target so such tools as Darwin's
otool(1) can now print things like branch targets

Adding support for printing operands symbolically to llvm's public 'C'
disassembler API. Hooked this up to the ARM target so such tools as Darwin's
otool(1) can now print things like branch targets for example this:
blx _puts
instead of this:
blx #-36
And even print the expression encoded in the Mach-O relocation entried for
things like this:
movt r0, :upper16:((_foo-_bar)+1234)

llvm-svn: 129284

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Fixed the t2PLD and friends disassembly and add two test cases.

llvm-svn: 128322

Plug a leak by ThumbDisassembler::getInstruction(), thanks to Benjamin Kramer!

llvm-svn: 128241

Plug a leak in the arm disassembler and put the tests back.

llvm-svn: 128238

For ARM Disassembler, start a newline to dump the opcode and friends for an instruction.
Change inspired by llvm-bug 9530 submitted by Jyun-Yan You.

llvm-svn: 128122