1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARMDisassembler.h" 13 #include "ARM.h" 14 #include "ARMRegisterInfo.h" 15 #include "MCTargetDesc/ARMAddressingModes.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/Target/TargetRegistry.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/raw_ostream.h" 26 27 // Forward declare these because the autogenerated code will reference them. 28 // Definitions are further down. 29 static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 30 uint64_t Address, const void *Decoder); 31 static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 32 uint64_t Address, const void *Decoder); 33 static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 34 uint64_t Address, const void *Decoder); 35 static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 36 uint64_t Address, const void *Decoder); 37 static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 38 uint64_t Address, const void *Decoder); 39 static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 40 uint64_t Address, const void *Decoder); 41 static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 42 uint64_t Address, const void *Decoder); 43 static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 44 uint64_t Address, const void *Decoder); 45 static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 46 uint64_t Address, const void *Decoder); 47 static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 48 uint64_t Address, const void *Decoder); 49 50 static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 51 uint64_t Address, const void *Decoder); 52 static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 53 uint64_t Address, const void *Decoder); 54 static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 55 uint64_t Address, const void *Decoder); 56 static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 57 uint64_t Address, const void *Decoder); 58 static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 59 uint64_t Address, const void *Decoder); 60 static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 61 uint64_t Address, const void *Decoder); 62 static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 63 uint64_t Address, const void *Decoder); 64 65 static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 66 uint64_t Address, const void *Decoder); 67 static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 68 uint64_t Address, const void *Decoder); 69 static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 70 uint64_t Address, const void *Decoder); 71 static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 72 uint64_t Address, const void *Decoder); 73 static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 74 uint64_t Address, const void *Decoder); 75 static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 76 uint64_t Address, const void *Decoder); 77 static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 78 uint64_t Address, const void *Decoder); 79 80 static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 81 unsigned Insn, 82 uint64_t Adddress, 83 const void *Decoder); 84 static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 85 uint64_t Address, const void *Decoder); 86 static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 87 uint64_t Address, const void *Decoder); 88 static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 89 uint64_t Address, const void *Decoder); 90 static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 91 uint64_t Address, const void *Decoder); 92 static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 93 uint64_t Address, const void *Decoder); 94 static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 95 uint64_t Address, const void *Decoder); 96 static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 97 uint64_t Address, const void *Decoder); 98 static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 99 uint64_t Address, const void *Decoder); 100 static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 101 uint64_t Address, const void *Decoder); 102 static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 103 uint64_t Address, const void *Decoder); 104 static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 105 uint64_t Address, const void *Decoder); 106 static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 107 uint64_t Address, const void *Decoder); 108 static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 109 uint64_t Address, const void *Decoder); 110 static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 111 uint64_t Address, const void *Decoder); 112 static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Val, 113 uint64_t Address, const void *Decoder); 114 static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 115 uint64_t Address, const void *Decoder); 116 static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 117 uint64_t Address, const void *Decoder); 118 static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 119 uint64_t Address, const void *Decoder); 120 static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 121 uint64_t Address, const void *Decoder); 122 static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 123 uint64_t Address, const void *Decoder); 124 static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 125 uint64_t Address, const void *Decoder); 126 static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 127 uint64_t Address, const void *Decoder); 128 static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 129 uint64_t Address, const void *Decoder); 130 static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 131 uint64_t Address, const void *Decoder); 132 static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Insn, 133 uint64_t Address, const void *Decoder); 134 static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 135 uint64_t Address, const void *Decoder); 136 137 138 static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 139 uint64_t Address, const void *Decoder); 140 static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 141 uint64_t Address, const void *Decoder); 142 static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 143 uint64_t Address, const void *Decoder); 144 static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 145 uint64_t Address, const void *Decoder); 146 static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 147 uint64_t Address, const void *Decoder); 148 static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 149 uint64_t Address, const void *Decoder); 150 static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 151 uint64_t Address, const void *Decoder); 152 static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 153 uint64_t Address, const void *Decoder); 154 static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 155 uint64_t Address, const void *Decoder); 156 static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 157 uint64_t Address, const void *Decoder); 158 static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 159 uint64_t Address, const void *Decoder); 160 static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 161 uint64_t Address, const void *Decoder); 162 static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 163 uint64_t Address, const void *Decoder); 164 static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 165 uint64_t Address, const void *Decoder); 166 static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 167 uint64_t Address, const void *Decoder); 168 static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 169 uint64_t Address, const void *Decoder); 170 static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 171 uint64_t Address, const void *Decoder); 172 static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 173 uint64_t Address, const void *Decoder); 174 static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 175 uint64_t Address, const void *Decoder); 176 static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, 177 uint64_t Address, const void *Decoder); 178 static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 179 uint64_t Address, const void *Decoder); 180 static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 181 uint64_t Address, const void *Decoder); 182 static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 183 uint64_t Address, const void *Decoder); 184 static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 185 uint64_t Address, const void *Decoder); 186 187 #include "ARMGenDisassemblerTables.inc" 188 #include "ARMGenInstrInfo.inc" 189 #include "ARMGenEDInfo.inc" 190 191 using namespace llvm; 192 193 static MCDisassembler *createARMDisassembler(const Target &T) { 194 return new ARMDisassembler; 195 } 196 197 static MCDisassembler *createThumbDisassembler(const Target &T) { 198 return new ThumbDisassembler; 199 } 200 201 EDInstInfo *ARMDisassembler::getEDInfo() const { 202 return instInfoARM; 203 } 204 205 EDInstInfo *ThumbDisassembler::getEDInfo() const { 206 return instInfoARM; 207 } 208 209 210 bool ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 211 const MemoryObject &Region, 212 uint64_t Address,raw_ostream &os) const { 213 uint8_t bytes[4]; 214 215 // We want to read exactly 4 bytes of data. 216 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 217 return false; 218 219 // Encoded as a small-endian 32-bit word in the stream. 220 uint32_t insn = (bytes[3] << 24) | 221 (bytes[2] << 16) | 222 (bytes[1] << 8) | 223 (bytes[0] << 0); 224 225 // Calling the auto-generated decoder function. 226 bool result = decodeARMInstruction32(MI, insn, Address, this); 227 if (result) { 228 Size = 4; 229 return true; 230 } 231 232 // Instructions that are shared between ARM and Thumb modes. 233 // FIXME: This shouldn't really exist. It's an artifact of the 234 // fact that we fail to encode a few instructions properly for Thumb. 235 MI.clear(); 236 result = decodeCommonInstruction32(MI, insn, Address, this); 237 if (result) { 238 Size = 4; 239 return true; 240 } 241 242 // VFP and NEON instructions, similarly, are shared between ARM 243 // and Thumb modes. 244 MI.clear(); 245 result = decodeVFPInstruction32(MI, insn, Address, this); 246 if (result) { 247 Size = 4; 248 return true; 249 } 250 251 MI.clear(); 252 result = decodeNEONDataInstruction32(MI, insn, Address, this); 253 if (result) { 254 Size = 4; 255 // Add a fake predicate operand, because we share these instruction 256 // definitions with Thumb2 where these instructions are predicable. 257 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 258 return true; 259 } 260 261 MI.clear(); 262 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this); 263 if (result) { 264 Size = 4; 265 // Add a fake predicate operand, because we share these instruction 266 // definitions with Thumb2 where these instructions are predicable. 267 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 268 return true; 269 } 270 271 MI.clear(); 272 result = decodeNEONDupInstruction32(MI, insn, Address, this); 273 if (result) { 274 Size = 4; 275 // Add a fake predicate operand, because we share these instruction 276 // definitions with Thumb2 where these instructions are predicable. 277 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 278 return true; 279 } 280 281 MI.clear(); 282 283 return false; 284 } 285 286 namespace llvm { 287 extern MCInstrDesc ARMInsts[]; 288 } 289 290 // Thumb1 instructions don't have explicit S bits. Rather, they 291 // implicitly set CPSR. Since it's not represented in the encoding, the 292 // auto-generated decoder won't inject the CPSR operand. We need to fix 293 // that as a post-pass. 294 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 295 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 296 MCInst::iterator I = MI.begin(); 297 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 298 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 299 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 300 return; 301 } 302 } 303 304 if (OpInfo[MI.size()].isOptionalDef() && 305 OpInfo[MI.size()].RegClass == ARM::CCRRegClassID) 306 MI.insert(MI.end(), MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 307 } 308 309 // Most Thumb instructions don't have explicit predicates in the 310 // encoding, but rather get their predicates from IT context. We need 311 // to fix up the predicate operands using this context information as a 312 // post-pass. 313 void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 314 // A few instructions actually have predicates encoded in them. Don't 315 // try to overwrite it if we're seeing one of those. 316 switch (MI.getOpcode()) { 317 case ARM::tBcc: 318 case ARM::t2Bcc: 319 return; 320 default: 321 break; 322 } 323 324 // If we're in an IT block, base the predicate on that. Otherwise, 325 // assume a predicate of AL. 326 unsigned CC; 327 if (!ITBlock.empty()) { 328 CC = ITBlock.back(); 329 ITBlock.pop_back(); 330 } else 331 CC = ARMCC::AL; 332 333 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 334 MCInst::iterator I = MI.begin(); 335 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 336 if (OpInfo[i].isPredicate()) { 337 I = MI.insert(I, MCOperand::CreateImm(CC)); 338 ++I; 339 if (CC == ARMCC::AL) 340 MI.insert(I, MCOperand::CreateReg(0)); 341 else 342 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 343 return; 344 } 345 } 346 347 MI.insert(MI.end(), MCOperand::CreateImm(CC)); 348 if (CC == ARMCC::AL) 349 MI.insert(MI.end(), MCOperand::CreateReg(0)); 350 else 351 MI.insert(MI.end(), MCOperand::CreateReg(ARM::CPSR)); 352 } 353 354 // Thumb VFP instructions are a special case. Because we share their 355 // encodings between ARM and Thumb modes, and they are predicable in ARM 356 // mode, the auto-generated decoder will give them an (incorrect) 357 // predicate operand. We need to rewrite these operands based on the IT 358 // context as a post-pass. 359 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 360 unsigned CC; 361 if (!ITBlock.empty()) { 362 CC = ITBlock.back(); 363 ITBlock.pop_back(); 364 } else 365 CC = ARMCC::AL; 366 367 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 368 MCInst::iterator I = MI.begin(); 369 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 370 if (OpInfo[i].isPredicate() ) { 371 I->setImm(CC); 372 ++I; 373 if (CC == ARMCC::AL) 374 I->setReg(0); 375 else 376 I->setReg(ARM::CPSR); 377 return; 378 } 379 } 380 } 381 382 383 bool ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 384 const MemoryObject &Region, 385 uint64_t Address,raw_ostream &os) const { 386 uint8_t bytes[4]; 387 388 // We want to read exactly 2 bytes of data. 389 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) 390 return false; 391 392 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 393 bool result = decodeThumbInstruction16(MI, insn16, Address, this); 394 if (result) { 395 Size = 2; 396 bool InITBlock = !ITBlock.empty(); 397 AddThumbPredicate(MI); 398 AddThumb1SBit(MI, InITBlock); 399 return true; 400 } 401 402 MI.clear(); 403 result = decodeThumb2Instruction16(MI, insn16, Address, this); 404 if (result) { 405 Size = 2; 406 AddThumbPredicate(MI); 407 408 // If we find an IT instruction, we need to parse its condition 409 // code and mask operands so that we can apply them correctly 410 // to the subsequent instructions. 411 if (MI.getOpcode() == ARM::t2IT) { 412 unsigned firstcond = MI.getOperand(0).getImm(); 413 uint32_t mask = MI.getOperand(1).getImm(); 414 unsigned zeros = CountTrailingZeros_32(mask); 415 mask >>= zeros+1; 416 417 for (unsigned i = 0; i < 4 - (zeros+1); ++i) { 418 if (firstcond ^ (mask & 1)) 419 ITBlock.push_back(firstcond ^ 1); 420 else 421 ITBlock.push_back(firstcond); 422 mask >>= 1; 423 } 424 ITBlock.push_back(firstcond); 425 } 426 427 return true; 428 } 429 430 // We want to read exactly 4 bytes of data. 431 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 432 return false; 433 434 uint32_t insn32 = (bytes[3] << 8) | 435 (bytes[2] << 0) | 436 (bytes[1] << 24) | 437 (bytes[0] << 16); 438 MI.clear(); 439 result = decodeThumbInstruction32(MI, insn32, Address, this); 440 if (result) { 441 Size = 4; 442 bool InITBlock = ITBlock.size(); 443 AddThumbPredicate(MI); 444 AddThumb1SBit(MI, InITBlock); 445 return true; 446 } 447 448 MI.clear(); 449 result = decodeThumb2Instruction32(MI, insn32, Address, this); 450 if (result) { 451 Size = 4; 452 AddThumbPredicate(MI); 453 return true; 454 } 455 456 MI.clear(); 457 result = decodeCommonInstruction32(MI, insn32, Address, this); 458 if (result) { 459 Size = 4; 460 AddThumbPredicate(MI); 461 return true; 462 } 463 464 MI.clear(); 465 result = decodeVFPInstruction32(MI, insn32, Address, this); 466 if (result) { 467 Size = 4; 468 UpdateThumbVFPPredicate(MI); 469 return true; 470 } 471 472 MI.clear(); 473 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 474 uint32_t NEONDataInsn = insn32; 475 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 476 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 477 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 478 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this); 479 if (result) { 480 Size = 4; 481 AddThumbPredicate(MI); 482 return true; 483 } 484 } 485 486 MI.clear(); 487 result = decodeNEONLoadStoreInstruction32(MI, insn32, Address, this); 488 if (result) { 489 Size = 4; 490 AddThumbPredicate(MI); 491 return true; 492 } 493 494 MI.clear(); 495 result = decodeNEONDupInstruction32(MI, insn32, Address, this); 496 if (result) { 497 Size = 4; 498 AddThumbPredicate(MI); 499 return true; 500 } 501 502 return false; 503 } 504 505 506 extern "C" void LLVMInitializeARMDisassembler() { 507 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 508 createARMDisassembler); 509 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 510 createThumbDisassembler); 511 } 512 513 static const unsigned GPRDecoderTable[] = { 514 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 515 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 516 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 517 ARM::R12, ARM::SP, ARM::LR, ARM::PC 518 }; 519 520 static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 521 uint64_t Address, const void *Decoder) { 522 if (RegNo > 15) 523 return false; 524 525 unsigned Register = GPRDecoderTable[RegNo]; 526 Inst.addOperand(MCOperand::CreateReg(Register)); 527 return true; 528 } 529 530 static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 531 uint64_t Address, const void *Decoder) { 532 if (RegNo == 15) return false; 533 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 534 } 535 536 static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 537 uint64_t Address, const void *Decoder) { 538 if (RegNo > 7) 539 return false; 540 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 541 } 542 543 static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 544 uint64_t Address, const void *Decoder) { 545 unsigned Register = 0; 546 switch (RegNo) { 547 case 0: 548 Register = ARM::R0; 549 break; 550 case 1: 551 Register = ARM::R1; 552 break; 553 case 2: 554 Register = ARM::R2; 555 break; 556 case 3: 557 Register = ARM::R3; 558 break; 559 case 9: 560 Register = ARM::R9; 561 break; 562 case 12: 563 Register = ARM::R12; 564 break; 565 default: 566 return false; 567 } 568 569 Inst.addOperand(MCOperand::CreateReg(Register)); 570 return true; 571 } 572 573 static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 574 uint64_t Address, const void *Decoder) { 575 if (RegNo == 13 || RegNo == 15) return false; 576 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 577 } 578 579 static const unsigned SPRDecoderTable[] = { 580 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 581 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 582 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 583 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 584 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 585 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 586 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 587 ARM::S28, ARM::S29, ARM::S30, ARM::S31 588 }; 589 590 static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 591 uint64_t Address, const void *Decoder) { 592 if (RegNo > 31) 593 return false; 594 595 unsigned Register = SPRDecoderTable[RegNo]; 596 Inst.addOperand(MCOperand::CreateReg(Register)); 597 return true; 598 } 599 600 static const unsigned DPRDecoderTable[] = { 601 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 602 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 603 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 604 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 605 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 606 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 607 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 608 ARM::D28, ARM::D29, ARM::D30, ARM::D31 609 }; 610 611 static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 612 uint64_t Address, const void *Decoder) { 613 if (RegNo > 31) 614 return false; 615 616 unsigned Register = DPRDecoderTable[RegNo]; 617 Inst.addOperand(MCOperand::CreateReg(Register)); 618 return true; 619 } 620 621 static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 622 uint64_t Address, const void *Decoder) { 623 if (RegNo > 7) 624 return false; 625 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 626 } 627 628 static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 629 uint64_t Address, const void *Decoder) { 630 if (RegNo > 15) 631 return false; 632 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 633 } 634 635 static const unsigned QPRDecoderTable[] = { 636 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 637 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 638 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 639 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 640 }; 641 642 643 static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 644 uint64_t Address, const void *Decoder) { 645 if (RegNo > 31) 646 return false; 647 RegNo >>= 1; 648 649 unsigned Register = QPRDecoderTable[RegNo]; 650 Inst.addOperand(MCOperand::CreateReg(Register)); 651 return true; 652 } 653 654 static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 655 uint64_t Address, const void *Decoder) { 656 if (Val == 0xF) return false; 657 // AL predicate is not allowed on Thumb1 branches. 658 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 659 return false; 660 Inst.addOperand(MCOperand::CreateImm(Val)); 661 if (Val == ARMCC::AL) { 662 Inst.addOperand(MCOperand::CreateReg(0)); 663 } else 664 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 665 return true; 666 } 667 668 static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 669 uint64_t Address, const void *Decoder) { 670 if (Val) 671 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 672 else 673 Inst.addOperand(MCOperand::CreateReg(0)); 674 return true; 675 } 676 677 static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 678 uint64_t Address, const void *Decoder) { 679 uint32_t imm = Val & 0xFF; 680 uint32_t rot = (Val & 0xF00) >> 7; 681 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 682 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 683 return true; 684 } 685 686 static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 687 uint64_t Address, const void *Decoder) { 688 Val <<= 2; 689 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val))); 690 return true; 691 } 692 693 static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 694 uint64_t Address, const void *Decoder) { 695 696 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 697 unsigned type = fieldFromInstruction32(Val, 5, 2); 698 unsigned imm = fieldFromInstruction32(Val, 7, 5); 699 700 // Register-immediate 701 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 702 703 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 704 switch (type) { 705 case 0: 706 Shift = ARM_AM::lsl; 707 break; 708 case 1: 709 Shift = ARM_AM::lsr; 710 break; 711 case 2: 712 Shift = ARM_AM::asr; 713 break; 714 case 3: 715 Shift = ARM_AM::ror; 716 break; 717 } 718 719 if (Shift == ARM_AM::ror && imm == 0) 720 Shift = ARM_AM::rrx; 721 722 unsigned Op = Shift | (imm << 3); 723 Inst.addOperand(MCOperand::CreateImm(Op)); 724 725 return true; 726 } 727 728 static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 729 uint64_t Address, const void *Decoder) { 730 731 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 732 unsigned type = fieldFromInstruction32(Val, 5, 2); 733 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 734 735 // Register-register 736 if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; 737 if (!DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)) return false; 738 739 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 740 switch (type) { 741 case 0: 742 Shift = ARM_AM::lsl; 743 break; 744 case 1: 745 Shift = ARM_AM::lsr; 746 break; 747 case 2: 748 Shift = ARM_AM::asr; 749 break; 750 case 3: 751 Shift = ARM_AM::ror; 752 break; 753 } 754 755 Inst.addOperand(MCOperand::CreateImm(Shift)); 756 757 return true; 758 } 759 760 static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 761 uint64_t Address, const void *Decoder) { 762 for (unsigned i = 0; i < 16; ++i) { 763 if (Val & (1 << i)) { 764 if (!DecodeGPRRegisterClass(Inst, i, Address, Decoder)) return false; 765 } 766 } 767 768 return true; 769 } 770 771 static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 772 uint64_t Address, const void *Decoder) { 773 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 774 unsigned regs = Val & 0xFF; 775 776 if (!DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)) return false; 777 for (unsigned i = 0; i < (regs - 1); ++i) { 778 if (!DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false; 779 } 780 781 return true; 782 } 783 784 static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 785 uint64_t Address, const void *Decoder) { 786 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 787 unsigned regs = (Val & 0xFF) / 2; 788 789 if (!DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)) return false; 790 for (unsigned i = 0; i < (regs - 1); ++i) { 791 if (!DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false; 792 } 793 794 return true; 795 } 796 797 static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 798 uint64_t Address, const void *Decoder) { 799 // This operand encodes a mask of contiguous zeros between a specified MSB 800 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 801 // the mask of all bits LSB-and-lower, and then xor them to create 802 // the mask of that's all ones on [msb, lsb]. Finally we not it to 803 // create the final mask. 804 unsigned msb = fieldFromInstruction32(Val, 5, 5); 805 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 806 uint32_t msb_mask = (1 << (msb+1)) - 1; 807 uint32_t lsb_mask = (1 << lsb) - 1; 808 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 809 return true; 810 } 811 812 static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 813 uint64_t Address, const void *Decoder) { 814 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 815 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 816 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 817 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 818 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 819 unsigned U = fieldFromInstruction32(Insn, 23, 1); 820 821 switch (Inst.getOpcode()) { 822 case ARM::LDC_OFFSET: 823 case ARM::LDC_PRE: 824 case ARM::LDC_POST: 825 case ARM::LDC_OPTION: 826 case ARM::LDCL_OFFSET: 827 case ARM::LDCL_PRE: 828 case ARM::LDCL_POST: 829 case ARM::LDCL_OPTION: 830 case ARM::STC_OFFSET: 831 case ARM::STC_PRE: 832 case ARM::STC_POST: 833 case ARM::STC_OPTION: 834 case ARM::STCL_OFFSET: 835 case ARM::STCL_PRE: 836 case ARM::STCL_POST: 837 case ARM::STCL_OPTION: 838 if (coproc == 0xA || coproc == 0xB) 839 return false; 840 break; 841 default: 842 break; 843 } 844 845 Inst.addOperand(MCOperand::CreateImm(coproc)); 846 Inst.addOperand(MCOperand::CreateImm(CRd)); 847 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 848 switch (Inst.getOpcode()) { 849 case ARM::LDC_OPTION: 850 case ARM::LDCL_OPTION: 851 case ARM::LDC2_OPTION: 852 case ARM::LDC2L_OPTION: 853 case ARM::STC_OPTION: 854 case ARM::STCL_OPTION: 855 case ARM::STC2_OPTION: 856 case ARM::STC2L_OPTION: 857 case ARM::LDCL_POST: 858 case ARM::STCL_POST: 859 break; 860 default: 861 Inst.addOperand(MCOperand::CreateReg(0)); 862 break; 863 } 864 865 unsigned P = fieldFromInstruction32(Insn, 24, 1); 866 unsigned W = fieldFromInstruction32(Insn, 21, 1); 867 868 bool writeback = (P == 0) || (W == 1); 869 unsigned idx_mode = 0; 870 if (P && writeback) 871 idx_mode = ARMII::IndexModePre; 872 else if (!P && writeback) 873 idx_mode = ARMII::IndexModePost; 874 875 switch (Inst.getOpcode()) { 876 case ARM::LDCL_POST: 877 case ARM::STCL_POST: 878 imm |= U << 8; 879 case ARM::LDC_OPTION: 880 case ARM::LDCL_OPTION: 881 case ARM::LDC2_OPTION: 882 case ARM::LDC2L_OPTION: 883 case ARM::STC_OPTION: 884 case ARM::STCL_OPTION: 885 case ARM::STC2_OPTION: 886 case ARM::STC2L_OPTION: 887 Inst.addOperand(MCOperand::CreateImm(imm)); 888 break; 889 default: 890 if (U) 891 Inst.addOperand(MCOperand::CreateImm( 892 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 893 else 894 Inst.addOperand(MCOperand::CreateImm( 895 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 896 break; 897 } 898 899 switch (Inst.getOpcode()) { 900 case ARM::LDC_OFFSET: 901 case ARM::LDC_PRE: 902 case ARM::LDC_POST: 903 case ARM::LDC_OPTION: 904 case ARM::LDCL_OFFSET: 905 case ARM::LDCL_PRE: 906 case ARM::LDCL_POST: 907 case ARM::LDCL_OPTION: 908 case ARM::STC_OFFSET: 909 case ARM::STC_PRE: 910 case ARM::STC_POST: 911 case ARM::STC_OPTION: 912 case ARM::STCL_OFFSET: 913 case ARM::STCL_PRE: 914 case ARM::STCL_POST: 915 case ARM::STCL_OPTION: 916 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 917 break; 918 default: 919 break; 920 } 921 922 return true; 923 } 924 925 static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 926 uint64_t Address, const void *Decoder) { 927 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 928 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 929 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 930 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 931 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 932 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 933 unsigned P = fieldFromInstruction32(Insn, 24, 1); 934 unsigned W = fieldFromInstruction32(Insn, 21, 1); 935 936 // On stores, the writeback operand precedes Rt. 937 switch (Inst.getOpcode()) { 938 case ARM::STR_POST_IMM: 939 case ARM::STR_POST_REG: 940 case ARM::STRTr: 941 case ARM::STRTi: 942 case ARM::STRBTr: 943 case ARM::STRBTi: 944 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 945 break; 946 default: 947 break; 948 } 949 950 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 951 952 // On loads, the writeback operand comes after Rt. 953 switch (Inst.getOpcode()) { 954 case ARM::LDR_POST_IMM: 955 case ARM::LDR_POST_REG: 956 case ARM::LDR_PRE: 957 case ARM::LDRBT_POST_REG: 958 case ARM::LDRBT_POST_IMM: 959 case ARM::LDRT_POST_REG: 960 case ARM::LDRT_POST_IMM: 961 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 962 return false; 963 break; 964 default: 965 break; 966 } 967 968 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 969 970 ARM_AM::AddrOpc Op = ARM_AM::add; 971 if (!fieldFromInstruction32(Insn, 23, 1)) 972 Op = ARM_AM::sub; 973 974 bool writeback = (P == 0) || (W == 1); 975 unsigned idx_mode = 0; 976 if (P && writeback) 977 idx_mode = ARMII::IndexModePre; 978 else if (!P && writeback) 979 idx_mode = ARMII::IndexModePost; 980 981 if (reg) { 982 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 983 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 984 switch( fieldFromInstruction32(Insn, 5, 2)) { 985 case 0: 986 Opc = ARM_AM::lsl; 987 break; 988 case 1: 989 Opc = ARM_AM::lsr; 990 break; 991 case 2: 992 Opc = ARM_AM::asr; 993 break; 994 case 3: 995 Opc = ARM_AM::ror; 996 break; 997 default: 998 return false; 999 } 1000 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1001 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1002 1003 Inst.addOperand(MCOperand::CreateImm(imm)); 1004 } else { 1005 Inst.addOperand(MCOperand::CreateReg(0)); 1006 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1007 Inst.addOperand(MCOperand::CreateImm(tmp)); 1008 } 1009 1010 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1011 1012 return true; 1013 } 1014 1015 static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1016 uint64_t Address, const void *Decoder) { 1017 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1018 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1019 unsigned type = fieldFromInstruction32(Val, 5, 2); 1020 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1021 unsigned U = fieldFromInstruction32(Val, 12, 1); 1022 1023 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1024 switch (type) { 1025 case 0: 1026 ShOp = ARM_AM::lsl; 1027 break; 1028 case 1: 1029 ShOp = ARM_AM::lsr; 1030 break; 1031 case 2: 1032 ShOp = ARM_AM::asr; 1033 break; 1034 case 3: 1035 ShOp = ARM_AM::ror; 1036 break; 1037 } 1038 1039 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1040 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1041 unsigned shift; 1042 if (U) 1043 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1044 else 1045 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1046 Inst.addOperand(MCOperand::CreateImm(shift)); 1047 1048 return true; 1049 } 1050 1051 static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1052 uint64_t Address, const void *Decoder) { 1053 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1054 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1055 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1056 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1057 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1058 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1059 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1060 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1061 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1062 1063 bool writeback = (W == 1) | (P == 0); 1064 if (writeback) { // Writeback 1065 if (P) 1066 U |= ARMII::IndexModePre << 9; 1067 else 1068 U |= ARMII::IndexModePost << 9; 1069 1070 // On stores, the writeback operand precedes Rt. 1071 switch (Inst.getOpcode()) { 1072 case ARM::STRD: 1073 case ARM::STRD_PRE: 1074 case ARM::STRD_POST: 1075 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1076 return false; 1077 break; 1078 default: 1079 break; 1080 } 1081 } 1082 1083 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) 1084 return false; 1085 switch (Inst.getOpcode()) { 1086 case ARM::STRD: 1087 case ARM::STRD_PRE: 1088 case ARM::STRD_POST: 1089 case ARM::LDRD: 1090 case ARM::LDRD_PRE: 1091 case ARM::LDRD_POST: 1092 if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) 1093 return false; 1094 break; 1095 default: 1096 break; 1097 } 1098 1099 if (writeback) { 1100 // On loads, the writeback operand comes after Rt. 1101 switch (Inst.getOpcode()) { 1102 case ARM::LDRD: 1103 case ARM::LDRD_PRE: 1104 case ARM::LDRD_POST: 1105 case ARM::LDRHTr: 1106 case ARM::LDRSBTr: 1107 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1108 return false; 1109 break; 1110 default: 1111 break; 1112 } 1113 } 1114 1115 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1116 return false; 1117 1118 if (type) { 1119 Inst.addOperand(MCOperand::CreateReg(0)); 1120 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1121 } else { 1122 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1123 return false; 1124 Inst.addOperand(MCOperand::CreateImm(U)); 1125 } 1126 1127 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1128 1129 return true; 1130 } 1131 1132 static bool DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1133 uint64_t Address, const void *Decoder) { 1134 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1135 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1136 1137 switch (mode) { 1138 case 0: 1139 mode = ARM_AM::da; 1140 break; 1141 case 1: 1142 mode = ARM_AM::ia; 1143 break; 1144 case 2: 1145 mode = ARM_AM::db; 1146 break; 1147 case 3: 1148 mode = ARM_AM::ib; 1149 break; 1150 } 1151 1152 Inst.addOperand(MCOperand::CreateImm(mode)); 1153 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1154 1155 return true; 1156 } 1157 1158 static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1159 unsigned Insn, 1160 uint64_t Address, const void *Decoder) { 1161 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1162 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1163 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1164 1165 if (pred == 0xF) { 1166 switch (Inst.getOpcode()) { 1167 case ARM::STMDA: 1168 Inst.setOpcode(ARM::RFEDA); 1169 break; 1170 case ARM::STMDA_UPD: 1171 Inst.setOpcode(ARM::RFEDA_UPD); 1172 break; 1173 case ARM::STMDB: 1174 Inst.setOpcode(ARM::RFEDB); 1175 break; 1176 case ARM::STMDB_UPD: 1177 Inst.setOpcode(ARM::RFEDB_UPD); 1178 break; 1179 case ARM::STMIA: 1180 Inst.setOpcode(ARM::RFEIA); 1181 break; 1182 case ARM::STMIA_UPD: 1183 Inst.setOpcode(ARM::RFEIA_UPD); 1184 break; 1185 case ARM::STMIB: 1186 Inst.setOpcode(ARM::RFEIB); 1187 break; 1188 case ARM::STMIB_UPD: 1189 Inst.setOpcode(ARM::RFEIB_UPD); 1190 break; 1191 } 1192 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1193 } 1194 1195 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 1196 !DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || // Tied 1197 !DecodePredicateOperand(Inst, pred, Address, Decoder) || 1198 !DecodeRegListOperand(Inst, reglist, Address, Decoder)) 1199 return false; 1200 1201 return true; 1202 } 1203 1204 static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1205 uint64_t Address, const void *Decoder) { 1206 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1207 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1208 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1209 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1210 1211 // imod == '01' --> UNPREDICTABLE 1212 if (imod == 1) return false; 1213 1214 if (M && mode && imod && iflags) { 1215 Inst.setOpcode(ARM::CPS3p); 1216 Inst.addOperand(MCOperand::CreateImm(imod)); 1217 Inst.addOperand(MCOperand::CreateImm(iflags)); 1218 Inst.addOperand(MCOperand::CreateImm(mode)); 1219 return true; 1220 } else if (!mode && !M) { 1221 Inst.setOpcode(ARM::CPS2p); 1222 Inst.addOperand(MCOperand::CreateImm(imod)); 1223 Inst.addOperand(MCOperand::CreateImm(iflags)); 1224 return true; 1225 } else if (!imod && !iflags && M) { 1226 Inst.setOpcode(ARM::CPS1p); 1227 Inst.addOperand(MCOperand::CreateImm(mode)); 1228 return true; 1229 } 1230 1231 return false; 1232 } 1233 1234 static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1235 uint64_t Address, const void *Decoder) { 1236 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1237 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1238 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1239 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1240 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1241 1242 if (pred == 0xF) 1243 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1244 1245 if (!DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder) || 1246 !DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder) || 1247 !DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder) || 1248 !DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)) 1249 return false; 1250 1251 return true; 1252 } 1253 1254 static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1255 uint64_t Address, const void *Decoder) { 1256 unsigned add = fieldFromInstruction32(Val, 12, 1); 1257 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1258 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1259 1260 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1261 return false; 1262 1263 if (!add) imm *= -1; 1264 if (imm == 0 && !add) imm = INT32_MIN; 1265 Inst.addOperand(MCOperand::CreateImm(imm)); 1266 1267 return true; 1268 } 1269 1270 static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1271 uint64_t Address, const void *Decoder) { 1272 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1273 unsigned U = fieldFromInstruction32(Val, 8, 1); 1274 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1275 1276 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1277 return false; 1278 1279 if (U) 1280 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1281 else 1282 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1283 1284 return true; 1285 } 1286 1287 static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1288 uint64_t Address, const void *Decoder) { 1289 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1290 } 1291 1292 static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1293 uint64_t Address, const void *Decoder) { 1294 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1295 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1296 1297 if (pred == 0xF) { 1298 Inst.setOpcode(ARM::BLXi); 1299 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1300 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1301 return true; 1302 } 1303 1304 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1305 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1306 1307 return true; 1308 } 1309 1310 1311 static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1312 uint64_t Address, const void *Decoder) { 1313 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1314 return true; 1315 } 1316 1317 static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1318 uint64_t Address, const void *Decoder) { 1319 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1320 unsigned align = fieldFromInstruction32(Val, 4, 2); 1321 1322 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1323 return false; 1324 if (!align) 1325 Inst.addOperand(MCOperand::CreateImm(0)); 1326 else 1327 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1328 1329 return true; 1330 } 1331 1332 static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1333 uint64_t Address, const void *Decoder) { 1334 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1335 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1336 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1337 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1338 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1339 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1340 1341 // First output register 1342 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1343 1344 // Second output register 1345 switch (Inst.getOpcode()) { 1346 case ARM::VLD1q8: 1347 case ARM::VLD1q16: 1348 case ARM::VLD1q32: 1349 case ARM::VLD1q64: 1350 case ARM::VLD1q8_UPD: 1351 case ARM::VLD1q16_UPD: 1352 case ARM::VLD1q32_UPD: 1353 case ARM::VLD1q64_UPD: 1354 case ARM::VLD1d8T: 1355 case ARM::VLD1d16T: 1356 case ARM::VLD1d32T: 1357 case ARM::VLD1d64T: 1358 case ARM::VLD1d8T_UPD: 1359 case ARM::VLD1d16T_UPD: 1360 case ARM::VLD1d32T_UPD: 1361 case ARM::VLD1d64T_UPD: 1362 case ARM::VLD1d8Q: 1363 case ARM::VLD1d16Q: 1364 case ARM::VLD1d32Q: 1365 case ARM::VLD1d64Q: 1366 case ARM::VLD1d8Q_UPD: 1367 case ARM::VLD1d16Q_UPD: 1368 case ARM::VLD1d32Q_UPD: 1369 case ARM::VLD1d64Q_UPD: 1370 case ARM::VLD2d8: 1371 case ARM::VLD2d16: 1372 case ARM::VLD2d32: 1373 case ARM::VLD2d8_UPD: 1374 case ARM::VLD2d16_UPD: 1375 case ARM::VLD2d32_UPD: 1376 case ARM::VLD2q8: 1377 case ARM::VLD2q16: 1378 case ARM::VLD2q32: 1379 case ARM::VLD2q8_UPD: 1380 case ARM::VLD2q16_UPD: 1381 case ARM::VLD2q32_UPD: 1382 case ARM::VLD3d8: 1383 case ARM::VLD3d16: 1384 case ARM::VLD3d32: 1385 case ARM::VLD3d8_UPD: 1386 case ARM::VLD3d16_UPD: 1387 case ARM::VLD3d32_UPD: 1388 case ARM::VLD4d8: 1389 case ARM::VLD4d16: 1390 case ARM::VLD4d32: 1391 case ARM::VLD4d8_UPD: 1392 case ARM::VLD4d16_UPD: 1393 case ARM::VLD4d32_UPD: 1394 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1395 break; 1396 case ARM::VLD2b8: 1397 case ARM::VLD2b16: 1398 case ARM::VLD2b32: 1399 case ARM::VLD2b8_UPD: 1400 case ARM::VLD2b16_UPD: 1401 case ARM::VLD2b32_UPD: 1402 case ARM::VLD3q8: 1403 case ARM::VLD3q16: 1404 case ARM::VLD3q32: 1405 case ARM::VLD3q8_UPD: 1406 case ARM::VLD3q16_UPD: 1407 case ARM::VLD3q32_UPD: 1408 case ARM::VLD4q8: 1409 case ARM::VLD4q16: 1410 case ARM::VLD4q32: 1411 case ARM::VLD4q8_UPD: 1412 case ARM::VLD4q16_UPD: 1413 case ARM::VLD4q32_UPD: 1414 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1415 default: 1416 break; 1417 } 1418 1419 // Third output register 1420 switch(Inst.getOpcode()) { 1421 case ARM::VLD1d8T: 1422 case ARM::VLD1d16T: 1423 case ARM::VLD1d32T: 1424 case ARM::VLD1d64T: 1425 case ARM::VLD1d8T_UPD: 1426 case ARM::VLD1d16T_UPD: 1427 case ARM::VLD1d32T_UPD: 1428 case ARM::VLD1d64T_UPD: 1429 case ARM::VLD1d8Q: 1430 case ARM::VLD1d16Q: 1431 case ARM::VLD1d32Q: 1432 case ARM::VLD1d64Q: 1433 case ARM::VLD1d8Q_UPD: 1434 case ARM::VLD1d16Q_UPD: 1435 case ARM::VLD1d32Q_UPD: 1436 case ARM::VLD1d64Q_UPD: 1437 case ARM::VLD2q8: 1438 case ARM::VLD2q16: 1439 case ARM::VLD2q32: 1440 case ARM::VLD2q8_UPD: 1441 case ARM::VLD2q16_UPD: 1442 case ARM::VLD2q32_UPD: 1443 case ARM::VLD3d8: 1444 case ARM::VLD3d16: 1445 case ARM::VLD3d32: 1446 case ARM::VLD3d8_UPD: 1447 case ARM::VLD3d16_UPD: 1448 case ARM::VLD3d32_UPD: 1449 case ARM::VLD4d8: 1450 case ARM::VLD4d16: 1451 case ARM::VLD4d32: 1452 case ARM::VLD4d8_UPD: 1453 case ARM::VLD4d16_UPD: 1454 case ARM::VLD4d32_UPD: 1455 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1456 break; 1457 case ARM::VLD3q8: 1458 case ARM::VLD3q16: 1459 case ARM::VLD3q32: 1460 case ARM::VLD3q8_UPD: 1461 case ARM::VLD3q16_UPD: 1462 case ARM::VLD3q32_UPD: 1463 case ARM::VLD4q8: 1464 case ARM::VLD4q16: 1465 case ARM::VLD4q32: 1466 case ARM::VLD4q8_UPD: 1467 case ARM::VLD4q16_UPD: 1468 case ARM::VLD4q32_UPD: 1469 if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false; 1470 break; 1471 default: 1472 break; 1473 } 1474 1475 // Fourth output register 1476 switch (Inst.getOpcode()) { 1477 case ARM::VLD1d8Q: 1478 case ARM::VLD1d16Q: 1479 case ARM::VLD1d32Q: 1480 case ARM::VLD1d64Q: 1481 case ARM::VLD1d8Q_UPD: 1482 case ARM::VLD1d16Q_UPD: 1483 case ARM::VLD1d32Q_UPD: 1484 case ARM::VLD1d64Q_UPD: 1485 case ARM::VLD2q8: 1486 case ARM::VLD2q16: 1487 case ARM::VLD2q32: 1488 case ARM::VLD2q8_UPD: 1489 case ARM::VLD2q16_UPD: 1490 case ARM::VLD2q32_UPD: 1491 case ARM::VLD4d8: 1492 case ARM::VLD4d16: 1493 case ARM::VLD4d32: 1494 case ARM::VLD4d8_UPD: 1495 case ARM::VLD4d16_UPD: 1496 case ARM::VLD4d32_UPD: 1497 if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false; 1498 break; 1499 case ARM::VLD4q8: 1500 case ARM::VLD4q16: 1501 case ARM::VLD4q32: 1502 case ARM::VLD4q8_UPD: 1503 case ARM::VLD4q16_UPD: 1504 case ARM::VLD4q32_UPD: 1505 if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false; 1506 break; 1507 default: 1508 break; 1509 } 1510 1511 // Writeback operand 1512 switch (Inst.getOpcode()) { 1513 case ARM::VLD1d8_UPD: 1514 case ARM::VLD1d16_UPD: 1515 case ARM::VLD1d32_UPD: 1516 case ARM::VLD1d64_UPD: 1517 case ARM::VLD1q8_UPD: 1518 case ARM::VLD1q16_UPD: 1519 case ARM::VLD1q32_UPD: 1520 case ARM::VLD1q64_UPD: 1521 case ARM::VLD1d8T_UPD: 1522 case ARM::VLD1d16T_UPD: 1523 case ARM::VLD1d32T_UPD: 1524 case ARM::VLD1d64T_UPD: 1525 case ARM::VLD1d8Q_UPD: 1526 case ARM::VLD1d16Q_UPD: 1527 case ARM::VLD1d32Q_UPD: 1528 case ARM::VLD1d64Q_UPD: 1529 case ARM::VLD2d8_UPD: 1530 case ARM::VLD2d16_UPD: 1531 case ARM::VLD2d32_UPD: 1532 case ARM::VLD2q8_UPD: 1533 case ARM::VLD2q16_UPD: 1534 case ARM::VLD2q32_UPD: 1535 case ARM::VLD2b8_UPD: 1536 case ARM::VLD2b16_UPD: 1537 case ARM::VLD2b32_UPD: 1538 case ARM::VLD3d8_UPD: 1539 case ARM::VLD3d16_UPD: 1540 case ARM::VLD3d32_UPD: 1541 case ARM::VLD3q8_UPD: 1542 case ARM::VLD3q16_UPD: 1543 case ARM::VLD3q32_UPD: 1544 case ARM::VLD4d8_UPD: 1545 case ARM::VLD4d16_UPD: 1546 case ARM::VLD4d32_UPD: 1547 case ARM::VLD4q8_UPD: 1548 case ARM::VLD4q16_UPD: 1549 case ARM::VLD4q32_UPD: 1550 if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) return false; 1551 break; 1552 default: 1553 break; 1554 } 1555 1556 // AddrMode6 Base (register+alignment) 1557 if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false; 1558 1559 // AddrMode6 Offset (register) 1560 if (Rm == 0xD) 1561 Inst.addOperand(MCOperand::CreateReg(0)); 1562 else if (Rm != 0xF) { 1563 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1564 return false; 1565 } 1566 1567 return true; 1568 } 1569 1570 static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1571 uint64_t Address, const void *Decoder) { 1572 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1573 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1574 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1575 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1576 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1577 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1578 1579 // Writeback Operand 1580 switch (Inst.getOpcode()) { 1581 case ARM::VST1d8_UPD: 1582 case ARM::VST1d16_UPD: 1583 case ARM::VST1d32_UPD: 1584 case ARM::VST1d64_UPD: 1585 case ARM::VST1q8_UPD: 1586 case ARM::VST1q16_UPD: 1587 case ARM::VST1q32_UPD: 1588 case ARM::VST1q64_UPD: 1589 case ARM::VST1d8T_UPD: 1590 case ARM::VST1d16T_UPD: 1591 case ARM::VST1d32T_UPD: 1592 case ARM::VST1d64T_UPD: 1593 case ARM::VST1d8Q_UPD: 1594 case ARM::VST1d16Q_UPD: 1595 case ARM::VST1d32Q_UPD: 1596 case ARM::VST1d64Q_UPD: 1597 case ARM::VST2d8_UPD: 1598 case ARM::VST2d16_UPD: 1599 case ARM::VST2d32_UPD: 1600 case ARM::VST2q8_UPD: 1601 case ARM::VST2q16_UPD: 1602 case ARM::VST2q32_UPD: 1603 case ARM::VST2b8_UPD: 1604 case ARM::VST2b16_UPD: 1605 case ARM::VST2b32_UPD: 1606 case ARM::VST3d8_UPD: 1607 case ARM::VST3d16_UPD: 1608 case ARM::VST3d32_UPD: 1609 case ARM::VST3q8_UPD: 1610 case ARM::VST3q16_UPD: 1611 case ARM::VST3q32_UPD: 1612 case ARM::VST4d8_UPD: 1613 case ARM::VST4d16_UPD: 1614 case ARM::VST4d32_UPD: 1615 case ARM::VST4q8_UPD: 1616 case ARM::VST4q16_UPD: 1617 case ARM::VST4q32_UPD: 1618 if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) 1619 return false; 1620 break; 1621 default: 1622 break; 1623 } 1624 1625 // AddrMode6 Base (register+alignment) 1626 if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false; 1627 1628 // AddrMode6 Offset (register) 1629 if (Rm == 0xD) 1630 Inst.addOperand(MCOperand::CreateReg(0)); 1631 else if (Rm != 0xF) { 1632 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1633 } 1634 1635 // First input register 1636 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1637 1638 // Second input register 1639 switch (Inst.getOpcode()) { 1640 case ARM::VST1q8: 1641 case ARM::VST1q16: 1642 case ARM::VST1q32: 1643 case ARM::VST1q64: 1644 case ARM::VST1q8_UPD: 1645 case ARM::VST1q16_UPD: 1646 case ARM::VST1q32_UPD: 1647 case ARM::VST1q64_UPD: 1648 case ARM::VST1d8T: 1649 case ARM::VST1d16T: 1650 case ARM::VST1d32T: 1651 case ARM::VST1d64T: 1652 case ARM::VST1d8T_UPD: 1653 case ARM::VST1d16T_UPD: 1654 case ARM::VST1d32T_UPD: 1655 case ARM::VST1d64T_UPD: 1656 case ARM::VST1d8Q: 1657 case ARM::VST1d16Q: 1658 case ARM::VST1d32Q: 1659 case ARM::VST1d64Q: 1660 case ARM::VST1d8Q_UPD: 1661 case ARM::VST1d16Q_UPD: 1662 case ARM::VST1d32Q_UPD: 1663 case ARM::VST1d64Q_UPD: 1664 case ARM::VST2d8: 1665 case ARM::VST2d16: 1666 case ARM::VST2d32: 1667 case ARM::VST2d8_UPD: 1668 case ARM::VST2d16_UPD: 1669 case ARM::VST2d32_UPD: 1670 case ARM::VST2q8: 1671 case ARM::VST2q16: 1672 case ARM::VST2q32: 1673 case ARM::VST2q8_UPD: 1674 case ARM::VST2q16_UPD: 1675 case ARM::VST2q32_UPD: 1676 case ARM::VST3d8: 1677 case ARM::VST3d16: 1678 case ARM::VST3d32: 1679 case ARM::VST3d8_UPD: 1680 case ARM::VST3d16_UPD: 1681 case ARM::VST3d32_UPD: 1682 case ARM::VST4d8: 1683 case ARM::VST4d16: 1684 case ARM::VST4d32: 1685 case ARM::VST4d8_UPD: 1686 case ARM::VST4d16_UPD: 1687 case ARM::VST4d32_UPD: 1688 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1689 break; 1690 case ARM::VST2b8: 1691 case ARM::VST2b16: 1692 case ARM::VST2b32: 1693 case ARM::VST2b8_UPD: 1694 case ARM::VST2b16_UPD: 1695 case ARM::VST2b32_UPD: 1696 case ARM::VST3q8: 1697 case ARM::VST3q16: 1698 case ARM::VST3q32: 1699 case ARM::VST3q8_UPD: 1700 case ARM::VST3q16_UPD: 1701 case ARM::VST3q32_UPD: 1702 case ARM::VST4q8: 1703 case ARM::VST4q16: 1704 case ARM::VST4q32: 1705 case ARM::VST4q8_UPD: 1706 case ARM::VST4q16_UPD: 1707 case ARM::VST4q32_UPD: 1708 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1709 break; 1710 default: 1711 break; 1712 } 1713 1714 // Third input register 1715 switch (Inst.getOpcode()) { 1716 case ARM::VST1d8T: 1717 case ARM::VST1d16T: 1718 case ARM::VST1d32T: 1719 case ARM::VST1d64T: 1720 case ARM::VST1d8T_UPD: 1721 case ARM::VST1d16T_UPD: 1722 case ARM::VST1d32T_UPD: 1723 case ARM::VST1d64T_UPD: 1724 case ARM::VST1d8Q: 1725 case ARM::VST1d16Q: 1726 case ARM::VST1d32Q: 1727 case ARM::VST1d64Q: 1728 case ARM::VST1d8Q_UPD: 1729 case ARM::VST1d16Q_UPD: 1730 case ARM::VST1d32Q_UPD: 1731 case ARM::VST1d64Q_UPD: 1732 case ARM::VST2q8: 1733 case ARM::VST2q16: 1734 case ARM::VST2q32: 1735 case ARM::VST2q8_UPD: 1736 case ARM::VST2q16_UPD: 1737 case ARM::VST2q32_UPD: 1738 case ARM::VST3d8: 1739 case ARM::VST3d16: 1740 case ARM::VST3d32: 1741 case ARM::VST3d8_UPD: 1742 case ARM::VST3d16_UPD: 1743 case ARM::VST3d32_UPD: 1744 case ARM::VST4d8: 1745 case ARM::VST4d16: 1746 case ARM::VST4d32: 1747 case ARM::VST4d8_UPD: 1748 case ARM::VST4d16_UPD: 1749 case ARM::VST4d32_UPD: 1750 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1751 break; 1752 case ARM::VST3q8: 1753 case ARM::VST3q16: 1754 case ARM::VST3q32: 1755 case ARM::VST3q8_UPD: 1756 case ARM::VST3q16_UPD: 1757 case ARM::VST3q32_UPD: 1758 case ARM::VST4q8: 1759 case ARM::VST4q16: 1760 case ARM::VST4q32: 1761 case ARM::VST4q8_UPD: 1762 case ARM::VST4q16_UPD: 1763 case ARM::VST4q32_UPD: 1764 if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false; 1765 break; 1766 default: 1767 break; 1768 } 1769 1770 // Fourth input register 1771 switch (Inst.getOpcode()) { 1772 case ARM::VST1d8Q: 1773 case ARM::VST1d16Q: 1774 case ARM::VST1d32Q: 1775 case ARM::VST1d64Q: 1776 case ARM::VST1d8Q_UPD: 1777 case ARM::VST1d16Q_UPD: 1778 case ARM::VST1d32Q_UPD: 1779 case ARM::VST1d64Q_UPD: 1780 case ARM::VST2q8: 1781 case ARM::VST2q16: 1782 case ARM::VST2q32: 1783 case ARM::VST2q8_UPD: 1784 case ARM::VST2q16_UPD: 1785 case ARM::VST2q32_UPD: 1786 case ARM::VST4d8: 1787 case ARM::VST4d16: 1788 case ARM::VST4d32: 1789 case ARM::VST4d8_UPD: 1790 case ARM::VST4d16_UPD: 1791 case ARM::VST4d32_UPD: 1792 if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false; 1793 break; 1794 case ARM::VST4q8: 1795 case ARM::VST4q16: 1796 case ARM::VST4q32: 1797 case ARM::VST4q8_UPD: 1798 case ARM::VST4q16_UPD: 1799 case ARM::VST4q32_UPD: 1800 if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false; 1801 break; 1802 default: 1803 break; 1804 } 1805 1806 return true; 1807 } 1808 1809 static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1810 uint64_t Address, const void *Decoder) { 1811 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1812 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1813 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1814 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1815 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1816 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1817 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 1818 1819 align *= (1 << size); 1820 1821 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1822 if (regs == 2) { 1823 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1824 } 1825 if (Rm == 0xD) { 1826 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1827 } 1828 1829 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1830 Inst.addOperand(MCOperand::CreateImm(align)); 1831 1832 if (Rm == 0xD) 1833 Inst.addOperand(MCOperand::CreateReg(0)); 1834 else if (Rm != 0xF) { 1835 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1836 } 1837 1838 return true; 1839 } 1840 1841 static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1842 uint64_t Address, const void *Decoder) { 1843 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1844 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1845 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1846 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1847 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1848 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 1849 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1850 align *= 2*size; 1851 1852 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1853 if (!DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)) return false; 1854 if (Rm == 0xD) { 1855 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1856 } 1857 1858 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1859 Inst.addOperand(MCOperand::CreateImm(align)); 1860 1861 if (Rm == 0xD) 1862 Inst.addOperand(MCOperand::CreateReg(0)); 1863 else if (Rm != 0xF) { 1864 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1865 } 1866 1867 return true; 1868 } 1869 1870 static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1871 uint64_t Address, const void *Decoder) { 1872 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1873 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1874 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1875 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1876 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1877 1878 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) || 1879 !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) || 1880 !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)) 1881 return false; 1882 if (Rm == 0xD) { 1883 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1884 } 1885 1886 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1887 Inst.addOperand(MCOperand::CreateImm(0)); 1888 1889 if (Rm == 0xD) 1890 Inst.addOperand(MCOperand::CreateReg(0)); 1891 else if (Rm != 0xF) { 1892 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1893 } 1894 1895 return true; 1896 } 1897 1898 static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1899 uint64_t Address, const void *Decoder) { 1900 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1901 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1902 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1903 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1904 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1905 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1906 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1907 1908 if (size == 0x3) { 1909 size = 4; 1910 align = 16; 1911 } else { 1912 if (size == 2) { 1913 size = 1 << size; 1914 align *= 8; 1915 } else { 1916 size = 1 << size; 1917 align *= 4*size; 1918 } 1919 } 1920 1921 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) || 1922 !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) || 1923 !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder) || 1924 !DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)) 1925 return false; 1926 if (Rm == 0xD) { 1927 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1928 } 1929 1930 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1931 Inst.addOperand(MCOperand::CreateImm(align)); 1932 1933 if (Rm == 0xD) 1934 Inst.addOperand(MCOperand::CreateReg(0)); 1935 else if (Rm != 0xF) { 1936 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1937 } 1938 1939 return true; 1940 } 1941 1942 static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1943 uint64_t Address, const void *Decoder) { 1944 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1945 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1946 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 1947 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 1948 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 1949 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 1950 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 1951 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 1952 1953 if (Q) { 1954 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1955 } else { 1956 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1957 } 1958 1959 Inst.addOperand(MCOperand::CreateImm(imm)); 1960 1961 switch (Inst.getOpcode()) { 1962 case ARM::VORRiv4i16: 1963 case ARM::VORRiv2i32: 1964 case ARM::VBICiv4i16: 1965 case ARM::VBICiv2i32: 1966 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1967 break; 1968 case ARM::VORRiv8i16: 1969 case ARM::VORRiv4i32: 1970 case ARM::VBICiv8i16: 1971 case ARM::VBICiv4i32: 1972 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1973 break; 1974 default: 1975 break; 1976 } 1977 1978 return true; 1979 } 1980 1981 static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 1982 uint64_t Address, const void *Decoder) { 1983 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1984 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1985 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1986 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 1987 unsigned size = fieldFromInstruction32(Insn, 18, 2); 1988 1989 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1990 if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1991 Inst.addOperand(MCOperand::CreateImm(8 << size)); 1992 1993 return true; 1994 } 1995 1996 static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 1997 uint64_t Address, const void *Decoder) { 1998 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 1999 return true; 2000 } 2001 2002 static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2003 uint64_t Address, const void *Decoder) { 2004 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2005 return true; 2006 } 2007 2008 static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2009 uint64_t Address, const void *Decoder) { 2010 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2011 return true; 2012 } 2013 2014 static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2015 uint64_t Address, const void *Decoder) { 2016 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2017 return true; 2018 } 2019 2020 static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2021 uint64_t Address, const void *Decoder) { 2022 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2023 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2024 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2025 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2026 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2027 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2028 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2029 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2030 2031 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2032 if (op) { 2033 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; // Writeback 2034 } 2035 2036 for (unsigned i = 0; i < length; ++i) { 2037 if (!DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)) return false; 2038 } 2039 2040 if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2041 2042 return true; 2043 } 2044 2045 static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 2046 uint64_t Address, const void *Decoder) { 2047 // The immediate needs to be a fully instantiated float. However, the 2048 // auto-generated decoder is only able to fill in some of the bits 2049 // necessary. For instance, the 'b' bit is replicated multiple times, 2050 // and is even present in inverted form in one bit. We do a little 2051 // binary parsing here to fill in those missing bits, and then 2052 // reinterpret it all as a float. 2053 union { 2054 uint32_t integer; 2055 float fp; 2056 } fp_conv; 2057 2058 fp_conv.integer = Val; 2059 uint32_t b = fieldFromInstruction32(Val, 25, 1); 2060 fp_conv.integer |= b << 26; 2061 fp_conv.integer |= b << 27; 2062 fp_conv.integer |= b << 28; 2063 fp_conv.integer |= b << 29; 2064 fp_conv.integer |= (~b & 0x1) << 30; 2065 2066 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 2067 return true; 2068 } 2069 2070 static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2071 uint64_t Address, const void *Decoder) { 2072 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2073 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2074 2075 if (!DecodetGPRRegisterClass(Inst, dst, Address, Decoder)) return false; 2076 2077 if (Inst.getOpcode() == ARM::tADR) 2078 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2079 else if (Inst.getOpcode() == ARM::tADDrSPi) 2080 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2081 else 2082 return false; 2083 2084 Inst.addOperand(MCOperand::CreateImm(imm)); 2085 return true; 2086 } 2087 2088 static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2089 uint64_t Address, const void *Decoder) { 2090 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2091 return true; 2092 } 2093 2094 static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2095 uint64_t Address, const void *Decoder) { 2096 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2097 return true; 2098 } 2099 2100 static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2101 uint64_t Address, const void *Decoder) { 2102 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2103 return true; 2104 } 2105 2106 static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2107 uint64_t Address, const void *Decoder) { 2108 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2109 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2110 2111 if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder) || 2112 !DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)) 2113 return false; 2114 2115 return true; 2116 } 2117 2118 static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2119 uint64_t Address, const void *Decoder) { 2120 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2121 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2122 2123 if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2124 Inst.addOperand(MCOperand::CreateImm(imm)); 2125 2126 return true; 2127 } 2128 2129 static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2130 uint64_t Address, const void *Decoder) { 2131 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2132 2133 return true; 2134 } 2135 2136 static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2137 uint64_t Address, const void *Decoder) { 2138 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2139 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2140 2141 return true; 2142 } 2143 2144 static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2145 uint64_t Address, const void *Decoder) { 2146 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2147 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2148 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2149 2150 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2151 !DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)) 2152 return false; 2153 Inst.addOperand(MCOperand::CreateImm(imm)); 2154 2155 return true; 2156 } 2157 2158 static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2159 uint64_t Address, const void *Decoder) { 2160 if (Inst.getOpcode() != ARM::t2PLDs) { 2161 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2162 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2163 } 2164 2165 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2166 if (Rn == 0xF) { 2167 switch (Inst.getOpcode()) { 2168 case ARM::t2LDRBs: 2169 Inst.setOpcode(ARM::t2LDRBpci); 2170 break; 2171 case ARM::t2LDRHs: 2172 Inst.setOpcode(ARM::t2LDRHpci); 2173 break; 2174 case ARM::t2LDRSHs: 2175 Inst.setOpcode(ARM::t2LDRSHpci); 2176 break; 2177 case ARM::t2LDRSBs: 2178 Inst.setOpcode(ARM::t2LDRSBpci); 2179 break; 2180 case ARM::t2PLDs: 2181 Inst.setOpcode(ARM::t2PLDi12); 2182 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2183 break; 2184 default: 2185 return false; 2186 } 2187 2188 int imm = fieldFromInstruction32(Insn, 0, 12); 2189 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2190 Inst.addOperand(MCOperand::CreateImm(imm)); 2191 2192 return true; 2193 } 2194 2195 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2196 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2197 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2198 DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder); 2199 2200 return true; 2201 } 2202 2203 static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2204 uint64_t Address, const void *Decoder) { 2205 int imm = Val & 0xFF; 2206 if (!(Val & 0x100)) imm *= -1; 2207 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2208 2209 return true; 2210 } 2211 2212 static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2213 uint64_t Address, const void *Decoder) { 2214 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2215 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2216 2217 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2218 !DecodeT2Imm8S4(Inst, imm, Address, Decoder)) 2219 return false; 2220 2221 return true; 2222 } 2223 2224 static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2225 uint64_t Address, const void *Decoder) { 2226 int imm = Val & 0xFF; 2227 if (!(Val & 0x100)) imm *= -1; 2228 Inst.addOperand(MCOperand::CreateImm(imm)); 2229 2230 return true; 2231 } 2232 2233 2234 static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2235 uint64_t Address, const void *Decoder) { 2236 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2237 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2238 2239 // Some instructions always use an additive offset. 2240 switch (Inst.getOpcode()) { 2241 case ARM::t2LDRT: 2242 case ARM::t2LDRBT: 2243 case ARM::t2LDRHT: 2244 case ARM::t2LDRSBT: 2245 case ARM::t2LDRSHT: 2246 imm |= 0x100; 2247 break; 2248 default: 2249 break; 2250 } 2251 2252 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2253 !DecodeT2Imm8(Inst, imm, Address, Decoder)) 2254 return false; 2255 2256 return true; 2257 } 2258 2259 2260 static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2261 uint64_t Address, const void *Decoder) { 2262 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2263 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2264 2265 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2266 Inst.addOperand(MCOperand::CreateImm(imm)); 2267 2268 return true; 2269 } 2270 2271 2272 static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2273 uint64_t Address, const void *Decoder) { 2274 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2275 2276 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2277 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2278 Inst.addOperand(MCOperand::CreateImm(imm)); 2279 2280 return true; 2281 } 2282 2283 static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2284 uint64_t Address, const void *Decoder) { 2285 if (Inst.getOpcode() == ARM::tADDrSP) { 2286 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2287 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2288 2289 if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false; 2290 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2291 if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false; 2292 } else if (Inst.getOpcode() == ARM::tADDspr) { 2293 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2294 2295 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2296 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2297 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2298 } 2299 2300 return true; 2301 } 2302 2303 static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2304 uint64_t Address, const void *Decoder) { 2305 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2306 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2307 2308 Inst.addOperand(MCOperand::CreateImm(imod)); 2309 Inst.addOperand(MCOperand::CreateImm(flags)); 2310 2311 return true; 2312 } 2313 2314 static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2315 uint64_t Address, const void *Decoder) { 2316 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2317 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2318 2319 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2320 Inst.addOperand(MCOperand::CreateImm(add)); 2321 2322 return true; 2323 } 2324 2325 static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2326 uint64_t Address, const void *Decoder) { 2327 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2328 return true; 2329 } 2330 2331 static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2332 uint64_t Address, const void *Decoder) { 2333 if (Val == 0xA || Val == 0xB) 2334 return false; 2335 2336 Inst.addOperand(MCOperand::CreateImm(Val)); 2337 return true; 2338 } 2339 2340 static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, 2341 uint64_t Address, const void *Decoder) { 2342 if (Val == 0) 2343 Inst.addOperand(MCOperand::CreateImm(32)); 2344 else 2345 Inst.addOperand(MCOperand::CreateImm(Val)); 2346 return true; 2347 } 2348 2349 static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2350 uint64_t Address, const void *Decoder) { 2351 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2352 if (pred == 0xE || pred == 0xF) { 2353 unsigned opc = fieldFromInstruction32(Insn, 4, 2); 2354 switch (opc) { 2355 default: 2356 return false; 2357 case 0: 2358 Inst.setOpcode(ARM::t2DSB); 2359 break; 2360 case 1: 2361 Inst.setOpcode(ARM::t2DMB); 2362 break; 2363 case 2: 2364 Inst.setOpcode(ARM::t2ISB); 2365 return true; 2366 } 2367 2368 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2369 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2370 } 2371 2372 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2373 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2374 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2375 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2376 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2377 2378 if (!DecodeT2BROperand(Inst, brtarget, Address, Decoder) || 2379 !DecodePredicateOperand(Inst, pred, Address, Decoder)) 2380 return false; 2381 2382 return true; 2383 } 2384 2385 // Decode a shifted immediate operand. These basically consist 2386 // of an 8-bit value, and a 4-bit directive that specifies either 2387 // a splat operation or a rotation. 2388 static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2389 uint64_t Address, const void *Decoder) { 2390 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2391 if (ctrl == 0) { 2392 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2393 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2394 switch (byte) { 2395 case 0: 2396 Inst.addOperand(MCOperand::CreateImm(imm)); 2397 break; 2398 case 1: 2399 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2400 break; 2401 case 2: 2402 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2403 break; 2404 case 3: 2405 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2406 (imm << 8) | imm)); 2407 break; 2408 } 2409 } else { 2410 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2411 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2412 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2413 Inst.addOperand(MCOperand::CreateImm(imm)); 2414 } 2415 2416 return true; 2417 } 2418 2419 static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 2420 uint64_t Address, const void *Decoder){ 2421 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 2422 return true; 2423 } 2424 2425 static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 2426 uint64_t Address, const void *Decoder){ 2427 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2428 return true; 2429 } 2430 2431 static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Val, 2432 uint64_t Address, const void *Decoder) { 2433 bool isImm = fieldFromInstruction32(Val, 9, 1); 2434 bool isAdd = fieldFromInstruction32(Val, 8, 1); 2435 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2436 2437 if (!isImm) { 2438 if (!DecodeGPRRegisterClass(Inst, imm, Address, Decoder)) return false; 2439 Inst.addOperand(MCOperand::CreateImm(!isAdd << 8)); 2440 } else { 2441 Inst.addOperand(MCOperand::CreateReg(0)); 2442 Inst.addOperand(MCOperand::CreateImm(imm | (!isAdd << 8))); 2443 } 2444 2445 return true; 2446 } 2447 2448 static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 2449 uint64_t Address, const void *Decoder) { 2450 switch (Val) { 2451 default: 2452 return false; 2453 case 0xF: // SY 2454 case 0xE: // ST 2455 case 0xB: // ISH 2456 case 0xA: // ISHST 2457 case 0x7: // NSH 2458 case 0x6: // NSHST 2459 case 0x3: // OSH 2460 case 0x2: // OSHST 2461 break; 2462 } 2463 2464 Inst.addOperand(MCOperand::CreateImm(Val)); 2465 return true; 2466 } 2467 2468