1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARMDisassembler.h" 13 #include "ARM.h" 14 #include "ARMRegisterInfo.h" 15 #include "MCTargetDesc/ARMAddressingModes.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/Target/TargetRegistry.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/raw_ostream.h" 26 27 // Forward declare these because the autogenerated code will reference them. 28 // Definitions are further down. 29 static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 30 uint64_t Address, const void *Decoder); 31 static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 32 uint64_t Address, const void *Decoder); 33 static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 34 uint64_t Address, const void *Decoder); 35 static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 36 uint64_t Address, const void *Decoder); 37 static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 38 uint64_t Address, const void *Decoder); 39 static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 40 uint64_t Address, const void *Decoder); 41 static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 42 uint64_t Address, const void *Decoder); 43 static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 44 uint64_t Address, const void *Decoder); 45 static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 46 uint64_t Address, const void *Decoder); 47 48 static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 49 uint64_t Address, const void *Decoder); 50 static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 51 uint64_t Address, const void *Decoder); 52 static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 53 uint64_t Address, const void *Decoder); 54 static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 55 uint64_t Address, const void *Decoder); 56 static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 57 uint64_t Address, const void *Decoder); 58 static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 59 uint64_t Address, const void *Decoder); 60 static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 61 uint64_t Address, const void *Decoder); 62 63 static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 64 uint64_t Address, const void *Decoder); 65 static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 66 uint64_t Address, const void *Decoder); 67 static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 68 uint64_t Address, const void *Decoder); 69 static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 70 uint64_t Address, const void *Decoder); 71 static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 72 uint64_t Address, const void *Decoder); 73 static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 74 uint64_t Address, const void *Decoder); 75 static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 76 uint64_t Address, const void *Decoder); 77 78 static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 79 unsigned Insn, 80 uint64_t Adddress, 81 const void *Decoder); 82 static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 83 uint64_t Address, const void *Decoder); 84 static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 85 uint64_t Address, const void *Decoder); 86 static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 87 uint64_t Address, const void *Decoder); 88 static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 89 uint64_t Address, const void *Decoder); 90 static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 91 uint64_t Address, const void *Decoder); 92 static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 93 uint64_t Address, const void *Decoder); 94 static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 95 uint64_t Address, const void *Decoder); 96 static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 97 uint64_t Address, const void *Decoder); 98 static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 99 uint64_t Address, const void *Decoder); 100 static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 101 uint64_t Address, const void *Decoder); 102 static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 103 uint64_t Address, const void *Decoder); 104 static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 105 uint64_t Address, const void *Decoder); 106 static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 107 uint64_t Address, const void *Decoder); 108 static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Val, 109 uint64_t Address, const void *Decoder); 110 static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 111 uint64_t Address, const void *Decoder); 112 static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 113 uint64_t Address, const void *Decoder); 114 static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 115 uint64_t Address, const void *Decoder); 116 static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 117 uint64_t Address, const void *Decoder); 118 static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 119 uint64_t Address, const void *Decoder); 120 static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 121 uint64_t Address, const void *Decoder); 122 static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 123 uint64_t Address, const void *Decoder); 124 static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 125 uint64_t Address, const void *Decoder); 126 static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 127 uint64_t Address, const void *Decoder); 128 static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Insn, 129 uint64_t Address, const void *Decoder); 130 131 132 static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 133 uint64_t Address, const void *Decoder); 134 static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 135 uint64_t Address, const void *Decoder); 136 static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 137 uint64_t Address, const void *Decoder); 138 static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 139 uint64_t Address, const void *Decoder); 140 static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 141 uint64_t Address, const void *Decoder); 142 static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 143 uint64_t Address, const void *Decoder); 144 static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 145 uint64_t Address, const void *Decoder); 146 static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 147 uint64_t Address, const void *Decoder); 148 static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 149 uint64_t Address, const void *Decoder); 150 static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 151 uint64_t Address, const void *Decoder); 152 static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 153 uint64_t Address, const void *Decoder); 154 static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 155 uint64_t Address, const void *Decoder); 156 static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 157 uint64_t Address, const void *Decoder); 158 static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 159 uint64_t Address, const void *Decoder); 160 static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 161 uint64_t Address, const void *Decoder); 162 static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 163 uint64_t Address, const void *Decoder); 164 static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 165 uint64_t Address, const void *Decoder); 166 static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 167 uint64_t Address, const void *Decoder); 168 static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 169 uint64_t Address, const void *Decoder); 170 static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, 171 uint64_t Address, const void *Decoder); 172 static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 173 uint64_t Address, const void *Decoder); 174 static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 175 uint64_t Address, const void *Decoder); 176 static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 177 uint64_t Address, const void *Decoder); 178 static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 179 uint64_t Address, const void *Decoder); 180 181 #include "ARMGenDisassemblerTables.inc" 182 #include "ARMGenInstrInfo.inc" 183 #include "ARMGenEDInfo.inc" 184 185 using namespace llvm; 186 187 static MCDisassembler *createARMDisassembler(const Target &T) { 188 return new ARMDisassembler; 189 } 190 191 static MCDisassembler *createThumbDisassembler(const Target &T) { 192 return new ThumbDisassembler; 193 } 194 195 EDInstInfo *ARMDisassembler::getEDInfo() const { 196 return instInfoARM; 197 } 198 199 EDInstInfo *ThumbDisassembler::getEDInfo() const { 200 return instInfoARM; 201 } 202 203 204 bool ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 205 const MemoryObject &Region, 206 uint64_t Address,raw_ostream &os) const { 207 uint8_t bytes[4]; 208 209 // We want to read exactly 4 bytes of data. 210 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 211 return false; 212 213 // Encoded as a small-endian 32-bit word in the stream. 214 uint32_t insn = (bytes[3] << 24) | 215 (bytes[2] << 16) | 216 (bytes[1] << 8) | 217 (bytes[0] << 0); 218 219 // Calling the auto-generated decoder function. 220 bool result = decodeARMInstruction32(MI, insn, Address, this); 221 if (result) { 222 Size = 4; 223 return true; 224 } 225 226 // Instructions that are shared between ARM and Thumb modes. 227 // FIXME: This shouldn't really exist. It's an artifact of the 228 // fact that we fail to encode a few instructions properly for Thumb. 229 MI.clear(); 230 result = decodeCommonInstruction32(MI, insn, Address, this); 231 if (result) { 232 Size = 4; 233 return true; 234 } 235 236 // VFP and NEON instructions, similarly, are shared between ARM 237 // and Thumb modes. 238 MI.clear(); 239 result = decodeVFPInstruction32(MI, insn, Address, this); 240 if (result) { 241 Size = 4; 242 return true; 243 } 244 245 MI.clear(); 246 result = decodeNEONInstruction32(MI, insn, Address, this); 247 if (result) { 248 // Add a fake predicate operand, because we share these instruction 249 // definitions with Thumb2 where these instructions are predicable. 250 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 251 Size = 4; 252 return true; 253 } 254 255 MI.clear(); 256 257 return false; 258 } 259 260 namespace llvm { 261 extern MCInstrDesc ARMInsts[]; 262 } 263 264 // Thumb1 instructions don't have explicit S bits. Rather, they 265 // implicitly set CPSR. Since it's not represented in the encoding, the 266 // auto-generated decoder won't inject the CPSR operand. We need to fix 267 // that as a post-pass. 268 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 269 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 270 MCInst::iterator I = MI.begin(); 271 for (unsigned i = 0; i < MI.size(); ++i, ++I) { 272 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 273 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 274 return; 275 } 276 } 277 278 if (OpInfo[MI.size()].isOptionalDef() && 279 OpInfo[MI.size()].RegClass == ARM::CCRRegClassID) 280 MI.insert(MI.end(), MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 281 } 282 283 // Most Thumb instructions don't have explicit predicates in the 284 // encoding, but rather get their predicates from IT context. We need 285 // to fix up the predicate operands using this context information as a 286 // post-pass. 287 void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 288 // A few instructions actually have predicates encoded in them. Don't 289 // try to overwrite it if we're seeing one of those. 290 switch (MI.getOpcode()) { 291 case ARM::tBcc: 292 case ARM::t2Bcc: 293 return; 294 default: 295 break; 296 } 297 298 // If we're in an IT block, base the predicate on that. Otherwise, 299 // assume a predicate of AL. 300 unsigned CC; 301 if (ITBlock.size()) { 302 CC = ITBlock.back(); 303 ITBlock.pop_back(); 304 } else 305 CC = ARMCC::AL; 306 307 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 308 MCInst::iterator I = MI.begin(); 309 for (unsigned i = 0; i < MI.size(); ++i, ++I) { 310 if (OpInfo[i].isPredicate()) { 311 I = MI.insert(I, MCOperand::CreateImm(CC)); 312 ++I; 313 if (CC == ARMCC::AL) 314 MI.insert(I, MCOperand::CreateReg(0)); 315 else 316 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 317 return; 318 } 319 } 320 321 MI.insert(MI.end(), MCOperand::CreateImm(CC)); 322 if (CC == ARMCC::AL) 323 MI.insert(MI.end(), MCOperand::CreateReg(0)); 324 else 325 MI.insert(MI.end(), MCOperand::CreateReg(ARM::CPSR)); 326 } 327 328 // Thumb VFP instructions are a special case. Because we share their 329 // encodings between ARM and Thumb modes, and they are predicable in ARM 330 // mode, the auto-generated decoder will give them an (incorrect) 331 // predicate operand. We need to rewrite these operands based on the IT 332 // context as a post-pass. 333 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 334 unsigned CC; 335 if (ITBlock.size()) { 336 CC = ITBlock.back(); 337 ITBlock.pop_back(); 338 } else 339 CC = ARMCC::AL; 340 341 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 342 MCInst::iterator I = MI.begin(); 343 for (unsigned i = 0; i < MI.size(); ++i, ++I) { 344 if (OpInfo[i].isPredicate() ) { 345 I->setImm(CC); 346 ++I; 347 if (CC == ARMCC::AL) 348 I->setReg(0); 349 else 350 I->setReg(ARM::CPSR); 351 return; 352 } 353 } 354 } 355 356 357 bool ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 358 const MemoryObject &Region, 359 uint64_t Address,raw_ostream &os) const { 360 uint8_t bytes[4]; 361 362 // We want to read exactly 2 bytes of data. 363 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) 364 return false; 365 366 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 367 bool result = decodeThumbInstruction16(MI, insn16, Address, this); 368 if (result) { 369 Size = 2; 370 bool InITBlock = ITBlock.size(); 371 AddThumbPredicate(MI); 372 AddThumb1SBit(MI, InITBlock); 373 return true; 374 } 375 376 MI.clear(); 377 result = decodeThumb2Instruction16(MI, insn16, Address, this); 378 if (result) { 379 Size = 2; 380 AddThumbPredicate(MI); 381 382 // If we find an IT instruction, we need to parse its condition 383 // code and mask operands so that we can apply them correctly 384 // to the subsequent instructions. 385 if (MI.getOpcode() == ARM::t2IT) { 386 unsigned firstcond = MI.getOperand(0).getImm(); 387 uint32_t mask = MI.getOperand(1).getImm(); 388 unsigned zeros = CountTrailingZeros_32(mask); 389 mask >>= zeros+1; 390 391 for (unsigned i = 0; i < 4 - (zeros+1); ++i) { 392 if (firstcond ^ (mask & 1)) 393 ITBlock.push_back(firstcond ^ 1); 394 else 395 ITBlock.push_back(firstcond); 396 mask >>= 1; 397 } 398 ITBlock.push_back(firstcond); 399 } 400 401 return true; 402 } 403 404 // We want to read exactly 4 bytes of data. 405 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 406 return false; 407 408 uint32_t insn32 = (bytes[3] << 8) | 409 (bytes[2] << 0) | 410 (bytes[1] << 24) | 411 (bytes[0] << 16); 412 MI.clear(); 413 result = decodeThumbInstruction32(MI, insn32, Address, this); 414 if (result) { 415 Size = 4; 416 bool InITBlock = ITBlock.size(); 417 AddThumbPredicate(MI); 418 AddThumb1SBit(MI, InITBlock); 419 return true; 420 } 421 422 MI.clear(); 423 result = decodeThumb2Instruction32(MI, insn32, Address, this); 424 if (result) { 425 Size = 4; 426 AddThumbPredicate(MI); 427 return true; 428 } 429 430 MI.clear(); 431 result = decodeVFPInstruction32(MI, insn32, Address, this); 432 if (result) { 433 Size = 4; 434 UpdateThumbVFPPredicate(MI); 435 return true; 436 } 437 438 MI.clear(); 439 result = decodeCommonInstruction32(MI, insn32, Address, this); 440 if (result) { 441 Size = 4; 442 AddThumbPredicate(MI); 443 return true; 444 } 445 446 return false; 447 } 448 449 450 extern "C" void LLVMInitializeARMDisassembler() { 451 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 452 createARMDisassembler); 453 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 454 createThumbDisassembler); 455 } 456 457 static const unsigned GPRDecoderTable[] = { 458 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 459 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 460 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 461 ARM::R12, ARM::SP, ARM::LR, ARM::PC 462 }; 463 464 static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 465 uint64_t Address, const void *Decoder) { 466 if (RegNo > 15) 467 return false; 468 469 unsigned Register = GPRDecoderTable[RegNo]; 470 Inst.addOperand(MCOperand::CreateReg(Register)); 471 return true; 472 } 473 474 static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 475 uint64_t Address, const void *Decoder) { 476 if (RegNo > 7) 477 return false; 478 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 479 } 480 481 static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 482 uint64_t Address, const void *Decoder) { 483 unsigned Register = 0; 484 switch (RegNo) { 485 case 0: 486 Register = ARM::R0; 487 break; 488 case 1: 489 Register = ARM::R1; 490 break; 491 case 2: 492 Register = ARM::R2; 493 break; 494 case 3: 495 Register = ARM::R3; 496 break; 497 case 9: 498 Register = ARM::R9; 499 break; 500 case 12: 501 Register = ARM::R12; 502 break; 503 default: 504 return false; 505 } 506 507 Inst.addOperand(MCOperand::CreateReg(Register)); 508 return true; 509 } 510 511 static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 512 uint64_t Address, const void *Decoder) { 513 if (RegNo == 13 || RegNo == 15) return false; 514 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 515 } 516 517 static const unsigned SPRDecoderTable[] = { 518 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 519 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 520 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 521 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 522 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 523 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 524 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 525 ARM::S28, ARM::S29, ARM::S30, ARM::S31 526 }; 527 528 static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 529 uint64_t Address, const void *Decoder) { 530 if (RegNo > 31) 531 return false; 532 533 unsigned Register = SPRDecoderTable[RegNo]; 534 Inst.addOperand(MCOperand::CreateReg(Register)); 535 return true; 536 } 537 538 static const unsigned DPRDecoderTable[] = { 539 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 540 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 541 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 542 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 543 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 544 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 545 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 546 ARM::D28, ARM::D29, ARM::D30, ARM::D31 547 }; 548 549 static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 550 uint64_t Address, const void *Decoder) { 551 if (RegNo > 31) 552 return false; 553 554 unsigned Register = DPRDecoderTable[RegNo]; 555 Inst.addOperand(MCOperand::CreateReg(Register)); 556 return true; 557 } 558 559 static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 560 uint64_t Address, const void *Decoder) { 561 if (RegNo > 7) 562 return false; 563 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 564 } 565 566 static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 567 uint64_t Address, const void *Decoder) { 568 if (RegNo > 15) 569 return false; 570 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 571 } 572 573 static const unsigned QPRDecoderTable[] = { 574 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 575 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 576 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 577 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 578 }; 579 580 581 static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 582 uint64_t Address, const void *Decoder) { 583 if (RegNo > 31) 584 return false; 585 RegNo >>= 1; 586 587 unsigned Register = QPRDecoderTable[RegNo]; 588 Inst.addOperand(MCOperand::CreateReg(Register)); 589 return true; 590 } 591 592 static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 593 uint64_t Address, const void *Decoder) { 594 if (Val == 0xF) return false; 595 Inst.addOperand(MCOperand::CreateImm(Val)); 596 if (Val == ARMCC::AL) { 597 Inst.addOperand(MCOperand::CreateReg(0)); 598 } else 599 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 600 return true; 601 } 602 603 static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 604 uint64_t Address, const void *Decoder) { 605 if (Val) 606 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 607 else 608 Inst.addOperand(MCOperand::CreateReg(0)); 609 return true; 610 } 611 612 static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 613 uint64_t Address, const void *Decoder) { 614 uint32_t imm = Val & 0xFF; 615 uint32_t rot = (Val & 0xF00) >> 7; 616 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 617 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 618 return true; 619 } 620 621 static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 622 uint64_t Address, const void *Decoder) { 623 Val <<= 2; 624 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val))); 625 return true; 626 } 627 628 static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 629 uint64_t Address, const void *Decoder) { 630 631 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 632 unsigned type = fieldFromInstruction32(Val, 5, 2); 633 unsigned imm = fieldFromInstruction32(Val, 7, 5); 634 635 // Register-immediate 636 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 637 638 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 639 switch (type) { 640 case 0: 641 Shift = ARM_AM::lsl; 642 break; 643 case 1: 644 Shift = ARM_AM::lsr; 645 break; 646 case 2: 647 Shift = ARM_AM::asr; 648 break; 649 case 3: 650 Shift = ARM_AM::ror; 651 break; 652 } 653 654 if (Shift == ARM_AM::ror && imm == 0) 655 Shift = ARM_AM::rrx; 656 657 unsigned Op = Shift | (imm << 3); 658 Inst.addOperand(MCOperand::CreateImm(Op)); 659 660 return true; 661 } 662 663 static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 664 uint64_t Address, const void *Decoder) { 665 666 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 667 unsigned type = fieldFromInstruction32(Val, 5, 2); 668 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 669 670 // Register-register 671 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 672 DecodeGPRRegisterClass(Inst, Rs, Address, Decoder); 673 674 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 675 switch (type) { 676 case 0: 677 Shift = ARM_AM::lsl; 678 break; 679 case 1: 680 Shift = ARM_AM::lsr; 681 break; 682 case 2: 683 Shift = ARM_AM::asr; 684 break; 685 case 3: 686 Shift = ARM_AM::ror; 687 break; 688 } 689 690 Inst.addOperand(MCOperand::CreateImm(Shift)); 691 692 return true; 693 } 694 695 static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 696 uint64_t Address, const void *Decoder) { 697 for (unsigned i = 0; i < 16; ++i) { 698 if (Val & (1 << i)) 699 DecodeGPRRegisterClass(Inst, i, Address, Decoder); 700 } 701 702 return true; 703 } 704 705 static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 706 uint64_t Address, const void *Decoder) { 707 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 708 unsigned regs = Val & 0xFF; 709 710 DecodeSPRRegisterClass(Inst, Vd, Address, Decoder); 711 for (unsigned i = 0; i < (regs - 1); ++i) 712 DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder); 713 714 return true; 715 } 716 717 static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 718 uint64_t Address, const void *Decoder) { 719 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 720 unsigned regs = (Val & 0xFF) / 2; 721 722 DecodeDPRRegisterClass(Inst, Vd, Address, Decoder); 723 for (unsigned i = 0; i < (regs - 1); ++i) 724 DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder); 725 726 return true; 727 } 728 729 static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 730 uint64_t Address, const void *Decoder) { 731 unsigned msb = fieldFromInstruction32(Val, 5, 5); 732 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 733 uint32_t msb_mask = (1 << (msb+1)) - 1; 734 uint32_t lsb_mask = (1 << lsb) - 1; 735 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 736 return true; 737 } 738 739 static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 740 uint64_t Address, const void *Decoder) { 741 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 742 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 743 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 744 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 745 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 746 unsigned U = fieldFromInstruction32(Insn, 23, 1); 747 748 switch (Inst.getOpcode()) { 749 case ARM::LDC_OFFSET: 750 case ARM::LDC_PRE: 751 case ARM::LDC_POST: 752 case ARM::LDC_OPTION: 753 case ARM::LDCL_OFFSET: 754 case ARM::LDCL_PRE: 755 case ARM::LDCL_POST: 756 case ARM::LDCL_OPTION: 757 case ARM::STC_OFFSET: 758 case ARM::STC_PRE: 759 case ARM::STC_POST: 760 case ARM::STC_OPTION: 761 case ARM::STCL_OFFSET: 762 case ARM::STCL_PRE: 763 case ARM::STCL_POST: 764 case ARM::STCL_OPTION: 765 if (coproc == 0xA || coproc == 0xB) 766 return false; 767 break; 768 default: 769 break; 770 } 771 772 Inst.addOperand(MCOperand::CreateImm(coproc)); 773 Inst.addOperand(MCOperand::CreateImm(CRd)); 774 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 775 switch (Inst.getOpcode()) { 776 case ARM::LDC_OPTION: 777 case ARM::LDCL_OPTION: 778 case ARM::LDC2_OPTION: 779 case ARM::LDC2L_OPTION: 780 case ARM::STC_OPTION: 781 case ARM::STCL_OPTION: 782 case ARM::STC2_OPTION: 783 case ARM::STC2L_OPTION: 784 case ARM::LDCL_POST: 785 case ARM::STCL_POST: 786 break; 787 default: 788 Inst.addOperand(MCOperand::CreateReg(0)); 789 break; 790 } 791 792 unsigned P = fieldFromInstruction32(Insn, 24, 1); 793 unsigned W = fieldFromInstruction32(Insn, 21, 1); 794 795 bool writeback = (P == 0) || (W == 1); 796 unsigned idx_mode = 0; 797 if (P && writeback) 798 idx_mode = ARMII::IndexModePre; 799 else if (!P && writeback) 800 idx_mode = ARMII::IndexModePost; 801 802 switch (Inst.getOpcode()) { 803 case ARM::LDCL_POST: 804 case ARM::STCL_POST: 805 imm |= U << 8; 806 case ARM::LDC_OPTION: 807 case ARM::LDCL_OPTION: 808 case ARM::LDC2_OPTION: 809 case ARM::LDC2L_OPTION: 810 case ARM::STC_OPTION: 811 case ARM::STCL_OPTION: 812 case ARM::STC2_OPTION: 813 case ARM::STC2L_OPTION: 814 Inst.addOperand(MCOperand::CreateImm(imm)); 815 break; 816 default: 817 if (U) 818 Inst.addOperand(MCOperand::CreateImm( 819 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 820 else 821 Inst.addOperand(MCOperand::CreateImm( 822 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 823 break; 824 } 825 826 switch (Inst.getOpcode()) { 827 case ARM::LDC_OFFSET: 828 case ARM::LDC_PRE: 829 case ARM::LDC_POST: 830 case ARM::LDC_OPTION: 831 case ARM::LDCL_OFFSET: 832 case ARM::LDCL_PRE: 833 case ARM::LDCL_POST: 834 case ARM::LDCL_OPTION: 835 case ARM::STC_OFFSET: 836 case ARM::STC_PRE: 837 case ARM::STC_POST: 838 case ARM::STC_OPTION: 839 case ARM::STCL_OFFSET: 840 case ARM::STCL_PRE: 841 case ARM::STCL_POST: 842 case ARM::STCL_OPTION: 843 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 844 break; 845 default: 846 break; 847 } 848 849 return true; 850 } 851 852 static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 853 uint64_t Address, const void *Decoder) { 854 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 855 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 856 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 857 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 858 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 859 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 860 unsigned P = fieldFromInstruction32(Insn, 24, 1); 861 unsigned W = fieldFromInstruction32(Insn, 21, 1); 862 863 // On stores, the writeback operand precedes Rt. 864 switch (Inst.getOpcode()) { 865 case ARM::STR_POST_IMM: 866 case ARM::STR_POST_REG: 867 case ARM::STRTr: 868 case ARM::STRTi: 869 case ARM::STRBTr: 870 case ARM::STRBTi: 871 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 872 break; 873 default: 874 break; 875 } 876 877 DecodeGPRRegisterClass(Inst, Rt, Address, Decoder); 878 879 // On loads, the writeback operand comes after Rt. 880 switch (Inst.getOpcode()) { 881 case ARM::LDR_POST_IMM: 882 case ARM::LDR_POST_REG: 883 case ARM::LDR_PRE: 884 case ARM::LDRBT_POST_REG: 885 case ARM::LDRBT_POST_IMM: 886 case ARM::LDRTr: 887 case ARM::LDRTi: 888 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 889 break; 890 default: 891 break; 892 } 893 894 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 895 896 ARM_AM::AddrOpc Op = ARM_AM::add; 897 if (!fieldFromInstruction32(Insn, 23, 1)) 898 Op = ARM_AM::sub; 899 900 bool writeback = (P == 0) || (W == 1); 901 unsigned idx_mode = 0; 902 if (P && writeback) 903 idx_mode = ARMII::IndexModePre; 904 else if (!P && writeback) 905 idx_mode = ARMII::IndexModePost; 906 907 if (reg) { 908 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 909 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 910 switch( fieldFromInstruction32(Insn, 5, 2)) { 911 case 0: 912 Opc = ARM_AM::lsl; 913 break; 914 case 1: 915 Opc = ARM_AM::lsr; 916 break; 917 case 2: 918 Opc = ARM_AM::asr; 919 break; 920 case 3: 921 Opc = ARM_AM::ror; 922 break; 923 default: 924 return false; 925 } 926 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 927 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 928 929 Inst.addOperand(MCOperand::CreateImm(imm)); 930 } else { 931 Inst.addOperand(MCOperand::CreateReg(0)); 932 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 933 Inst.addOperand(MCOperand::CreateImm(tmp)); 934 } 935 936 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 937 938 return true; 939 } 940 941 static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 942 uint64_t Address, const void *Decoder) { 943 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 944 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 945 unsigned type = fieldFromInstruction32(Val, 5, 2); 946 unsigned imm = fieldFromInstruction32(Val, 7, 5); 947 unsigned U = fieldFromInstruction32(Val, 12, 1); 948 949 ARM_AM::ShiftOpc ShOp; 950 switch (type) { 951 case 0: 952 ShOp = ARM_AM::lsl; 953 break; 954 case 1: 955 ShOp = ARM_AM::lsr; 956 break; 957 case 2: 958 ShOp = ARM_AM::asr; 959 break; 960 case 3: 961 ShOp = ARM_AM::ror; 962 break; 963 } 964 965 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 966 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 967 unsigned shift; 968 if (U) 969 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 970 else 971 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 972 Inst.addOperand(MCOperand::CreateImm(shift)); 973 974 return true; 975 } 976 977 static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 978 uint64_t Address, const void *Decoder) { 979 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 980 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 981 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 982 unsigned type = fieldFromInstruction32(Insn, 22, 1); 983 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 984 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 985 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 986 unsigned W = fieldFromInstruction32(Insn, 21, 1); 987 unsigned P = fieldFromInstruction32(Insn, 24, 1); 988 989 bool writeback = (W == 1) | (P == 0); 990 if (writeback) { // Writeback 991 if (P) 992 U |= ARMII::IndexModePre << 9; 993 else 994 U |= ARMII::IndexModePost << 9; 995 996 // On stores, the writeback operand precedes Rt. 997 switch (Inst.getOpcode()) { 998 case ARM::STRD: 999 case ARM::STRD_PRE: 1000 case ARM::STRD_POST: 1001 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1002 break; 1003 default: 1004 break; 1005 } 1006 } 1007 1008 DecodeGPRRegisterClass(Inst, Rt, Address, Decoder); 1009 switch (Inst.getOpcode()) { 1010 case ARM::STRD: 1011 case ARM::STRD_PRE: 1012 case ARM::STRD_POST: 1013 case ARM::LDRD: 1014 case ARM::LDRD_PRE: 1015 case ARM::LDRD_POST: 1016 DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder); 1017 break; 1018 default: 1019 break; 1020 } 1021 1022 if (writeback) { 1023 // On loads, the writeback operand comes after Rt. 1024 switch (Inst.getOpcode()) { 1025 case ARM::LDRD: 1026 case ARM::LDRD_PRE: 1027 case ARM::LDRD_POST: 1028 case ARM::LDRHTr: 1029 case ARM::LDRSBTr: 1030 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1031 break; 1032 default: 1033 break; 1034 } 1035 } 1036 1037 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1038 1039 if (type) { 1040 Inst.addOperand(MCOperand::CreateReg(0)); 1041 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1042 } else { 1043 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 1044 Inst.addOperand(MCOperand::CreateImm(U)); 1045 } 1046 1047 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1048 1049 return true; 1050 } 1051 1052 static bool DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1053 uint64_t Address, const void *Decoder) { 1054 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1055 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1056 1057 switch (mode) { 1058 case 0: 1059 mode = ARM_AM::da; 1060 break; 1061 case 1: 1062 mode = ARM_AM::ia; 1063 break; 1064 case 2: 1065 mode = ARM_AM::db; 1066 break; 1067 case 3: 1068 mode = ARM_AM::ib; 1069 break; 1070 } 1071 1072 Inst.addOperand(MCOperand::CreateImm(mode)); 1073 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1074 1075 return true; 1076 } 1077 1078 static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1079 unsigned Insn, 1080 uint64_t Address, const void *Decoder) { 1081 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1082 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1083 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1084 1085 if (pred == 0xF) { 1086 switch (Inst.getOpcode()) { 1087 case ARM::STMDA: 1088 Inst.setOpcode(ARM::RFEDA); 1089 break; 1090 case ARM::STMDA_UPD: 1091 Inst.setOpcode(ARM::RFEDA_UPD); 1092 break; 1093 case ARM::STMDB: 1094 Inst.setOpcode(ARM::RFEDB); 1095 break; 1096 case ARM::STMDB_UPD: 1097 Inst.setOpcode(ARM::RFEDB_UPD); 1098 break; 1099 case ARM::STMIA: 1100 Inst.setOpcode(ARM::RFEIA); 1101 break; 1102 case ARM::STMIA_UPD: 1103 Inst.setOpcode(ARM::RFEIA_UPD); 1104 break; 1105 case ARM::STMIB: 1106 Inst.setOpcode(ARM::RFEIB); 1107 break; 1108 case ARM::STMIB_UPD: 1109 Inst.setOpcode(ARM::RFEIB_UPD); 1110 break; 1111 1112 } 1113 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1114 } 1115 1116 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1117 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); // Tied 1118 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1119 DecodeRegListOperand(Inst, reglist, Address, Decoder); 1120 1121 return true; 1122 } 1123 1124 static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1125 uint64_t Address, const void *Decoder) { 1126 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1127 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1128 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1129 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1130 1131 if (M && mode && imod && iflags) { 1132 Inst.setOpcode(ARM::CPS3p); 1133 Inst.addOperand(MCOperand::CreateImm(imod)); 1134 Inst.addOperand(MCOperand::CreateImm(iflags)); 1135 Inst.addOperand(MCOperand::CreateImm(mode)); 1136 return true; 1137 } else if (!mode && !M) { 1138 Inst.setOpcode(ARM::CPS2p); 1139 Inst.addOperand(MCOperand::CreateImm(imod)); 1140 Inst.addOperand(MCOperand::CreateImm(iflags)); 1141 return true; 1142 } else if (!imod && !iflags && M) { 1143 Inst.setOpcode(ARM::CPS1p); 1144 Inst.addOperand(MCOperand::CreateImm(mode)); 1145 return true; 1146 } 1147 1148 return false; 1149 } 1150 1151 static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1152 uint64_t Address, const void *Decoder) { 1153 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1154 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1155 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1156 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1157 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1158 1159 if (pred == 0xF) 1160 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1161 1162 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder); 1163 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1164 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 1165 DecodeGPRRegisterClass(Inst, Ra, Address, Decoder); 1166 1167 return true; 1168 } 1169 1170 static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1171 uint64_t Address, const void *Decoder) { 1172 unsigned add = fieldFromInstruction32(Val, 12, 1); 1173 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1174 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1175 1176 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1177 1178 if (!add) imm *= -1; 1179 if (imm == 0 && !add) imm = INT32_MIN; 1180 Inst.addOperand(MCOperand::CreateImm(imm)); 1181 1182 return true; 1183 } 1184 1185 static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1186 uint64_t Address, const void *Decoder) { 1187 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1188 unsigned U = fieldFromInstruction32(Val, 8, 1); 1189 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1190 1191 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1192 1193 if (U) 1194 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1195 else 1196 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1197 1198 return true; 1199 } 1200 1201 static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1202 uint64_t Address, const void *Decoder) { 1203 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1204 } 1205 1206 static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1207 uint64_t Address, const void *Decoder) { 1208 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1209 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1210 1211 if (pred == 0xF) { 1212 Inst.setOpcode(ARM::BLXi); 1213 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1214 Inst.addOperand(MCOperand::CreateImm(imm)); 1215 return true; 1216 } 1217 1218 Inst.addOperand(MCOperand::CreateImm(imm)); 1219 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1220 1221 return true; 1222 } 1223 1224 1225 static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1226 uint64_t Address, const void *Decoder) { 1227 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1228 return true; 1229 } 1230 1231 static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1232 uint64_t Address, const void *Decoder) { 1233 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1234 unsigned align = fieldFromInstruction32(Val, 4, 2); 1235 1236 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 1237 if (!align) 1238 Inst.addOperand(MCOperand::CreateImm(0)); 1239 else 1240 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1241 1242 return true; 1243 } 1244 1245 static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1246 uint64_t Address, const void *Decoder) { 1247 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1248 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1249 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1250 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1251 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1252 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1253 1254 // First output register 1255 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); 1256 1257 // Second output register 1258 switch (Inst.getOpcode()) { 1259 case ARM::VLD1q8: 1260 case ARM::VLD1q16: 1261 case ARM::VLD1q32: 1262 case ARM::VLD1q64: 1263 case ARM::VLD1q8_UPD: 1264 case ARM::VLD1q16_UPD: 1265 case ARM::VLD1q32_UPD: 1266 case ARM::VLD1q64_UPD: 1267 case ARM::VLD1d8T: 1268 case ARM::VLD1d16T: 1269 case ARM::VLD1d32T: 1270 case ARM::VLD1d64T: 1271 case ARM::VLD1d8T_UPD: 1272 case ARM::VLD1d16T_UPD: 1273 case ARM::VLD1d32T_UPD: 1274 case ARM::VLD1d64T_UPD: 1275 case ARM::VLD1d8Q: 1276 case ARM::VLD1d16Q: 1277 case ARM::VLD1d32Q: 1278 case ARM::VLD1d64Q: 1279 case ARM::VLD1d8Q_UPD: 1280 case ARM::VLD1d16Q_UPD: 1281 case ARM::VLD1d32Q_UPD: 1282 case ARM::VLD1d64Q_UPD: 1283 case ARM::VLD2d8: 1284 case ARM::VLD2d16: 1285 case ARM::VLD2d32: 1286 case ARM::VLD2d8_UPD: 1287 case ARM::VLD2d16_UPD: 1288 case ARM::VLD2d32_UPD: 1289 case ARM::VLD2q8: 1290 case ARM::VLD2q16: 1291 case ARM::VLD2q32: 1292 case ARM::VLD2q8_UPD: 1293 case ARM::VLD2q16_UPD: 1294 case ARM::VLD2q32_UPD: 1295 case ARM::VLD3d8: 1296 case ARM::VLD3d16: 1297 case ARM::VLD3d32: 1298 case ARM::VLD3d8_UPD: 1299 case ARM::VLD3d16_UPD: 1300 case ARM::VLD3d32_UPD: 1301 case ARM::VLD4d8: 1302 case ARM::VLD4d16: 1303 case ARM::VLD4d32: 1304 case ARM::VLD4d8_UPD: 1305 case ARM::VLD4d16_UPD: 1306 case ARM::VLD4d32_UPD: 1307 DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder); 1308 break; 1309 case ARM::VLD2b8: 1310 case ARM::VLD2b16: 1311 case ARM::VLD2b32: 1312 case ARM::VLD2b8_UPD: 1313 case ARM::VLD2b16_UPD: 1314 case ARM::VLD2b32_UPD: 1315 case ARM::VLD3q8: 1316 case ARM::VLD3q16: 1317 case ARM::VLD3q32: 1318 case ARM::VLD3q8_UPD: 1319 case ARM::VLD3q16_UPD: 1320 case ARM::VLD3q32_UPD: 1321 case ARM::VLD4q8: 1322 case ARM::VLD4q16: 1323 case ARM::VLD4q32: 1324 case ARM::VLD4q8_UPD: 1325 case ARM::VLD4q16_UPD: 1326 case ARM::VLD4q32_UPD: 1327 DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder); 1328 default: 1329 break; 1330 } 1331 1332 // Third output register 1333 switch(Inst.getOpcode()) { 1334 case ARM::VLD1d8T: 1335 case ARM::VLD1d16T: 1336 case ARM::VLD1d32T: 1337 case ARM::VLD1d64T: 1338 case ARM::VLD1d8T_UPD: 1339 case ARM::VLD1d16T_UPD: 1340 case ARM::VLD1d32T_UPD: 1341 case ARM::VLD1d64T_UPD: 1342 case ARM::VLD1d8Q: 1343 case ARM::VLD1d16Q: 1344 case ARM::VLD1d32Q: 1345 case ARM::VLD1d64Q: 1346 case ARM::VLD1d8Q_UPD: 1347 case ARM::VLD1d16Q_UPD: 1348 case ARM::VLD1d32Q_UPD: 1349 case ARM::VLD1d64Q_UPD: 1350 case ARM::VLD2q8: 1351 case ARM::VLD2q16: 1352 case ARM::VLD2q32: 1353 case ARM::VLD2q8_UPD: 1354 case ARM::VLD2q16_UPD: 1355 case ARM::VLD2q32_UPD: 1356 case ARM::VLD3d8: 1357 case ARM::VLD3d16: 1358 case ARM::VLD3d32: 1359 case ARM::VLD3d8_UPD: 1360 case ARM::VLD3d16_UPD: 1361 case ARM::VLD3d32_UPD: 1362 case ARM::VLD4d8: 1363 case ARM::VLD4d16: 1364 case ARM::VLD4d32: 1365 case ARM::VLD4d8_UPD: 1366 case ARM::VLD4d16_UPD: 1367 case ARM::VLD4d32_UPD: 1368 DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder); 1369 break; 1370 case ARM::VLD3q8: 1371 case ARM::VLD3q16: 1372 case ARM::VLD3q32: 1373 case ARM::VLD3q8_UPD: 1374 case ARM::VLD3q16_UPD: 1375 case ARM::VLD3q32_UPD: 1376 case ARM::VLD4q8: 1377 case ARM::VLD4q16: 1378 case ARM::VLD4q32: 1379 case ARM::VLD4q8_UPD: 1380 case ARM::VLD4q16_UPD: 1381 case ARM::VLD4q32_UPD: 1382 DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder); 1383 break; 1384 default: 1385 break; 1386 } 1387 1388 // Fourth output register 1389 switch (Inst.getOpcode()) { 1390 case ARM::VLD1d8Q: 1391 case ARM::VLD1d16Q: 1392 case ARM::VLD1d32Q: 1393 case ARM::VLD1d64Q: 1394 case ARM::VLD1d8Q_UPD: 1395 case ARM::VLD1d16Q_UPD: 1396 case ARM::VLD1d32Q_UPD: 1397 case ARM::VLD1d64Q_UPD: 1398 case ARM::VLD2q8: 1399 case ARM::VLD2q16: 1400 case ARM::VLD2q32: 1401 case ARM::VLD2q8_UPD: 1402 case ARM::VLD2q16_UPD: 1403 case ARM::VLD2q32_UPD: 1404 case ARM::VLD4d8: 1405 case ARM::VLD4d16: 1406 case ARM::VLD4d32: 1407 case ARM::VLD4d8_UPD: 1408 case ARM::VLD4d16_UPD: 1409 case ARM::VLD4d32_UPD: 1410 DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder); 1411 break; 1412 case ARM::VLD4q8: 1413 case ARM::VLD4q16: 1414 case ARM::VLD4q32: 1415 case ARM::VLD4q8_UPD: 1416 case ARM::VLD4q16_UPD: 1417 case ARM::VLD4q32_UPD: 1418 DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder); 1419 break; 1420 default: 1421 break; 1422 } 1423 1424 // Writeback operand 1425 switch (Inst.getOpcode()) { 1426 case ARM::VLD1d8_UPD: 1427 case ARM::VLD1d16_UPD: 1428 case ARM::VLD1d32_UPD: 1429 case ARM::VLD1d64_UPD: 1430 case ARM::VLD1q8_UPD: 1431 case ARM::VLD1q16_UPD: 1432 case ARM::VLD1q32_UPD: 1433 case ARM::VLD1q64_UPD: 1434 case ARM::VLD1d8T_UPD: 1435 case ARM::VLD1d16T_UPD: 1436 case ARM::VLD1d32T_UPD: 1437 case ARM::VLD1d64T_UPD: 1438 case ARM::VLD1d8Q_UPD: 1439 case ARM::VLD1d16Q_UPD: 1440 case ARM::VLD1d32Q_UPD: 1441 case ARM::VLD1d64Q_UPD: 1442 case ARM::VLD2d8_UPD: 1443 case ARM::VLD2d16_UPD: 1444 case ARM::VLD2d32_UPD: 1445 case ARM::VLD2q8_UPD: 1446 case ARM::VLD2q16_UPD: 1447 case ARM::VLD2q32_UPD: 1448 case ARM::VLD2b8_UPD: 1449 case ARM::VLD2b16_UPD: 1450 case ARM::VLD2b32_UPD: 1451 case ARM::VLD3d8_UPD: 1452 case ARM::VLD3d16_UPD: 1453 case ARM::VLD3d32_UPD: 1454 case ARM::VLD3q8_UPD: 1455 case ARM::VLD3q16_UPD: 1456 case ARM::VLD3q32_UPD: 1457 case ARM::VLD4d8_UPD: 1458 case ARM::VLD4d16_UPD: 1459 case ARM::VLD4d32_UPD: 1460 case ARM::VLD4q8_UPD: 1461 case ARM::VLD4q16_UPD: 1462 case ARM::VLD4q32_UPD: 1463 DecodeGPRRegisterClass(Inst, wb, Address, Decoder); 1464 break; 1465 default: 1466 break; 1467 } 1468 1469 // AddrMode6 Base (register+alignment) 1470 DecodeAddrMode6Operand(Inst, Rn, Address, Decoder); 1471 1472 // AddrMode6 Offset (register) 1473 if (Rm == 0xD) 1474 Inst.addOperand(MCOperand::CreateReg(0)); 1475 else if (Rm != 0xF) 1476 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 1477 1478 return true; 1479 } 1480 1481 static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1482 uint64_t Address, const void *Decoder) { 1483 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1484 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1485 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1486 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1487 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1488 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1489 1490 // Writeback Operand 1491 switch (Inst.getOpcode()) { 1492 case ARM::VST1d8_UPD: 1493 case ARM::VST1d16_UPD: 1494 case ARM::VST1d32_UPD: 1495 case ARM::VST1d64_UPD: 1496 case ARM::VST1q8_UPD: 1497 case ARM::VST1q16_UPD: 1498 case ARM::VST1q32_UPD: 1499 case ARM::VST1q64_UPD: 1500 case ARM::VST1d8T_UPD: 1501 case ARM::VST1d16T_UPD: 1502 case ARM::VST1d32T_UPD: 1503 case ARM::VST1d64T_UPD: 1504 case ARM::VST1d8Q_UPD: 1505 case ARM::VST1d16Q_UPD: 1506 case ARM::VST1d32Q_UPD: 1507 case ARM::VST1d64Q_UPD: 1508 case ARM::VST2d8_UPD: 1509 case ARM::VST2d16_UPD: 1510 case ARM::VST2d32_UPD: 1511 case ARM::VST2q8_UPD: 1512 case ARM::VST2q16_UPD: 1513 case ARM::VST2q32_UPD: 1514 case ARM::VST2b8_UPD: 1515 case ARM::VST2b16_UPD: 1516 case ARM::VST2b32_UPD: 1517 case ARM::VST3d8_UPD: 1518 case ARM::VST3d16_UPD: 1519 case ARM::VST3d32_UPD: 1520 case ARM::VST3q8_UPD: 1521 case ARM::VST3q16_UPD: 1522 case ARM::VST3q32_UPD: 1523 case ARM::VST4d8_UPD: 1524 case ARM::VST4d16_UPD: 1525 case ARM::VST4d32_UPD: 1526 case ARM::VST4q8_UPD: 1527 case ARM::VST4q16_UPD: 1528 case ARM::VST4q32_UPD: 1529 DecodeGPRRegisterClass(Inst, wb, Address, Decoder); 1530 break; 1531 default: 1532 break; 1533 } 1534 1535 // AddrMode6 Base (register+alignment) 1536 DecodeAddrMode6Operand(Inst, Rn, Address, Decoder); 1537 1538 // AddrMode6 Offset (register) 1539 if (Rm == 0xD) 1540 Inst.addOperand(MCOperand::CreateReg(0)); 1541 else if (Rm != 0xF) 1542 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 1543 1544 // First input register 1545 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); 1546 1547 // Second input register 1548 switch (Inst.getOpcode()) { 1549 case ARM::VST1q8: 1550 case ARM::VST1q16: 1551 case ARM::VST1q32: 1552 case ARM::VST1q64: 1553 case ARM::VST1q8_UPD: 1554 case ARM::VST1q16_UPD: 1555 case ARM::VST1q32_UPD: 1556 case ARM::VST1q64_UPD: 1557 case ARM::VST1d8T: 1558 case ARM::VST1d16T: 1559 case ARM::VST1d32T: 1560 case ARM::VST1d64T: 1561 case ARM::VST1d8T_UPD: 1562 case ARM::VST1d16T_UPD: 1563 case ARM::VST1d32T_UPD: 1564 case ARM::VST1d64T_UPD: 1565 case ARM::VST1d8Q: 1566 case ARM::VST1d16Q: 1567 case ARM::VST1d32Q: 1568 case ARM::VST1d64Q: 1569 case ARM::VST1d8Q_UPD: 1570 case ARM::VST1d16Q_UPD: 1571 case ARM::VST1d32Q_UPD: 1572 case ARM::VST1d64Q_UPD: 1573 case ARM::VST2d8: 1574 case ARM::VST2d16: 1575 case ARM::VST2d32: 1576 case ARM::VST2d8_UPD: 1577 case ARM::VST2d16_UPD: 1578 case ARM::VST2d32_UPD: 1579 case ARM::VST2q8: 1580 case ARM::VST2q16: 1581 case ARM::VST2q32: 1582 case ARM::VST2q8_UPD: 1583 case ARM::VST2q16_UPD: 1584 case ARM::VST2q32_UPD: 1585 case ARM::VST3d8: 1586 case ARM::VST3d16: 1587 case ARM::VST3d32: 1588 case ARM::VST3d8_UPD: 1589 case ARM::VST3d16_UPD: 1590 case ARM::VST3d32_UPD: 1591 case ARM::VST4d8: 1592 case ARM::VST4d16: 1593 case ARM::VST4d32: 1594 case ARM::VST4d8_UPD: 1595 case ARM::VST4d16_UPD: 1596 case ARM::VST4d32_UPD: 1597 DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder); 1598 break; 1599 case ARM::VST2b8: 1600 case ARM::VST2b16: 1601 case ARM::VST2b32: 1602 case ARM::VST2b8_UPD: 1603 case ARM::VST2b16_UPD: 1604 case ARM::VST2b32_UPD: 1605 case ARM::VST3q8: 1606 case ARM::VST3q16: 1607 case ARM::VST3q32: 1608 case ARM::VST3q8_UPD: 1609 case ARM::VST3q16_UPD: 1610 case ARM::VST3q32_UPD: 1611 case ARM::VST4q8: 1612 case ARM::VST4q16: 1613 case ARM::VST4q32: 1614 case ARM::VST4q8_UPD: 1615 case ARM::VST4q16_UPD: 1616 case ARM::VST4q32_UPD: 1617 DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder); 1618 break; 1619 default: 1620 break; 1621 } 1622 1623 // Third input register 1624 switch (Inst.getOpcode()) { 1625 case ARM::VST1d8T: 1626 case ARM::VST1d16T: 1627 case ARM::VST1d32T: 1628 case ARM::VST1d64T: 1629 case ARM::VST1d8T_UPD: 1630 case ARM::VST1d16T_UPD: 1631 case ARM::VST1d32T_UPD: 1632 case ARM::VST1d64T_UPD: 1633 case ARM::VST1d8Q: 1634 case ARM::VST1d16Q: 1635 case ARM::VST1d32Q: 1636 case ARM::VST1d64Q: 1637 case ARM::VST1d8Q_UPD: 1638 case ARM::VST1d16Q_UPD: 1639 case ARM::VST1d32Q_UPD: 1640 case ARM::VST1d64Q_UPD: 1641 case ARM::VST2q8: 1642 case ARM::VST2q16: 1643 case ARM::VST2q32: 1644 case ARM::VST2q8_UPD: 1645 case ARM::VST2q16_UPD: 1646 case ARM::VST2q32_UPD: 1647 case ARM::VST3d8: 1648 case ARM::VST3d16: 1649 case ARM::VST3d32: 1650 case ARM::VST3d8_UPD: 1651 case ARM::VST3d16_UPD: 1652 case ARM::VST3d32_UPD: 1653 case ARM::VST4d8: 1654 case ARM::VST4d16: 1655 case ARM::VST4d32: 1656 case ARM::VST4d8_UPD: 1657 case ARM::VST4d16_UPD: 1658 case ARM::VST4d32_UPD: 1659 DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder); 1660 break; 1661 case ARM::VST3q8: 1662 case ARM::VST3q16: 1663 case ARM::VST3q32: 1664 case ARM::VST3q8_UPD: 1665 case ARM::VST3q16_UPD: 1666 case ARM::VST3q32_UPD: 1667 case ARM::VST4q8: 1668 case ARM::VST4q16: 1669 case ARM::VST4q32: 1670 case ARM::VST4q8_UPD: 1671 case ARM::VST4q16_UPD: 1672 case ARM::VST4q32_UPD: 1673 DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder); 1674 break; 1675 default: 1676 break; 1677 } 1678 1679 // Fourth input register 1680 switch (Inst.getOpcode()) { 1681 case ARM::VST1d8Q: 1682 case ARM::VST1d16Q: 1683 case ARM::VST1d32Q: 1684 case ARM::VST1d64Q: 1685 case ARM::VST1d8Q_UPD: 1686 case ARM::VST1d16Q_UPD: 1687 case ARM::VST1d32Q_UPD: 1688 case ARM::VST1d64Q_UPD: 1689 case ARM::VST2q8: 1690 case ARM::VST2q16: 1691 case ARM::VST2q32: 1692 case ARM::VST2q8_UPD: 1693 case ARM::VST2q16_UPD: 1694 case ARM::VST2q32_UPD: 1695 case ARM::VST4d8: 1696 case ARM::VST4d16: 1697 case ARM::VST4d32: 1698 case ARM::VST4d8_UPD: 1699 case ARM::VST4d16_UPD: 1700 case ARM::VST4d32_UPD: 1701 DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder); 1702 break; 1703 case ARM::VST4q8: 1704 case ARM::VST4q16: 1705 case ARM::VST4q32: 1706 case ARM::VST4q8_UPD: 1707 case ARM::VST4q16_UPD: 1708 case ARM::VST4q32_UPD: 1709 DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder); 1710 break; 1711 default: 1712 break; 1713 } 1714 1715 return true; 1716 } 1717 1718 static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1719 uint64_t Address, const void *Decoder) { 1720 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1721 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1722 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1723 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1724 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1725 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1726 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 1727 1728 align *= (1 << size); 1729 1730 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); 1731 if (regs == 2) DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder); 1732 if (Rm == 0xD) DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1733 1734 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1735 Inst.addOperand(MCOperand::CreateImm(align)); 1736 1737 if (Rm == 0xD) 1738 Inst.addOperand(MCOperand::CreateReg(0)); 1739 else if (Rm != 0xF) 1740 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 1741 1742 return true; 1743 } 1744 1745 static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1746 uint64_t Address, const void *Decoder) { 1747 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1748 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1749 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1750 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1751 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1752 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 1753 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1754 align *= 2*size; 1755 1756 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); 1757 DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder); 1758 if (Rm == 0xD) DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1759 1760 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1761 Inst.addOperand(MCOperand::CreateImm(align)); 1762 1763 if (Rm == 0xD) 1764 Inst.addOperand(MCOperand::CreateReg(0)); 1765 else if (Rm != 0xF) 1766 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 1767 1768 return true; 1769 } 1770 1771 static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1772 uint64_t Address, const void *Decoder) { 1773 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1774 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1775 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1776 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1777 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1778 1779 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); 1780 DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder); 1781 DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder); 1782 if (Rm == 0xD) DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1783 1784 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1785 Inst.addOperand(MCOperand::CreateImm(0)); 1786 1787 if (Rm == 0xD) 1788 Inst.addOperand(MCOperand::CreateReg(0)); 1789 else if (Rm != 0xF) 1790 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 1791 1792 return true; 1793 } 1794 1795 static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1796 uint64_t Address, const void *Decoder) { 1797 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1798 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1799 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1800 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1801 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1802 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1803 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1804 1805 if (size == 0x3) { 1806 size = 4; 1807 align = 16; 1808 } else { 1809 if (size == 2) { 1810 size = 1 << size; 1811 align *= 8; 1812 } else { 1813 size = 1 << size; 1814 align *= 4*size; 1815 } 1816 } 1817 1818 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); 1819 DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder); 1820 DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder); 1821 DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder); 1822 if (Rm == 0xD) DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1823 1824 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1825 Inst.addOperand(MCOperand::CreateImm(align)); 1826 1827 if (Rm == 0xD) 1828 Inst.addOperand(MCOperand::CreateReg(0)); 1829 else if (Rm != 0xF) 1830 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 1831 1832 return true; 1833 } 1834 1835 static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1836 uint64_t Address, const void *Decoder) { 1837 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1838 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1839 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 1840 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 1841 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 1842 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 1843 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 1844 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 1845 1846 if (Q) 1847 DecodeQPRRegisterClass(Inst, Rd, Address, Decoder); 1848 else 1849 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); 1850 1851 Inst.addOperand(MCOperand::CreateImm(imm)); 1852 1853 switch (Inst.getOpcode()) { 1854 case ARM::VORRiv4i16: 1855 case ARM::VORRiv2i32: 1856 case ARM::VBICiv4i16: 1857 case ARM::VBICiv2i32: 1858 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); 1859 break; 1860 case ARM::VORRiv8i16: 1861 case ARM::VORRiv4i32: 1862 case ARM::VBICiv8i16: 1863 case ARM::VBICiv4i32: 1864 DecodeQPRRegisterClass(Inst, Rd, Address, Decoder); 1865 break; 1866 default: 1867 break; 1868 } 1869 1870 1871 return true; 1872 } 1873 1874 static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 1875 uint64_t Address, const void *Decoder) { 1876 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1877 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1878 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1879 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 1880 unsigned size = fieldFromInstruction32(Insn, 18, 2); 1881 1882 DecodeQPRRegisterClass(Inst, Rd, Address, Decoder); 1883 DecodeDPRRegisterClass(Inst, Rm, Address, Decoder); 1884 Inst.addOperand(MCOperand::CreateImm(8 << size)); 1885 1886 return true; 1887 } 1888 1889 static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 1890 uint64_t Address, const void *Decoder) { 1891 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 1892 return true; 1893 } 1894 1895 static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 1896 uint64_t Address, const void *Decoder) { 1897 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 1898 return true; 1899 } 1900 1901 static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 1902 uint64_t Address, const void *Decoder) { 1903 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 1904 return true; 1905 } 1906 1907 static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 1908 uint64_t Address, const void *Decoder) { 1909 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1910 return true; 1911 } 1912 1913 static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 1914 uint64_t Address, const void *Decoder) { 1915 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1916 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1917 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1918 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 1919 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1920 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 1921 unsigned op = fieldFromInstruction32(Insn, 6, 1); 1922 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 1923 1924 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); 1925 if (op) DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); // Writeback 1926 1927 for (unsigned i = 0; i < length; ++i) 1928 DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder); 1929 1930 DecodeDPRRegisterClass(Inst, Rm, Address, Decoder); 1931 1932 return true; 1933 } 1934 1935 static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 1936 uint64_t Address, const void *Decoder) { 1937 // The immediate needs to be a fully instantiated float. However, the 1938 // auto-generated decoder is only able to fill in some of the bits 1939 // necessary. For instance, the 'b' bit is replicated multiple times, 1940 // and is even present in inverted form in one bit. We do a little 1941 // binary parsing here to fill in those missing bits, and then 1942 // reinterpret it all as a float. 1943 union { 1944 uint32_t integer; 1945 float fp; 1946 } fp_conv; 1947 1948 fp_conv.integer = Val; 1949 uint32_t b = fieldFromInstruction32(Val, 25, 1); 1950 fp_conv.integer |= b << 26; 1951 fp_conv.integer |= b << 27; 1952 fp_conv.integer |= b << 28; 1953 fp_conv.integer |= b << 29; 1954 fp_conv.integer |= (~b & 0x1) << 30; 1955 1956 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 1957 return true; 1958 } 1959 1960 static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 1961 uint64_t Address, const void *Decoder) { 1962 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 1963 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 1964 1965 DecodetGPRRegisterClass(Inst, dst, Address, Decoder); 1966 1967 if (Inst.getOpcode() == ARM::tADR) 1968 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 1969 else if (Inst.getOpcode() == ARM::tADDrSPi) 1970 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 1971 else 1972 return false; 1973 1974 Inst.addOperand(MCOperand::CreateImm(imm)); 1975 return true; 1976 } 1977 1978 static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 1979 uint64_t Address, const void *Decoder) { 1980 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 1981 return true; 1982 } 1983 1984 static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 1985 uint64_t Address, const void *Decoder) { 1986 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 1987 return true; 1988 } 1989 1990 static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 1991 uint64_t Address, const void *Decoder) { 1992 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 1993 return true; 1994 } 1995 1996 static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 1997 uint64_t Address, const void *Decoder) { 1998 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 1999 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2000 2001 DecodetGPRRegisterClass(Inst, Rn, Address, Decoder); 2002 DecodetGPRRegisterClass(Inst, Rm, Address, Decoder); 2003 2004 return true; 2005 } 2006 2007 static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2008 uint64_t Address, const void *Decoder) { 2009 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2010 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2011 2012 DecodetGPRRegisterClass(Inst, Rn, Address, Decoder); 2013 Inst.addOperand(MCOperand::CreateImm(imm)); 2014 2015 return true; 2016 } 2017 2018 static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2019 uint64_t Address, const void *Decoder) { 2020 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2021 2022 return true; 2023 } 2024 2025 static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2026 uint64_t Address, const void *Decoder) { 2027 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2028 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2029 2030 return true; 2031 } 2032 2033 static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2034 uint64_t Address, const void *Decoder) { 2035 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2036 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2037 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2038 2039 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 2040 DecoderGPRRegisterClass(Inst, Rm, Address, Decoder); 2041 Inst.addOperand(MCOperand::CreateImm(imm)); 2042 2043 return true; 2044 } 2045 2046 static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2047 uint64_t Address, const void *Decoder) { 2048 if (Inst.getOpcode() != ARM::t2PLDs) { 2049 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2050 DecodeGPRRegisterClass(Inst, Rt, Address, Decoder); 2051 } 2052 2053 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2054 if (Rn == 0xF) { 2055 switch (Inst.getOpcode()) { 2056 case ARM::t2LDRBs: 2057 Inst.setOpcode(ARM::t2LDRBpci); 2058 break; 2059 case ARM::t2LDRHs: 2060 Inst.setOpcode(ARM::t2LDRHpci); 2061 break; 2062 case ARM::t2LDRSHs: 2063 Inst.setOpcode(ARM::t2LDRSHpci); 2064 break; 2065 case ARM::t2LDRSBs: 2066 Inst.setOpcode(ARM::t2LDRSBpci); 2067 break; 2068 case ARM::t2PLDs: 2069 Inst.setOpcode(ARM::t2PLDi12); 2070 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2071 break; 2072 default: 2073 return false; 2074 } 2075 2076 int imm = fieldFromInstruction32(Insn, 0, 12); 2077 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2078 Inst.addOperand(MCOperand::CreateImm(imm)); 2079 2080 return true; 2081 } 2082 2083 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2084 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2085 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2086 DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder); 2087 2088 return true; 2089 } 2090 2091 static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2092 uint64_t Address, const void *Decoder) { 2093 int imm = Val & 0xFF; 2094 if (!(Val & 0x100)) imm *= -1; 2095 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2096 2097 return true; 2098 } 2099 2100 static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2101 uint64_t Address, const void *Decoder) { 2102 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2103 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2104 2105 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 2106 DecodeT2Imm8S4(Inst, imm, Address, Decoder); 2107 2108 return true; 2109 } 2110 2111 static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2112 uint64_t Address, const void *Decoder) { 2113 int imm = Val & 0xFF; 2114 if (!(Val & 0x100)) imm *= -1; 2115 Inst.addOperand(MCOperand::CreateImm(imm)); 2116 2117 return true; 2118 } 2119 2120 2121 static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2122 uint64_t Address, const void *Decoder) { 2123 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2124 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2125 2126 // Some instructions always use an additive offset. 2127 switch (Inst.getOpcode()) { 2128 case ARM::t2LDRT: 2129 case ARM::t2LDRBT: 2130 case ARM::t2LDRHT: 2131 case ARM::t2LDRSBT: 2132 case ARM::t2LDRSHT: 2133 imm |= 0x100; 2134 break; 2135 default: 2136 break; 2137 } 2138 2139 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 2140 DecodeT2Imm8(Inst, imm, Address, Decoder); 2141 2142 return true; 2143 } 2144 2145 2146 static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2147 uint64_t Address, const void *Decoder) { 2148 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2149 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2150 2151 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 2152 Inst.addOperand(MCOperand::CreateImm(imm)); 2153 2154 return true; 2155 } 2156 2157 2158 static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2159 uint64_t Address, const void *Decoder) { 2160 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2161 2162 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2163 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2164 Inst.addOperand(MCOperand::CreateImm(imm)); 2165 2166 return true; 2167 } 2168 2169 static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2170 uint64_t Address, const void *Decoder) { 2171 if (Inst.getOpcode() == ARM::tADDrSP) { 2172 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2173 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2174 2175 DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder); 2176 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2177 DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder); 2178 } else if (Inst.getOpcode() == ARM::tADDspr) { 2179 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2180 2181 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2182 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2183 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 2184 } 2185 2186 return true; 2187 } 2188 2189 static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2190 uint64_t Address, const void *Decoder) { 2191 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2192 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2193 2194 Inst.addOperand(MCOperand::CreateImm(imod)); 2195 Inst.addOperand(MCOperand::CreateImm(flags)); 2196 2197 return true; 2198 } 2199 2200 static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2201 uint64_t Address, const void *Decoder) { 2202 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2203 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2204 2205 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 2206 Inst.addOperand(MCOperand::CreateImm(add)); 2207 2208 return true; 2209 } 2210 2211 static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2212 uint64_t Address, const void *Decoder) { 2213 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2214 return true; 2215 } 2216 2217 static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2218 uint64_t Address, const void *Decoder) { 2219 if (Val == 0xA || Val == 0xB) 2220 return false; 2221 2222 Inst.addOperand(MCOperand::CreateImm(Val)); 2223 return true; 2224 } 2225 2226 static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, 2227 uint64_t Address, const void *Decoder) { 2228 if (Val == 0) 2229 Inst.addOperand(MCOperand::CreateImm(32)); 2230 else 2231 Inst.addOperand(MCOperand::CreateImm(Val)); 2232 return true; 2233 } 2234 2235 static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2236 uint64_t Address, const void *Decoder) { 2237 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2238 if (pred == 0xE || pred == 0xF) { 2239 unsigned opc = fieldFromInstruction32(Insn, 4, 2); 2240 switch (opc) { 2241 default: 2242 return false; 2243 case 0: 2244 Inst.setOpcode(ARM::t2DSB); 2245 break; 2246 case 1: 2247 Inst.setOpcode(ARM::t2DMB); 2248 break; 2249 case 2: 2250 Inst.setOpcode(ARM::t2ISB); 2251 return true; 2252 } 2253 2254 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2255 Inst.addOperand(MCOperand::CreateImm(imm)); 2256 return true; 2257 } 2258 2259 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2260 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2261 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2262 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2263 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2264 2265 DecodeT2BROperand(Inst, brtarget, Address, Decoder); 2266 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) 2267 return false; 2268 2269 return true; 2270 } 2271 2272 // Decode a shifted immediate operand. These basically consist 2273 // of an 8-bit value, and a 4-bit directive that specifies either 2274 // a splat operation or a rotation. 2275 static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2276 uint64_t Address, const void *Decoder) { 2277 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2278 if (ctrl == 0) { 2279 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2280 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2281 switch (byte) { 2282 case 0: 2283 Inst.addOperand(MCOperand::CreateImm(imm)); 2284 break; 2285 case 1: 2286 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2287 break; 2288 case 2: 2289 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2290 break; 2291 case 3: 2292 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2293 (imm << 8) | imm)); 2294 break; 2295 } 2296 } else { 2297 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2298 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2299 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2300 Inst.addOperand(MCOperand::CreateImm(imm)); 2301 } 2302 2303 return true; 2304 } 2305 2306 static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 2307 uint64_t Address, const void *Decoder){ 2308 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 2309 return true; 2310 } 2311 2312 static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 2313 uint64_t Address, const void *Decoder){ 2314 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2315 return true; 2316 } 2317 2318 static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Val, 2319 uint64_t Address, const void *Decoder) { 2320 bool isImm = fieldFromInstruction32(Val, 9, 1); 2321 bool isAdd = fieldFromInstruction32(Val, 8, 1); 2322 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2323 2324 if (!isImm) { 2325 DecodeGPRRegisterClass(Inst, imm, Address, Decoder); 2326 Inst.addOperand(MCOperand::CreateImm(!isAdd << 8)); 2327 } else { 2328 Inst.addOperand(MCOperand::CreateReg(0)); 2329 Inst.addOperand(MCOperand::CreateImm(imm | (!isAdd << 8))); 2330 } 2331 2332 return true; 2333 } 2334