1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARMDisassembler.h" 13 #include "ARM.h" 14 #include "ARMRegisterInfo.h" 15 #include "MCTargetDesc/ARMAddressingModes.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/Target/TargetRegistry.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/raw_ostream.h" 26 27 // Forward declare these because the autogenerated code will reference them. 28 // Definitions are further down. 29 static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 30 uint64_t Address, const void *Decoder); 31 static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 32 uint64_t Address, const void *Decoder); 33 static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 34 uint64_t Address, const void *Decoder); 35 static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 36 uint64_t Address, const void *Decoder); 37 static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 38 uint64_t Address, const void *Decoder); 39 static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 40 uint64_t Address, const void *Decoder); 41 static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 42 uint64_t Address, const void *Decoder); 43 static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 44 uint64_t Address, const void *Decoder); 45 static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 46 uint64_t Address, const void *Decoder); 47 static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 48 uint64_t Address, const void *Decoder); 49 50 static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 51 uint64_t Address, const void *Decoder); 52 static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 53 uint64_t Address, const void *Decoder); 54 static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 55 uint64_t Address, const void *Decoder); 56 static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 57 uint64_t Address, const void *Decoder); 58 static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 59 uint64_t Address, const void *Decoder); 60 static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 61 uint64_t Address, const void *Decoder); 62 static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 63 uint64_t Address, const void *Decoder); 64 65 static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 66 uint64_t Address, const void *Decoder); 67 static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 68 uint64_t Address, const void *Decoder); 69 static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 70 uint64_t Address, const void *Decoder); 71 static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 72 uint64_t Address, const void *Decoder); 73 static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 74 uint64_t Address, const void *Decoder); 75 static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 76 uint64_t Address, const void *Decoder); 77 static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 78 uint64_t Address, const void *Decoder); 79 80 static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 81 unsigned Insn, 82 uint64_t Adddress, 83 const void *Decoder); 84 static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 85 uint64_t Address, const void *Decoder); 86 static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 87 uint64_t Address, const void *Decoder); 88 static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 89 uint64_t Address, const void *Decoder); 90 static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 91 uint64_t Address, const void *Decoder); 92 static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 93 uint64_t Address, const void *Decoder); 94 static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 95 uint64_t Address, const void *Decoder); 96 static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 97 uint64_t Address, const void *Decoder); 98 static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 99 uint64_t Address, const void *Decoder); 100 static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 101 uint64_t Address, const void *Decoder); 102 static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 103 uint64_t Address, const void *Decoder); 104 static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 105 uint64_t Address, const void *Decoder); 106 static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 107 uint64_t Address, const void *Decoder); 108 static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 109 uint64_t Address, const void *Decoder); 110 static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 111 uint64_t Address, const void *Decoder); 112 static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Val, 113 uint64_t Address, const void *Decoder); 114 static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 115 uint64_t Address, const void *Decoder); 116 static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 117 uint64_t Address, const void *Decoder); 118 static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 119 uint64_t Address, const void *Decoder); 120 static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 121 uint64_t Address, const void *Decoder); 122 static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 123 uint64_t Address, const void *Decoder); 124 static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 125 uint64_t Address, const void *Decoder); 126 static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 127 uint64_t Address, const void *Decoder); 128 static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 129 uint64_t Address, const void *Decoder); 130 static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 131 uint64_t Address, const void *Decoder); 132 static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Insn, 133 uint64_t Address, const void *Decoder); 134 static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 135 uint64_t Address, const void *Decoder); 136 static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 137 uint64_t Address, const void *Decoder); 138 139 140 static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 141 uint64_t Address, const void *Decoder); 142 static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 143 uint64_t Address, const void *Decoder); 144 static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 145 uint64_t Address, const void *Decoder); 146 static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 147 uint64_t Address, const void *Decoder); 148 static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 149 uint64_t Address, const void *Decoder); 150 static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 151 uint64_t Address, const void *Decoder); 152 static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 153 uint64_t Address, const void *Decoder); 154 static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 155 uint64_t Address, const void *Decoder); 156 static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 157 uint64_t Address, const void *Decoder); 158 static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 159 uint64_t Address, const void *Decoder); 160 static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 161 uint64_t Address, const void *Decoder); 162 static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 163 uint64_t Address, const void *Decoder); 164 static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 165 uint64_t Address, const void *Decoder); 166 static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 167 uint64_t Address, const void *Decoder); 168 static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 169 uint64_t Address, const void *Decoder); 170 static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 171 uint64_t Address, const void *Decoder); 172 static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 173 uint64_t Address, const void *Decoder); 174 static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 175 uint64_t Address, const void *Decoder); 176 static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 177 uint64_t Address, const void *Decoder); 178 static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, 179 uint64_t Address, const void *Decoder); 180 static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 181 uint64_t Address, const void *Decoder); 182 static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 183 uint64_t Address, const void *Decoder); 184 static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 185 uint64_t Address, const void *Decoder); 186 static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188 189 #include "ARMGenDisassemblerTables.inc" 190 #include "ARMGenInstrInfo.inc" 191 #include "ARMGenEDInfo.inc" 192 193 using namespace llvm; 194 195 static MCDisassembler *createARMDisassembler(const Target &T) { 196 return new ARMDisassembler; 197 } 198 199 static MCDisassembler *createThumbDisassembler(const Target &T) { 200 return new ThumbDisassembler; 201 } 202 203 EDInstInfo *ARMDisassembler::getEDInfo() const { 204 return instInfoARM; 205 } 206 207 EDInstInfo *ThumbDisassembler::getEDInfo() const { 208 return instInfoARM; 209 } 210 211 212 bool ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 213 const MemoryObject &Region, 214 uint64_t Address,raw_ostream &os) const { 215 uint8_t bytes[4]; 216 217 // We want to read exactly 4 bytes of data. 218 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 219 return false; 220 221 // Encoded as a small-endian 32-bit word in the stream. 222 uint32_t insn = (bytes[3] << 24) | 223 (bytes[2] << 16) | 224 (bytes[1] << 8) | 225 (bytes[0] << 0); 226 227 // Calling the auto-generated decoder function. 228 bool result = decodeARMInstruction32(MI, insn, Address, this); 229 if (result) { 230 Size = 4; 231 return true; 232 } 233 234 // Instructions that are shared between ARM and Thumb modes. 235 // FIXME: This shouldn't really exist. It's an artifact of the 236 // fact that we fail to encode a few instructions properly for Thumb. 237 MI.clear(); 238 result = decodeCommonInstruction32(MI, insn, Address, this); 239 if (result) { 240 Size = 4; 241 return true; 242 } 243 244 // VFP and NEON instructions, similarly, are shared between ARM 245 // and Thumb modes. 246 MI.clear(); 247 result = decodeVFPInstruction32(MI, insn, Address, this); 248 if (result) { 249 Size = 4; 250 return true; 251 } 252 253 MI.clear(); 254 result = decodeNEONDataInstruction32(MI, insn, Address, this); 255 if (result) { 256 Size = 4; 257 // Add a fake predicate operand, because we share these instruction 258 // definitions with Thumb2 where these instructions are predicable. 259 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 260 return true; 261 } 262 263 MI.clear(); 264 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this); 265 if (result) { 266 Size = 4; 267 // Add a fake predicate operand, because we share these instruction 268 // definitions with Thumb2 where these instructions are predicable. 269 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 270 return true; 271 } 272 273 MI.clear(); 274 result = decodeNEONDupInstruction32(MI, insn, Address, this); 275 if (result) { 276 Size = 4; 277 // Add a fake predicate operand, because we share these instruction 278 // definitions with Thumb2 where these instructions are predicable. 279 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 280 return true; 281 } 282 283 MI.clear(); 284 285 return false; 286 } 287 288 namespace llvm { 289 extern MCInstrDesc ARMInsts[]; 290 } 291 292 // Thumb1 instructions don't have explicit S bits. Rather, they 293 // implicitly set CPSR. Since it's not represented in the encoding, the 294 // auto-generated decoder won't inject the CPSR operand. We need to fix 295 // that as a post-pass. 296 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 297 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 298 MCInst::iterator I = MI.begin(); 299 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 300 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 301 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 302 return; 303 } 304 } 305 306 if (OpInfo[MI.size()].isOptionalDef() && 307 OpInfo[MI.size()].RegClass == ARM::CCRRegClassID) 308 MI.insert(MI.end(), MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 309 } 310 311 // Most Thumb instructions don't have explicit predicates in the 312 // encoding, but rather get their predicates from IT context. We need 313 // to fix up the predicate operands using this context information as a 314 // post-pass. 315 void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 316 // A few instructions actually have predicates encoded in them. Don't 317 // try to overwrite it if we're seeing one of those. 318 switch (MI.getOpcode()) { 319 case ARM::tBcc: 320 case ARM::t2Bcc: 321 return; 322 default: 323 break; 324 } 325 326 // If we're in an IT block, base the predicate on that. Otherwise, 327 // assume a predicate of AL. 328 unsigned CC; 329 if (!ITBlock.empty()) { 330 CC = ITBlock.back(); 331 ITBlock.pop_back(); 332 } else 333 CC = ARMCC::AL; 334 335 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 336 MCInst::iterator I = MI.begin(); 337 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 338 if (OpInfo[i].isPredicate()) { 339 I = MI.insert(I, MCOperand::CreateImm(CC)); 340 ++I; 341 if (CC == ARMCC::AL) 342 MI.insert(I, MCOperand::CreateReg(0)); 343 else 344 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 345 return; 346 } 347 } 348 349 MI.insert(MI.end(), MCOperand::CreateImm(CC)); 350 if (CC == ARMCC::AL) 351 MI.insert(MI.end(), MCOperand::CreateReg(0)); 352 else 353 MI.insert(MI.end(), MCOperand::CreateReg(ARM::CPSR)); 354 } 355 356 // Thumb VFP instructions are a special case. Because we share their 357 // encodings between ARM and Thumb modes, and they are predicable in ARM 358 // mode, the auto-generated decoder will give them an (incorrect) 359 // predicate operand. We need to rewrite these operands based on the IT 360 // context as a post-pass. 361 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 362 unsigned CC; 363 if (!ITBlock.empty()) { 364 CC = ITBlock.back(); 365 ITBlock.pop_back(); 366 } else 367 CC = ARMCC::AL; 368 369 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 370 MCInst::iterator I = MI.begin(); 371 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 372 if (OpInfo[i].isPredicate() ) { 373 I->setImm(CC); 374 ++I; 375 if (CC == ARMCC::AL) 376 I->setReg(0); 377 else 378 I->setReg(ARM::CPSR); 379 return; 380 } 381 } 382 } 383 384 385 bool ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 386 const MemoryObject &Region, 387 uint64_t Address,raw_ostream &os) const { 388 uint8_t bytes[4]; 389 390 // We want to read exactly 2 bytes of data. 391 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) 392 return false; 393 394 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 395 bool result = decodeThumbInstruction16(MI, insn16, Address, this); 396 if (result) { 397 Size = 2; 398 bool InITBlock = !ITBlock.empty(); 399 AddThumbPredicate(MI); 400 AddThumb1SBit(MI, InITBlock); 401 return true; 402 } 403 404 MI.clear(); 405 result = decodeThumb2Instruction16(MI, insn16, Address, this); 406 if (result) { 407 Size = 2; 408 AddThumbPredicate(MI); 409 410 // If we find an IT instruction, we need to parse its condition 411 // code and mask operands so that we can apply them correctly 412 // to the subsequent instructions. 413 if (MI.getOpcode() == ARM::t2IT) { 414 unsigned firstcond = MI.getOperand(0).getImm(); 415 uint32_t mask = MI.getOperand(1).getImm(); 416 unsigned zeros = CountTrailingZeros_32(mask); 417 mask >>= zeros+1; 418 419 for (unsigned i = 0; i < 4 - (zeros+1); ++i) { 420 if (firstcond ^ (mask & 1)) 421 ITBlock.push_back(firstcond ^ 1); 422 else 423 ITBlock.push_back(firstcond); 424 mask >>= 1; 425 } 426 ITBlock.push_back(firstcond); 427 } 428 429 return true; 430 } 431 432 // We want to read exactly 4 bytes of data. 433 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 434 return false; 435 436 uint32_t insn32 = (bytes[3] << 8) | 437 (bytes[2] << 0) | 438 (bytes[1] << 24) | 439 (bytes[0] << 16); 440 MI.clear(); 441 result = decodeThumbInstruction32(MI, insn32, Address, this); 442 if (result) { 443 Size = 4; 444 bool InITBlock = ITBlock.size(); 445 AddThumbPredicate(MI); 446 AddThumb1SBit(MI, InITBlock); 447 return true; 448 } 449 450 MI.clear(); 451 result = decodeThumb2Instruction32(MI, insn32, Address, this); 452 if (result) { 453 Size = 4; 454 AddThumbPredicate(MI); 455 return true; 456 } 457 458 MI.clear(); 459 result = decodeCommonInstruction32(MI, insn32, Address, this); 460 if (result) { 461 Size = 4; 462 AddThumbPredicate(MI); 463 return true; 464 } 465 466 MI.clear(); 467 result = decodeVFPInstruction32(MI, insn32, Address, this); 468 if (result) { 469 Size = 4; 470 UpdateThumbVFPPredicate(MI); 471 return true; 472 } 473 474 MI.clear(); 475 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 476 uint32_t NEONDataInsn = insn32; 477 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 478 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 479 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 480 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this); 481 if (result) { 482 Size = 4; 483 AddThumbPredicate(MI); 484 return true; 485 } 486 } 487 488 MI.clear(); 489 result = decodeNEONLoadStoreInstruction32(MI, insn32, Address, this); 490 if (result) { 491 Size = 4; 492 AddThumbPredicate(MI); 493 return true; 494 } 495 496 MI.clear(); 497 result = decodeNEONDupInstruction32(MI, insn32, Address, this); 498 if (result) { 499 Size = 4; 500 AddThumbPredicate(MI); 501 return true; 502 } 503 504 return false; 505 } 506 507 508 extern "C" void LLVMInitializeARMDisassembler() { 509 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 510 createARMDisassembler); 511 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 512 createThumbDisassembler); 513 } 514 515 static const unsigned GPRDecoderTable[] = { 516 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 517 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 518 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 519 ARM::R12, ARM::SP, ARM::LR, ARM::PC 520 }; 521 522 static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 523 uint64_t Address, const void *Decoder) { 524 if (RegNo > 15) 525 return false; 526 527 unsigned Register = GPRDecoderTable[RegNo]; 528 Inst.addOperand(MCOperand::CreateReg(Register)); 529 return true; 530 } 531 532 static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 533 uint64_t Address, const void *Decoder) { 534 if (RegNo == 15) return false; 535 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 536 } 537 538 static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 539 uint64_t Address, const void *Decoder) { 540 if (RegNo > 7) 541 return false; 542 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 543 } 544 545 static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 546 uint64_t Address, const void *Decoder) { 547 unsigned Register = 0; 548 switch (RegNo) { 549 case 0: 550 Register = ARM::R0; 551 break; 552 case 1: 553 Register = ARM::R1; 554 break; 555 case 2: 556 Register = ARM::R2; 557 break; 558 case 3: 559 Register = ARM::R3; 560 break; 561 case 9: 562 Register = ARM::R9; 563 break; 564 case 12: 565 Register = ARM::R12; 566 break; 567 default: 568 return false; 569 } 570 571 Inst.addOperand(MCOperand::CreateReg(Register)); 572 return true; 573 } 574 575 static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 576 uint64_t Address, const void *Decoder) { 577 if (RegNo == 13 || RegNo == 15) return false; 578 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 579 } 580 581 static const unsigned SPRDecoderTable[] = { 582 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 583 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 584 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 585 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 586 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 587 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 588 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 589 ARM::S28, ARM::S29, ARM::S30, ARM::S31 590 }; 591 592 static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 593 uint64_t Address, const void *Decoder) { 594 if (RegNo > 31) 595 return false; 596 597 unsigned Register = SPRDecoderTable[RegNo]; 598 Inst.addOperand(MCOperand::CreateReg(Register)); 599 return true; 600 } 601 602 static const unsigned DPRDecoderTable[] = { 603 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 604 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 605 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 606 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 607 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 608 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 609 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 610 ARM::D28, ARM::D29, ARM::D30, ARM::D31 611 }; 612 613 static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 614 uint64_t Address, const void *Decoder) { 615 if (RegNo > 31) 616 return false; 617 618 unsigned Register = DPRDecoderTable[RegNo]; 619 Inst.addOperand(MCOperand::CreateReg(Register)); 620 return true; 621 } 622 623 static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 624 uint64_t Address, const void *Decoder) { 625 if (RegNo > 7) 626 return false; 627 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 628 } 629 630 static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 631 uint64_t Address, const void *Decoder) { 632 if (RegNo > 15) 633 return false; 634 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 635 } 636 637 static const unsigned QPRDecoderTable[] = { 638 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 639 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 640 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 641 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 642 }; 643 644 645 static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 646 uint64_t Address, const void *Decoder) { 647 if (RegNo > 31) 648 return false; 649 RegNo >>= 1; 650 651 unsigned Register = QPRDecoderTable[RegNo]; 652 Inst.addOperand(MCOperand::CreateReg(Register)); 653 return true; 654 } 655 656 static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 657 uint64_t Address, const void *Decoder) { 658 if (Val == 0xF) return false; 659 // AL predicate is not allowed on Thumb1 branches. 660 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 661 return false; 662 Inst.addOperand(MCOperand::CreateImm(Val)); 663 if (Val == ARMCC::AL) { 664 Inst.addOperand(MCOperand::CreateReg(0)); 665 } else 666 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 667 return true; 668 } 669 670 static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 671 uint64_t Address, const void *Decoder) { 672 if (Val) 673 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 674 else 675 Inst.addOperand(MCOperand::CreateReg(0)); 676 return true; 677 } 678 679 static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 680 uint64_t Address, const void *Decoder) { 681 uint32_t imm = Val & 0xFF; 682 uint32_t rot = (Val & 0xF00) >> 7; 683 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 684 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 685 return true; 686 } 687 688 static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 689 uint64_t Address, const void *Decoder) { 690 Val <<= 2; 691 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val))); 692 return true; 693 } 694 695 static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 696 uint64_t Address, const void *Decoder) { 697 698 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 699 unsigned type = fieldFromInstruction32(Val, 5, 2); 700 unsigned imm = fieldFromInstruction32(Val, 7, 5); 701 702 // Register-immediate 703 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 704 705 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 706 switch (type) { 707 case 0: 708 Shift = ARM_AM::lsl; 709 break; 710 case 1: 711 Shift = ARM_AM::lsr; 712 break; 713 case 2: 714 Shift = ARM_AM::asr; 715 break; 716 case 3: 717 Shift = ARM_AM::ror; 718 break; 719 } 720 721 if (Shift == ARM_AM::ror && imm == 0) 722 Shift = ARM_AM::rrx; 723 724 unsigned Op = Shift | (imm << 3); 725 Inst.addOperand(MCOperand::CreateImm(Op)); 726 727 return true; 728 } 729 730 static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 731 uint64_t Address, const void *Decoder) { 732 733 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 734 unsigned type = fieldFromInstruction32(Val, 5, 2); 735 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 736 737 // Register-register 738 if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; 739 if (!DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)) return false; 740 741 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 742 switch (type) { 743 case 0: 744 Shift = ARM_AM::lsl; 745 break; 746 case 1: 747 Shift = ARM_AM::lsr; 748 break; 749 case 2: 750 Shift = ARM_AM::asr; 751 break; 752 case 3: 753 Shift = ARM_AM::ror; 754 break; 755 } 756 757 Inst.addOperand(MCOperand::CreateImm(Shift)); 758 759 return true; 760 } 761 762 static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 763 uint64_t Address, const void *Decoder) { 764 // Empty register lists are not allowed. 765 if (CountPopulation_32(Val) == 0) return false; 766 for (unsigned i = 0; i < 16; ++i) { 767 if (Val & (1 << i)) { 768 if (!DecodeGPRRegisterClass(Inst, i, Address, Decoder)) return false; 769 } 770 } 771 772 return true; 773 } 774 775 static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 776 uint64_t Address, const void *Decoder) { 777 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 778 unsigned regs = Val & 0xFF; 779 780 if (!DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)) return false; 781 for (unsigned i = 0; i < (regs - 1); ++i) { 782 if (!DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false; 783 } 784 785 return true; 786 } 787 788 static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 789 uint64_t Address, const void *Decoder) { 790 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 791 unsigned regs = (Val & 0xFF) / 2; 792 793 if (!DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)) return false; 794 for (unsigned i = 0; i < (regs - 1); ++i) { 795 if (!DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false; 796 } 797 798 return true; 799 } 800 801 static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 802 uint64_t Address, const void *Decoder) { 803 // This operand encodes a mask of contiguous zeros between a specified MSB 804 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 805 // the mask of all bits LSB-and-lower, and then xor them to create 806 // the mask of that's all ones on [msb, lsb]. Finally we not it to 807 // create the final mask. 808 unsigned msb = fieldFromInstruction32(Val, 5, 5); 809 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 810 uint32_t msb_mask = (1 << (msb+1)) - 1; 811 uint32_t lsb_mask = (1 << lsb) - 1; 812 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 813 return true; 814 } 815 816 static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 817 uint64_t Address, const void *Decoder) { 818 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 819 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 820 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 821 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 822 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 823 unsigned U = fieldFromInstruction32(Insn, 23, 1); 824 825 switch (Inst.getOpcode()) { 826 case ARM::LDC_OFFSET: 827 case ARM::LDC_PRE: 828 case ARM::LDC_POST: 829 case ARM::LDC_OPTION: 830 case ARM::LDCL_OFFSET: 831 case ARM::LDCL_PRE: 832 case ARM::LDCL_POST: 833 case ARM::LDCL_OPTION: 834 case ARM::STC_OFFSET: 835 case ARM::STC_PRE: 836 case ARM::STC_POST: 837 case ARM::STC_OPTION: 838 case ARM::STCL_OFFSET: 839 case ARM::STCL_PRE: 840 case ARM::STCL_POST: 841 case ARM::STCL_OPTION: 842 if (coproc == 0xA || coproc == 0xB) 843 return false; 844 break; 845 default: 846 break; 847 } 848 849 Inst.addOperand(MCOperand::CreateImm(coproc)); 850 Inst.addOperand(MCOperand::CreateImm(CRd)); 851 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 852 switch (Inst.getOpcode()) { 853 case ARM::LDC_OPTION: 854 case ARM::LDCL_OPTION: 855 case ARM::LDC2_OPTION: 856 case ARM::LDC2L_OPTION: 857 case ARM::STC_OPTION: 858 case ARM::STCL_OPTION: 859 case ARM::STC2_OPTION: 860 case ARM::STC2L_OPTION: 861 case ARM::LDCL_POST: 862 case ARM::STCL_POST: 863 break; 864 default: 865 Inst.addOperand(MCOperand::CreateReg(0)); 866 break; 867 } 868 869 unsigned P = fieldFromInstruction32(Insn, 24, 1); 870 unsigned W = fieldFromInstruction32(Insn, 21, 1); 871 872 bool writeback = (P == 0) || (W == 1); 873 unsigned idx_mode = 0; 874 if (P && writeback) 875 idx_mode = ARMII::IndexModePre; 876 else if (!P && writeback) 877 idx_mode = ARMII::IndexModePost; 878 879 switch (Inst.getOpcode()) { 880 case ARM::LDCL_POST: 881 case ARM::STCL_POST: 882 imm |= U << 8; 883 case ARM::LDC_OPTION: 884 case ARM::LDCL_OPTION: 885 case ARM::LDC2_OPTION: 886 case ARM::LDC2L_OPTION: 887 case ARM::STC_OPTION: 888 case ARM::STCL_OPTION: 889 case ARM::STC2_OPTION: 890 case ARM::STC2L_OPTION: 891 Inst.addOperand(MCOperand::CreateImm(imm)); 892 break; 893 default: 894 if (U) 895 Inst.addOperand(MCOperand::CreateImm( 896 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 897 else 898 Inst.addOperand(MCOperand::CreateImm( 899 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 900 break; 901 } 902 903 switch (Inst.getOpcode()) { 904 case ARM::LDC_OFFSET: 905 case ARM::LDC_PRE: 906 case ARM::LDC_POST: 907 case ARM::LDC_OPTION: 908 case ARM::LDCL_OFFSET: 909 case ARM::LDCL_PRE: 910 case ARM::LDCL_POST: 911 case ARM::LDCL_OPTION: 912 case ARM::STC_OFFSET: 913 case ARM::STC_PRE: 914 case ARM::STC_POST: 915 case ARM::STC_OPTION: 916 case ARM::STCL_OFFSET: 917 case ARM::STCL_PRE: 918 case ARM::STCL_POST: 919 case ARM::STCL_OPTION: 920 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 921 break; 922 default: 923 break; 924 } 925 926 return true; 927 } 928 929 static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 930 uint64_t Address, const void *Decoder) { 931 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 932 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 933 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 934 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 935 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 936 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 937 unsigned P = fieldFromInstruction32(Insn, 24, 1); 938 unsigned W = fieldFromInstruction32(Insn, 21, 1); 939 940 // On stores, the writeback operand precedes Rt. 941 switch (Inst.getOpcode()) { 942 case ARM::STR_POST_IMM: 943 case ARM::STR_POST_REG: 944 case ARM::STRB_POST_IMM: 945 case ARM::STRB_POST_REG: 946 case ARM::STRTr: 947 case ARM::STRTi: 948 case ARM::STRBT_POST_REG: 949 case ARM::STRBT_POST_IMM: 950 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 951 break; 952 default: 953 break; 954 } 955 956 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 957 958 // On loads, the writeback operand comes after Rt. 959 switch (Inst.getOpcode()) { 960 case ARM::LDR_POST_IMM: 961 case ARM::LDR_POST_REG: 962 case ARM::LDRB_POST_IMM: 963 case ARM::LDRB_POST_REG: 964 case ARM::LDR_PRE: 965 case ARM::LDRBT_POST_REG: 966 case ARM::LDRBT_POST_IMM: 967 case ARM::LDRT_POST_REG: 968 case ARM::LDRT_POST_IMM: 969 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 970 return false; 971 break; 972 default: 973 break; 974 } 975 976 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 977 978 ARM_AM::AddrOpc Op = ARM_AM::add; 979 if (!fieldFromInstruction32(Insn, 23, 1)) 980 Op = ARM_AM::sub; 981 982 bool writeback = (P == 0) || (W == 1); 983 unsigned idx_mode = 0; 984 if (P && writeback) 985 idx_mode = ARMII::IndexModePre; 986 else if (!P && writeback) 987 idx_mode = ARMII::IndexModePost; 988 989 if (writeback && (Rn == 15 || Rn == Rt)) return false; // UNPREDICTABLE 990 991 if (reg) { 992 if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; 993 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 994 switch( fieldFromInstruction32(Insn, 5, 2)) { 995 case 0: 996 Opc = ARM_AM::lsl; 997 break; 998 case 1: 999 Opc = ARM_AM::lsr; 1000 break; 1001 case 2: 1002 Opc = ARM_AM::asr; 1003 break; 1004 case 3: 1005 Opc = ARM_AM::ror; 1006 break; 1007 default: 1008 return false; 1009 } 1010 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1011 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1012 1013 Inst.addOperand(MCOperand::CreateImm(imm)); 1014 } else { 1015 Inst.addOperand(MCOperand::CreateReg(0)); 1016 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1017 Inst.addOperand(MCOperand::CreateImm(tmp)); 1018 } 1019 1020 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1021 1022 return true; 1023 } 1024 1025 static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1026 uint64_t Address, const void *Decoder) { 1027 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1028 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1029 unsigned type = fieldFromInstruction32(Val, 5, 2); 1030 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1031 unsigned U = fieldFromInstruction32(Val, 12, 1); 1032 1033 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1034 switch (type) { 1035 case 0: 1036 ShOp = ARM_AM::lsl; 1037 break; 1038 case 1: 1039 ShOp = ARM_AM::lsr; 1040 break; 1041 case 2: 1042 ShOp = ARM_AM::asr; 1043 break; 1044 case 3: 1045 ShOp = ARM_AM::ror; 1046 break; 1047 } 1048 1049 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1050 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1051 unsigned shift; 1052 if (U) 1053 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1054 else 1055 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1056 Inst.addOperand(MCOperand::CreateImm(shift)); 1057 1058 return true; 1059 } 1060 1061 static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1062 uint64_t Address, const void *Decoder) { 1063 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1064 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1065 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1066 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1067 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1068 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1069 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1070 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1071 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1072 1073 bool writeback = (W == 1) | (P == 0); 1074 if (writeback) { // Writeback 1075 if (P) 1076 U |= ARMII::IndexModePre << 9; 1077 else 1078 U |= ARMII::IndexModePost << 9; 1079 1080 // On stores, the writeback operand precedes Rt. 1081 switch (Inst.getOpcode()) { 1082 case ARM::STRD: 1083 case ARM::STRD_PRE: 1084 case ARM::STRD_POST: 1085 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1086 return false; 1087 break; 1088 default: 1089 break; 1090 } 1091 } 1092 1093 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) 1094 return false; 1095 switch (Inst.getOpcode()) { 1096 case ARM::STRD: 1097 case ARM::STRD_PRE: 1098 case ARM::STRD_POST: 1099 case ARM::LDRD: 1100 case ARM::LDRD_PRE: 1101 case ARM::LDRD_POST: 1102 if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) 1103 return false; 1104 break; 1105 default: 1106 break; 1107 } 1108 1109 if (writeback) { 1110 // On loads, the writeback operand comes after Rt. 1111 switch (Inst.getOpcode()) { 1112 case ARM::LDRD: 1113 case ARM::LDRD_PRE: 1114 case ARM::LDRD_POST: 1115 case ARM::LDRHTr: 1116 case ARM::LDRSBTr: 1117 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1118 return false; 1119 break; 1120 default: 1121 break; 1122 } 1123 } 1124 1125 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1126 return false; 1127 1128 if (type) { 1129 Inst.addOperand(MCOperand::CreateReg(0)); 1130 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1131 } else { 1132 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1133 return false; 1134 Inst.addOperand(MCOperand::CreateImm(U)); 1135 } 1136 1137 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1138 1139 return true; 1140 } 1141 1142 static bool DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1143 uint64_t Address, const void *Decoder) { 1144 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1145 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1146 1147 switch (mode) { 1148 case 0: 1149 mode = ARM_AM::da; 1150 break; 1151 case 1: 1152 mode = ARM_AM::ia; 1153 break; 1154 case 2: 1155 mode = ARM_AM::db; 1156 break; 1157 case 3: 1158 mode = ARM_AM::ib; 1159 break; 1160 } 1161 1162 Inst.addOperand(MCOperand::CreateImm(mode)); 1163 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1164 1165 return true; 1166 } 1167 1168 static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1169 unsigned Insn, 1170 uint64_t Address, const void *Decoder) { 1171 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1172 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1173 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1174 1175 if (pred == 0xF) { 1176 switch (Inst.getOpcode()) { 1177 case ARM::STMDA: 1178 Inst.setOpcode(ARM::RFEDA); 1179 break; 1180 case ARM::STMDA_UPD: 1181 Inst.setOpcode(ARM::RFEDA_UPD); 1182 break; 1183 case ARM::STMDB: 1184 Inst.setOpcode(ARM::RFEDB); 1185 break; 1186 case ARM::STMDB_UPD: 1187 Inst.setOpcode(ARM::RFEDB_UPD); 1188 break; 1189 case ARM::STMIA: 1190 Inst.setOpcode(ARM::RFEIA); 1191 break; 1192 case ARM::STMIA_UPD: 1193 Inst.setOpcode(ARM::RFEIA_UPD); 1194 break; 1195 case ARM::STMIB: 1196 Inst.setOpcode(ARM::RFEIB); 1197 break; 1198 case ARM::STMIB_UPD: 1199 Inst.setOpcode(ARM::RFEIB_UPD); 1200 break; 1201 } 1202 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1203 } 1204 1205 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 1206 !DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || // Tied 1207 !DecodePredicateOperand(Inst, pred, Address, Decoder) || 1208 !DecodeRegListOperand(Inst, reglist, Address, Decoder)) 1209 return false; 1210 1211 return true; 1212 } 1213 1214 static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1215 uint64_t Address, const void *Decoder) { 1216 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1217 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1218 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1219 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1220 1221 // imod == '01' --> UNPREDICTABLE 1222 if (imod == 1) return false; 1223 1224 if (M && mode && imod && iflags) { 1225 Inst.setOpcode(ARM::CPS3p); 1226 Inst.addOperand(MCOperand::CreateImm(imod)); 1227 Inst.addOperand(MCOperand::CreateImm(iflags)); 1228 Inst.addOperand(MCOperand::CreateImm(mode)); 1229 return true; 1230 } else if (!mode && !M) { 1231 Inst.setOpcode(ARM::CPS2p); 1232 Inst.addOperand(MCOperand::CreateImm(imod)); 1233 Inst.addOperand(MCOperand::CreateImm(iflags)); 1234 return true; 1235 } else if (!imod && !iflags && M) { 1236 Inst.setOpcode(ARM::CPS1p); 1237 Inst.addOperand(MCOperand::CreateImm(mode)); 1238 return true; 1239 } 1240 1241 return false; 1242 } 1243 1244 static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1245 uint64_t Address, const void *Decoder) { 1246 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1247 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1248 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1249 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1250 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1251 1252 if (pred == 0xF) 1253 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1254 1255 if (!DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder) || 1256 !DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder) || 1257 !DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder) || 1258 !DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)) 1259 return false; 1260 1261 return true; 1262 } 1263 1264 static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1265 uint64_t Address, const void *Decoder) { 1266 unsigned add = fieldFromInstruction32(Val, 12, 1); 1267 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1268 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1269 1270 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1271 return false; 1272 1273 if (!add) imm *= -1; 1274 if (imm == 0 && !add) imm = INT32_MIN; 1275 Inst.addOperand(MCOperand::CreateImm(imm)); 1276 1277 return true; 1278 } 1279 1280 static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1281 uint64_t Address, const void *Decoder) { 1282 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1283 unsigned U = fieldFromInstruction32(Val, 8, 1); 1284 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1285 1286 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1287 return false; 1288 1289 if (U) 1290 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1291 else 1292 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1293 1294 return true; 1295 } 1296 1297 static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1298 uint64_t Address, const void *Decoder) { 1299 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1300 } 1301 1302 static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1303 uint64_t Address, const void *Decoder) { 1304 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1305 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1306 1307 if (pred == 0xF) { 1308 Inst.setOpcode(ARM::BLXi); 1309 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1310 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1311 return true; 1312 } 1313 1314 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1315 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1316 1317 return true; 1318 } 1319 1320 1321 static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1322 uint64_t Address, const void *Decoder) { 1323 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1324 return true; 1325 } 1326 1327 static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1328 uint64_t Address, const void *Decoder) { 1329 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1330 unsigned align = fieldFromInstruction32(Val, 4, 2); 1331 1332 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1333 return false; 1334 if (!align) 1335 Inst.addOperand(MCOperand::CreateImm(0)); 1336 else 1337 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1338 1339 return true; 1340 } 1341 1342 static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1343 uint64_t Address, const void *Decoder) { 1344 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1345 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1346 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1347 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1348 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1349 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1350 1351 // First output register 1352 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1353 1354 // Second output register 1355 switch (Inst.getOpcode()) { 1356 case ARM::VLD1q8: 1357 case ARM::VLD1q16: 1358 case ARM::VLD1q32: 1359 case ARM::VLD1q64: 1360 case ARM::VLD1q8_UPD: 1361 case ARM::VLD1q16_UPD: 1362 case ARM::VLD1q32_UPD: 1363 case ARM::VLD1q64_UPD: 1364 case ARM::VLD1d8T: 1365 case ARM::VLD1d16T: 1366 case ARM::VLD1d32T: 1367 case ARM::VLD1d64T: 1368 case ARM::VLD1d8T_UPD: 1369 case ARM::VLD1d16T_UPD: 1370 case ARM::VLD1d32T_UPD: 1371 case ARM::VLD1d64T_UPD: 1372 case ARM::VLD1d8Q: 1373 case ARM::VLD1d16Q: 1374 case ARM::VLD1d32Q: 1375 case ARM::VLD1d64Q: 1376 case ARM::VLD1d8Q_UPD: 1377 case ARM::VLD1d16Q_UPD: 1378 case ARM::VLD1d32Q_UPD: 1379 case ARM::VLD1d64Q_UPD: 1380 case ARM::VLD2d8: 1381 case ARM::VLD2d16: 1382 case ARM::VLD2d32: 1383 case ARM::VLD2d8_UPD: 1384 case ARM::VLD2d16_UPD: 1385 case ARM::VLD2d32_UPD: 1386 case ARM::VLD2q8: 1387 case ARM::VLD2q16: 1388 case ARM::VLD2q32: 1389 case ARM::VLD2q8_UPD: 1390 case ARM::VLD2q16_UPD: 1391 case ARM::VLD2q32_UPD: 1392 case ARM::VLD3d8: 1393 case ARM::VLD3d16: 1394 case ARM::VLD3d32: 1395 case ARM::VLD3d8_UPD: 1396 case ARM::VLD3d16_UPD: 1397 case ARM::VLD3d32_UPD: 1398 case ARM::VLD4d8: 1399 case ARM::VLD4d16: 1400 case ARM::VLD4d32: 1401 case ARM::VLD4d8_UPD: 1402 case ARM::VLD4d16_UPD: 1403 case ARM::VLD4d32_UPD: 1404 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1405 break; 1406 case ARM::VLD2b8: 1407 case ARM::VLD2b16: 1408 case ARM::VLD2b32: 1409 case ARM::VLD2b8_UPD: 1410 case ARM::VLD2b16_UPD: 1411 case ARM::VLD2b32_UPD: 1412 case ARM::VLD3q8: 1413 case ARM::VLD3q16: 1414 case ARM::VLD3q32: 1415 case ARM::VLD3q8_UPD: 1416 case ARM::VLD3q16_UPD: 1417 case ARM::VLD3q32_UPD: 1418 case ARM::VLD4q8: 1419 case ARM::VLD4q16: 1420 case ARM::VLD4q32: 1421 case ARM::VLD4q8_UPD: 1422 case ARM::VLD4q16_UPD: 1423 case ARM::VLD4q32_UPD: 1424 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1425 default: 1426 break; 1427 } 1428 1429 // Third output register 1430 switch(Inst.getOpcode()) { 1431 case ARM::VLD1d8T: 1432 case ARM::VLD1d16T: 1433 case ARM::VLD1d32T: 1434 case ARM::VLD1d64T: 1435 case ARM::VLD1d8T_UPD: 1436 case ARM::VLD1d16T_UPD: 1437 case ARM::VLD1d32T_UPD: 1438 case ARM::VLD1d64T_UPD: 1439 case ARM::VLD1d8Q: 1440 case ARM::VLD1d16Q: 1441 case ARM::VLD1d32Q: 1442 case ARM::VLD1d64Q: 1443 case ARM::VLD1d8Q_UPD: 1444 case ARM::VLD1d16Q_UPD: 1445 case ARM::VLD1d32Q_UPD: 1446 case ARM::VLD1d64Q_UPD: 1447 case ARM::VLD2q8: 1448 case ARM::VLD2q16: 1449 case ARM::VLD2q32: 1450 case ARM::VLD2q8_UPD: 1451 case ARM::VLD2q16_UPD: 1452 case ARM::VLD2q32_UPD: 1453 case ARM::VLD3d8: 1454 case ARM::VLD3d16: 1455 case ARM::VLD3d32: 1456 case ARM::VLD3d8_UPD: 1457 case ARM::VLD3d16_UPD: 1458 case ARM::VLD3d32_UPD: 1459 case ARM::VLD4d8: 1460 case ARM::VLD4d16: 1461 case ARM::VLD4d32: 1462 case ARM::VLD4d8_UPD: 1463 case ARM::VLD4d16_UPD: 1464 case ARM::VLD4d32_UPD: 1465 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1466 break; 1467 case ARM::VLD3q8: 1468 case ARM::VLD3q16: 1469 case ARM::VLD3q32: 1470 case ARM::VLD3q8_UPD: 1471 case ARM::VLD3q16_UPD: 1472 case ARM::VLD3q32_UPD: 1473 case ARM::VLD4q8: 1474 case ARM::VLD4q16: 1475 case ARM::VLD4q32: 1476 case ARM::VLD4q8_UPD: 1477 case ARM::VLD4q16_UPD: 1478 case ARM::VLD4q32_UPD: 1479 if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false; 1480 break; 1481 default: 1482 break; 1483 } 1484 1485 // Fourth output register 1486 switch (Inst.getOpcode()) { 1487 case ARM::VLD1d8Q: 1488 case ARM::VLD1d16Q: 1489 case ARM::VLD1d32Q: 1490 case ARM::VLD1d64Q: 1491 case ARM::VLD1d8Q_UPD: 1492 case ARM::VLD1d16Q_UPD: 1493 case ARM::VLD1d32Q_UPD: 1494 case ARM::VLD1d64Q_UPD: 1495 case ARM::VLD2q8: 1496 case ARM::VLD2q16: 1497 case ARM::VLD2q32: 1498 case ARM::VLD2q8_UPD: 1499 case ARM::VLD2q16_UPD: 1500 case ARM::VLD2q32_UPD: 1501 case ARM::VLD4d8: 1502 case ARM::VLD4d16: 1503 case ARM::VLD4d32: 1504 case ARM::VLD4d8_UPD: 1505 case ARM::VLD4d16_UPD: 1506 case ARM::VLD4d32_UPD: 1507 if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false; 1508 break; 1509 case ARM::VLD4q8: 1510 case ARM::VLD4q16: 1511 case ARM::VLD4q32: 1512 case ARM::VLD4q8_UPD: 1513 case ARM::VLD4q16_UPD: 1514 case ARM::VLD4q32_UPD: 1515 if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false; 1516 break; 1517 default: 1518 break; 1519 } 1520 1521 // Writeback operand 1522 switch (Inst.getOpcode()) { 1523 case ARM::VLD1d8_UPD: 1524 case ARM::VLD1d16_UPD: 1525 case ARM::VLD1d32_UPD: 1526 case ARM::VLD1d64_UPD: 1527 case ARM::VLD1q8_UPD: 1528 case ARM::VLD1q16_UPD: 1529 case ARM::VLD1q32_UPD: 1530 case ARM::VLD1q64_UPD: 1531 case ARM::VLD1d8T_UPD: 1532 case ARM::VLD1d16T_UPD: 1533 case ARM::VLD1d32T_UPD: 1534 case ARM::VLD1d64T_UPD: 1535 case ARM::VLD1d8Q_UPD: 1536 case ARM::VLD1d16Q_UPD: 1537 case ARM::VLD1d32Q_UPD: 1538 case ARM::VLD1d64Q_UPD: 1539 case ARM::VLD2d8_UPD: 1540 case ARM::VLD2d16_UPD: 1541 case ARM::VLD2d32_UPD: 1542 case ARM::VLD2q8_UPD: 1543 case ARM::VLD2q16_UPD: 1544 case ARM::VLD2q32_UPD: 1545 case ARM::VLD2b8_UPD: 1546 case ARM::VLD2b16_UPD: 1547 case ARM::VLD2b32_UPD: 1548 case ARM::VLD3d8_UPD: 1549 case ARM::VLD3d16_UPD: 1550 case ARM::VLD3d32_UPD: 1551 case ARM::VLD3q8_UPD: 1552 case ARM::VLD3q16_UPD: 1553 case ARM::VLD3q32_UPD: 1554 case ARM::VLD4d8_UPD: 1555 case ARM::VLD4d16_UPD: 1556 case ARM::VLD4d32_UPD: 1557 case ARM::VLD4q8_UPD: 1558 case ARM::VLD4q16_UPD: 1559 case ARM::VLD4q32_UPD: 1560 if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) return false; 1561 break; 1562 default: 1563 break; 1564 } 1565 1566 // AddrMode6 Base (register+alignment) 1567 if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false; 1568 1569 // AddrMode6 Offset (register) 1570 if (Rm == 0xD) 1571 Inst.addOperand(MCOperand::CreateReg(0)); 1572 else if (Rm != 0xF) { 1573 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1574 return false; 1575 } 1576 1577 return true; 1578 } 1579 1580 static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1581 uint64_t Address, const void *Decoder) { 1582 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1583 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1584 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1585 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1586 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1587 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1588 1589 // Writeback Operand 1590 switch (Inst.getOpcode()) { 1591 case ARM::VST1d8_UPD: 1592 case ARM::VST1d16_UPD: 1593 case ARM::VST1d32_UPD: 1594 case ARM::VST1d64_UPD: 1595 case ARM::VST1q8_UPD: 1596 case ARM::VST1q16_UPD: 1597 case ARM::VST1q32_UPD: 1598 case ARM::VST1q64_UPD: 1599 case ARM::VST1d8T_UPD: 1600 case ARM::VST1d16T_UPD: 1601 case ARM::VST1d32T_UPD: 1602 case ARM::VST1d64T_UPD: 1603 case ARM::VST1d8Q_UPD: 1604 case ARM::VST1d16Q_UPD: 1605 case ARM::VST1d32Q_UPD: 1606 case ARM::VST1d64Q_UPD: 1607 case ARM::VST2d8_UPD: 1608 case ARM::VST2d16_UPD: 1609 case ARM::VST2d32_UPD: 1610 case ARM::VST2q8_UPD: 1611 case ARM::VST2q16_UPD: 1612 case ARM::VST2q32_UPD: 1613 case ARM::VST2b8_UPD: 1614 case ARM::VST2b16_UPD: 1615 case ARM::VST2b32_UPD: 1616 case ARM::VST3d8_UPD: 1617 case ARM::VST3d16_UPD: 1618 case ARM::VST3d32_UPD: 1619 case ARM::VST3q8_UPD: 1620 case ARM::VST3q16_UPD: 1621 case ARM::VST3q32_UPD: 1622 case ARM::VST4d8_UPD: 1623 case ARM::VST4d16_UPD: 1624 case ARM::VST4d32_UPD: 1625 case ARM::VST4q8_UPD: 1626 case ARM::VST4q16_UPD: 1627 case ARM::VST4q32_UPD: 1628 if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) 1629 return false; 1630 break; 1631 default: 1632 break; 1633 } 1634 1635 // AddrMode6 Base (register+alignment) 1636 if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false; 1637 1638 // AddrMode6 Offset (register) 1639 if (Rm == 0xD) 1640 Inst.addOperand(MCOperand::CreateReg(0)); 1641 else if (Rm != 0xF) { 1642 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1643 } 1644 1645 // First input register 1646 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1647 1648 // Second input register 1649 switch (Inst.getOpcode()) { 1650 case ARM::VST1q8: 1651 case ARM::VST1q16: 1652 case ARM::VST1q32: 1653 case ARM::VST1q64: 1654 case ARM::VST1q8_UPD: 1655 case ARM::VST1q16_UPD: 1656 case ARM::VST1q32_UPD: 1657 case ARM::VST1q64_UPD: 1658 case ARM::VST1d8T: 1659 case ARM::VST1d16T: 1660 case ARM::VST1d32T: 1661 case ARM::VST1d64T: 1662 case ARM::VST1d8T_UPD: 1663 case ARM::VST1d16T_UPD: 1664 case ARM::VST1d32T_UPD: 1665 case ARM::VST1d64T_UPD: 1666 case ARM::VST1d8Q: 1667 case ARM::VST1d16Q: 1668 case ARM::VST1d32Q: 1669 case ARM::VST1d64Q: 1670 case ARM::VST1d8Q_UPD: 1671 case ARM::VST1d16Q_UPD: 1672 case ARM::VST1d32Q_UPD: 1673 case ARM::VST1d64Q_UPD: 1674 case ARM::VST2d8: 1675 case ARM::VST2d16: 1676 case ARM::VST2d32: 1677 case ARM::VST2d8_UPD: 1678 case ARM::VST2d16_UPD: 1679 case ARM::VST2d32_UPD: 1680 case ARM::VST2q8: 1681 case ARM::VST2q16: 1682 case ARM::VST2q32: 1683 case ARM::VST2q8_UPD: 1684 case ARM::VST2q16_UPD: 1685 case ARM::VST2q32_UPD: 1686 case ARM::VST3d8: 1687 case ARM::VST3d16: 1688 case ARM::VST3d32: 1689 case ARM::VST3d8_UPD: 1690 case ARM::VST3d16_UPD: 1691 case ARM::VST3d32_UPD: 1692 case ARM::VST4d8: 1693 case ARM::VST4d16: 1694 case ARM::VST4d32: 1695 case ARM::VST4d8_UPD: 1696 case ARM::VST4d16_UPD: 1697 case ARM::VST4d32_UPD: 1698 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1699 break; 1700 case ARM::VST2b8: 1701 case ARM::VST2b16: 1702 case ARM::VST2b32: 1703 case ARM::VST2b8_UPD: 1704 case ARM::VST2b16_UPD: 1705 case ARM::VST2b32_UPD: 1706 case ARM::VST3q8: 1707 case ARM::VST3q16: 1708 case ARM::VST3q32: 1709 case ARM::VST3q8_UPD: 1710 case ARM::VST3q16_UPD: 1711 case ARM::VST3q32_UPD: 1712 case ARM::VST4q8: 1713 case ARM::VST4q16: 1714 case ARM::VST4q32: 1715 case ARM::VST4q8_UPD: 1716 case ARM::VST4q16_UPD: 1717 case ARM::VST4q32_UPD: 1718 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1719 break; 1720 default: 1721 break; 1722 } 1723 1724 // Third input register 1725 switch (Inst.getOpcode()) { 1726 case ARM::VST1d8T: 1727 case ARM::VST1d16T: 1728 case ARM::VST1d32T: 1729 case ARM::VST1d64T: 1730 case ARM::VST1d8T_UPD: 1731 case ARM::VST1d16T_UPD: 1732 case ARM::VST1d32T_UPD: 1733 case ARM::VST1d64T_UPD: 1734 case ARM::VST1d8Q: 1735 case ARM::VST1d16Q: 1736 case ARM::VST1d32Q: 1737 case ARM::VST1d64Q: 1738 case ARM::VST1d8Q_UPD: 1739 case ARM::VST1d16Q_UPD: 1740 case ARM::VST1d32Q_UPD: 1741 case ARM::VST1d64Q_UPD: 1742 case ARM::VST2q8: 1743 case ARM::VST2q16: 1744 case ARM::VST2q32: 1745 case ARM::VST2q8_UPD: 1746 case ARM::VST2q16_UPD: 1747 case ARM::VST2q32_UPD: 1748 case ARM::VST3d8: 1749 case ARM::VST3d16: 1750 case ARM::VST3d32: 1751 case ARM::VST3d8_UPD: 1752 case ARM::VST3d16_UPD: 1753 case ARM::VST3d32_UPD: 1754 case ARM::VST4d8: 1755 case ARM::VST4d16: 1756 case ARM::VST4d32: 1757 case ARM::VST4d8_UPD: 1758 case ARM::VST4d16_UPD: 1759 case ARM::VST4d32_UPD: 1760 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1761 break; 1762 case ARM::VST3q8: 1763 case ARM::VST3q16: 1764 case ARM::VST3q32: 1765 case ARM::VST3q8_UPD: 1766 case ARM::VST3q16_UPD: 1767 case ARM::VST3q32_UPD: 1768 case ARM::VST4q8: 1769 case ARM::VST4q16: 1770 case ARM::VST4q32: 1771 case ARM::VST4q8_UPD: 1772 case ARM::VST4q16_UPD: 1773 case ARM::VST4q32_UPD: 1774 if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false; 1775 break; 1776 default: 1777 break; 1778 } 1779 1780 // Fourth input register 1781 switch (Inst.getOpcode()) { 1782 case ARM::VST1d8Q: 1783 case ARM::VST1d16Q: 1784 case ARM::VST1d32Q: 1785 case ARM::VST1d64Q: 1786 case ARM::VST1d8Q_UPD: 1787 case ARM::VST1d16Q_UPD: 1788 case ARM::VST1d32Q_UPD: 1789 case ARM::VST1d64Q_UPD: 1790 case ARM::VST2q8: 1791 case ARM::VST2q16: 1792 case ARM::VST2q32: 1793 case ARM::VST2q8_UPD: 1794 case ARM::VST2q16_UPD: 1795 case ARM::VST2q32_UPD: 1796 case ARM::VST4d8: 1797 case ARM::VST4d16: 1798 case ARM::VST4d32: 1799 case ARM::VST4d8_UPD: 1800 case ARM::VST4d16_UPD: 1801 case ARM::VST4d32_UPD: 1802 if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false; 1803 break; 1804 case ARM::VST4q8: 1805 case ARM::VST4q16: 1806 case ARM::VST4q32: 1807 case ARM::VST4q8_UPD: 1808 case ARM::VST4q16_UPD: 1809 case ARM::VST4q32_UPD: 1810 if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false; 1811 break; 1812 default: 1813 break; 1814 } 1815 1816 return true; 1817 } 1818 1819 static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1820 uint64_t Address, const void *Decoder) { 1821 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1822 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1823 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1824 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1825 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1826 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1827 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 1828 1829 align *= (1 << size); 1830 1831 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1832 if (regs == 2) { 1833 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1834 } 1835 if (Rm == 0xD) { 1836 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1837 } 1838 1839 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1840 Inst.addOperand(MCOperand::CreateImm(align)); 1841 1842 if (Rm == 0xD) 1843 Inst.addOperand(MCOperand::CreateReg(0)); 1844 else if (Rm != 0xF) { 1845 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1846 } 1847 1848 return true; 1849 } 1850 1851 static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1852 uint64_t Address, const void *Decoder) { 1853 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1854 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1855 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1856 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1857 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1858 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 1859 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1860 align *= 2*size; 1861 1862 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1863 if (!DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)) return false; 1864 if (Rm == 0xD) { 1865 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1866 } 1867 1868 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1869 Inst.addOperand(MCOperand::CreateImm(align)); 1870 1871 if (Rm == 0xD) 1872 Inst.addOperand(MCOperand::CreateReg(0)); 1873 else if (Rm != 0xF) { 1874 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1875 } 1876 1877 return true; 1878 } 1879 1880 static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1881 uint64_t Address, const void *Decoder) { 1882 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1883 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1884 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1885 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1886 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1887 1888 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) || 1889 !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) || 1890 !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)) 1891 return false; 1892 if (Rm == 0xD) { 1893 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1894 } 1895 1896 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1897 Inst.addOperand(MCOperand::CreateImm(0)); 1898 1899 if (Rm == 0xD) 1900 Inst.addOperand(MCOperand::CreateReg(0)); 1901 else if (Rm != 0xF) { 1902 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1903 } 1904 1905 return true; 1906 } 1907 1908 static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1909 uint64_t Address, const void *Decoder) { 1910 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1911 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1912 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1913 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1914 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1915 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1916 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1917 1918 if (size == 0x3) { 1919 size = 4; 1920 align = 16; 1921 } else { 1922 if (size == 2) { 1923 size = 1 << size; 1924 align *= 8; 1925 } else { 1926 size = 1 << size; 1927 align *= 4*size; 1928 } 1929 } 1930 1931 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) || 1932 !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) || 1933 !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder) || 1934 !DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)) 1935 return false; 1936 if (Rm == 0xD) { 1937 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1938 } 1939 1940 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1941 Inst.addOperand(MCOperand::CreateImm(align)); 1942 1943 if (Rm == 0xD) 1944 Inst.addOperand(MCOperand::CreateReg(0)); 1945 else if (Rm != 0xF) { 1946 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1947 } 1948 1949 return true; 1950 } 1951 1952 static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1953 uint64_t Address, const void *Decoder) { 1954 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1955 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1956 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 1957 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 1958 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 1959 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 1960 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 1961 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 1962 1963 if (Q) { 1964 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1965 } else { 1966 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1967 } 1968 1969 Inst.addOperand(MCOperand::CreateImm(imm)); 1970 1971 switch (Inst.getOpcode()) { 1972 case ARM::VORRiv4i16: 1973 case ARM::VORRiv2i32: 1974 case ARM::VBICiv4i16: 1975 case ARM::VBICiv2i32: 1976 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1977 break; 1978 case ARM::VORRiv8i16: 1979 case ARM::VORRiv4i32: 1980 case ARM::VBICiv8i16: 1981 case ARM::VBICiv4i32: 1982 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1983 break; 1984 default: 1985 break; 1986 } 1987 1988 return true; 1989 } 1990 1991 static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 1992 uint64_t Address, const void *Decoder) { 1993 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1994 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1995 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1996 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 1997 unsigned size = fieldFromInstruction32(Insn, 18, 2); 1998 1999 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2000 if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2001 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2002 2003 return true; 2004 } 2005 2006 static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2007 uint64_t Address, const void *Decoder) { 2008 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2009 return true; 2010 } 2011 2012 static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2013 uint64_t Address, const void *Decoder) { 2014 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2015 return true; 2016 } 2017 2018 static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2019 uint64_t Address, const void *Decoder) { 2020 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2021 return true; 2022 } 2023 2024 static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2025 uint64_t Address, const void *Decoder) { 2026 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2027 return true; 2028 } 2029 2030 static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2031 uint64_t Address, const void *Decoder) { 2032 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2033 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2034 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2035 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2036 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2037 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2038 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2039 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2040 2041 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2042 if (op) { 2043 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; // Writeback 2044 } 2045 2046 for (unsigned i = 0; i < length; ++i) { 2047 if (!DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)) return false; 2048 } 2049 2050 if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2051 2052 return true; 2053 } 2054 2055 static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 2056 uint64_t Address, const void *Decoder) { 2057 // The immediate needs to be a fully instantiated float. However, the 2058 // auto-generated decoder is only able to fill in some of the bits 2059 // necessary. For instance, the 'b' bit is replicated multiple times, 2060 // and is even present in inverted form in one bit. We do a little 2061 // binary parsing here to fill in those missing bits, and then 2062 // reinterpret it all as a float. 2063 union { 2064 uint32_t integer; 2065 float fp; 2066 } fp_conv; 2067 2068 fp_conv.integer = Val; 2069 uint32_t b = fieldFromInstruction32(Val, 25, 1); 2070 fp_conv.integer |= b << 26; 2071 fp_conv.integer |= b << 27; 2072 fp_conv.integer |= b << 28; 2073 fp_conv.integer |= b << 29; 2074 fp_conv.integer |= (~b & 0x1) << 30; 2075 2076 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 2077 return true; 2078 } 2079 2080 static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2081 uint64_t Address, const void *Decoder) { 2082 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2083 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2084 2085 if (!DecodetGPRRegisterClass(Inst, dst, Address, Decoder)) return false; 2086 2087 if (Inst.getOpcode() == ARM::tADR) 2088 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2089 else if (Inst.getOpcode() == ARM::tADDrSPi) 2090 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2091 else 2092 return false; 2093 2094 Inst.addOperand(MCOperand::CreateImm(imm)); 2095 return true; 2096 } 2097 2098 static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2099 uint64_t Address, const void *Decoder) { 2100 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2101 return true; 2102 } 2103 2104 static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2105 uint64_t Address, const void *Decoder) { 2106 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2107 return true; 2108 } 2109 2110 static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2111 uint64_t Address, const void *Decoder) { 2112 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2113 return true; 2114 } 2115 2116 static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2117 uint64_t Address, const void *Decoder) { 2118 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2119 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2120 2121 if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder) || 2122 !DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)) 2123 return false; 2124 2125 return true; 2126 } 2127 2128 static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2129 uint64_t Address, const void *Decoder) { 2130 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2131 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2132 2133 if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2134 Inst.addOperand(MCOperand::CreateImm(imm)); 2135 2136 return true; 2137 } 2138 2139 static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2140 uint64_t Address, const void *Decoder) { 2141 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2142 2143 return true; 2144 } 2145 2146 static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2147 uint64_t Address, const void *Decoder) { 2148 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2149 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2150 2151 return true; 2152 } 2153 2154 static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2155 uint64_t Address, const void *Decoder) { 2156 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2157 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2158 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2159 2160 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2161 !DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)) 2162 return false; 2163 Inst.addOperand(MCOperand::CreateImm(imm)); 2164 2165 return true; 2166 } 2167 2168 static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2169 uint64_t Address, const void *Decoder) { 2170 if (Inst.getOpcode() != ARM::t2PLDs) { 2171 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2172 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2173 } 2174 2175 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2176 if (Rn == 0xF) { 2177 switch (Inst.getOpcode()) { 2178 case ARM::t2LDRBs: 2179 Inst.setOpcode(ARM::t2LDRBpci); 2180 break; 2181 case ARM::t2LDRHs: 2182 Inst.setOpcode(ARM::t2LDRHpci); 2183 break; 2184 case ARM::t2LDRSHs: 2185 Inst.setOpcode(ARM::t2LDRSHpci); 2186 break; 2187 case ARM::t2LDRSBs: 2188 Inst.setOpcode(ARM::t2LDRSBpci); 2189 break; 2190 case ARM::t2PLDs: 2191 Inst.setOpcode(ARM::t2PLDi12); 2192 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2193 break; 2194 default: 2195 return false; 2196 } 2197 2198 int imm = fieldFromInstruction32(Insn, 0, 12); 2199 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2200 Inst.addOperand(MCOperand::CreateImm(imm)); 2201 2202 return true; 2203 } 2204 2205 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2206 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2207 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2208 DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder); 2209 2210 return true; 2211 } 2212 2213 static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2214 uint64_t Address, const void *Decoder) { 2215 int imm = Val & 0xFF; 2216 if (!(Val & 0x100)) imm *= -1; 2217 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2218 2219 return true; 2220 } 2221 2222 static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2223 uint64_t Address, const void *Decoder) { 2224 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2225 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2226 2227 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2228 !DecodeT2Imm8S4(Inst, imm, Address, Decoder)) 2229 return false; 2230 2231 return true; 2232 } 2233 2234 static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2235 uint64_t Address, const void *Decoder) { 2236 int imm = Val & 0xFF; 2237 if (!(Val & 0x100)) imm *= -1; 2238 Inst.addOperand(MCOperand::CreateImm(imm)); 2239 2240 return true; 2241 } 2242 2243 2244 static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2245 uint64_t Address, const void *Decoder) { 2246 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2247 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2248 2249 // Some instructions always use an additive offset. 2250 switch (Inst.getOpcode()) { 2251 case ARM::t2LDRT: 2252 case ARM::t2LDRBT: 2253 case ARM::t2LDRHT: 2254 case ARM::t2LDRSBT: 2255 case ARM::t2LDRSHT: 2256 imm |= 0x100; 2257 break; 2258 default: 2259 break; 2260 } 2261 2262 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2263 !DecodeT2Imm8(Inst, imm, Address, Decoder)) 2264 return false; 2265 2266 return true; 2267 } 2268 2269 2270 static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2271 uint64_t Address, const void *Decoder) { 2272 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2273 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2274 2275 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2276 Inst.addOperand(MCOperand::CreateImm(imm)); 2277 2278 return true; 2279 } 2280 2281 2282 static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2283 uint64_t Address, const void *Decoder) { 2284 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2285 2286 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2287 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2288 Inst.addOperand(MCOperand::CreateImm(imm)); 2289 2290 return true; 2291 } 2292 2293 static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2294 uint64_t Address, const void *Decoder) { 2295 if (Inst.getOpcode() == ARM::tADDrSP) { 2296 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2297 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2298 2299 if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false; 2300 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2301 if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false; 2302 } else if (Inst.getOpcode() == ARM::tADDspr) { 2303 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2304 2305 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2306 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2307 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2308 } 2309 2310 return true; 2311 } 2312 2313 static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2314 uint64_t Address, const void *Decoder) { 2315 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2316 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2317 2318 Inst.addOperand(MCOperand::CreateImm(imod)); 2319 Inst.addOperand(MCOperand::CreateImm(flags)); 2320 2321 return true; 2322 } 2323 2324 static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2325 uint64_t Address, const void *Decoder) { 2326 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2327 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2328 2329 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2330 Inst.addOperand(MCOperand::CreateImm(add)); 2331 2332 return true; 2333 } 2334 2335 static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2336 uint64_t Address, const void *Decoder) { 2337 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2338 return true; 2339 } 2340 2341 static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2342 uint64_t Address, const void *Decoder) { 2343 if (Val == 0xA || Val == 0xB) 2344 return false; 2345 2346 Inst.addOperand(MCOperand::CreateImm(Val)); 2347 return true; 2348 } 2349 2350 static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, 2351 uint64_t Address, const void *Decoder) { 2352 if (Val == 0) 2353 Inst.addOperand(MCOperand::CreateImm(32)); 2354 else 2355 Inst.addOperand(MCOperand::CreateImm(Val)); 2356 return true; 2357 } 2358 2359 static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2360 uint64_t Address, const void *Decoder) { 2361 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2362 if (pred == 0xE || pred == 0xF) { 2363 unsigned opc = fieldFromInstruction32(Insn, 4, 2); 2364 switch (opc) { 2365 default: 2366 return false; 2367 case 0: 2368 Inst.setOpcode(ARM::t2DSB); 2369 break; 2370 case 1: 2371 Inst.setOpcode(ARM::t2DMB); 2372 break; 2373 case 2: 2374 Inst.setOpcode(ARM::t2ISB); 2375 return true; 2376 } 2377 2378 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2379 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2380 } 2381 2382 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2383 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2384 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2385 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2386 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2387 2388 if (!DecodeT2BROperand(Inst, brtarget, Address, Decoder) || 2389 !DecodePredicateOperand(Inst, pred, Address, Decoder)) 2390 return false; 2391 2392 return true; 2393 } 2394 2395 // Decode a shifted immediate operand. These basically consist 2396 // of an 8-bit value, and a 4-bit directive that specifies either 2397 // a splat operation or a rotation. 2398 static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2399 uint64_t Address, const void *Decoder) { 2400 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2401 if (ctrl == 0) { 2402 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2403 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2404 switch (byte) { 2405 case 0: 2406 Inst.addOperand(MCOperand::CreateImm(imm)); 2407 break; 2408 case 1: 2409 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2410 break; 2411 case 2: 2412 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2413 break; 2414 case 3: 2415 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2416 (imm << 8) | imm)); 2417 break; 2418 } 2419 } else { 2420 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2421 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2422 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2423 Inst.addOperand(MCOperand::CreateImm(imm)); 2424 } 2425 2426 return true; 2427 } 2428 2429 static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 2430 uint64_t Address, const void *Decoder){ 2431 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 2432 return true; 2433 } 2434 2435 static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 2436 uint64_t Address, const void *Decoder){ 2437 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2438 return true; 2439 } 2440 2441 static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Val, 2442 uint64_t Address, const void *Decoder) { 2443 bool isImm = fieldFromInstruction32(Val, 9, 1); 2444 bool isAdd = fieldFromInstruction32(Val, 8, 1); 2445 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2446 2447 if (!isImm) { 2448 if (!DecodeGPRRegisterClass(Inst, imm, Address, Decoder)) return false; 2449 Inst.addOperand(MCOperand::CreateImm(!isAdd << 8)); 2450 } else { 2451 Inst.addOperand(MCOperand::CreateReg(0)); 2452 Inst.addOperand(MCOperand::CreateImm(imm | (!isAdd << 8))); 2453 } 2454 2455 return true; 2456 } 2457 2458 static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 2459 uint64_t Address, const void *Decoder) { 2460 switch (Val) { 2461 default: 2462 return false; 2463 case 0xF: // SY 2464 case 0xE: // ST 2465 case 0xB: // ISH 2466 case 0xA: // ISHST 2467 case 0x7: // NSH 2468 case 0x6: // NSHST 2469 case 0x3: // OSH 2470 case 0x2: // OSHST 2471 break; 2472 } 2473 2474 Inst.addOperand(MCOperand::CreateImm(Val)); 2475 return true; 2476 } 2477 2478 static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 2479 uint64_t Address, const void *Decoder) { 2480 if (!Val) return false; 2481 Inst.addOperand(MCOperand::CreateImm(Val)); 2482 return true; 2483 } 2484