1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARMDisassembler.h" 13 #include "ARM.h" 14 #include "ARMRegisterInfo.h" 15 #include "MCTargetDesc/ARMAddressingModes.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/Target/TargetRegistry.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/raw_ostream.h" 26 27 // Forward declare these because the autogenerated code will reference them. 28 // Definitions are further down. 29 static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 30 uint64_t Address, const void *Decoder); 31 static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 32 uint64_t Address, const void *Decoder); 33 static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 34 uint64_t Address, const void *Decoder); 35 static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 36 uint64_t Address, const void *Decoder); 37 static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 38 uint64_t Address, const void *Decoder); 39 static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 40 uint64_t Address, const void *Decoder); 41 static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 42 uint64_t Address, const void *Decoder); 43 static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 44 uint64_t Address, const void *Decoder); 45 static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 46 uint64_t Address, const void *Decoder); 47 static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 48 uint64_t Address, const void *Decoder); 49 50 static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 51 uint64_t Address, const void *Decoder); 52 static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 53 uint64_t Address, const void *Decoder); 54 static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 55 uint64_t Address, const void *Decoder); 56 static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 57 uint64_t Address, const void *Decoder); 58 static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 59 uint64_t Address, const void *Decoder); 60 static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 61 uint64_t Address, const void *Decoder); 62 static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 63 uint64_t Address, const void *Decoder); 64 65 static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 66 uint64_t Address, const void *Decoder); 67 static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 68 uint64_t Address, const void *Decoder); 69 static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 70 uint64_t Address, const void *Decoder); 71 static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 72 uint64_t Address, const void *Decoder); 73 static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 74 uint64_t Address, const void *Decoder); 75 static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 76 uint64_t Address, const void *Decoder); 77 static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 78 uint64_t Address, const void *Decoder); 79 80 static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 81 unsigned Insn, 82 uint64_t Adddress, 83 const void *Decoder); 84 static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 85 uint64_t Address, const void *Decoder); 86 static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 87 uint64_t Address, const void *Decoder); 88 static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 89 uint64_t Address, const void *Decoder); 90 static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 91 uint64_t Address, const void *Decoder); 92 static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 93 uint64_t Address, const void *Decoder); 94 static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 95 uint64_t Address, const void *Decoder); 96 static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 97 uint64_t Address, const void *Decoder); 98 static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 99 uint64_t Address, const void *Decoder); 100 static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 101 uint64_t Address, const void *Decoder); 102 static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 103 uint64_t Address, const void *Decoder); 104 static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 105 uint64_t Address, const void *Decoder); 106 static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 107 uint64_t Address, const void *Decoder); 108 static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 109 uint64_t Address, const void *Decoder); 110 static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 111 uint64_t Address, const void *Decoder); 112 static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Val, 113 uint64_t Address, const void *Decoder); 114 static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 115 uint64_t Address, const void *Decoder); 116 static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 117 uint64_t Address, const void *Decoder); 118 static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 119 uint64_t Address, const void *Decoder); 120 static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 121 uint64_t Address, const void *Decoder); 122 static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 123 uint64_t Address, const void *Decoder); 124 static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 125 uint64_t Address, const void *Decoder); 126 static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 127 uint64_t Address, const void *Decoder); 128 static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 129 uint64_t Address, const void *Decoder); 130 static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 131 uint64_t Address, const void *Decoder); 132 static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Insn, 133 uint64_t Address, const void *Decoder); 134 static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 135 uint64_t Address, const void *Decoder); 136 137 138 static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 139 uint64_t Address, const void *Decoder); 140 static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 141 uint64_t Address, const void *Decoder); 142 static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 143 uint64_t Address, const void *Decoder); 144 static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 145 uint64_t Address, const void *Decoder); 146 static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 147 uint64_t Address, const void *Decoder); 148 static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 149 uint64_t Address, const void *Decoder); 150 static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 151 uint64_t Address, const void *Decoder); 152 static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 153 uint64_t Address, const void *Decoder); 154 static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 155 uint64_t Address, const void *Decoder); 156 static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 157 uint64_t Address, const void *Decoder); 158 static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 159 uint64_t Address, const void *Decoder); 160 static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 161 uint64_t Address, const void *Decoder); 162 static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 163 uint64_t Address, const void *Decoder); 164 static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 165 uint64_t Address, const void *Decoder); 166 static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 167 uint64_t Address, const void *Decoder); 168 static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 169 uint64_t Address, const void *Decoder); 170 static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 171 uint64_t Address, const void *Decoder); 172 static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 173 uint64_t Address, const void *Decoder); 174 static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 175 uint64_t Address, const void *Decoder); 176 static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, 177 uint64_t Address, const void *Decoder); 178 static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 179 uint64_t Address, const void *Decoder); 180 static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 181 uint64_t Address, const void *Decoder); 182 static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 183 uint64_t Address, const void *Decoder); 184 static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 185 uint64_t Address, const void *Decoder); 186 187 #include "ARMGenDisassemblerTables.inc" 188 #include "ARMGenInstrInfo.inc" 189 #include "ARMGenEDInfo.inc" 190 191 using namespace llvm; 192 193 static MCDisassembler *createARMDisassembler(const Target &T) { 194 return new ARMDisassembler; 195 } 196 197 static MCDisassembler *createThumbDisassembler(const Target &T) { 198 return new ThumbDisassembler; 199 } 200 201 EDInstInfo *ARMDisassembler::getEDInfo() const { 202 return instInfoARM; 203 } 204 205 EDInstInfo *ThumbDisassembler::getEDInfo() const { 206 return instInfoARM; 207 } 208 209 210 bool ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 211 const MemoryObject &Region, 212 uint64_t Address,raw_ostream &os) const { 213 uint8_t bytes[4]; 214 215 // We want to read exactly 4 bytes of data. 216 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 217 return false; 218 219 // Encoded as a small-endian 32-bit word in the stream. 220 uint32_t insn = (bytes[3] << 24) | 221 (bytes[2] << 16) | 222 (bytes[1] << 8) | 223 (bytes[0] << 0); 224 225 // Calling the auto-generated decoder function. 226 bool result = decodeARMInstruction32(MI, insn, Address, this); 227 if (result) { 228 Size = 4; 229 return true; 230 } 231 232 // Instructions that are shared between ARM and Thumb modes. 233 // FIXME: This shouldn't really exist. It's an artifact of the 234 // fact that we fail to encode a few instructions properly for Thumb. 235 MI.clear(); 236 result = decodeCommonInstruction32(MI, insn, Address, this); 237 if (result) { 238 Size = 4; 239 return true; 240 } 241 242 // VFP and NEON instructions, similarly, are shared between ARM 243 // and Thumb modes. 244 MI.clear(); 245 result = decodeVFPInstruction32(MI, insn, Address, this); 246 if (result) { 247 Size = 4; 248 return true; 249 } 250 251 MI.clear(); 252 result = decodeNEONDataInstruction32(MI, insn, Address, this); 253 if (result) { 254 Size = 4; 255 // Add a fake predicate operand, because we share these instruction 256 // definitions with Thumb2 where these instructions are predicable. 257 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 258 return true; 259 } 260 261 MI.clear(); 262 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this); 263 if (result) { 264 Size = 4; 265 // Add a fake predicate operand, because we share these instruction 266 // definitions with Thumb2 where these instructions are predicable. 267 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 268 return true; 269 } 270 271 MI.clear(); 272 result = decodeNEONDupInstruction32(MI, insn, Address, this); 273 if (result) { 274 Size = 4; 275 // Add a fake predicate operand, because we share these instruction 276 // definitions with Thumb2 where these instructions are predicable. 277 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 278 return true; 279 } 280 281 MI.clear(); 282 283 return false; 284 } 285 286 namespace llvm { 287 extern MCInstrDesc ARMInsts[]; 288 } 289 290 // Thumb1 instructions don't have explicit S bits. Rather, they 291 // implicitly set CPSR. Since it's not represented in the encoding, the 292 // auto-generated decoder won't inject the CPSR operand. We need to fix 293 // that as a post-pass. 294 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 295 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 296 MCInst::iterator I = MI.begin(); 297 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 298 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 299 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 300 return; 301 } 302 } 303 304 if (OpInfo[MI.size()].isOptionalDef() && 305 OpInfo[MI.size()].RegClass == ARM::CCRRegClassID) 306 MI.insert(MI.end(), MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 307 } 308 309 // Most Thumb instructions don't have explicit predicates in the 310 // encoding, but rather get their predicates from IT context. We need 311 // to fix up the predicate operands using this context information as a 312 // post-pass. 313 void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 314 // A few instructions actually have predicates encoded in them. Don't 315 // try to overwrite it if we're seeing one of those. 316 switch (MI.getOpcode()) { 317 case ARM::tBcc: 318 case ARM::t2Bcc: 319 return; 320 default: 321 break; 322 } 323 324 // If we're in an IT block, base the predicate on that. Otherwise, 325 // assume a predicate of AL. 326 unsigned CC; 327 if (!ITBlock.empty()) { 328 CC = ITBlock.back(); 329 ITBlock.pop_back(); 330 } else 331 CC = ARMCC::AL; 332 333 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 334 MCInst::iterator I = MI.begin(); 335 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 336 if (OpInfo[i].isPredicate()) { 337 I = MI.insert(I, MCOperand::CreateImm(CC)); 338 ++I; 339 if (CC == ARMCC::AL) 340 MI.insert(I, MCOperand::CreateReg(0)); 341 else 342 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 343 return; 344 } 345 } 346 347 MI.insert(MI.end(), MCOperand::CreateImm(CC)); 348 if (CC == ARMCC::AL) 349 MI.insert(MI.end(), MCOperand::CreateReg(0)); 350 else 351 MI.insert(MI.end(), MCOperand::CreateReg(ARM::CPSR)); 352 } 353 354 // Thumb VFP instructions are a special case. Because we share their 355 // encodings between ARM and Thumb modes, and they are predicable in ARM 356 // mode, the auto-generated decoder will give them an (incorrect) 357 // predicate operand. We need to rewrite these operands based on the IT 358 // context as a post-pass. 359 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 360 unsigned CC; 361 if (!ITBlock.empty()) { 362 CC = ITBlock.back(); 363 ITBlock.pop_back(); 364 } else 365 CC = ARMCC::AL; 366 367 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 368 MCInst::iterator I = MI.begin(); 369 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 370 if (OpInfo[i].isPredicate() ) { 371 I->setImm(CC); 372 ++I; 373 if (CC == ARMCC::AL) 374 I->setReg(0); 375 else 376 I->setReg(ARM::CPSR); 377 return; 378 } 379 } 380 } 381 382 383 bool ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 384 const MemoryObject &Region, 385 uint64_t Address,raw_ostream &os) const { 386 uint8_t bytes[4]; 387 388 // We want to read exactly 2 bytes of data. 389 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) 390 return false; 391 392 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 393 bool result = decodeThumbInstruction16(MI, insn16, Address, this); 394 if (result) { 395 Size = 2; 396 bool InITBlock = !ITBlock.empty(); 397 AddThumbPredicate(MI); 398 AddThumb1SBit(MI, InITBlock); 399 return true; 400 } 401 402 MI.clear(); 403 result = decodeThumb2Instruction16(MI, insn16, Address, this); 404 if (result) { 405 Size = 2; 406 AddThumbPredicate(MI); 407 408 // If we find an IT instruction, we need to parse its condition 409 // code and mask operands so that we can apply them correctly 410 // to the subsequent instructions. 411 if (MI.getOpcode() == ARM::t2IT) { 412 unsigned firstcond = MI.getOperand(0).getImm(); 413 uint32_t mask = MI.getOperand(1).getImm(); 414 unsigned zeros = CountTrailingZeros_32(mask); 415 mask >>= zeros+1; 416 417 for (unsigned i = 0; i < 4 - (zeros+1); ++i) { 418 if (firstcond ^ (mask & 1)) 419 ITBlock.push_back(firstcond ^ 1); 420 else 421 ITBlock.push_back(firstcond); 422 mask >>= 1; 423 } 424 ITBlock.push_back(firstcond); 425 } 426 427 return true; 428 } 429 430 // We want to read exactly 4 bytes of data. 431 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 432 return false; 433 434 uint32_t insn32 = (bytes[3] << 8) | 435 (bytes[2] << 0) | 436 (bytes[1] << 24) | 437 (bytes[0] << 16); 438 MI.clear(); 439 result = decodeThumbInstruction32(MI, insn32, Address, this); 440 if (result) { 441 Size = 4; 442 bool InITBlock = ITBlock.size(); 443 AddThumbPredicate(MI); 444 AddThumb1SBit(MI, InITBlock); 445 return true; 446 } 447 448 MI.clear(); 449 result = decodeThumb2Instruction32(MI, insn32, Address, this); 450 if (result) { 451 Size = 4; 452 AddThumbPredicate(MI); 453 return true; 454 } 455 456 MI.clear(); 457 result = decodeCommonInstruction32(MI, insn32, Address, this); 458 if (result) { 459 Size = 4; 460 AddThumbPredicate(MI); 461 return true; 462 } 463 464 MI.clear(); 465 result = decodeVFPInstruction32(MI, insn32, Address, this); 466 if (result) { 467 Size = 4; 468 UpdateThumbVFPPredicate(MI); 469 return true; 470 } 471 472 MI.clear(); 473 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 474 uint32_t NEONDataInsn = insn32; 475 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 476 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 477 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 478 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this); 479 if (result) { 480 Size = 4; 481 AddThumbPredicate(MI); 482 return true; 483 } 484 } 485 486 MI.clear(); 487 result = decodeNEONLoadStoreInstruction32(MI, insn32, Address, this); 488 if (result) { 489 Size = 4; 490 AddThumbPredicate(MI); 491 return true; 492 } 493 494 MI.clear(); 495 result = decodeNEONDupInstruction32(MI, insn32, Address, this); 496 if (result) { 497 Size = 4; 498 AddThumbPredicate(MI); 499 return true; 500 } 501 502 return false; 503 } 504 505 506 extern "C" void LLVMInitializeARMDisassembler() { 507 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 508 createARMDisassembler); 509 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 510 createThumbDisassembler); 511 } 512 513 static const unsigned GPRDecoderTable[] = { 514 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 515 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 516 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 517 ARM::R12, ARM::SP, ARM::LR, ARM::PC 518 }; 519 520 static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 521 uint64_t Address, const void *Decoder) { 522 if (RegNo > 15) 523 return false; 524 525 unsigned Register = GPRDecoderTable[RegNo]; 526 Inst.addOperand(MCOperand::CreateReg(Register)); 527 return true; 528 } 529 530 static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 531 uint64_t Address, const void *Decoder) { 532 if (RegNo == 15) return false; 533 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 534 } 535 536 static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 537 uint64_t Address, const void *Decoder) { 538 if (RegNo > 7) 539 return false; 540 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 541 } 542 543 static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 544 uint64_t Address, const void *Decoder) { 545 unsigned Register = 0; 546 switch (RegNo) { 547 case 0: 548 Register = ARM::R0; 549 break; 550 case 1: 551 Register = ARM::R1; 552 break; 553 case 2: 554 Register = ARM::R2; 555 break; 556 case 3: 557 Register = ARM::R3; 558 break; 559 case 9: 560 Register = ARM::R9; 561 break; 562 case 12: 563 Register = ARM::R12; 564 break; 565 default: 566 return false; 567 } 568 569 Inst.addOperand(MCOperand::CreateReg(Register)); 570 return true; 571 } 572 573 static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 574 uint64_t Address, const void *Decoder) { 575 if (RegNo == 13 || RegNo == 15) return false; 576 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 577 } 578 579 static const unsigned SPRDecoderTable[] = { 580 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 581 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 582 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 583 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 584 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 585 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 586 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 587 ARM::S28, ARM::S29, ARM::S30, ARM::S31 588 }; 589 590 static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 591 uint64_t Address, const void *Decoder) { 592 if (RegNo > 31) 593 return false; 594 595 unsigned Register = SPRDecoderTable[RegNo]; 596 Inst.addOperand(MCOperand::CreateReg(Register)); 597 return true; 598 } 599 600 static const unsigned DPRDecoderTable[] = { 601 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 602 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 603 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 604 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 605 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 606 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 607 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 608 ARM::D28, ARM::D29, ARM::D30, ARM::D31 609 }; 610 611 static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 612 uint64_t Address, const void *Decoder) { 613 if (RegNo > 31) 614 return false; 615 616 unsigned Register = DPRDecoderTable[RegNo]; 617 Inst.addOperand(MCOperand::CreateReg(Register)); 618 return true; 619 } 620 621 static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 622 uint64_t Address, const void *Decoder) { 623 if (RegNo > 7) 624 return false; 625 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 626 } 627 628 static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 629 uint64_t Address, const void *Decoder) { 630 if (RegNo > 15) 631 return false; 632 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 633 } 634 635 static const unsigned QPRDecoderTable[] = { 636 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 637 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 638 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 639 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 640 }; 641 642 643 static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 644 uint64_t Address, const void *Decoder) { 645 if (RegNo > 31) 646 return false; 647 RegNo >>= 1; 648 649 unsigned Register = QPRDecoderTable[RegNo]; 650 Inst.addOperand(MCOperand::CreateReg(Register)); 651 return true; 652 } 653 654 static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 655 uint64_t Address, const void *Decoder) { 656 if (Val == 0xF) return false; 657 // AL predicate is not allowed on Thumb1 branches. 658 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 659 return false; 660 Inst.addOperand(MCOperand::CreateImm(Val)); 661 if (Val == ARMCC::AL) { 662 Inst.addOperand(MCOperand::CreateReg(0)); 663 } else 664 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 665 return true; 666 } 667 668 static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 669 uint64_t Address, const void *Decoder) { 670 if (Val) 671 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 672 else 673 Inst.addOperand(MCOperand::CreateReg(0)); 674 return true; 675 } 676 677 static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 678 uint64_t Address, const void *Decoder) { 679 uint32_t imm = Val & 0xFF; 680 uint32_t rot = (Val & 0xF00) >> 7; 681 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 682 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 683 return true; 684 } 685 686 static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 687 uint64_t Address, const void *Decoder) { 688 Val <<= 2; 689 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val))); 690 return true; 691 } 692 693 static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 694 uint64_t Address, const void *Decoder) { 695 696 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 697 unsigned type = fieldFromInstruction32(Val, 5, 2); 698 unsigned imm = fieldFromInstruction32(Val, 7, 5); 699 700 // Register-immediate 701 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 702 703 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 704 switch (type) { 705 case 0: 706 Shift = ARM_AM::lsl; 707 break; 708 case 1: 709 Shift = ARM_AM::lsr; 710 break; 711 case 2: 712 Shift = ARM_AM::asr; 713 break; 714 case 3: 715 Shift = ARM_AM::ror; 716 break; 717 } 718 719 if (Shift == ARM_AM::ror && imm == 0) 720 Shift = ARM_AM::rrx; 721 722 unsigned Op = Shift | (imm << 3); 723 Inst.addOperand(MCOperand::CreateImm(Op)); 724 725 return true; 726 } 727 728 static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 729 uint64_t Address, const void *Decoder) { 730 731 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 732 unsigned type = fieldFromInstruction32(Val, 5, 2); 733 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 734 735 // Register-register 736 if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; 737 if (!DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)) return false; 738 739 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 740 switch (type) { 741 case 0: 742 Shift = ARM_AM::lsl; 743 break; 744 case 1: 745 Shift = ARM_AM::lsr; 746 break; 747 case 2: 748 Shift = ARM_AM::asr; 749 break; 750 case 3: 751 Shift = ARM_AM::ror; 752 break; 753 } 754 755 Inst.addOperand(MCOperand::CreateImm(Shift)); 756 757 return true; 758 } 759 760 static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 761 uint64_t Address, const void *Decoder) { 762 for (unsigned i = 0; i < 16; ++i) { 763 if (Val & (1 << i)) { 764 if (!DecodeGPRRegisterClass(Inst, i, Address, Decoder)) return false; 765 } 766 } 767 768 return true; 769 } 770 771 static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 772 uint64_t Address, const void *Decoder) { 773 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 774 unsigned regs = Val & 0xFF; 775 776 if (!DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)) return false; 777 for (unsigned i = 0; i < (regs - 1); ++i) { 778 if (!DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false; 779 } 780 781 return true; 782 } 783 784 static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 785 uint64_t Address, const void *Decoder) { 786 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 787 unsigned regs = (Val & 0xFF) / 2; 788 789 if (!DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)) return false; 790 for (unsigned i = 0; i < (regs - 1); ++i) { 791 if (!DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false; 792 } 793 794 return true; 795 } 796 797 static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 798 uint64_t Address, const void *Decoder) { 799 // This operand encodes a mask of contiguous zeros between a specified MSB 800 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 801 // the mask of all bits LSB-and-lower, and then xor them to create 802 // the mask of that's all ones on [msb, lsb]. Finally we not it to 803 // create the final mask. 804 unsigned msb = fieldFromInstruction32(Val, 5, 5); 805 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 806 uint32_t msb_mask = (1 << (msb+1)) - 1; 807 uint32_t lsb_mask = (1 << lsb) - 1; 808 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 809 return true; 810 } 811 812 static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 813 uint64_t Address, const void *Decoder) { 814 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 815 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 816 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 817 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 818 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 819 unsigned U = fieldFromInstruction32(Insn, 23, 1); 820 821 switch (Inst.getOpcode()) { 822 case ARM::LDC_OFFSET: 823 case ARM::LDC_PRE: 824 case ARM::LDC_POST: 825 case ARM::LDC_OPTION: 826 case ARM::LDCL_OFFSET: 827 case ARM::LDCL_PRE: 828 case ARM::LDCL_POST: 829 case ARM::LDCL_OPTION: 830 case ARM::STC_OFFSET: 831 case ARM::STC_PRE: 832 case ARM::STC_POST: 833 case ARM::STC_OPTION: 834 case ARM::STCL_OFFSET: 835 case ARM::STCL_PRE: 836 case ARM::STCL_POST: 837 case ARM::STCL_OPTION: 838 if (coproc == 0xA || coproc == 0xB) 839 return false; 840 break; 841 default: 842 break; 843 } 844 845 Inst.addOperand(MCOperand::CreateImm(coproc)); 846 Inst.addOperand(MCOperand::CreateImm(CRd)); 847 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 848 switch (Inst.getOpcode()) { 849 case ARM::LDC_OPTION: 850 case ARM::LDCL_OPTION: 851 case ARM::LDC2_OPTION: 852 case ARM::LDC2L_OPTION: 853 case ARM::STC_OPTION: 854 case ARM::STCL_OPTION: 855 case ARM::STC2_OPTION: 856 case ARM::STC2L_OPTION: 857 case ARM::LDCL_POST: 858 case ARM::STCL_POST: 859 break; 860 default: 861 Inst.addOperand(MCOperand::CreateReg(0)); 862 break; 863 } 864 865 unsigned P = fieldFromInstruction32(Insn, 24, 1); 866 unsigned W = fieldFromInstruction32(Insn, 21, 1); 867 868 bool writeback = (P == 0) || (W == 1); 869 unsigned idx_mode = 0; 870 if (P && writeback) 871 idx_mode = ARMII::IndexModePre; 872 else if (!P && writeback) 873 idx_mode = ARMII::IndexModePost; 874 875 switch (Inst.getOpcode()) { 876 case ARM::LDCL_POST: 877 case ARM::STCL_POST: 878 imm |= U << 8; 879 case ARM::LDC_OPTION: 880 case ARM::LDCL_OPTION: 881 case ARM::LDC2_OPTION: 882 case ARM::LDC2L_OPTION: 883 case ARM::STC_OPTION: 884 case ARM::STCL_OPTION: 885 case ARM::STC2_OPTION: 886 case ARM::STC2L_OPTION: 887 Inst.addOperand(MCOperand::CreateImm(imm)); 888 break; 889 default: 890 if (U) 891 Inst.addOperand(MCOperand::CreateImm( 892 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 893 else 894 Inst.addOperand(MCOperand::CreateImm( 895 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 896 break; 897 } 898 899 switch (Inst.getOpcode()) { 900 case ARM::LDC_OFFSET: 901 case ARM::LDC_PRE: 902 case ARM::LDC_POST: 903 case ARM::LDC_OPTION: 904 case ARM::LDCL_OFFSET: 905 case ARM::LDCL_PRE: 906 case ARM::LDCL_POST: 907 case ARM::LDCL_OPTION: 908 case ARM::STC_OFFSET: 909 case ARM::STC_PRE: 910 case ARM::STC_POST: 911 case ARM::STC_OPTION: 912 case ARM::STCL_OFFSET: 913 case ARM::STCL_PRE: 914 case ARM::STCL_POST: 915 case ARM::STCL_OPTION: 916 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 917 break; 918 default: 919 break; 920 } 921 922 return true; 923 } 924 925 static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 926 uint64_t Address, const void *Decoder) { 927 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 928 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 929 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 930 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 931 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 932 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 933 unsigned P = fieldFromInstruction32(Insn, 24, 1); 934 unsigned W = fieldFromInstruction32(Insn, 21, 1); 935 936 // On stores, the writeback operand precedes Rt. 937 switch (Inst.getOpcode()) { 938 case ARM::STR_POST_IMM: 939 case ARM::STR_POST_REG: 940 case ARM::STRTr: 941 case ARM::STRTi: 942 case ARM::STRBTr: 943 case ARM::STRBTi: 944 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 945 break; 946 default: 947 break; 948 } 949 950 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 951 952 // On loads, the writeback operand comes after Rt. 953 switch (Inst.getOpcode()) { 954 case ARM::LDR_POST_IMM: 955 case ARM::LDR_POST_REG: 956 case ARM::LDR_PRE: 957 case ARM::LDRBT_POST_REG: 958 case ARM::LDRBT_POST_IMM: 959 case ARM::LDRT_POST_REG: 960 case ARM::LDRT_POST_IMM: 961 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 962 return false; 963 break; 964 default: 965 break; 966 } 967 968 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 969 970 ARM_AM::AddrOpc Op = ARM_AM::add; 971 if (!fieldFromInstruction32(Insn, 23, 1)) 972 Op = ARM_AM::sub; 973 974 bool writeback = (P == 0) || (W == 1); 975 unsigned idx_mode = 0; 976 if (P && writeback) 977 idx_mode = ARMII::IndexModePre; 978 else if (!P && writeback) 979 idx_mode = ARMII::IndexModePost; 980 981 if (writeback && (Rn == 15 || Rn == Rt)) return false; // UNPREDICTABLE 982 983 if (reg) { 984 if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; 985 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 986 switch( fieldFromInstruction32(Insn, 5, 2)) { 987 case 0: 988 Opc = ARM_AM::lsl; 989 break; 990 case 1: 991 Opc = ARM_AM::lsr; 992 break; 993 case 2: 994 Opc = ARM_AM::asr; 995 break; 996 case 3: 997 Opc = ARM_AM::ror; 998 break; 999 default: 1000 return false; 1001 } 1002 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1003 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1004 1005 Inst.addOperand(MCOperand::CreateImm(imm)); 1006 } else { 1007 Inst.addOperand(MCOperand::CreateReg(0)); 1008 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1009 Inst.addOperand(MCOperand::CreateImm(tmp)); 1010 } 1011 1012 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1013 1014 return true; 1015 } 1016 1017 static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1018 uint64_t Address, const void *Decoder) { 1019 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1020 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1021 unsigned type = fieldFromInstruction32(Val, 5, 2); 1022 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1023 unsigned U = fieldFromInstruction32(Val, 12, 1); 1024 1025 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1026 switch (type) { 1027 case 0: 1028 ShOp = ARM_AM::lsl; 1029 break; 1030 case 1: 1031 ShOp = ARM_AM::lsr; 1032 break; 1033 case 2: 1034 ShOp = ARM_AM::asr; 1035 break; 1036 case 3: 1037 ShOp = ARM_AM::ror; 1038 break; 1039 } 1040 1041 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1042 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1043 unsigned shift; 1044 if (U) 1045 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1046 else 1047 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1048 Inst.addOperand(MCOperand::CreateImm(shift)); 1049 1050 return true; 1051 } 1052 1053 static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1054 uint64_t Address, const void *Decoder) { 1055 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1056 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1057 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1058 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1059 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1060 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1061 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1062 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1063 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1064 1065 bool writeback = (W == 1) | (P == 0); 1066 if (writeback) { // Writeback 1067 if (P) 1068 U |= ARMII::IndexModePre << 9; 1069 else 1070 U |= ARMII::IndexModePost << 9; 1071 1072 // On stores, the writeback operand precedes Rt. 1073 switch (Inst.getOpcode()) { 1074 case ARM::STRD: 1075 case ARM::STRD_PRE: 1076 case ARM::STRD_POST: 1077 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1078 return false; 1079 break; 1080 default: 1081 break; 1082 } 1083 } 1084 1085 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) 1086 return false; 1087 switch (Inst.getOpcode()) { 1088 case ARM::STRD: 1089 case ARM::STRD_PRE: 1090 case ARM::STRD_POST: 1091 case ARM::LDRD: 1092 case ARM::LDRD_PRE: 1093 case ARM::LDRD_POST: 1094 if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) 1095 return false; 1096 break; 1097 default: 1098 break; 1099 } 1100 1101 if (writeback) { 1102 // On loads, the writeback operand comes after Rt. 1103 switch (Inst.getOpcode()) { 1104 case ARM::LDRD: 1105 case ARM::LDRD_PRE: 1106 case ARM::LDRD_POST: 1107 case ARM::LDRHTr: 1108 case ARM::LDRSBTr: 1109 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1110 return false; 1111 break; 1112 default: 1113 break; 1114 } 1115 } 1116 1117 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1118 return false; 1119 1120 if (type) { 1121 Inst.addOperand(MCOperand::CreateReg(0)); 1122 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1123 } else { 1124 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1125 return false; 1126 Inst.addOperand(MCOperand::CreateImm(U)); 1127 } 1128 1129 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1130 1131 return true; 1132 } 1133 1134 static bool DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1135 uint64_t Address, const void *Decoder) { 1136 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1137 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1138 1139 switch (mode) { 1140 case 0: 1141 mode = ARM_AM::da; 1142 break; 1143 case 1: 1144 mode = ARM_AM::ia; 1145 break; 1146 case 2: 1147 mode = ARM_AM::db; 1148 break; 1149 case 3: 1150 mode = ARM_AM::ib; 1151 break; 1152 } 1153 1154 Inst.addOperand(MCOperand::CreateImm(mode)); 1155 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1156 1157 return true; 1158 } 1159 1160 static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1161 unsigned Insn, 1162 uint64_t Address, const void *Decoder) { 1163 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1164 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1165 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1166 1167 if (pred == 0xF) { 1168 switch (Inst.getOpcode()) { 1169 case ARM::STMDA: 1170 Inst.setOpcode(ARM::RFEDA); 1171 break; 1172 case ARM::STMDA_UPD: 1173 Inst.setOpcode(ARM::RFEDA_UPD); 1174 break; 1175 case ARM::STMDB: 1176 Inst.setOpcode(ARM::RFEDB); 1177 break; 1178 case ARM::STMDB_UPD: 1179 Inst.setOpcode(ARM::RFEDB_UPD); 1180 break; 1181 case ARM::STMIA: 1182 Inst.setOpcode(ARM::RFEIA); 1183 break; 1184 case ARM::STMIA_UPD: 1185 Inst.setOpcode(ARM::RFEIA_UPD); 1186 break; 1187 case ARM::STMIB: 1188 Inst.setOpcode(ARM::RFEIB); 1189 break; 1190 case ARM::STMIB_UPD: 1191 Inst.setOpcode(ARM::RFEIB_UPD); 1192 break; 1193 } 1194 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1195 } 1196 1197 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 1198 !DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || // Tied 1199 !DecodePredicateOperand(Inst, pred, Address, Decoder) || 1200 !DecodeRegListOperand(Inst, reglist, Address, Decoder)) 1201 return false; 1202 1203 return true; 1204 } 1205 1206 static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1207 uint64_t Address, const void *Decoder) { 1208 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1209 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1210 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1211 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1212 1213 // imod == '01' --> UNPREDICTABLE 1214 if (imod == 1) return false; 1215 1216 if (M && mode && imod && iflags) { 1217 Inst.setOpcode(ARM::CPS3p); 1218 Inst.addOperand(MCOperand::CreateImm(imod)); 1219 Inst.addOperand(MCOperand::CreateImm(iflags)); 1220 Inst.addOperand(MCOperand::CreateImm(mode)); 1221 return true; 1222 } else if (!mode && !M) { 1223 Inst.setOpcode(ARM::CPS2p); 1224 Inst.addOperand(MCOperand::CreateImm(imod)); 1225 Inst.addOperand(MCOperand::CreateImm(iflags)); 1226 return true; 1227 } else if (!imod && !iflags && M) { 1228 Inst.setOpcode(ARM::CPS1p); 1229 Inst.addOperand(MCOperand::CreateImm(mode)); 1230 return true; 1231 } 1232 1233 return false; 1234 } 1235 1236 static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1237 uint64_t Address, const void *Decoder) { 1238 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1239 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1240 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1241 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1242 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1243 1244 if (pred == 0xF) 1245 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1246 1247 if (!DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder) || 1248 !DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder) || 1249 !DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder) || 1250 !DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)) 1251 return false; 1252 1253 return true; 1254 } 1255 1256 static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1257 uint64_t Address, const void *Decoder) { 1258 unsigned add = fieldFromInstruction32(Val, 12, 1); 1259 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1260 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1261 1262 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1263 return false; 1264 1265 if (!add) imm *= -1; 1266 if (imm == 0 && !add) imm = INT32_MIN; 1267 Inst.addOperand(MCOperand::CreateImm(imm)); 1268 1269 return true; 1270 } 1271 1272 static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1273 uint64_t Address, const void *Decoder) { 1274 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1275 unsigned U = fieldFromInstruction32(Val, 8, 1); 1276 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1277 1278 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1279 return false; 1280 1281 if (U) 1282 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1283 else 1284 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1285 1286 return true; 1287 } 1288 1289 static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1290 uint64_t Address, const void *Decoder) { 1291 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1292 } 1293 1294 static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1295 uint64_t Address, const void *Decoder) { 1296 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1297 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1298 1299 if (pred == 0xF) { 1300 Inst.setOpcode(ARM::BLXi); 1301 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1302 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1303 return true; 1304 } 1305 1306 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1307 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1308 1309 return true; 1310 } 1311 1312 1313 static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1314 uint64_t Address, const void *Decoder) { 1315 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1316 return true; 1317 } 1318 1319 static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1320 uint64_t Address, const void *Decoder) { 1321 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1322 unsigned align = fieldFromInstruction32(Val, 4, 2); 1323 1324 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1325 return false; 1326 if (!align) 1327 Inst.addOperand(MCOperand::CreateImm(0)); 1328 else 1329 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1330 1331 return true; 1332 } 1333 1334 static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1335 uint64_t Address, const void *Decoder) { 1336 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1337 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1338 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1339 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1340 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1341 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1342 1343 // First output register 1344 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1345 1346 // Second output register 1347 switch (Inst.getOpcode()) { 1348 case ARM::VLD1q8: 1349 case ARM::VLD1q16: 1350 case ARM::VLD1q32: 1351 case ARM::VLD1q64: 1352 case ARM::VLD1q8_UPD: 1353 case ARM::VLD1q16_UPD: 1354 case ARM::VLD1q32_UPD: 1355 case ARM::VLD1q64_UPD: 1356 case ARM::VLD1d8T: 1357 case ARM::VLD1d16T: 1358 case ARM::VLD1d32T: 1359 case ARM::VLD1d64T: 1360 case ARM::VLD1d8T_UPD: 1361 case ARM::VLD1d16T_UPD: 1362 case ARM::VLD1d32T_UPD: 1363 case ARM::VLD1d64T_UPD: 1364 case ARM::VLD1d8Q: 1365 case ARM::VLD1d16Q: 1366 case ARM::VLD1d32Q: 1367 case ARM::VLD1d64Q: 1368 case ARM::VLD1d8Q_UPD: 1369 case ARM::VLD1d16Q_UPD: 1370 case ARM::VLD1d32Q_UPD: 1371 case ARM::VLD1d64Q_UPD: 1372 case ARM::VLD2d8: 1373 case ARM::VLD2d16: 1374 case ARM::VLD2d32: 1375 case ARM::VLD2d8_UPD: 1376 case ARM::VLD2d16_UPD: 1377 case ARM::VLD2d32_UPD: 1378 case ARM::VLD2q8: 1379 case ARM::VLD2q16: 1380 case ARM::VLD2q32: 1381 case ARM::VLD2q8_UPD: 1382 case ARM::VLD2q16_UPD: 1383 case ARM::VLD2q32_UPD: 1384 case ARM::VLD3d8: 1385 case ARM::VLD3d16: 1386 case ARM::VLD3d32: 1387 case ARM::VLD3d8_UPD: 1388 case ARM::VLD3d16_UPD: 1389 case ARM::VLD3d32_UPD: 1390 case ARM::VLD4d8: 1391 case ARM::VLD4d16: 1392 case ARM::VLD4d32: 1393 case ARM::VLD4d8_UPD: 1394 case ARM::VLD4d16_UPD: 1395 case ARM::VLD4d32_UPD: 1396 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1397 break; 1398 case ARM::VLD2b8: 1399 case ARM::VLD2b16: 1400 case ARM::VLD2b32: 1401 case ARM::VLD2b8_UPD: 1402 case ARM::VLD2b16_UPD: 1403 case ARM::VLD2b32_UPD: 1404 case ARM::VLD3q8: 1405 case ARM::VLD3q16: 1406 case ARM::VLD3q32: 1407 case ARM::VLD3q8_UPD: 1408 case ARM::VLD3q16_UPD: 1409 case ARM::VLD3q32_UPD: 1410 case ARM::VLD4q8: 1411 case ARM::VLD4q16: 1412 case ARM::VLD4q32: 1413 case ARM::VLD4q8_UPD: 1414 case ARM::VLD4q16_UPD: 1415 case ARM::VLD4q32_UPD: 1416 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1417 default: 1418 break; 1419 } 1420 1421 // Third output register 1422 switch(Inst.getOpcode()) { 1423 case ARM::VLD1d8T: 1424 case ARM::VLD1d16T: 1425 case ARM::VLD1d32T: 1426 case ARM::VLD1d64T: 1427 case ARM::VLD1d8T_UPD: 1428 case ARM::VLD1d16T_UPD: 1429 case ARM::VLD1d32T_UPD: 1430 case ARM::VLD1d64T_UPD: 1431 case ARM::VLD1d8Q: 1432 case ARM::VLD1d16Q: 1433 case ARM::VLD1d32Q: 1434 case ARM::VLD1d64Q: 1435 case ARM::VLD1d8Q_UPD: 1436 case ARM::VLD1d16Q_UPD: 1437 case ARM::VLD1d32Q_UPD: 1438 case ARM::VLD1d64Q_UPD: 1439 case ARM::VLD2q8: 1440 case ARM::VLD2q16: 1441 case ARM::VLD2q32: 1442 case ARM::VLD2q8_UPD: 1443 case ARM::VLD2q16_UPD: 1444 case ARM::VLD2q32_UPD: 1445 case ARM::VLD3d8: 1446 case ARM::VLD3d16: 1447 case ARM::VLD3d32: 1448 case ARM::VLD3d8_UPD: 1449 case ARM::VLD3d16_UPD: 1450 case ARM::VLD3d32_UPD: 1451 case ARM::VLD4d8: 1452 case ARM::VLD4d16: 1453 case ARM::VLD4d32: 1454 case ARM::VLD4d8_UPD: 1455 case ARM::VLD4d16_UPD: 1456 case ARM::VLD4d32_UPD: 1457 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1458 break; 1459 case ARM::VLD3q8: 1460 case ARM::VLD3q16: 1461 case ARM::VLD3q32: 1462 case ARM::VLD3q8_UPD: 1463 case ARM::VLD3q16_UPD: 1464 case ARM::VLD3q32_UPD: 1465 case ARM::VLD4q8: 1466 case ARM::VLD4q16: 1467 case ARM::VLD4q32: 1468 case ARM::VLD4q8_UPD: 1469 case ARM::VLD4q16_UPD: 1470 case ARM::VLD4q32_UPD: 1471 if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false; 1472 break; 1473 default: 1474 break; 1475 } 1476 1477 // Fourth output register 1478 switch (Inst.getOpcode()) { 1479 case ARM::VLD1d8Q: 1480 case ARM::VLD1d16Q: 1481 case ARM::VLD1d32Q: 1482 case ARM::VLD1d64Q: 1483 case ARM::VLD1d8Q_UPD: 1484 case ARM::VLD1d16Q_UPD: 1485 case ARM::VLD1d32Q_UPD: 1486 case ARM::VLD1d64Q_UPD: 1487 case ARM::VLD2q8: 1488 case ARM::VLD2q16: 1489 case ARM::VLD2q32: 1490 case ARM::VLD2q8_UPD: 1491 case ARM::VLD2q16_UPD: 1492 case ARM::VLD2q32_UPD: 1493 case ARM::VLD4d8: 1494 case ARM::VLD4d16: 1495 case ARM::VLD4d32: 1496 case ARM::VLD4d8_UPD: 1497 case ARM::VLD4d16_UPD: 1498 case ARM::VLD4d32_UPD: 1499 if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false; 1500 break; 1501 case ARM::VLD4q8: 1502 case ARM::VLD4q16: 1503 case ARM::VLD4q32: 1504 case ARM::VLD4q8_UPD: 1505 case ARM::VLD4q16_UPD: 1506 case ARM::VLD4q32_UPD: 1507 if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false; 1508 break; 1509 default: 1510 break; 1511 } 1512 1513 // Writeback operand 1514 switch (Inst.getOpcode()) { 1515 case ARM::VLD1d8_UPD: 1516 case ARM::VLD1d16_UPD: 1517 case ARM::VLD1d32_UPD: 1518 case ARM::VLD1d64_UPD: 1519 case ARM::VLD1q8_UPD: 1520 case ARM::VLD1q16_UPD: 1521 case ARM::VLD1q32_UPD: 1522 case ARM::VLD1q64_UPD: 1523 case ARM::VLD1d8T_UPD: 1524 case ARM::VLD1d16T_UPD: 1525 case ARM::VLD1d32T_UPD: 1526 case ARM::VLD1d64T_UPD: 1527 case ARM::VLD1d8Q_UPD: 1528 case ARM::VLD1d16Q_UPD: 1529 case ARM::VLD1d32Q_UPD: 1530 case ARM::VLD1d64Q_UPD: 1531 case ARM::VLD2d8_UPD: 1532 case ARM::VLD2d16_UPD: 1533 case ARM::VLD2d32_UPD: 1534 case ARM::VLD2q8_UPD: 1535 case ARM::VLD2q16_UPD: 1536 case ARM::VLD2q32_UPD: 1537 case ARM::VLD2b8_UPD: 1538 case ARM::VLD2b16_UPD: 1539 case ARM::VLD2b32_UPD: 1540 case ARM::VLD3d8_UPD: 1541 case ARM::VLD3d16_UPD: 1542 case ARM::VLD3d32_UPD: 1543 case ARM::VLD3q8_UPD: 1544 case ARM::VLD3q16_UPD: 1545 case ARM::VLD3q32_UPD: 1546 case ARM::VLD4d8_UPD: 1547 case ARM::VLD4d16_UPD: 1548 case ARM::VLD4d32_UPD: 1549 case ARM::VLD4q8_UPD: 1550 case ARM::VLD4q16_UPD: 1551 case ARM::VLD4q32_UPD: 1552 if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) return false; 1553 break; 1554 default: 1555 break; 1556 } 1557 1558 // AddrMode6 Base (register+alignment) 1559 if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false; 1560 1561 // AddrMode6 Offset (register) 1562 if (Rm == 0xD) 1563 Inst.addOperand(MCOperand::CreateReg(0)); 1564 else if (Rm != 0xF) { 1565 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1566 return false; 1567 } 1568 1569 return true; 1570 } 1571 1572 static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1573 uint64_t Address, const void *Decoder) { 1574 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1575 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1576 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1577 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1578 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1579 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1580 1581 // Writeback Operand 1582 switch (Inst.getOpcode()) { 1583 case ARM::VST1d8_UPD: 1584 case ARM::VST1d16_UPD: 1585 case ARM::VST1d32_UPD: 1586 case ARM::VST1d64_UPD: 1587 case ARM::VST1q8_UPD: 1588 case ARM::VST1q16_UPD: 1589 case ARM::VST1q32_UPD: 1590 case ARM::VST1q64_UPD: 1591 case ARM::VST1d8T_UPD: 1592 case ARM::VST1d16T_UPD: 1593 case ARM::VST1d32T_UPD: 1594 case ARM::VST1d64T_UPD: 1595 case ARM::VST1d8Q_UPD: 1596 case ARM::VST1d16Q_UPD: 1597 case ARM::VST1d32Q_UPD: 1598 case ARM::VST1d64Q_UPD: 1599 case ARM::VST2d8_UPD: 1600 case ARM::VST2d16_UPD: 1601 case ARM::VST2d32_UPD: 1602 case ARM::VST2q8_UPD: 1603 case ARM::VST2q16_UPD: 1604 case ARM::VST2q32_UPD: 1605 case ARM::VST2b8_UPD: 1606 case ARM::VST2b16_UPD: 1607 case ARM::VST2b32_UPD: 1608 case ARM::VST3d8_UPD: 1609 case ARM::VST3d16_UPD: 1610 case ARM::VST3d32_UPD: 1611 case ARM::VST3q8_UPD: 1612 case ARM::VST3q16_UPD: 1613 case ARM::VST3q32_UPD: 1614 case ARM::VST4d8_UPD: 1615 case ARM::VST4d16_UPD: 1616 case ARM::VST4d32_UPD: 1617 case ARM::VST4q8_UPD: 1618 case ARM::VST4q16_UPD: 1619 case ARM::VST4q32_UPD: 1620 if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) 1621 return false; 1622 break; 1623 default: 1624 break; 1625 } 1626 1627 // AddrMode6 Base (register+alignment) 1628 if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false; 1629 1630 // AddrMode6 Offset (register) 1631 if (Rm == 0xD) 1632 Inst.addOperand(MCOperand::CreateReg(0)); 1633 else if (Rm != 0xF) { 1634 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1635 } 1636 1637 // First input register 1638 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1639 1640 // Second input register 1641 switch (Inst.getOpcode()) { 1642 case ARM::VST1q8: 1643 case ARM::VST1q16: 1644 case ARM::VST1q32: 1645 case ARM::VST1q64: 1646 case ARM::VST1q8_UPD: 1647 case ARM::VST1q16_UPD: 1648 case ARM::VST1q32_UPD: 1649 case ARM::VST1q64_UPD: 1650 case ARM::VST1d8T: 1651 case ARM::VST1d16T: 1652 case ARM::VST1d32T: 1653 case ARM::VST1d64T: 1654 case ARM::VST1d8T_UPD: 1655 case ARM::VST1d16T_UPD: 1656 case ARM::VST1d32T_UPD: 1657 case ARM::VST1d64T_UPD: 1658 case ARM::VST1d8Q: 1659 case ARM::VST1d16Q: 1660 case ARM::VST1d32Q: 1661 case ARM::VST1d64Q: 1662 case ARM::VST1d8Q_UPD: 1663 case ARM::VST1d16Q_UPD: 1664 case ARM::VST1d32Q_UPD: 1665 case ARM::VST1d64Q_UPD: 1666 case ARM::VST2d8: 1667 case ARM::VST2d16: 1668 case ARM::VST2d32: 1669 case ARM::VST2d8_UPD: 1670 case ARM::VST2d16_UPD: 1671 case ARM::VST2d32_UPD: 1672 case ARM::VST2q8: 1673 case ARM::VST2q16: 1674 case ARM::VST2q32: 1675 case ARM::VST2q8_UPD: 1676 case ARM::VST2q16_UPD: 1677 case ARM::VST2q32_UPD: 1678 case ARM::VST3d8: 1679 case ARM::VST3d16: 1680 case ARM::VST3d32: 1681 case ARM::VST3d8_UPD: 1682 case ARM::VST3d16_UPD: 1683 case ARM::VST3d32_UPD: 1684 case ARM::VST4d8: 1685 case ARM::VST4d16: 1686 case ARM::VST4d32: 1687 case ARM::VST4d8_UPD: 1688 case ARM::VST4d16_UPD: 1689 case ARM::VST4d32_UPD: 1690 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1691 break; 1692 case ARM::VST2b8: 1693 case ARM::VST2b16: 1694 case ARM::VST2b32: 1695 case ARM::VST2b8_UPD: 1696 case ARM::VST2b16_UPD: 1697 case ARM::VST2b32_UPD: 1698 case ARM::VST3q8: 1699 case ARM::VST3q16: 1700 case ARM::VST3q32: 1701 case ARM::VST3q8_UPD: 1702 case ARM::VST3q16_UPD: 1703 case ARM::VST3q32_UPD: 1704 case ARM::VST4q8: 1705 case ARM::VST4q16: 1706 case ARM::VST4q32: 1707 case ARM::VST4q8_UPD: 1708 case ARM::VST4q16_UPD: 1709 case ARM::VST4q32_UPD: 1710 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1711 break; 1712 default: 1713 break; 1714 } 1715 1716 // Third input register 1717 switch (Inst.getOpcode()) { 1718 case ARM::VST1d8T: 1719 case ARM::VST1d16T: 1720 case ARM::VST1d32T: 1721 case ARM::VST1d64T: 1722 case ARM::VST1d8T_UPD: 1723 case ARM::VST1d16T_UPD: 1724 case ARM::VST1d32T_UPD: 1725 case ARM::VST1d64T_UPD: 1726 case ARM::VST1d8Q: 1727 case ARM::VST1d16Q: 1728 case ARM::VST1d32Q: 1729 case ARM::VST1d64Q: 1730 case ARM::VST1d8Q_UPD: 1731 case ARM::VST1d16Q_UPD: 1732 case ARM::VST1d32Q_UPD: 1733 case ARM::VST1d64Q_UPD: 1734 case ARM::VST2q8: 1735 case ARM::VST2q16: 1736 case ARM::VST2q32: 1737 case ARM::VST2q8_UPD: 1738 case ARM::VST2q16_UPD: 1739 case ARM::VST2q32_UPD: 1740 case ARM::VST3d8: 1741 case ARM::VST3d16: 1742 case ARM::VST3d32: 1743 case ARM::VST3d8_UPD: 1744 case ARM::VST3d16_UPD: 1745 case ARM::VST3d32_UPD: 1746 case ARM::VST4d8: 1747 case ARM::VST4d16: 1748 case ARM::VST4d32: 1749 case ARM::VST4d8_UPD: 1750 case ARM::VST4d16_UPD: 1751 case ARM::VST4d32_UPD: 1752 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1753 break; 1754 case ARM::VST3q8: 1755 case ARM::VST3q16: 1756 case ARM::VST3q32: 1757 case ARM::VST3q8_UPD: 1758 case ARM::VST3q16_UPD: 1759 case ARM::VST3q32_UPD: 1760 case ARM::VST4q8: 1761 case ARM::VST4q16: 1762 case ARM::VST4q32: 1763 case ARM::VST4q8_UPD: 1764 case ARM::VST4q16_UPD: 1765 case ARM::VST4q32_UPD: 1766 if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false; 1767 break; 1768 default: 1769 break; 1770 } 1771 1772 // Fourth input register 1773 switch (Inst.getOpcode()) { 1774 case ARM::VST1d8Q: 1775 case ARM::VST1d16Q: 1776 case ARM::VST1d32Q: 1777 case ARM::VST1d64Q: 1778 case ARM::VST1d8Q_UPD: 1779 case ARM::VST1d16Q_UPD: 1780 case ARM::VST1d32Q_UPD: 1781 case ARM::VST1d64Q_UPD: 1782 case ARM::VST2q8: 1783 case ARM::VST2q16: 1784 case ARM::VST2q32: 1785 case ARM::VST2q8_UPD: 1786 case ARM::VST2q16_UPD: 1787 case ARM::VST2q32_UPD: 1788 case ARM::VST4d8: 1789 case ARM::VST4d16: 1790 case ARM::VST4d32: 1791 case ARM::VST4d8_UPD: 1792 case ARM::VST4d16_UPD: 1793 case ARM::VST4d32_UPD: 1794 if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false; 1795 break; 1796 case ARM::VST4q8: 1797 case ARM::VST4q16: 1798 case ARM::VST4q32: 1799 case ARM::VST4q8_UPD: 1800 case ARM::VST4q16_UPD: 1801 case ARM::VST4q32_UPD: 1802 if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false; 1803 break; 1804 default: 1805 break; 1806 } 1807 1808 return true; 1809 } 1810 1811 static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1812 uint64_t Address, const void *Decoder) { 1813 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1814 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1815 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1816 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1817 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1818 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1819 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 1820 1821 align *= (1 << size); 1822 1823 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1824 if (regs == 2) { 1825 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1826 } 1827 if (Rm == 0xD) { 1828 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1829 } 1830 1831 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1832 Inst.addOperand(MCOperand::CreateImm(align)); 1833 1834 if (Rm == 0xD) 1835 Inst.addOperand(MCOperand::CreateReg(0)); 1836 else if (Rm != 0xF) { 1837 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1838 } 1839 1840 return true; 1841 } 1842 1843 static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1844 uint64_t Address, const void *Decoder) { 1845 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1846 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1847 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1848 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1849 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1850 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 1851 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1852 align *= 2*size; 1853 1854 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1855 if (!DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)) return false; 1856 if (Rm == 0xD) { 1857 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1858 } 1859 1860 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1861 Inst.addOperand(MCOperand::CreateImm(align)); 1862 1863 if (Rm == 0xD) 1864 Inst.addOperand(MCOperand::CreateReg(0)); 1865 else if (Rm != 0xF) { 1866 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1867 } 1868 1869 return true; 1870 } 1871 1872 static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1873 uint64_t Address, const void *Decoder) { 1874 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1875 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1876 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1877 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1878 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1879 1880 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) || 1881 !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) || 1882 !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)) 1883 return false; 1884 if (Rm == 0xD) { 1885 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1886 } 1887 1888 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1889 Inst.addOperand(MCOperand::CreateImm(0)); 1890 1891 if (Rm == 0xD) 1892 Inst.addOperand(MCOperand::CreateReg(0)); 1893 else if (Rm != 0xF) { 1894 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1895 } 1896 1897 return true; 1898 } 1899 1900 static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1901 uint64_t Address, const void *Decoder) { 1902 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1903 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1904 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1905 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1906 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1907 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1908 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1909 1910 if (size == 0x3) { 1911 size = 4; 1912 align = 16; 1913 } else { 1914 if (size == 2) { 1915 size = 1 << size; 1916 align *= 8; 1917 } else { 1918 size = 1 << size; 1919 align *= 4*size; 1920 } 1921 } 1922 1923 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) || 1924 !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) || 1925 !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder) || 1926 !DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)) 1927 return false; 1928 if (Rm == 0xD) { 1929 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1930 } 1931 1932 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1933 Inst.addOperand(MCOperand::CreateImm(align)); 1934 1935 if (Rm == 0xD) 1936 Inst.addOperand(MCOperand::CreateReg(0)); 1937 else if (Rm != 0xF) { 1938 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1939 } 1940 1941 return true; 1942 } 1943 1944 static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1945 uint64_t Address, const void *Decoder) { 1946 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1947 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1948 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 1949 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 1950 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 1951 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 1952 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 1953 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 1954 1955 if (Q) { 1956 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1957 } else { 1958 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1959 } 1960 1961 Inst.addOperand(MCOperand::CreateImm(imm)); 1962 1963 switch (Inst.getOpcode()) { 1964 case ARM::VORRiv4i16: 1965 case ARM::VORRiv2i32: 1966 case ARM::VBICiv4i16: 1967 case ARM::VBICiv2i32: 1968 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1969 break; 1970 case ARM::VORRiv8i16: 1971 case ARM::VORRiv4i32: 1972 case ARM::VBICiv8i16: 1973 case ARM::VBICiv4i32: 1974 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1975 break; 1976 default: 1977 break; 1978 } 1979 1980 return true; 1981 } 1982 1983 static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 1984 uint64_t Address, const void *Decoder) { 1985 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1986 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1987 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1988 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 1989 unsigned size = fieldFromInstruction32(Insn, 18, 2); 1990 1991 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1992 if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1993 Inst.addOperand(MCOperand::CreateImm(8 << size)); 1994 1995 return true; 1996 } 1997 1998 static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 1999 uint64_t Address, const void *Decoder) { 2000 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2001 return true; 2002 } 2003 2004 static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2005 uint64_t Address, const void *Decoder) { 2006 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2007 return true; 2008 } 2009 2010 static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2011 uint64_t Address, const void *Decoder) { 2012 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2013 return true; 2014 } 2015 2016 static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2017 uint64_t Address, const void *Decoder) { 2018 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2019 return true; 2020 } 2021 2022 static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2023 uint64_t Address, const void *Decoder) { 2024 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2025 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2026 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2027 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2028 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2029 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2030 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2031 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2032 2033 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2034 if (op) { 2035 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; // Writeback 2036 } 2037 2038 for (unsigned i = 0; i < length; ++i) { 2039 if (!DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)) return false; 2040 } 2041 2042 if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2043 2044 return true; 2045 } 2046 2047 static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 2048 uint64_t Address, const void *Decoder) { 2049 // The immediate needs to be a fully instantiated float. However, the 2050 // auto-generated decoder is only able to fill in some of the bits 2051 // necessary. For instance, the 'b' bit is replicated multiple times, 2052 // and is even present in inverted form in one bit. We do a little 2053 // binary parsing here to fill in those missing bits, and then 2054 // reinterpret it all as a float. 2055 union { 2056 uint32_t integer; 2057 float fp; 2058 } fp_conv; 2059 2060 fp_conv.integer = Val; 2061 uint32_t b = fieldFromInstruction32(Val, 25, 1); 2062 fp_conv.integer |= b << 26; 2063 fp_conv.integer |= b << 27; 2064 fp_conv.integer |= b << 28; 2065 fp_conv.integer |= b << 29; 2066 fp_conv.integer |= (~b & 0x1) << 30; 2067 2068 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 2069 return true; 2070 } 2071 2072 static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2073 uint64_t Address, const void *Decoder) { 2074 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2075 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2076 2077 if (!DecodetGPRRegisterClass(Inst, dst, Address, Decoder)) return false; 2078 2079 if (Inst.getOpcode() == ARM::tADR) 2080 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2081 else if (Inst.getOpcode() == ARM::tADDrSPi) 2082 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2083 else 2084 return false; 2085 2086 Inst.addOperand(MCOperand::CreateImm(imm)); 2087 return true; 2088 } 2089 2090 static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2091 uint64_t Address, const void *Decoder) { 2092 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2093 return true; 2094 } 2095 2096 static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2097 uint64_t Address, const void *Decoder) { 2098 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2099 return true; 2100 } 2101 2102 static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2103 uint64_t Address, const void *Decoder) { 2104 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2105 return true; 2106 } 2107 2108 static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2109 uint64_t Address, const void *Decoder) { 2110 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2111 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2112 2113 if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder) || 2114 !DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)) 2115 return false; 2116 2117 return true; 2118 } 2119 2120 static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2121 uint64_t Address, const void *Decoder) { 2122 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2123 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2124 2125 if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2126 Inst.addOperand(MCOperand::CreateImm(imm)); 2127 2128 return true; 2129 } 2130 2131 static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2132 uint64_t Address, const void *Decoder) { 2133 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2134 2135 return true; 2136 } 2137 2138 static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2139 uint64_t Address, const void *Decoder) { 2140 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2141 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2142 2143 return true; 2144 } 2145 2146 static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2147 uint64_t Address, const void *Decoder) { 2148 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2149 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2150 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2151 2152 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2153 !DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)) 2154 return false; 2155 Inst.addOperand(MCOperand::CreateImm(imm)); 2156 2157 return true; 2158 } 2159 2160 static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2161 uint64_t Address, const void *Decoder) { 2162 if (Inst.getOpcode() != ARM::t2PLDs) { 2163 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2164 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2165 } 2166 2167 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2168 if (Rn == 0xF) { 2169 switch (Inst.getOpcode()) { 2170 case ARM::t2LDRBs: 2171 Inst.setOpcode(ARM::t2LDRBpci); 2172 break; 2173 case ARM::t2LDRHs: 2174 Inst.setOpcode(ARM::t2LDRHpci); 2175 break; 2176 case ARM::t2LDRSHs: 2177 Inst.setOpcode(ARM::t2LDRSHpci); 2178 break; 2179 case ARM::t2LDRSBs: 2180 Inst.setOpcode(ARM::t2LDRSBpci); 2181 break; 2182 case ARM::t2PLDs: 2183 Inst.setOpcode(ARM::t2PLDi12); 2184 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2185 break; 2186 default: 2187 return false; 2188 } 2189 2190 int imm = fieldFromInstruction32(Insn, 0, 12); 2191 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2192 Inst.addOperand(MCOperand::CreateImm(imm)); 2193 2194 return true; 2195 } 2196 2197 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2198 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2199 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2200 DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder); 2201 2202 return true; 2203 } 2204 2205 static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2206 uint64_t Address, const void *Decoder) { 2207 int imm = Val & 0xFF; 2208 if (!(Val & 0x100)) imm *= -1; 2209 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2210 2211 return true; 2212 } 2213 2214 static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2215 uint64_t Address, const void *Decoder) { 2216 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2217 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2218 2219 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2220 !DecodeT2Imm8S4(Inst, imm, Address, Decoder)) 2221 return false; 2222 2223 return true; 2224 } 2225 2226 static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2227 uint64_t Address, const void *Decoder) { 2228 int imm = Val & 0xFF; 2229 if (!(Val & 0x100)) imm *= -1; 2230 Inst.addOperand(MCOperand::CreateImm(imm)); 2231 2232 return true; 2233 } 2234 2235 2236 static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2237 uint64_t Address, const void *Decoder) { 2238 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2239 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2240 2241 // Some instructions always use an additive offset. 2242 switch (Inst.getOpcode()) { 2243 case ARM::t2LDRT: 2244 case ARM::t2LDRBT: 2245 case ARM::t2LDRHT: 2246 case ARM::t2LDRSBT: 2247 case ARM::t2LDRSHT: 2248 imm |= 0x100; 2249 break; 2250 default: 2251 break; 2252 } 2253 2254 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2255 !DecodeT2Imm8(Inst, imm, Address, Decoder)) 2256 return false; 2257 2258 return true; 2259 } 2260 2261 2262 static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2263 uint64_t Address, const void *Decoder) { 2264 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2265 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2266 2267 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2268 Inst.addOperand(MCOperand::CreateImm(imm)); 2269 2270 return true; 2271 } 2272 2273 2274 static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2275 uint64_t Address, const void *Decoder) { 2276 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2277 2278 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2279 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2280 Inst.addOperand(MCOperand::CreateImm(imm)); 2281 2282 return true; 2283 } 2284 2285 static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2286 uint64_t Address, const void *Decoder) { 2287 if (Inst.getOpcode() == ARM::tADDrSP) { 2288 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2289 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2290 2291 if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false; 2292 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2293 if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false; 2294 } else if (Inst.getOpcode() == ARM::tADDspr) { 2295 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2296 2297 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2298 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2299 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2300 } 2301 2302 return true; 2303 } 2304 2305 static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2306 uint64_t Address, const void *Decoder) { 2307 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2308 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2309 2310 Inst.addOperand(MCOperand::CreateImm(imod)); 2311 Inst.addOperand(MCOperand::CreateImm(flags)); 2312 2313 return true; 2314 } 2315 2316 static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2317 uint64_t Address, const void *Decoder) { 2318 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2319 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2320 2321 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2322 Inst.addOperand(MCOperand::CreateImm(add)); 2323 2324 return true; 2325 } 2326 2327 static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2328 uint64_t Address, const void *Decoder) { 2329 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2330 return true; 2331 } 2332 2333 static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2334 uint64_t Address, const void *Decoder) { 2335 if (Val == 0xA || Val == 0xB) 2336 return false; 2337 2338 Inst.addOperand(MCOperand::CreateImm(Val)); 2339 return true; 2340 } 2341 2342 static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, 2343 uint64_t Address, const void *Decoder) { 2344 if (Val == 0) 2345 Inst.addOperand(MCOperand::CreateImm(32)); 2346 else 2347 Inst.addOperand(MCOperand::CreateImm(Val)); 2348 return true; 2349 } 2350 2351 static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2352 uint64_t Address, const void *Decoder) { 2353 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2354 if (pred == 0xE || pred == 0xF) { 2355 unsigned opc = fieldFromInstruction32(Insn, 4, 2); 2356 switch (opc) { 2357 default: 2358 return false; 2359 case 0: 2360 Inst.setOpcode(ARM::t2DSB); 2361 break; 2362 case 1: 2363 Inst.setOpcode(ARM::t2DMB); 2364 break; 2365 case 2: 2366 Inst.setOpcode(ARM::t2ISB); 2367 return true; 2368 } 2369 2370 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2371 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2372 } 2373 2374 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2375 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2376 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2377 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2378 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2379 2380 if (!DecodeT2BROperand(Inst, brtarget, Address, Decoder) || 2381 !DecodePredicateOperand(Inst, pred, Address, Decoder)) 2382 return false; 2383 2384 return true; 2385 } 2386 2387 // Decode a shifted immediate operand. These basically consist 2388 // of an 8-bit value, and a 4-bit directive that specifies either 2389 // a splat operation or a rotation. 2390 static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2391 uint64_t Address, const void *Decoder) { 2392 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2393 if (ctrl == 0) { 2394 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2395 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2396 switch (byte) { 2397 case 0: 2398 Inst.addOperand(MCOperand::CreateImm(imm)); 2399 break; 2400 case 1: 2401 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2402 break; 2403 case 2: 2404 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2405 break; 2406 case 3: 2407 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2408 (imm << 8) | imm)); 2409 break; 2410 } 2411 } else { 2412 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2413 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2414 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2415 Inst.addOperand(MCOperand::CreateImm(imm)); 2416 } 2417 2418 return true; 2419 } 2420 2421 static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 2422 uint64_t Address, const void *Decoder){ 2423 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 2424 return true; 2425 } 2426 2427 static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 2428 uint64_t Address, const void *Decoder){ 2429 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2430 return true; 2431 } 2432 2433 static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Val, 2434 uint64_t Address, const void *Decoder) { 2435 bool isImm = fieldFromInstruction32(Val, 9, 1); 2436 bool isAdd = fieldFromInstruction32(Val, 8, 1); 2437 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2438 2439 if (!isImm) { 2440 if (!DecodeGPRRegisterClass(Inst, imm, Address, Decoder)) return false; 2441 Inst.addOperand(MCOperand::CreateImm(!isAdd << 8)); 2442 } else { 2443 Inst.addOperand(MCOperand::CreateReg(0)); 2444 Inst.addOperand(MCOperand::CreateImm(imm | (!isAdd << 8))); 2445 } 2446 2447 return true; 2448 } 2449 2450 static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 2451 uint64_t Address, const void *Decoder) { 2452 switch (Val) { 2453 default: 2454 return false; 2455 case 0xF: // SY 2456 case 0xE: // ST 2457 case 0xB: // ISH 2458 case 0xA: // ISHST 2459 case 0x7: // NSH 2460 case 0x6: // NSHST 2461 case 0x3: // OSH 2462 case 0x2: // OSHST 2463 break; 2464 } 2465 2466 Inst.addOperand(MCOperand::CreateImm(Val)); 2467 return true; 2468 } 2469 2470