1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARMDisassembler.h" 13 #include "ARM.h" 14 #include "ARMRegisterInfo.h" 15 #include "MCTargetDesc/ARMAddressingModes.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/Target/TargetRegistry.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/raw_ostream.h" 26 27 // Forward declare these because the autogenerated code will reference them. 28 // Definitions are further down. 29 static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 30 uint64_t Address, const void *Decoder); 31 static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 32 uint64_t Address, const void *Decoder); 33 static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 34 uint64_t Address, const void *Decoder); 35 static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 36 uint64_t Address, const void *Decoder); 37 static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 38 uint64_t Address, const void *Decoder); 39 static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 40 uint64_t Address, const void *Decoder); 41 static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 42 uint64_t Address, const void *Decoder); 43 static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 44 uint64_t Address, const void *Decoder); 45 static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 46 uint64_t Address, const void *Decoder); 47 static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 48 uint64_t Address, const void *Decoder); 49 50 static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 51 uint64_t Address, const void *Decoder); 52 static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 53 uint64_t Address, const void *Decoder); 54 static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 55 uint64_t Address, const void *Decoder); 56 static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 57 uint64_t Address, const void *Decoder); 58 static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 59 uint64_t Address, const void *Decoder); 60 static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 61 uint64_t Address, const void *Decoder); 62 static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 63 uint64_t Address, const void *Decoder); 64 65 static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 66 uint64_t Address, const void *Decoder); 67 static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 68 uint64_t Address, const void *Decoder); 69 static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 70 uint64_t Address, const void *Decoder); 71 static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 72 uint64_t Address, const void *Decoder); 73 static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 74 uint64_t Address, const void *Decoder); 75 static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 76 uint64_t Address, const void *Decoder); 77 static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 78 uint64_t Address, const void *Decoder); 79 80 static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 81 unsigned Insn, 82 uint64_t Adddress, 83 const void *Decoder); 84 static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 85 uint64_t Address, const void *Decoder); 86 static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 87 uint64_t Address, const void *Decoder); 88 static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 89 uint64_t Address, const void *Decoder); 90 static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 91 uint64_t Address, const void *Decoder); 92 static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 93 uint64_t Address, const void *Decoder); 94 static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 95 uint64_t Address, const void *Decoder); 96 static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 97 uint64_t Address, const void *Decoder); 98 static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 99 uint64_t Address, const void *Decoder); 100 static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 101 uint64_t Address, const void *Decoder); 102 static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 103 uint64_t Address, const void *Decoder); 104 static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 105 uint64_t Address, const void *Decoder); 106 static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 107 uint64_t Address, const void *Decoder); 108 static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 109 uint64_t Address, const void *Decoder); 110 static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 111 uint64_t Address, const void *Decoder); 112 static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Val, 113 uint64_t Address, const void *Decoder); 114 static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 115 uint64_t Address, const void *Decoder); 116 static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 117 uint64_t Address, const void *Decoder); 118 static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 119 uint64_t Address, const void *Decoder); 120 static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 121 uint64_t Address, const void *Decoder); 122 static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 123 uint64_t Address, const void *Decoder); 124 static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 125 uint64_t Address, const void *Decoder); 126 static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 127 uint64_t Address, const void *Decoder); 128 static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 129 uint64_t Address, const void *Decoder); 130 static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 131 uint64_t Address, const void *Decoder); 132 static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Insn, 133 uint64_t Address, const void *Decoder); 134 static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 135 uint64_t Address, const void *Decoder); 136 137 138 static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 139 uint64_t Address, const void *Decoder); 140 static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 141 uint64_t Address, const void *Decoder); 142 static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 143 uint64_t Address, const void *Decoder); 144 static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 145 uint64_t Address, const void *Decoder); 146 static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 147 uint64_t Address, const void *Decoder); 148 static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 149 uint64_t Address, const void *Decoder); 150 static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 151 uint64_t Address, const void *Decoder); 152 static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 153 uint64_t Address, const void *Decoder); 154 static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 155 uint64_t Address, const void *Decoder); 156 static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 157 uint64_t Address, const void *Decoder); 158 static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 159 uint64_t Address, const void *Decoder); 160 static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 161 uint64_t Address, const void *Decoder); 162 static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 163 uint64_t Address, const void *Decoder); 164 static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 165 uint64_t Address, const void *Decoder); 166 static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 167 uint64_t Address, const void *Decoder); 168 static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 169 uint64_t Address, const void *Decoder); 170 static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 171 uint64_t Address, const void *Decoder); 172 static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 173 uint64_t Address, const void *Decoder); 174 static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 175 uint64_t Address, const void *Decoder); 176 static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, 177 uint64_t Address, const void *Decoder); 178 static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 179 uint64_t Address, const void *Decoder); 180 static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 181 uint64_t Address, const void *Decoder); 182 static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 183 uint64_t Address, const void *Decoder); 184 static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 185 uint64_t Address, const void *Decoder); 186 187 #include "ARMGenDisassemblerTables.inc" 188 #include "ARMGenInstrInfo.inc" 189 #include "ARMGenEDInfo.inc" 190 191 using namespace llvm; 192 193 static MCDisassembler *createARMDisassembler(const Target &T) { 194 return new ARMDisassembler; 195 } 196 197 static MCDisassembler *createThumbDisassembler(const Target &T) { 198 return new ThumbDisassembler; 199 } 200 201 EDInstInfo *ARMDisassembler::getEDInfo() const { 202 return instInfoARM; 203 } 204 205 EDInstInfo *ThumbDisassembler::getEDInfo() const { 206 return instInfoARM; 207 } 208 209 210 bool ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 211 const MemoryObject &Region, 212 uint64_t Address,raw_ostream &os) const { 213 uint8_t bytes[4]; 214 215 // We want to read exactly 4 bytes of data. 216 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 217 return false; 218 219 // Encoded as a small-endian 32-bit word in the stream. 220 uint32_t insn = (bytes[3] << 24) | 221 (bytes[2] << 16) | 222 (bytes[1] << 8) | 223 (bytes[0] << 0); 224 225 // Calling the auto-generated decoder function. 226 bool result = decodeARMInstruction32(MI, insn, Address, this); 227 if (result) { 228 Size = 4; 229 return true; 230 } 231 232 // Instructions that are shared between ARM and Thumb modes. 233 // FIXME: This shouldn't really exist. It's an artifact of the 234 // fact that we fail to encode a few instructions properly for Thumb. 235 MI.clear(); 236 result = decodeCommonInstruction32(MI, insn, Address, this); 237 if (result) { 238 Size = 4; 239 return true; 240 } 241 242 // VFP and NEON instructions, similarly, are shared between ARM 243 // and Thumb modes. 244 MI.clear(); 245 result = decodeVFPInstruction32(MI, insn, Address, this); 246 if (result) { 247 Size = 4; 248 return true; 249 } 250 251 MI.clear(); 252 result = decodeNEONDataInstruction32(MI, insn, Address, this); 253 if (result) { 254 Size = 4; 255 // Add a fake predicate operand, because we share these instruction 256 // definitions with Thumb2 where these instructions are predicable. 257 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 258 return true; 259 } 260 261 MI.clear(); 262 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this); 263 if (result) { 264 Size = 4; 265 // Add a fake predicate operand, because we share these instruction 266 // definitions with Thumb2 where these instructions are predicable. 267 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 268 return true; 269 } 270 271 MI.clear(); 272 result = decodeNEONDupInstruction32(MI, insn, Address, this); 273 if (result) { 274 Size = 4; 275 // Add a fake predicate operand, because we share these instruction 276 // definitions with Thumb2 where these instructions are predicable. 277 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 278 return true; 279 } 280 281 MI.clear(); 282 283 return false; 284 } 285 286 namespace llvm { 287 extern MCInstrDesc ARMInsts[]; 288 } 289 290 // Thumb1 instructions don't have explicit S bits. Rather, they 291 // implicitly set CPSR. Since it's not represented in the encoding, the 292 // auto-generated decoder won't inject the CPSR operand. We need to fix 293 // that as a post-pass. 294 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 295 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 296 MCInst::iterator I = MI.begin(); 297 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 298 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 299 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 300 return; 301 } 302 } 303 304 if (OpInfo[MI.size()].isOptionalDef() && 305 OpInfo[MI.size()].RegClass == ARM::CCRRegClassID) 306 MI.insert(MI.end(), MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 307 } 308 309 // Most Thumb instructions don't have explicit predicates in the 310 // encoding, but rather get their predicates from IT context. We need 311 // to fix up the predicate operands using this context information as a 312 // post-pass. 313 void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 314 // A few instructions actually have predicates encoded in them. Don't 315 // try to overwrite it if we're seeing one of those. 316 switch (MI.getOpcode()) { 317 case ARM::tBcc: 318 case ARM::t2Bcc: 319 return; 320 default: 321 break; 322 } 323 324 // If we're in an IT block, base the predicate on that. Otherwise, 325 // assume a predicate of AL. 326 unsigned CC; 327 if (!ITBlock.empty()) { 328 CC = ITBlock.back(); 329 ITBlock.pop_back(); 330 } else 331 CC = ARMCC::AL; 332 333 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 334 MCInst::iterator I = MI.begin(); 335 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 336 if (OpInfo[i].isPredicate()) { 337 I = MI.insert(I, MCOperand::CreateImm(CC)); 338 ++I; 339 if (CC == ARMCC::AL) 340 MI.insert(I, MCOperand::CreateReg(0)); 341 else 342 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 343 return; 344 } 345 } 346 347 MI.insert(MI.end(), MCOperand::CreateImm(CC)); 348 if (CC == ARMCC::AL) 349 MI.insert(MI.end(), MCOperand::CreateReg(0)); 350 else 351 MI.insert(MI.end(), MCOperand::CreateReg(ARM::CPSR)); 352 } 353 354 // Thumb VFP instructions are a special case. Because we share their 355 // encodings between ARM and Thumb modes, and they are predicable in ARM 356 // mode, the auto-generated decoder will give them an (incorrect) 357 // predicate operand. We need to rewrite these operands based on the IT 358 // context as a post-pass. 359 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 360 unsigned CC; 361 if (!ITBlock.empty()) { 362 CC = ITBlock.back(); 363 ITBlock.pop_back(); 364 } else 365 CC = ARMCC::AL; 366 367 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 368 MCInst::iterator I = MI.begin(); 369 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 370 if (OpInfo[i].isPredicate() ) { 371 I->setImm(CC); 372 ++I; 373 if (CC == ARMCC::AL) 374 I->setReg(0); 375 else 376 I->setReg(ARM::CPSR); 377 return; 378 } 379 } 380 } 381 382 383 bool ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 384 const MemoryObject &Region, 385 uint64_t Address,raw_ostream &os) const { 386 uint8_t bytes[4]; 387 388 // We want to read exactly 2 bytes of data. 389 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) 390 return false; 391 392 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 393 bool result = decodeThumbInstruction16(MI, insn16, Address, this); 394 if (result) { 395 Size = 2; 396 bool InITBlock = !ITBlock.empty(); 397 AddThumbPredicate(MI); 398 AddThumb1SBit(MI, InITBlock); 399 return true; 400 } 401 402 MI.clear(); 403 result = decodeThumb2Instruction16(MI, insn16, Address, this); 404 if (result) { 405 Size = 2; 406 AddThumbPredicate(MI); 407 408 // If we find an IT instruction, we need to parse its condition 409 // code and mask operands so that we can apply them correctly 410 // to the subsequent instructions. 411 if (MI.getOpcode() == ARM::t2IT) { 412 unsigned firstcond = MI.getOperand(0).getImm(); 413 uint32_t mask = MI.getOperand(1).getImm(); 414 unsigned zeros = CountTrailingZeros_32(mask); 415 mask >>= zeros+1; 416 417 for (unsigned i = 0; i < 4 - (zeros+1); ++i) { 418 if (firstcond ^ (mask & 1)) 419 ITBlock.push_back(firstcond ^ 1); 420 else 421 ITBlock.push_back(firstcond); 422 mask >>= 1; 423 } 424 ITBlock.push_back(firstcond); 425 } 426 427 return true; 428 } 429 430 // We want to read exactly 4 bytes of data. 431 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 432 return false; 433 434 uint32_t insn32 = (bytes[3] << 8) | 435 (bytes[2] << 0) | 436 (bytes[1] << 24) | 437 (bytes[0] << 16); 438 MI.clear(); 439 result = decodeThumbInstruction32(MI, insn32, Address, this); 440 if (result) { 441 Size = 4; 442 bool InITBlock = ITBlock.size(); 443 AddThumbPredicate(MI); 444 AddThumb1SBit(MI, InITBlock); 445 return true; 446 } 447 448 MI.clear(); 449 result = decodeThumb2Instruction32(MI, insn32, Address, this); 450 if (result) { 451 Size = 4; 452 AddThumbPredicate(MI); 453 return true; 454 } 455 456 MI.clear(); 457 result = decodeCommonInstruction32(MI, insn32, Address, this); 458 if (result) { 459 Size = 4; 460 AddThumbPredicate(MI); 461 return true; 462 } 463 464 MI.clear(); 465 result = decodeVFPInstruction32(MI, insn32, Address, this); 466 if (result) { 467 Size = 4; 468 UpdateThumbVFPPredicate(MI); 469 return true; 470 } 471 472 MI.clear(); 473 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 474 uint32_t NEONDataInsn = insn32; 475 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 476 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 477 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 478 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this); 479 if (result) { 480 Size = 4; 481 AddThumbPredicate(MI); 482 return true; 483 } 484 } 485 486 MI.clear(); 487 result = decodeNEONLoadStoreInstruction32(MI, insn32, Address, this); 488 if (result) { 489 Size = 4; 490 AddThumbPredicate(MI); 491 return true; 492 } 493 494 MI.clear(); 495 result = decodeNEONDupInstruction32(MI, insn32, Address, this); 496 if (result) { 497 Size = 4; 498 AddThumbPredicate(MI); 499 return true; 500 } 501 502 return false; 503 } 504 505 506 extern "C" void LLVMInitializeARMDisassembler() { 507 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 508 createARMDisassembler); 509 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 510 createThumbDisassembler); 511 } 512 513 static const unsigned GPRDecoderTable[] = { 514 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 515 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 516 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 517 ARM::R12, ARM::SP, ARM::LR, ARM::PC 518 }; 519 520 static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 521 uint64_t Address, const void *Decoder) { 522 if (RegNo > 15) 523 return false; 524 525 unsigned Register = GPRDecoderTable[RegNo]; 526 Inst.addOperand(MCOperand::CreateReg(Register)); 527 return true; 528 } 529 530 static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 531 uint64_t Address, const void *Decoder) { 532 if (RegNo == 15) return false; 533 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 534 } 535 536 static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 537 uint64_t Address, const void *Decoder) { 538 if (RegNo > 7) 539 return false; 540 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 541 } 542 543 static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 544 uint64_t Address, const void *Decoder) { 545 unsigned Register = 0; 546 switch (RegNo) { 547 case 0: 548 Register = ARM::R0; 549 break; 550 case 1: 551 Register = ARM::R1; 552 break; 553 case 2: 554 Register = ARM::R2; 555 break; 556 case 3: 557 Register = ARM::R3; 558 break; 559 case 9: 560 Register = ARM::R9; 561 break; 562 case 12: 563 Register = ARM::R12; 564 break; 565 default: 566 return false; 567 } 568 569 Inst.addOperand(MCOperand::CreateReg(Register)); 570 return true; 571 } 572 573 static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 574 uint64_t Address, const void *Decoder) { 575 if (RegNo == 13 || RegNo == 15) return false; 576 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 577 } 578 579 static const unsigned SPRDecoderTable[] = { 580 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 581 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 582 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 583 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 584 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 585 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 586 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 587 ARM::S28, ARM::S29, ARM::S30, ARM::S31 588 }; 589 590 static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 591 uint64_t Address, const void *Decoder) { 592 if (RegNo > 31) 593 return false; 594 595 unsigned Register = SPRDecoderTable[RegNo]; 596 Inst.addOperand(MCOperand::CreateReg(Register)); 597 return true; 598 } 599 600 static const unsigned DPRDecoderTable[] = { 601 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 602 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 603 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 604 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 605 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 606 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 607 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 608 ARM::D28, ARM::D29, ARM::D30, ARM::D31 609 }; 610 611 static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 612 uint64_t Address, const void *Decoder) { 613 if (RegNo > 31) 614 return false; 615 616 unsigned Register = DPRDecoderTable[RegNo]; 617 Inst.addOperand(MCOperand::CreateReg(Register)); 618 return true; 619 } 620 621 static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 622 uint64_t Address, const void *Decoder) { 623 if (RegNo > 7) 624 return false; 625 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 626 } 627 628 static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 629 uint64_t Address, const void *Decoder) { 630 if (RegNo > 15) 631 return false; 632 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 633 } 634 635 static const unsigned QPRDecoderTable[] = { 636 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 637 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 638 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 639 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 640 }; 641 642 643 static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 644 uint64_t Address, const void *Decoder) { 645 if (RegNo > 31) 646 return false; 647 RegNo >>= 1; 648 649 unsigned Register = QPRDecoderTable[RegNo]; 650 Inst.addOperand(MCOperand::CreateReg(Register)); 651 return true; 652 } 653 654 static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 655 uint64_t Address, const void *Decoder) { 656 if (Val == 0xF) return false; 657 // AL predicate is not allowed on Thumb1 branches. 658 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 659 return false; 660 Inst.addOperand(MCOperand::CreateImm(Val)); 661 if (Val == ARMCC::AL) { 662 Inst.addOperand(MCOperand::CreateReg(0)); 663 } else 664 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 665 return true; 666 } 667 668 static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 669 uint64_t Address, const void *Decoder) { 670 if (Val) 671 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 672 else 673 Inst.addOperand(MCOperand::CreateReg(0)); 674 return true; 675 } 676 677 static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 678 uint64_t Address, const void *Decoder) { 679 uint32_t imm = Val & 0xFF; 680 uint32_t rot = (Val & 0xF00) >> 7; 681 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 682 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 683 return true; 684 } 685 686 static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 687 uint64_t Address, const void *Decoder) { 688 Val <<= 2; 689 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val))); 690 return true; 691 } 692 693 static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 694 uint64_t Address, const void *Decoder) { 695 696 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 697 unsigned type = fieldFromInstruction32(Val, 5, 2); 698 unsigned imm = fieldFromInstruction32(Val, 7, 5); 699 700 // Register-immediate 701 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 702 703 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 704 switch (type) { 705 case 0: 706 Shift = ARM_AM::lsl; 707 break; 708 case 1: 709 Shift = ARM_AM::lsr; 710 break; 711 case 2: 712 Shift = ARM_AM::asr; 713 break; 714 case 3: 715 Shift = ARM_AM::ror; 716 break; 717 } 718 719 if (Shift == ARM_AM::ror && imm == 0) 720 Shift = ARM_AM::rrx; 721 722 unsigned Op = Shift | (imm << 3); 723 Inst.addOperand(MCOperand::CreateImm(Op)); 724 725 return true; 726 } 727 728 static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 729 uint64_t Address, const void *Decoder) { 730 731 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 732 unsigned type = fieldFromInstruction32(Val, 5, 2); 733 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 734 735 // Register-register 736 if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; 737 if (!DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)) return false; 738 739 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 740 switch (type) { 741 case 0: 742 Shift = ARM_AM::lsl; 743 break; 744 case 1: 745 Shift = ARM_AM::lsr; 746 break; 747 case 2: 748 Shift = ARM_AM::asr; 749 break; 750 case 3: 751 Shift = ARM_AM::ror; 752 break; 753 } 754 755 Inst.addOperand(MCOperand::CreateImm(Shift)); 756 757 return true; 758 } 759 760 static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 761 uint64_t Address, const void *Decoder) { 762 for (unsigned i = 0; i < 16; ++i) { 763 if (Val & (1 << i)) 764 DecodeGPRRegisterClass(Inst, i, Address, Decoder); 765 } 766 767 return true; 768 } 769 770 static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 771 uint64_t Address, const void *Decoder) { 772 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 773 unsigned regs = Val & 0xFF; 774 775 DecodeSPRRegisterClass(Inst, Vd, Address, Decoder); 776 for (unsigned i = 0; i < (regs - 1); ++i) 777 DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder); 778 779 return true; 780 } 781 782 static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 783 uint64_t Address, const void *Decoder) { 784 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 785 unsigned regs = (Val & 0xFF) / 2; 786 787 DecodeDPRRegisterClass(Inst, Vd, Address, Decoder); 788 for (unsigned i = 0; i < (regs - 1); ++i) 789 DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder); 790 791 return true; 792 } 793 794 static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 795 uint64_t Address, const void *Decoder) { 796 // This operand encodes a mask of contiguous zeros between a specified MSB 797 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 798 // the mask of all bits LSB-and-lower, and then xor them to create 799 // the mask of that's all ones on [msb, lsb]. Finally we not it to 800 // create the final mask. 801 unsigned msb = fieldFromInstruction32(Val, 5, 5); 802 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 803 uint32_t msb_mask = (1 << (msb+1)) - 1; 804 uint32_t lsb_mask = (1 << lsb) - 1; 805 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 806 return true; 807 } 808 809 static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 810 uint64_t Address, const void *Decoder) { 811 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 812 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 813 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 814 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 815 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 816 unsigned U = fieldFromInstruction32(Insn, 23, 1); 817 818 switch (Inst.getOpcode()) { 819 case ARM::LDC_OFFSET: 820 case ARM::LDC_PRE: 821 case ARM::LDC_POST: 822 case ARM::LDC_OPTION: 823 case ARM::LDCL_OFFSET: 824 case ARM::LDCL_PRE: 825 case ARM::LDCL_POST: 826 case ARM::LDCL_OPTION: 827 case ARM::STC_OFFSET: 828 case ARM::STC_PRE: 829 case ARM::STC_POST: 830 case ARM::STC_OPTION: 831 case ARM::STCL_OFFSET: 832 case ARM::STCL_PRE: 833 case ARM::STCL_POST: 834 case ARM::STCL_OPTION: 835 if (coproc == 0xA || coproc == 0xB) 836 return false; 837 break; 838 default: 839 break; 840 } 841 842 Inst.addOperand(MCOperand::CreateImm(coproc)); 843 Inst.addOperand(MCOperand::CreateImm(CRd)); 844 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 845 switch (Inst.getOpcode()) { 846 case ARM::LDC_OPTION: 847 case ARM::LDCL_OPTION: 848 case ARM::LDC2_OPTION: 849 case ARM::LDC2L_OPTION: 850 case ARM::STC_OPTION: 851 case ARM::STCL_OPTION: 852 case ARM::STC2_OPTION: 853 case ARM::STC2L_OPTION: 854 case ARM::LDCL_POST: 855 case ARM::STCL_POST: 856 break; 857 default: 858 Inst.addOperand(MCOperand::CreateReg(0)); 859 break; 860 } 861 862 unsigned P = fieldFromInstruction32(Insn, 24, 1); 863 unsigned W = fieldFromInstruction32(Insn, 21, 1); 864 865 bool writeback = (P == 0) || (W == 1); 866 unsigned idx_mode = 0; 867 if (P && writeback) 868 idx_mode = ARMII::IndexModePre; 869 else if (!P && writeback) 870 idx_mode = ARMII::IndexModePost; 871 872 switch (Inst.getOpcode()) { 873 case ARM::LDCL_POST: 874 case ARM::STCL_POST: 875 imm |= U << 8; 876 case ARM::LDC_OPTION: 877 case ARM::LDCL_OPTION: 878 case ARM::LDC2_OPTION: 879 case ARM::LDC2L_OPTION: 880 case ARM::STC_OPTION: 881 case ARM::STCL_OPTION: 882 case ARM::STC2_OPTION: 883 case ARM::STC2L_OPTION: 884 Inst.addOperand(MCOperand::CreateImm(imm)); 885 break; 886 default: 887 if (U) 888 Inst.addOperand(MCOperand::CreateImm( 889 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 890 else 891 Inst.addOperand(MCOperand::CreateImm( 892 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 893 break; 894 } 895 896 switch (Inst.getOpcode()) { 897 case ARM::LDC_OFFSET: 898 case ARM::LDC_PRE: 899 case ARM::LDC_POST: 900 case ARM::LDC_OPTION: 901 case ARM::LDCL_OFFSET: 902 case ARM::LDCL_PRE: 903 case ARM::LDCL_POST: 904 case ARM::LDCL_OPTION: 905 case ARM::STC_OFFSET: 906 case ARM::STC_PRE: 907 case ARM::STC_POST: 908 case ARM::STC_OPTION: 909 case ARM::STCL_OFFSET: 910 case ARM::STCL_PRE: 911 case ARM::STCL_POST: 912 case ARM::STCL_OPTION: 913 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 914 break; 915 default: 916 break; 917 } 918 919 return true; 920 } 921 922 static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 923 uint64_t Address, const void *Decoder) { 924 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 925 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 926 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 927 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 928 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 929 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 930 unsigned P = fieldFromInstruction32(Insn, 24, 1); 931 unsigned W = fieldFromInstruction32(Insn, 21, 1); 932 933 // On stores, the writeback operand precedes Rt. 934 switch (Inst.getOpcode()) { 935 case ARM::STR_POST_IMM: 936 case ARM::STR_POST_REG: 937 case ARM::STRTr: 938 case ARM::STRTi: 939 case ARM::STRBTr: 940 case ARM::STRBTi: 941 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 942 break; 943 default: 944 break; 945 } 946 947 DecodeGPRRegisterClass(Inst, Rt, Address, Decoder); 948 949 // On loads, the writeback operand comes after Rt. 950 switch (Inst.getOpcode()) { 951 case ARM::LDR_POST_IMM: 952 case ARM::LDR_POST_REG: 953 case ARM::LDR_PRE: 954 case ARM::LDRBT_POST_REG: 955 case ARM::LDRBT_POST_IMM: 956 case ARM::LDRT_POST_REG: 957 case ARM::LDRT_POST_IMM: 958 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 959 break; 960 default: 961 break; 962 } 963 964 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 965 966 ARM_AM::AddrOpc Op = ARM_AM::add; 967 if (!fieldFromInstruction32(Insn, 23, 1)) 968 Op = ARM_AM::sub; 969 970 bool writeback = (P == 0) || (W == 1); 971 unsigned idx_mode = 0; 972 if (P && writeback) 973 idx_mode = ARMII::IndexModePre; 974 else if (!P && writeback) 975 idx_mode = ARMII::IndexModePost; 976 977 if (reg) { 978 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 979 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 980 switch( fieldFromInstruction32(Insn, 5, 2)) { 981 case 0: 982 Opc = ARM_AM::lsl; 983 break; 984 case 1: 985 Opc = ARM_AM::lsr; 986 break; 987 case 2: 988 Opc = ARM_AM::asr; 989 break; 990 case 3: 991 Opc = ARM_AM::ror; 992 break; 993 default: 994 return false; 995 } 996 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 997 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 998 999 Inst.addOperand(MCOperand::CreateImm(imm)); 1000 } else { 1001 Inst.addOperand(MCOperand::CreateReg(0)); 1002 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1003 Inst.addOperand(MCOperand::CreateImm(tmp)); 1004 } 1005 1006 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1007 1008 return true; 1009 } 1010 1011 static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1012 uint64_t Address, const void *Decoder) { 1013 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1014 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1015 unsigned type = fieldFromInstruction32(Val, 5, 2); 1016 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1017 unsigned U = fieldFromInstruction32(Val, 12, 1); 1018 1019 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1020 switch (type) { 1021 case 0: 1022 ShOp = ARM_AM::lsl; 1023 break; 1024 case 1: 1025 ShOp = ARM_AM::lsr; 1026 break; 1027 case 2: 1028 ShOp = ARM_AM::asr; 1029 break; 1030 case 3: 1031 ShOp = ARM_AM::ror; 1032 break; 1033 } 1034 1035 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1036 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 1037 unsigned shift; 1038 if (U) 1039 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1040 else 1041 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1042 Inst.addOperand(MCOperand::CreateImm(shift)); 1043 1044 return true; 1045 } 1046 1047 static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1048 uint64_t Address, const void *Decoder) { 1049 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1050 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1051 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1052 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1053 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1054 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1055 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1056 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1057 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1058 1059 bool writeback = (W == 1) | (P == 0); 1060 if (writeback) { // Writeback 1061 if (P) 1062 U |= ARMII::IndexModePre << 9; 1063 else 1064 U |= ARMII::IndexModePost << 9; 1065 1066 // On stores, the writeback operand precedes Rt. 1067 switch (Inst.getOpcode()) { 1068 case ARM::STRD: 1069 case ARM::STRD_PRE: 1070 case ARM::STRD_POST: 1071 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1072 break; 1073 default: 1074 break; 1075 } 1076 } 1077 1078 DecodeGPRRegisterClass(Inst, Rt, Address, Decoder); 1079 switch (Inst.getOpcode()) { 1080 case ARM::STRD: 1081 case ARM::STRD_PRE: 1082 case ARM::STRD_POST: 1083 case ARM::LDRD: 1084 case ARM::LDRD_PRE: 1085 case ARM::LDRD_POST: 1086 DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder); 1087 break; 1088 default: 1089 break; 1090 } 1091 1092 if (writeback) { 1093 // On loads, the writeback operand comes after Rt. 1094 switch (Inst.getOpcode()) { 1095 case ARM::LDRD: 1096 case ARM::LDRD_PRE: 1097 case ARM::LDRD_POST: 1098 case ARM::LDRHTr: 1099 case ARM::LDRSBTr: 1100 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1101 break; 1102 default: 1103 break; 1104 } 1105 } 1106 1107 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1108 1109 if (type) { 1110 Inst.addOperand(MCOperand::CreateReg(0)); 1111 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1112 } else { 1113 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 1114 Inst.addOperand(MCOperand::CreateImm(U)); 1115 } 1116 1117 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1118 1119 return true; 1120 } 1121 1122 static bool DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1123 uint64_t Address, const void *Decoder) { 1124 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1125 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1126 1127 switch (mode) { 1128 case 0: 1129 mode = ARM_AM::da; 1130 break; 1131 case 1: 1132 mode = ARM_AM::ia; 1133 break; 1134 case 2: 1135 mode = ARM_AM::db; 1136 break; 1137 case 3: 1138 mode = ARM_AM::ib; 1139 break; 1140 } 1141 1142 Inst.addOperand(MCOperand::CreateImm(mode)); 1143 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1144 1145 return true; 1146 } 1147 1148 static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1149 unsigned Insn, 1150 uint64_t Address, const void *Decoder) { 1151 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1152 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1153 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1154 1155 if (pred == 0xF) { 1156 switch (Inst.getOpcode()) { 1157 case ARM::STMDA: 1158 Inst.setOpcode(ARM::RFEDA); 1159 break; 1160 case ARM::STMDA_UPD: 1161 Inst.setOpcode(ARM::RFEDA_UPD); 1162 break; 1163 case ARM::STMDB: 1164 Inst.setOpcode(ARM::RFEDB); 1165 break; 1166 case ARM::STMDB_UPD: 1167 Inst.setOpcode(ARM::RFEDB_UPD); 1168 break; 1169 case ARM::STMIA: 1170 Inst.setOpcode(ARM::RFEIA); 1171 break; 1172 case ARM::STMIA_UPD: 1173 Inst.setOpcode(ARM::RFEIA_UPD); 1174 break; 1175 case ARM::STMIB: 1176 Inst.setOpcode(ARM::RFEIB); 1177 break; 1178 case ARM::STMIB_UPD: 1179 Inst.setOpcode(ARM::RFEIB_UPD); 1180 break; 1181 } 1182 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1183 } 1184 1185 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1186 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); // Tied 1187 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1188 DecodeRegListOperand(Inst, reglist, Address, Decoder); 1189 1190 return true; 1191 } 1192 1193 static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1194 uint64_t Address, const void *Decoder) { 1195 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1196 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1197 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1198 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1199 1200 // imod == '01' --> UNPREDICTABLE 1201 if (imod == 1) return false; 1202 1203 if (M && mode && imod && iflags) { 1204 Inst.setOpcode(ARM::CPS3p); 1205 Inst.addOperand(MCOperand::CreateImm(imod)); 1206 Inst.addOperand(MCOperand::CreateImm(iflags)); 1207 Inst.addOperand(MCOperand::CreateImm(mode)); 1208 return true; 1209 } else if (!mode && !M) { 1210 Inst.setOpcode(ARM::CPS2p); 1211 Inst.addOperand(MCOperand::CreateImm(imod)); 1212 Inst.addOperand(MCOperand::CreateImm(iflags)); 1213 return true; 1214 } else if (!imod && !iflags && M) { 1215 Inst.setOpcode(ARM::CPS1p); 1216 Inst.addOperand(MCOperand::CreateImm(mode)); 1217 return true; 1218 } 1219 1220 return false; 1221 } 1222 1223 static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1224 uint64_t Address, const void *Decoder) { 1225 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1226 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1227 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1228 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1229 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1230 1231 if (pred == 0xF) 1232 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1233 1234 DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder); 1235 DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder); 1236 DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder); 1237 DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder); 1238 1239 return true; 1240 } 1241 1242 static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1243 uint64_t Address, const void *Decoder) { 1244 unsigned add = fieldFromInstruction32(Val, 12, 1); 1245 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1246 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1247 1248 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1249 1250 if (!add) imm *= -1; 1251 if (imm == 0 && !add) imm = INT32_MIN; 1252 Inst.addOperand(MCOperand::CreateImm(imm)); 1253 1254 return true; 1255 } 1256 1257 static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1258 uint64_t Address, const void *Decoder) { 1259 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1260 unsigned U = fieldFromInstruction32(Val, 8, 1); 1261 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1262 1263 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1264 1265 if (U) 1266 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1267 else 1268 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1269 1270 return true; 1271 } 1272 1273 static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1274 uint64_t Address, const void *Decoder) { 1275 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1276 } 1277 1278 static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1279 uint64_t Address, const void *Decoder) { 1280 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1281 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1282 1283 if (pred == 0xF) { 1284 Inst.setOpcode(ARM::BLXi); 1285 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1286 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1287 return true; 1288 } 1289 1290 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1291 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1292 1293 return true; 1294 } 1295 1296 1297 static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1298 uint64_t Address, const void *Decoder) { 1299 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1300 return true; 1301 } 1302 1303 static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1304 uint64_t Address, const void *Decoder) { 1305 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1306 unsigned align = fieldFromInstruction32(Val, 4, 2); 1307 1308 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 1309 if (!align) 1310 Inst.addOperand(MCOperand::CreateImm(0)); 1311 else 1312 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1313 1314 return true; 1315 } 1316 1317 static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1318 uint64_t Address, const void *Decoder) { 1319 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1320 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1321 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1322 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1323 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1324 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1325 1326 // First output register 1327 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); 1328 1329 // Second output register 1330 switch (Inst.getOpcode()) { 1331 case ARM::VLD1q8: 1332 case ARM::VLD1q16: 1333 case ARM::VLD1q32: 1334 case ARM::VLD1q64: 1335 case ARM::VLD1q8_UPD: 1336 case ARM::VLD1q16_UPD: 1337 case ARM::VLD1q32_UPD: 1338 case ARM::VLD1q64_UPD: 1339 case ARM::VLD1d8T: 1340 case ARM::VLD1d16T: 1341 case ARM::VLD1d32T: 1342 case ARM::VLD1d64T: 1343 case ARM::VLD1d8T_UPD: 1344 case ARM::VLD1d16T_UPD: 1345 case ARM::VLD1d32T_UPD: 1346 case ARM::VLD1d64T_UPD: 1347 case ARM::VLD1d8Q: 1348 case ARM::VLD1d16Q: 1349 case ARM::VLD1d32Q: 1350 case ARM::VLD1d64Q: 1351 case ARM::VLD1d8Q_UPD: 1352 case ARM::VLD1d16Q_UPD: 1353 case ARM::VLD1d32Q_UPD: 1354 case ARM::VLD1d64Q_UPD: 1355 case ARM::VLD2d8: 1356 case ARM::VLD2d16: 1357 case ARM::VLD2d32: 1358 case ARM::VLD2d8_UPD: 1359 case ARM::VLD2d16_UPD: 1360 case ARM::VLD2d32_UPD: 1361 case ARM::VLD2q8: 1362 case ARM::VLD2q16: 1363 case ARM::VLD2q32: 1364 case ARM::VLD2q8_UPD: 1365 case ARM::VLD2q16_UPD: 1366 case ARM::VLD2q32_UPD: 1367 case ARM::VLD3d8: 1368 case ARM::VLD3d16: 1369 case ARM::VLD3d32: 1370 case ARM::VLD3d8_UPD: 1371 case ARM::VLD3d16_UPD: 1372 case ARM::VLD3d32_UPD: 1373 case ARM::VLD4d8: 1374 case ARM::VLD4d16: 1375 case ARM::VLD4d32: 1376 case ARM::VLD4d8_UPD: 1377 case ARM::VLD4d16_UPD: 1378 case ARM::VLD4d32_UPD: 1379 DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder); 1380 break; 1381 case ARM::VLD2b8: 1382 case ARM::VLD2b16: 1383 case ARM::VLD2b32: 1384 case ARM::VLD2b8_UPD: 1385 case ARM::VLD2b16_UPD: 1386 case ARM::VLD2b32_UPD: 1387 case ARM::VLD3q8: 1388 case ARM::VLD3q16: 1389 case ARM::VLD3q32: 1390 case ARM::VLD3q8_UPD: 1391 case ARM::VLD3q16_UPD: 1392 case ARM::VLD3q32_UPD: 1393 case ARM::VLD4q8: 1394 case ARM::VLD4q16: 1395 case ARM::VLD4q32: 1396 case ARM::VLD4q8_UPD: 1397 case ARM::VLD4q16_UPD: 1398 case ARM::VLD4q32_UPD: 1399 DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder); 1400 default: 1401 break; 1402 } 1403 1404 // Third output register 1405 switch(Inst.getOpcode()) { 1406 case ARM::VLD1d8T: 1407 case ARM::VLD1d16T: 1408 case ARM::VLD1d32T: 1409 case ARM::VLD1d64T: 1410 case ARM::VLD1d8T_UPD: 1411 case ARM::VLD1d16T_UPD: 1412 case ARM::VLD1d32T_UPD: 1413 case ARM::VLD1d64T_UPD: 1414 case ARM::VLD1d8Q: 1415 case ARM::VLD1d16Q: 1416 case ARM::VLD1d32Q: 1417 case ARM::VLD1d64Q: 1418 case ARM::VLD1d8Q_UPD: 1419 case ARM::VLD1d16Q_UPD: 1420 case ARM::VLD1d32Q_UPD: 1421 case ARM::VLD1d64Q_UPD: 1422 case ARM::VLD2q8: 1423 case ARM::VLD2q16: 1424 case ARM::VLD2q32: 1425 case ARM::VLD2q8_UPD: 1426 case ARM::VLD2q16_UPD: 1427 case ARM::VLD2q32_UPD: 1428 case ARM::VLD3d8: 1429 case ARM::VLD3d16: 1430 case ARM::VLD3d32: 1431 case ARM::VLD3d8_UPD: 1432 case ARM::VLD3d16_UPD: 1433 case ARM::VLD3d32_UPD: 1434 case ARM::VLD4d8: 1435 case ARM::VLD4d16: 1436 case ARM::VLD4d32: 1437 case ARM::VLD4d8_UPD: 1438 case ARM::VLD4d16_UPD: 1439 case ARM::VLD4d32_UPD: 1440 DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder); 1441 break; 1442 case ARM::VLD3q8: 1443 case ARM::VLD3q16: 1444 case ARM::VLD3q32: 1445 case ARM::VLD3q8_UPD: 1446 case ARM::VLD3q16_UPD: 1447 case ARM::VLD3q32_UPD: 1448 case ARM::VLD4q8: 1449 case ARM::VLD4q16: 1450 case ARM::VLD4q32: 1451 case ARM::VLD4q8_UPD: 1452 case ARM::VLD4q16_UPD: 1453 case ARM::VLD4q32_UPD: 1454 DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder); 1455 break; 1456 default: 1457 break; 1458 } 1459 1460 // Fourth output register 1461 switch (Inst.getOpcode()) { 1462 case ARM::VLD1d8Q: 1463 case ARM::VLD1d16Q: 1464 case ARM::VLD1d32Q: 1465 case ARM::VLD1d64Q: 1466 case ARM::VLD1d8Q_UPD: 1467 case ARM::VLD1d16Q_UPD: 1468 case ARM::VLD1d32Q_UPD: 1469 case ARM::VLD1d64Q_UPD: 1470 case ARM::VLD2q8: 1471 case ARM::VLD2q16: 1472 case ARM::VLD2q32: 1473 case ARM::VLD2q8_UPD: 1474 case ARM::VLD2q16_UPD: 1475 case ARM::VLD2q32_UPD: 1476 case ARM::VLD4d8: 1477 case ARM::VLD4d16: 1478 case ARM::VLD4d32: 1479 case ARM::VLD4d8_UPD: 1480 case ARM::VLD4d16_UPD: 1481 case ARM::VLD4d32_UPD: 1482 DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder); 1483 break; 1484 case ARM::VLD4q8: 1485 case ARM::VLD4q16: 1486 case ARM::VLD4q32: 1487 case ARM::VLD4q8_UPD: 1488 case ARM::VLD4q16_UPD: 1489 case ARM::VLD4q32_UPD: 1490 DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder); 1491 break; 1492 default: 1493 break; 1494 } 1495 1496 // Writeback operand 1497 switch (Inst.getOpcode()) { 1498 case ARM::VLD1d8_UPD: 1499 case ARM::VLD1d16_UPD: 1500 case ARM::VLD1d32_UPD: 1501 case ARM::VLD1d64_UPD: 1502 case ARM::VLD1q8_UPD: 1503 case ARM::VLD1q16_UPD: 1504 case ARM::VLD1q32_UPD: 1505 case ARM::VLD1q64_UPD: 1506 case ARM::VLD1d8T_UPD: 1507 case ARM::VLD1d16T_UPD: 1508 case ARM::VLD1d32T_UPD: 1509 case ARM::VLD1d64T_UPD: 1510 case ARM::VLD1d8Q_UPD: 1511 case ARM::VLD1d16Q_UPD: 1512 case ARM::VLD1d32Q_UPD: 1513 case ARM::VLD1d64Q_UPD: 1514 case ARM::VLD2d8_UPD: 1515 case ARM::VLD2d16_UPD: 1516 case ARM::VLD2d32_UPD: 1517 case ARM::VLD2q8_UPD: 1518 case ARM::VLD2q16_UPD: 1519 case ARM::VLD2q32_UPD: 1520 case ARM::VLD2b8_UPD: 1521 case ARM::VLD2b16_UPD: 1522 case ARM::VLD2b32_UPD: 1523 case ARM::VLD3d8_UPD: 1524 case ARM::VLD3d16_UPD: 1525 case ARM::VLD3d32_UPD: 1526 case ARM::VLD3q8_UPD: 1527 case ARM::VLD3q16_UPD: 1528 case ARM::VLD3q32_UPD: 1529 case ARM::VLD4d8_UPD: 1530 case ARM::VLD4d16_UPD: 1531 case ARM::VLD4d32_UPD: 1532 case ARM::VLD4q8_UPD: 1533 case ARM::VLD4q16_UPD: 1534 case ARM::VLD4q32_UPD: 1535 DecodeGPRRegisterClass(Inst, wb, Address, Decoder); 1536 break; 1537 default: 1538 break; 1539 } 1540 1541 // AddrMode6 Base (register+alignment) 1542 DecodeAddrMode6Operand(Inst, Rn, Address, Decoder); 1543 1544 // AddrMode6 Offset (register) 1545 if (Rm == 0xD) 1546 Inst.addOperand(MCOperand::CreateReg(0)); 1547 else if (Rm != 0xF) 1548 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 1549 1550 return true; 1551 } 1552 1553 static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1554 uint64_t Address, const void *Decoder) { 1555 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1556 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1557 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1558 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1559 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1560 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1561 1562 // Writeback Operand 1563 switch (Inst.getOpcode()) { 1564 case ARM::VST1d8_UPD: 1565 case ARM::VST1d16_UPD: 1566 case ARM::VST1d32_UPD: 1567 case ARM::VST1d64_UPD: 1568 case ARM::VST1q8_UPD: 1569 case ARM::VST1q16_UPD: 1570 case ARM::VST1q32_UPD: 1571 case ARM::VST1q64_UPD: 1572 case ARM::VST1d8T_UPD: 1573 case ARM::VST1d16T_UPD: 1574 case ARM::VST1d32T_UPD: 1575 case ARM::VST1d64T_UPD: 1576 case ARM::VST1d8Q_UPD: 1577 case ARM::VST1d16Q_UPD: 1578 case ARM::VST1d32Q_UPD: 1579 case ARM::VST1d64Q_UPD: 1580 case ARM::VST2d8_UPD: 1581 case ARM::VST2d16_UPD: 1582 case ARM::VST2d32_UPD: 1583 case ARM::VST2q8_UPD: 1584 case ARM::VST2q16_UPD: 1585 case ARM::VST2q32_UPD: 1586 case ARM::VST2b8_UPD: 1587 case ARM::VST2b16_UPD: 1588 case ARM::VST2b32_UPD: 1589 case ARM::VST3d8_UPD: 1590 case ARM::VST3d16_UPD: 1591 case ARM::VST3d32_UPD: 1592 case ARM::VST3q8_UPD: 1593 case ARM::VST3q16_UPD: 1594 case ARM::VST3q32_UPD: 1595 case ARM::VST4d8_UPD: 1596 case ARM::VST4d16_UPD: 1597 case ARM::VST4d32_UPD: 1598 case ARM::VST4q8_UPD: 1599 case ARM::VST4q16_UPD: 1600 case ARM::VST4q32_UPD: 1601 DecodeGPRRegisterClass(Inst, wb, Address, Decoder); 1602 break; 1603 default: 1604 break; 1605 } 1606 1607 // AddrMode6 Base (register+alignment) 1608 DecodeAddrMode6Operand(Inst, Rn, Address, Decoder); 1609 1610 // AddrMode6 Offset (register) 1611 if (Rm == 0xD) 1612 Inst.addOperand(MCOperand::CreateReg(0)); 1613 else if (Rm != 0xF) 1614 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 1615 1616 // First input register 1617 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); 1618 1619 // Second input register 1620 switch (Inst.getOpcode()) { 1621 case ARM::VST1q8: 1622 case ARM::VST1q16: 1623 case ARM::VST1q32: 1624 case ARM::VST1q64: 1625 case ARM::VST1q8_UPD: 1626 case ARM::VST1q16_UPD: 1627 case ARM::VST1q32_UPD: 1628 case ARM::VST1q64_UPD: 1629 case ARM::VST1d8T: 1630 case ARM::VST1d16T: 1631 case ARM::VST1d32T: 1632 case ARM::VST1d64T: 1633 case ARM::VST1d8T_UPD: 1634 case ARM::VST1d16T_UPD: 1635 case ARM::VST1d32T_UPD: 1636 case ARM::VST1d64T_UPD: 1637 case ARM::VST1d8Q: 1638 case ARM::VST1d16Q: 1639 case ARM::VST1d32Q: 1640 case ARM::VST1d64Q: 1641 case ARM::VST1d8Q_UPD: 1642 case ARM::VST1d16Q_UPD: 1643 case ARM::VST1d32Q_UPD: 1644 case ARM::VST1d64Q_UPD: 1645 case ARM::VST2d8: 1646 case ARM::VST2d16: 1647 case ARM::VST2d32: 1648 case ARM::VST2d8_UPD: 1649 case ARM::VST2d16_UPD: 1650 case ARM::VST2d32_UPD: 1651 case ARM::VST2q8: 1652 case ARM::VST2q16: 1653 case ARM::VST2q32: 1654 case ARM::VST2q8_UPD: 1655 case ARM::VST2q16_UPD: 1656 case ARM::VST2q32_UPD: 1657 case ARM::VST3d8: 1658 case ARM::VST3d16: 1659 case ARM::VST3d32: 1660 case ARM::VST3d8_UPD: 1661 case ARM::VST3d16_UPD: 1662 case ARM::VST3d32_UPD: 1663 case ARM::VST4d8: 1664 case ARM::VST4d16: 1665 case ARM::VST4d32: 1666 case ARM::VST4d8_UPD: 1667 case ARM::VST4d16_UPD: 1668 case ARM::VST4d32_UPD: 1669 DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder); 1670 break; 1671 case ARM::VST2b8: 1672 case ARM::VST2b16: 1673 case ARM::VST2b32: 1674 case ARM::VST2b8_UPD: 1675 case ARM::VST2b16_UPD: 1676 case ARM::VST2b32_UPD: 1677 case ARM::VST3q8: 1678 case ARM::VST3q16: 1679 case ARM::VST3q32: 1680 case ARM::VST3q8_UPD: 1681 case ARM::VST3q16_UPD: 1682 case ARM::VST3q32_UPD: 1683 case ARM::VST4q8: 1684 case ARM::VST4q16: 1685 case ARM::VST4q32: 1686 case ARM::VST4q8_UPD: 1687 case ARM::VST4q16_UPD: 1688 case ARM::VST4q32_UPD: 1689 DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder); 1690 break; 1691 default: 1692 break; 1693 } 1694 1695 // Third input register 1696 switch (Inst.getOpcode()) { 1697 case ARM::VST1d8T: 1698 case ARM::VST1d16T: 1699 case ARM::VST1d32T: 1700 case ARM::VST1d64T: 1701 case ARM::VST1d8T_UPD: 1702 case ARM::VST1d16T_UPD: 1703 case ARM::VST1d32T_UPD: 1704 case ARM::VST1d64T_UPD: 1705 case ARM::VST1d8Q: 1706 case ARM::VST1d16Q: 1707 case ARM::VST1d32Q: 1708 case ARM::VST1d64Q: 1709 case ARM::VST1d8Q_UPD: 1710 case ARM::VST1d16Q_UPD: 1711 case ARM::VST1d32Q_UPD: 1712 case ARM::VST1d64Q_UPD: 1713 case ARM::VST2q8: 1714 case ARM::VST2q16: 1715 case ARM::VST2q32: 1716 case ARM::VST2q8_UPD: 1717 case ARM::VST2q16_UPD: 1718 case ARM::VST2q32_UPD: 1719 case ARM::VST3d8: 1720 case ARM::VST3d16: 1721 case ARM::VST3d32: 1722 case ARM::VST3d8_UPD: 1723 case ARM::VST3d16_UPD: 1724 case ARM::VST3d32_UPD: 1725 case ARM::VST4d8: 1726 case ARM::VST4d16: 1727 case ARM::VST4d32: 1728 case ARM::VST4d8_UPD: 1729 case ARM::VST4d16_UPD: 1730 case ARM::VST4d32_UPD: 1731 DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder); 1732 break; 1733 case ARM::VST3q8: 1734 case ARM::VST3q16: 1735 case ARM::VST3q32: 1736 case ARM::VST3q8_UPD: 1737 case ARM::VST3q16_UPD: 1738 case ARM::VST3q32_UPD: 1739 case ARM::VST4q8: 1740 case ARM::VST4q16: 1741 case ARM::VST4q32: 1742 case ARM::VST4q8_UPD: 1743 case ARM::VST4q16_UPD: 1744 case ARM::VST4q32_UPD: 1745 DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder); 1746 break; 1747 default: 1748 break; 1749 } 1750 1751 // Fourth input register 1752 switch (Inst.getOpcode()) { 1753 case ARM::VST1d8Q: 1754 case ARM::VST1d16Q: 1755 case ARM::VST1d32Q: 1756 case ARM::VST1d64Q: 1757 case ARM::VST1d8Q_UPD: 1758 case ARM::VST1d16Q_UPD: 1759 case ARM::VST1d32Q_UPD: 1760 case ARM::VST1d64Q_UPD: 1761 case ARM::VST2q8: 1762 case ARM::VST2q16: 1763 case ARM::VST2q32: 1764 case ARM::VST2q8_UPD: 1765 case ARM::VST2q16_UPD: 1766 case ARM::VST2q32_UPD: 1767 case ARM::VST4d8: 1768 case ARM::VST4d16: 1769 case ARM::VST4d32: 1770 case ARM::VST4d8_UPD: 1771 case ARM::VST4d16_UPD: 1772 case ARM::VST4d32_UPD: 1773 DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder); 1774 break; 1775 case ARM::VST4q8: 1776 case ARM::VST4q16: 1777 case ARM::VST4q32: 1778 case ARM::VST4q8_UPD: 1779 case ARM::VST4q16_UPD: 1780 case ARM::VST4q32_UPD: 1781 DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder); 1782 break; 1783 default: 1784 break; 1785 } 1786 1787 return true; 1788 } 1789 1790 static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1791 uint64_t Address, const void *Decoder) { 1792 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1793 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1794 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1795 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1796 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1797 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1798 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 1799 1800 align *= (1 << size); 1801 1802 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); 1803 if (regs == 2) DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder); 1804 if (Rm == 0xD) DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1805 1806 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1807 Inst.addOperand(MCOperand::CreateImm(align)); 1808 1809 if (Rm == 0xD) 1810 Inst.addOperand(MCOperand::CreateReg(0)); 1811 else if (Rm != 0xF) 1812 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 1813 1814 return true; 1815 } 1816 1817 static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1818 uint64_t Address, const void *Decoder) { 1819 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1820 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1821 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1822 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1823 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1824 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 1825 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1826 align *= 2*size; 1827 1828 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); 1829 DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder); 1830 if (Rm == 0xD) DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1831 1832 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1833 Inst.addOperand(MCOperand::CreateImm(align)); 1834 1835 if (Rm == 0xD) 1836 Inst.addOperand(MCOperand::CreateReg(0)); 1837 else if (Rm != 0xF) 1838 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 1839 1840 return true; 1841 } 1842 1843 static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1844 uint64_t Address, const void *Decoder) { 1845 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1846 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1847 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1848 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1849 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1850 1851 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); 1852 DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder); 1853 DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder); 1854 if (Rm == 0xD) DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1855 1856 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1857 Inst.addOperand(MCOperand::CreateImm(0)); 1858 1859 if (Rm == 0xD) 1860 Inst.addOperand(MCOperand::CreateReg(0)); 1861 else if (Rm != 0xF) 1862 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 1863 1864 return true; 1865 } 1866 1867 static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1868 uint64_t Address, const void *Decoder) { 1869 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1870 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1871 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1872 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1873 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1874 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1875 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1876 1877 if (size == 0x3) { 1878 size = 4; 1879 align = 16; 1880 } else { 1881 if (size == 2) { 1882 size = 1 << size; 1883 align *= 8; 1884 } else { 1885 size = 1 << size; 1886 align *= 4*size; 1887 } 1888 } 1889 1890 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); 1891 DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder); 1892 DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder); 1893 DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder); 1894 if (Rm == 0xD) DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1895 1896 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1897 Inst.addOperand(MCOperand::CreateImm(align)); 1898 1899 if (Rm == 0xD) 1900 Inst.addOperand(MCOperand::CreateReg(0)); 1901 else if (Rm != 0xF) 1902 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 1903 1904 return true; 1905 } 1906 1907 static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1908 uint64_t Address, const void *Decoder) { 1909 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1910 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1911 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 1912 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 1913 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 1914 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 1915 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 1916 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 1917 1918 if (Q) 1919 DecodeQPRRegisterClass(Inst, Rd, Address, Decoder); 1920 else 1921 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); 1922 1923 Inst.addOperand(MCOperand::CreateImm(imm)); 1924 1925 switch (Inst.getOpcode()) { 1926 case ARM::VORRiv4i16: 1927 case ARM::VORRiv2i32: 1928 case ARM::VBICiv4i16: 1929 case ARM::VBICiv2i32: 1930 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); 1931 break; 1932 case ARM::VORRiv8i16: 1933 case ARM::VORRiv4i32: 1934 case ARM::VBICiv8i16: 1935 case ARM::VBICiv4i32: 1936 DecodeQPRRegisterClass(Inst, Rd, Address, Decoder); 1937 break; 1938 default: 1939 break; 1940 } 1941 1942 return true; 1943 } 1944 1945 static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 1946 uint64_t Address, const void *Decoder) { 1947 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1948 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1949 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1950 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 1951 unsigned size = fieldFromInstruction32(Insn, 18, 2); 1952 1953 DecodeQPRRegisterClass(Inst, Rd, Address, Decoder); 1954 DecodeDPRRegisterClass(Inst, Rm, Address, Decoder); 1955 Inst.addOperand(MCOperand::CreateImm(8 << size)); 1956 1957 return true; 1958 } 1959 1960 static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 1961 uint64_t Address, const void *Decoder) { 1962 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 1963 return true; 1964 } 1965 1966 static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 1967 uint64_t Address, const void *Decoder) { 1968 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 1969 return true; 1970 } 1971 1972 static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 1973 uint64_t Address, const void *Decoder) { 1974 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 1975 return true; 1976 } 1977 1978 static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 1979 uint64_t Address, const void *Decoder) { 1980 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1981 return true; 1982 } 1983 1984 static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 1985 uint64_t Address, const void *Decoder) { 1986 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1987 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1988 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1989 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 1990 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1991 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 1992 unsigned op = fieldFromInstruction32(Insn, 6, 1); 1993 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 1994 1995 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); 1996 if (op) DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); // Writeback 1997 1998 for (unsigned i = 0; i < length; ++i) 1999 DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder); 2000 2001 DecodeDPRRegisterClass(Inst, Rm, Address, Decoder); 2002 2003 return true; 2004 } 2005 2006 static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 2007 uint64_t Address, const void *Decoder) { 2008 // The immediate needs to be a fully instantiated float. However, the 2009 // auto-generated decoder is only able to fill in some of the bits 2010 // necessary. For instance, the 'b' bit is replicated multiple times, 2011 // and is even present in inverted form in one bit. We do a little 2012 // binary parsing here to fill in those missing bits, and then 2013 // reinterpret it all as a float. 2014 union { 2015 uint32_t integer; 2016 float fp; 2017 } fp_conv; 2018 2019 fp_conv.integer = Val; 2020 uint32_t b = fieldFromInstruction32(Val, 25, 1); 2021 fp_conv.integer |= b << 26; 2022 fp_conv.integer |= b << 27; 2023 fp_conv.integer |= b << 28; 2024 fp_conv.integer |= b << 29; 2025 fp_conv.integer |= (~b & 0x1) << 30; 2026 2027 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 2028 return true; 2029 } 2030 2031 static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2032 uint64_t Address, const void *Decoder) { 2033 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2034 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2035 2036 DecodetGPRRegisterClass(Inst, dst, Address, Decoder); 2037 2038 if (Inst.getOpcode() == ARM::tADR) 2039 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2040 else if (Inst.getOpcode() == ARM::tADDrSPi) 2041 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2042 else 2043 return false; 2044 2045 Inst.addOperand(MCOperand::CreateImm(imm)); 2046 return true; 2047 } 2048 2049 static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2050 uint64_t Address, const void *Decoder) { 2051 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2052 return true; 2053 } 2054 2055 static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2056 uint64_t Address, const void *Decoder) { 2057 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2058 return true; 2059 } 2060 2061 static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2062 uint64_t Address, const void *Decoder) { 2063 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2064 return true; 2065 } 2066 2067 static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2068 uint64_t Address, const void *Decoder) { 2069 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2070 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2071 2072 DecodetGPRRegisterClass(Inst, Rn, Address, Decoder); 2073 DecodetGPRRegisterClass(Inst, Rm, Address, Decoder); 2074 2075 return true; 2076 } 2077 2078 static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2079 uint64_t Address, const void *Decoder) { 2080 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2081 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2082 2083 DecodetGPRRegisterClass(Inst, Rn, Address, Decoder); 2084 Inst.addOperand(MCOperand::CreateImm(imm)); 2085 2086 return true; 2087 } 2088 2089 static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2090 uint64_t Address, const void *Decoder) { 2091 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2092 2093 return true; 2094 } 2095 2096 static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2097 uint64_t Address, const void *Decoder) { 2098 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2099 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2100 2101 return true; 2102 } 2103 2104 static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2105 uint64_t Address, const void *Decoder) { 2106 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2107 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2108 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2109 2110 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 2111 DecoderGPRRegisterClass(Inst, Rm, Address, Decoder); 2112 Inst.addOperand(MCOperand::CreateImm(imm)); 2113 2114 return true; 2115 } 2116 2117 static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2118 uint64_t Address, const void *Decoder) { 2119 if (Inst.getOpcode() != ARM::t2PLDs) { 2120 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2121 DecodeGPRRegisterClass(Inst, Rt, Address, Decoder); 2122 } 2123 2124 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2125 if (Rn == 0xF) { 2126 switch (Inst.getOpcode()) { 2127 case ARM::t2LDRBs: 2128 Inst.setOpcode(ARM::t2LDRBpci); 2129 break; 2130 case ARM::t2LDRHs: 2131 Inst.setOpcode(ARM::t2LDRHpci); 2132 break; 2133 case ARM::t2LDRSHs: 2134 Inst.setOpcode(ARM::t2LDRSHpci); 2135 break; 2136 case ARM::t2LDRSBs: 2137 Inst.setOpcode(ARM::t2LDRSBpci); 2138 break; 2139 case ARM::t2PLDs: 2140 Inst.setOpcode(ARM::t2PLDi12); 2141 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2142 break; 2143 default: 2144 return false; 2145 } 2146 2147 int imm = fieldFromInstruction32(Insn, 0, 12); 2148 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2149 Inst.addOperand(MCOperand::CreateImm(imm)); 2150 2151 return true; 2152 } 2153 2154 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2155 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2156 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2157 DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder); 2158 2159 return true; 2160 } 2161 2162 static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2163 uint64_t Address, const void *Decoder) { 2164 int imm = Val & 0xFF; 2165 if (!(Val & 0x100)) imm *= -1; 2166 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2167 2168 return true; 2169 } 2170 2171 static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2172 uint64_t Address, const void *Decoder) { 2173 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2174 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2175 2176 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 2177 DecodeT2Imm8S4(Inst, imm, Address, Decoder); 2178 2179 return true; 2180 } 2181 2182 static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2183 uint64_t Address, const void *Decoder) { 2184 int imm = Val & 0xFF; 2185 if (!(Val & 0x100)) imm *= -1; 2186 Inst.addOperand(MCOperand::CreateImm(imm)); 2187 2188 return true; 2189 } 2190 2191 2192 static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2193 uint64_t Address, const void *Decoder) { 2194 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2195 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2196 2197 // Some instructions always use an additive offset. 2198 switch (Inst.getOpcode()) { 2199 case ARM::t2LDRT: 2200 case ARM::t2LDRBT: 2201 case ARM::t2LDRHT: 2202 case ARM::t2LDRSBT: 2203 case ARM::t2LDRSHT: 2204 imm |= 0x100; 2205 break; 2206 default: 2207 break; 2208 } 2209 2210 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 2211 DecodeT2Imm8(Inst, imm, Address, Decoder); 2212 2213 return true; 2214 } 2215 2216 2217 static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2218 uint64_t Address, const void *Decoder) { 2219 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2220 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2221 2222 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 2223 Inst.addOperand(MCOperand::CreateImm(imm)); 2224 2225 return true; 2226 } 2227 2228 2229 static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2230 uint64_t Address, const void *Decoder) { 2231 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2232 2233 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2234 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2235 Inst.addOperand(MCOperand::CreateImm(imm)); 2236 2237 return true; 2238 } 2239 2240 static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2241 uint64_t Address, const void *Decoder) { 2242 if (Inst.getOpcode() == ARM::tADDrSP) { 2243 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2244 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2245 2246 DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder); 2247 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2248 DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder); 2249 } else if (Inst.getOpcode() == ARM::tADDspr) { 2250 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2251 2252 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2253 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2254 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 2255 } 2256 2257 return true; 2258 } 2259 2260 static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2261 uint64_t Address, const void *Decoder) { 2262 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2263 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2264 2265 Inst.addOperand(MCOperand::CreateImm(imod)); 2266 Inst.addOperand(MCOperand::CreateImm(flags)); 2267 2268 return true; 2269 } 2270 2271 static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2272 uint64_t Address, const void *Decoder) { 2273 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2274 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2275 2276 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 2277 Inst.addOperand(MCOperand::CreateImm(add)); 2278 2279 return true; 2280 } 2281 2282 static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2283 uint64_t Address, const void *Decoder) { 2284 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2285 return true; 2286 } 2287 2288 static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2289 uint64_t Address, const void *Decoder) { 2290 if (Val == 0xA || Val == 0xB) 2291 return false; 2292 2293 Inst.addOperand(MCOperand::CreateImm(Val)); 2294 return true; 2295 } 2296 2297 static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, 2298 uint64_t Address, const void *Decoder) { 2299 if (Val == 0) 2300 Inst.addOperand(MCOperand::CreateImm(32)); 2301 else 2302 Inst.addOperand(MCOperand::CreateImm(Val)); 2303 return true; 2304 } 2305 2306 static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2307 uint64_t Address, const void *Decoder) { 2308 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2309 if (pred == 0xE || pred == 0xF) { 2310 unsigned opc = fieldFromInstruction32(Insn, 4, 2); 2311 switch (opc) { 2312 default: 2313 return false; 2314 case 0: 2315 Inst.setOpcode(ARM::t2DSB); 2316 break; 2317 case 1: 2318 Inst.setOpcode(ARM::t2DMB); 2319 break; 2320 case 2: 2321 Inst.setOpcode(ARM::t2ISB); 2322 return true; 2323 } 2324 2325 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2326 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2327 } 2328 2329 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2330 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2331 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2332 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2333 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2334 2335 DecodeT2BROperand(Inst, brtarget, Address, Decoder); 2336 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) 2337 return false; 2338 2339 return true; 2340 } 2341 2342 // Decode a shifted immediate operand. These basically consist 2343 // of an 8-bit value, and a 4-bit directive that specifies either 2344 // a splat operation or a rotation. 2345 static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2346 uint64_t Address, const void *Decoder) { 2347 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2348 if (ctrl == 0) { 2349 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2350 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2351 switch (byte) { 2352 case 0: 2353 Inst.addOperand(MCOperand::CreateImm(imm)); 2354 break; 2355 case 1: 2356 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2357 break; 2358 case 2: 2359 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2360 break; 2361 case 3: 2362 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2363 (imm << 8) | imm)); 2364 break; 2365 } 2366 } else { 2367 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2368 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2369 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2370 Inst.addOperand(MCOperand::CreateImm(imm)); 2371 } 2372 2373 return true; 2374 } 2375 2376 static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 2377 uint64_t Address, const void *Decoder){ 2378 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 2379 return true; 2380 } 2381 2382 static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 2383 uint64_t Address, const void *Decoder){ 2384 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2385 return true; 2386 } 2387 2388 static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Val, 2389 uint64_t Address, const void *Decoder) { 2390 bool isImm = fieldFromInstruction32(Val, 9, 1); 2391 bool isAdd = fieldFromInstruction32(Val, 8, 1); 2392 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2393 2394 if (!isImm) { 2395 DecodeGPRRegisterClass(Inst, imm, Address, Decoder); 2396 Inst.addOperand(MCOperand::CreateImm(!isAdd << 8)); 2397 } else { 2398 Inst.addOperand(MCOperand::CreateReg(0)); 2399 Inst.addOperand(MCOperand::CreateImm(imm | (!isAdd << 8))); 2400 } 2401 2402 return true; 2403 } 2404 2405 static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 2406 uint64_t Address, const void *Decoder) { 2407 switch (Val) { 2408 default: 2409 return false; 2410 case 0xF: // SY 2411 case 0xE: // ST 2412 case 0xB: // ISH 2413 case 0xA: // ISHST 2414 case 0x7: // NSH 2415 case 0x6: // NSHST 2416 case 0x3: // OSH 2417 case 0x2: // OSHST 2418 break; 2419 } 2420 2421 Inst.addOperand(MCOperand::CreateImm(Val)); 2422 return true; 2423 } 2424 2425