whitespace

llvm-svn: 197413

Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size.

llvm-svn: 186274

Use the new script to sort the includes of every file under lib.

Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module

Use the new script to sort the includes of every file under lib.

Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

llvm-svn: 169131

show more ...

CSE: allow PerformTrivialCoalescing to check copies across basic block
boundaries.

Given the following case:
BB0
%vreg1<def> = SUBrr %vreg0, %vreg7
%vreg2<def> = COPY %vreg7
BB1
%vreg10<def> =

CSE: allow PerformTrivialCoalescing to check copies across basic block
boundaries.

Given the following case:
BB0
%vreg1<def> = SUBrr %vreg0, %vreg7
%vreg2<def> = COPY %vreg7
BB1
%vreg10<def> = SUBrr %vreg0, %vreg2
We should be able to CSE between SUBrr in BB0 and SUBrr in BB1.

rdar://12462006

llvm-svn: 168717

show more ...

Don't use iterator after being erased.

llvm-svn: 168622

Do not consider a machine instruction that uses and defines the same
physical register as candidate for common subexpression elimination
in MachineCSE.

This fixes a bug on PowerPC in MultiSource/App

Do not consider a machine instruction that uses and defines the same
physical register as candidate for common subexpression elimination
in MachineCSE.

This fixes a bug on PowerPC in MultiSource/Applications/oggenc/oggenc
caused by MachineCSE invalidly merging two separate DYNALLOC insns.

llvm-svn: 167855

show more ...

Remove unused BitVectors from getAllocatableSet().

llvm-svn: 165999

Switch most getReservedRegs() clients to the MRI equivalent.

Using the cached bit vector in MRI avoids comstantly allocating and
recomputing the reserved register bit vector.

llvm-svn: 165983

MachineCSE: Hoist isConstantPhysReg out of the loop, it checks for overlaps already.

llvm-svn: 161729

PR13578: Teach MachineCSE that instructions that use a constant register can be CSE'd safely.

This is common e.g. when doing rip-relative addressing on x86_64.

llvm-svn: 161728

X86: enable CSE between CMP and SUB

We perform the following:
1> Use SUB instead of CMP for i8,i16,i32 and i64 in ISel lowering.
2> Modify MachineCSE to correctly handle implicit defs.
3> Convert SU

X86: enable CSE between CMP and SUB

We perform the following:
1> Use SUB instead of CMP for i8,i16,i32 and i64 in ISel lowering.
2> Modify MachineCSE to correctly handle implicit defs.
3> Convert SUB back to CMP if possible at peephole.

Removed pattern matching of (a>b) ? (a-b):0 and like, since they are handled
by peephole now.

rdar://11873276

llvm-svn: 161462

show more ...

MachineCSE: Update the heuristics for isProfitableToCSE.

If the result of a common subexpression is used at all uses of the candidate
expression, CSE should not increase the live range of the common

MachineCSE: Update the heuristics for isProfitableToCSE.

If the result of a common subexpression is used at all uses of the candidate
expression, CSE should not increase the live range of the common subexpression.

rdar://11393714 and rdar://11819721

llvm-svn: 161396

show more ...

Remove tabs.

llvm-svn: 160475

Remove ParentMap. You can just ask the domnode for its parent. No functionality
change.

Move the "Not profitable, avoid CSE!" debug message next to where we fail the
check for profitability and use

Remove ParentMap. You can just ask the domnode for its parent. No functionality
change.

Move the "Not profitable, avoid CSE!" debug message next to where we fail the
check for profitability and use a different message for avoiding CSE due to
being in different register classes.

llvm-svn: 159729

show more ...

Switch some getAliasSet clients to MCRegAliasIterator.

MCRegAliasIterator can optionally visit the register itself, allowing
for simpler code.

llvm-svn: 157837

Use uint16_t to store register overlaps to reduce static data.

llvm-svn: 152001

Handle regmasks in MachineCSE.

Don't attempt to extend physreg live ranges across calls.

<rdar://problem/10942095>

llvm-svn: 151610

Re-enable 150652 and 150654 - Make FPSCR non-reserved, and make MachineCSE bail on reserved registers. This *should* be safe as of r150786.

llvm-svn: 150769

Oop - r150653 + r150654 broke one of my test cases. Backing out for now...

llvm-svn: 150655

MachineCSE shouldn't extend the live ranges of reserved or allocatable registers.

llvm-svn: 150653

Codegen pass definition cleanup. No functionality.

Moving toward a uniform style of pass definition to allow easier target configuration.
Globally declare Pass ID.
Globally declare pass initializer.

Codegen pass definition cleanup. No functionality.

Moving toward a uniform style of pass definition to allow easier target configuration.
Globally declare Pass ID.
Globally declare pass initializer.
Use INITIALIZE_PASS consistently.
Add a call to the initializer from CodeGen.cpp.
Remove redundant "createPass" functions and "getPassName" methods.

While cleaning up declarations, cleaned up comments (sorry for large diff).

llvm-svn: 150100

show more ...

whitespace

llvm-svn: 150094

Persuade GCC that there is nothing worth warning about here (there isn't).

llvm-svn: 149834

Avoid CSE of instructions which define physical registers across MBBs unless
the physical registers are not allocatable.

llvm-svn: 147902

Allow machine-cse to look across MBB boundary when cse'ing instructions that
define physical registers. It's currently very restrictive, only catching
cases where the CE is in an immediate (and only)

Allow machine-cse to look across MBB boundary when cse'ing instructions that
define physical registers. It's currently very restrictive, only catching
cases where the CE is in an immediate (and only) predecessor. But it catches
a surprising large number of cases.

rdar://10660865

llvm-svn: 147827

show more ...