| b15d75b2 | 21-Feb-2023 |
Gerry Gribbon <ggribbon@nvidia.com> |
regex/mlx5: fix doorbell record
We were writing a value that should represent the number of items to be
processed by hardware. The value being written was off by 1 (N*4)+3;
The value should be (N*4)
regex/mlx5: fix doorbell record
We were writing a value that should represent the number of items to be
processed by hardware. The value being written was off by 1 (N*4)+3;
The value should be (N*4) + 4 simplified to (N+1)*4
Fixes: 5dfa003db53f ("common/mlx5: fix post doorbell barrier")
Cc: stable@dpdk.org
Signed-off-by: Gerry Gribbon <ggribbon@nvidia.com>
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| 7dde9c84 | 12-Oct-2022 |
Abdullah Ömer Yamaç <omer.yamac@ceng.metu.edu.tr> |
drivers: omit symbol map when unneeded
In this patch, we removed the necessity of the version files and
you don't need to update these files for each release, you can just
remove them.
Suggested-by
drivers: omit symbol map when unneeded
In this patch, we removed the necessity of the version files and
you don't need to update these files for each release, you can just
remove them.
Suggested-by: Ferruh Yigit <ferruh.yigit@amd.com>
Signed-off-by: Abdullah Ömer Yamaç <omer.yamac@ceng.metu.edu.tr>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Tested-by: Ferruh Yigit <ferruh.yigit@amd.com>
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| 383049f1 | 01-Sep-2022 |
Gerry Gribbon <ggribbon@nvidia.com> |
regex/mlx5: forbid changing maximum match number
Added check so user gets error if they try to configure the
nb_max_matches value when using rte_regexdev_configure().
Signed-off-by: Gerry Gribbon <
regex/mlx5: forbid changing maximum match number
Added check so user gets error if they try to configure the
nb_max_matches value when using rte_regexdev_configure().
Signed-off-by: Gerry Gribbon <ggribbon@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>
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| ab746801 | 01-Sep-2022 |
Gerry Gribbon <ggribbon@nvidia.com> |
regex/mlx5: support combined ROF file
Added support to allow parsing of a combined ROF file to
locate compatible binary ROF data for the Bluefield hardware
being run on.
Signed-off-by: Gerry Gribbo
regex/mlx5: support combined ROF file
Added support to allow parsing of a combined ROF file to
locate compatible binary ROF data for the Bluefield hardware
being run on.
Signed-off-by: Gerry Gribbon <ggribbon@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>
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| bba8281d | 08-Nov-2021 |
Raja Zidane <rzidane@nvidia.com> |
common/mlx5: fix queue size in DevX queue pair creation
The number of WQEBBs was provided to QP create, and QP size was calculated
by multiplying the number of WQEBBs by 64, which is the send WQE si
common/mlx5: fix queue size in DevX queue pair creation
The number of WQEBBs was provided to QP create, and QP size was calculated
by multiplying the number of WQEBBs by 64, which is the send WQE size.
When creating RQ in the QP (i.e., vdpa driver), the queue size was bigger
because the receive WQE size is 16.
Provide queue size to QP create instead of the number of WQEBBs.
Fixes: f9213ab12cf9 ("common/mlx5: share DevX queue pair operations")
Signed-off-by: Raja Zidane <rzidane@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
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| 5dfa003d | 03-Nov-2021 |
Michael Baum <michaelba@nvidia.com> |
common/mlx5: fix post doorbell barrier
The rdma-core library can map doorbell register in two ways, depending
on the environment variable "MLX5_SHUT_UP_BF":
- as regular cached memory, the variab
common/mlx5: fix post doorbell barrier
The rdma-core library can map doorbell register in two ways, depending
on the environment variable "MLX5_SHUT_UP_BF":
- as regular cached memory, the variable is either missing or set to
zero. This type of mapping may cause the significant doorbell
register writing latency and requires an explicit memory write
barrier to mitigate this issue and prevent write combining.
- as non-cached memory, the variable is present and set to not "0"
value. This type of mapping may cause performance impact under
heavy loading conditions but the explicit write memory barrier is
not required and it may improve core performance.
The UAR creation function maps a doorbell in one of the above ways
according to the system. In run time, it always adds an explicit memory
barrier after writing to.
In cases where the doorbell was mapped as non-cached memory, the
explicit memory barrier is unnecessary and may impair performance.
The commit [1] solved this problem for a Tx queue. In run time, it
checks the mapping type and provides the memory barrier after writing to
a Tx doorbell register if it is needed. The mapping type is extracted
directly from the uar_mmap_offset field in the queue properties.
This patch shares this code between the drivers and extends the above
solution for each of them.
[1] commit 8409a28573d3
("net/mlx5: control transmit doorbell register mapping")
Fixes: f8c97babc9f4 ("compress/mlx5: add data-path functions")
Fixes: 8e196c08ab53 ("crypto/mlx5: support enqueue/dequeue operations")
Fixes: 4d4e245ad637 ("regex/mlx5: support enqueue")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Reviewed-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
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| b4371d3d | 03-Nov-2021 |
Michael Baum <michaelba@nvidia.com> |
common/mlx5: fix doorbell mapping configuration
UAR mapping type can be affected by the devarg tx_db_nc, which can cause
setting the environment variable MLX5_SHUT_UP_BF.
So, the MLX5_SHUT_UP_BF val
common/mlx5: fix doorbell mapping configuration
UAR mapping type can be affected by the devarg tx_db_nc, which can cause
setting the environment variable MLX5_SHUT_UP_BF.
So, the MLX5_SHUT_UP_BF value and the UAR mapping parameter affect the
UAR cache mode.
Wrongly, the devarg was considered for the MLX5_SHUT_UP_BF but not for
the UAR mapping parameter in all the drivers except the net.
Take the tx_db_nc devarg into account for all the drivers.
Fixes: ca1418ce3910 ("common/mlx5: share device context object")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Reviewed-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
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