1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2020 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <net/if.h> 13 #include <linux/rtnetlink.h> 14 #include <linux/sockios.h> 15 #include <linux/ethtool.h> 16 #include <fcntl.h> 17 18 #include <rte_malloc.h> 19 #include <ethdev_driver.h> 20 #include <ethdev_pci.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_bus_auxiliary.h> 24 #include <rte_common.h> 25 #include <rte_kvargs.h> 26 #include <rte_rwlock.h> 27 #include <rte_spinlock.h> 28 #include <rte_string_fns.h> 29 #include <rte_alarm.h> 30 #include <rte_eal_paging.h> 31 32 #include <mlx5_glue.h> 33 #include <mlx5_devx_cmds.h> 34 #include <mlx5_common.h> 35 #include <mlx5_common_mp.h> 36 #include <mlx5_common_mr.h> 37 #include <mlx5_malloc.h> 38 39 #include "mlx5_defs.h" 40 #include "mlx5.h" 41 #include "mlx5_common_os.h" 42 #include "mlx5_utils.h" 43 #include "mlx5_rxtx.h" 44 #include "mlx5_rx.h" 45 #include "mlx5_tx.h" 46 #include "mlx5_autoconf.h" 47 #include "mlx5_flow.h" 48 #include "rte_pmd_mlx5.h" 49 #include "mlx5_verbs.h" 50 #include "mlx5_nl.h" 51 #include "mlx5_devx.h" 52 53 #ifndef HAVE_IBV_MLX5_MOD_MPW 54 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 55 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 56 #endif 57 58 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 59 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 60 #endif 61 62 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 63 64 /* Spinlock for mlx5_shared_data allocation. */ 65 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 66 67 /* Process local data for secondary processes. */ 68 static struct mlx5_local_data mlx5_local_data; 69 70 /* rte flow indexed pool configuration. */ 71 static struct mlx5_indexed_pool_config icfg[] = { 72 { 73 .size = sizeof(struct rte_flow), 74 .trunk_size = 64, 75 .need_lock = 1, 76 .release_mem_en = 0, 77 .malloc = mlx5_malloc, 78 .free = mlx5_free, 79 .per_core_cache = 0, 80 .type = "ctl_flow_ipool", 81 }, 82 { 83 .size = sizeof(struct rte_flow), 84 .trunk_size = 64, 85 .grow_trunk = 3, 86 .grow_shift = 2, 87 .need_lock = 1, 88 .release_mem_en = 0, 89 .malloc = mlx5_malloc, 90 .free = mlx5_free, 91 .per_core_cache = 1 << 14, 92 .type = "rte_flow_ipool", 93 }, 94 { 95 .size = sizeof(struct rte_flow), 96 .trunk_size = 64, 97 .grow_trunk = 3, 98 .grow_shift = 2, 99 .need_lock = 1, 100 .release_mem_en = 0, 101 .malloc = mlx5_malloc, 102 .free = mlx5_free, 103 .per_core_cache = 0, 104 .type = "mcp_flow_ipool", 105 }, 106 }; 107 108 /** 109 * Set the completion channel file descriptor interrupt as non-blocking. 110 * 111 * @param[in] rxq_obj 112 * Pointer to RQ channel object, which includes the channel fd 113 * 114 * @param[out] fd 115 * The file descriptor (representing the interrupt) used in this channel. 116 * 117 * @return 118 * 0 on successfully setting the fd to non-blocking, non-zero otherwise. 119 */ 120 int 121 mlx5_os_set_nonblock_channel_fd(int fd) 122 { 123 int flags; 124 125 flags = fcntl(fd, F_GETFL); 126 return fcntl(fd, F_SETFL, flags | O_NONBLOCK); 127 } 128 129 /** 130 * Get mlx5 device attributes. The glue function query_device_ex() is called 131 * with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5 132 * device attributes from the glue out parameter. 133 * 134 * @param sh 135 * Pointer to shared device context. 136 * 137 * @return 138 * 0 on success, a negative errno value otherwise and rte_errno is set. 139 */ 140 int 141 mlx5_os_capabilities_prepare(struct mlx5_dev_ctx_shared *sh) 142 { 143 int err; 144 struct mlx5_common_device *cdev = sh->cdev; 145 struct mlx5_hca_attr *hca_attr = &cdev->config.hca_attr; 146 struct ibv_device_attr_ex attr_ex = { .comp_mask = 0 }; 147 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 148 149 err = mlx5_glue->query_device_ex(cdev->ctx, NULL, &attr_ex); 150 if (err) { 151 rte_errno = errno; 152 return -rte_errno; 153 } 154 #ifdef HAVE_IBV_MLX5_MOD_SWP 155 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 156 #endif 157 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 158 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 159 #endif 160 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 161 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 162 #endif 163 err = mlx5_glue->dv_query_device(cdev->ctx, &dv_attr); 164 if (err) { 165 rte_errno = errno; 166 return -rte_errno; 167 } 168 memset(&sh->dev_cap, 0, sizeof(struct mlx5_dev_cap)); 169 if (mlx5_dev_is_pci(cdev->dev)) 170 sh->dev_cap.vf = mlx5_dev_is_vf_pci(RTE_DEV_TO_PCI(cdev->dev)); 171 else 172 sh->dev_cap.sf = 1; 173 sh->dev_cap.max_qp_wr = attr_ex.orig_attr.max_qp_wr; 174 sh->dev_cap.max_sge = attr_ex.orig_attr.max_sge; 175 sh->dev_cap.max_cq = attr_ex.orig_attr.max_cq; 176 sh->dev_cap.max_qp = attr_ex.orig_attr.max_qp; 177 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 178 sh->dev_cap.dest_tir = 1; 179 #endif 180 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) && defined(HAVE_MLX5DV_DR) 181 DRV_LOG(DEBUG, "DV flow is supported."); 182 sh->dev_cap.dv_flow_en = 1; 183 #endif 184 #ifdef HAVE_MLX5DV_DR_ESWITCH 185 if (hca_attr->eswitch_manager && sh->dev_cap.dv_flow_en && sh->esw_mode) 186 sh->dev_cap.dv_esw_en = 1; 187 #endif 188 /* 189 * Multi-packet send is supported by ConnectX-4 Lx PF as well 190 * as all ConnectX-5 devices. 191 */ 192 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 193 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 194 DRV_LOG(DEBUG, "Enhanced MPW is supported."); 195 sh->dev_cap.mps = MLX5_MPW_ENHANCED; 196 } else { 197 DRV_LOG(DEBUG, "MPW is supported."); 198 sh->dev_cap.mps = MLX5_MPW; 199 } 200 } else { 201 DRV_LOG(DEBUG, "MPW isn't supported."); 202 sh->dev_cap.mps = MLX5_MPW_DISABLED; 203 } 204 #if (RTE_CACHE_LINE_SIZE == 128) 205 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP) 206 sh->dev_cap.cqe_comp = 1; 207 DRV_LOG(DEBUG, "Rx CQE 128B compression is %ssupported.", 208 sh->dev_cap.cqe_comp ? "" : "not "); 209 #else 210 sh->dev_cap.cqe_comp = 1; 211 #endif 212 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 213 sh->dev_cap.mpls_en = 214 ((dv_attr.tunnel_offloads_caps & 215 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 216 (dv_attr.tunnel_offloads_caps & 217 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 218 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported.", 219 sh->dev_cap.mpls_en ? "" : "not "); 220 #else 221 DRV_LOG(WARNING, 222 "MPLS over GRE/UDP tunnel offloading disabled due to old OFED/rdma-core version or firmware configuration"); 223 #endif 224 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 225 sh->dev_cap.hw_padding = !!attr_ex.rx_pad_end_addr_align; 226 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 227 sh->dev_cap.hw_padding = !!(attr_ex.device_cap_flags_ex & 228 IBV_DEVICE_PCI_WRITE_END_PADDING); 229 #endif 230 sh->dev_cap.hw_csum = 231 !!(attr_ex.device_cap_flags_ex & IBV_DEVICE_RAW_IP_CSUM); 232 DRV_LOG(DEBUG, "Checksum offloading is %ssupported.", 233 sh->dev_cap.hw_csum ? "" : "not "); 234 sh->dev_cap.hw_vlan_strip = !!(attr_ex.raw_packet_caps & 235 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 236 DRV_LOG(DEBUG, "VLAN stripping is %ssupported.", 237 (sh->dev_cap.hw_vlan_strip ? "" : "not ")); 238 sh->dev_cap.hw_fcs_strip = !!(attr_ex.raw_packet_caps & 239 IBV_RAW_PACKET_CAP_SCATTER_FCS); 240 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 241 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 242 DRV_LOG(DEBUG, "Counters are not supported."); 243 #endif 244 /* 245 * DPDK doesn't support larger/variable indirection tables. 246 * Once DPDK supports it, take max size from device attr. 247 */ 248 sh->dev_cap.ind_table_max_size = 249 RTE_MIN(attr_ex.rss_caps.max_rwq_indirection_table_size, 250 (unsigned int)RTE_ETH_RSS_RETA_SIZE_512); 251 DRV_LOG(DEBUG, "Maximum Rx indirection table size is %u", 252 sh->dev_cap.ind_table_max_size); 253 sh->dev_cap.tso = (attr_ex.tso_caps.max_tso > 0 && 254 (attr_ex.tso_caps.supported_qpts & 255 (1 << IBV_QPT_RAW_PACKET))); 256 if (sh->dev_cap.tso) 257 sh->dev_cap.tso_max_payload_sz = attr_ex.tso_caps.max_tso; 258 strlcpy(sh->dev_cap.fw_ver, attr_ex.orig_attr.fw_ver, 259 sizeof(sh->dev_cap.fw_ver)); 260 #ifdef HAVE_IBV_MLX5_MOD_SWP 261 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 262 sh->dev_cap.swp = dv_attr.sw_parsing_caps.sw_parsing_offloads & 263 (MLX5_SW_PARSING_CAP | 264 MLX5_SW_PARSING_CSUM_CAP | 265 MLX5_SW_PARSING_TSO_CAP); 266 DRV_LOG(DEBUG, "SWP support: %u", sh->dev_cap.swp); 267 #endif 268 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 269 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 270 struct mlx5dv_striding_rq_caps *strd_rq_caps = 271 &dv_attr.striding_rq_caps; 272 273 sh->dev_cap.mprq.enabled = 1; 274 sh->dev_cap.mprq.log_min_stride_size = 275 strd_rq_caps->min_single_stride_log_num_of_bytes; 276 sh->dev_cap.mprq.log_max_stride_size = 277 strd_rq_caps->max_single_stride_log_num_of_bytes; 278 sh->dev_cap.mprq.log_min_stride_num = 279 strd_rq_caps->min_single_wqe_log_num_of_strides; 280 sh->dev_cap.mprq.log_max_stride_num = 281 strd_rq_caps->max_single_wqe_log_num_of_strides; 282 sh->dev_cap.mprq.log_min_stride_wqe_size = 283 cdev->config.devx ? 284 hca_attr->log_min_stride_wqe_sz : 285 MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE; 286 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %u", 287 sh->dev_cap.mprq.log_min_stride_size); 288 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %u", 289 sh->dev_cap.mprq.log_max_stride_size); 290 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %u", 291 sh->dev_cap.mprq.log_min_stride_num); 292 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %u", 293 sh->dev_cap.mprq.log_max_stride_num); 294 DRV_LOG(DEBUG, "\tmin_stride_wqe_log_size: %u", 295 sh->dev_cap.mprq.log_min_stride_wqe_size); 296 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 297 strd_rq_caps->supported_qpts); 298 DRV_LOG(DEBUG, "Device supports Multi-Packet RQ."); 299 } 300 #endif 301 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 302 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 303 sh->dev_cap.tunnel_en = dv_attr.tunnel_offloads_caps & 304 (MLX5_TUNNELED_OFFLOADS_VXLAN_CAP | 305 MLX5_TUNNELED_OFFLOADS_GRE_CAP | 306 MLX5_TUNNELED_OFFLOADS_GENEVE_CAP); 307 } 308 if (sh->dev_cap.tunnel_en) { 309 DRV_LOG(DEBUG, "Tunnel offloading is supported for %s%s%s", 310 sh->dev_cap.tunnel_en & 311 MLX5_TUNNELED_OFFLOADS_VXLAN_CAP ? "[VXLAN]" : "", 312 sh->dev_cap.tunnel_en & 313 MLX5_TUNNELED_OFFLOADS_GRE_CAP ? "[GRE]" : "", 314 sh->dev_cap.tunnel_en & 315 MLX5_TUNNELED_OFFLOADS_GENEVE_CAP ? "[GENEVE]" : ""); 316 } else { 317 DRV_LOG(DEBUG, "Tunnel offloading is not supported."); 318 } 319 #else 320 DRV_LOG(WARNING, 321 "Tunnel offloading disabled due to old OFED/rdma-core version"); 322 #endif 323 if (!sh->cdev->config.devx) 324 return 0; 325 /* Check capabilities for Packet Pacing. */ 326 DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz.", 327 hca_attr->dev_freq_khz); 328 DRV_LOG(DEBUG, "Packet pacing is %ssupported.", 329 hca_attr->qos.packet_pacing ? "" : "not "); 330 DRV_LOG(DEBUG, "Cross channel ops are %ssupported.", 331 hca_attr->cross_channel ? "" : "not "); 332 DRV_LOG(DEBUG, "WQE index ignore is %ssupported.", 333 hca_attr->wqe_index_ignore ? "" : "not "); 334 DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported.", 335 hca_attr->non_wire_sq ? "" : "not "); 336 DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)", 337 hca_attr->log_max_static_sq_wq ? "" : "not ", 338 hca_attr->log_max_static_sq_wq); 339 DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported.", 340 hca_attr->qos.wqe_rate_pp ? "" : "not "); 341 sh->dev_cap.txpp_en = hca_attr->qos.packet_pacing; 342 if (!hca_attr->cross_channel) { 343 DRV_LOG(DEBUG, 344 "Cross channel operations are required for packet pacing."); 345 sh->dev_cap.txpp_en = 0; 346 } 347 if (!hca_attr->wqe_index_ignore) { 348 DRV_LOG(DEBUG, 349 "WQE index ignore feature is required for packet pacing."); 350 sh->dev_cap.txpp_en = 0; 351 } 352 if (!hca_attr->non_wire_sq) { 353 DRV_LOG(DEBUG, 354 "Non-wire SQ feature is required for packet pacing."); 355 sh->dev_cap.txpp_en = 0; 356 } 357 if (!hca_attr->log_max_static_sq_wq) { 358 DRV_LOG(DEBUG, 359 "Static WQE SQ feature is required for packet pacing."); 360 sh->dev_cap.txpp_en = 0; 361 } 362 if (!hca_attr->qos.wqe_rate_pp) { 363 DRV_LOG(DEBUG, 364 "WQE rate mode is required for packet pacing."); 365 sh->dev_cap.txpp_en = 0; 366 } 367 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 368 DRV_LOG(DEBUG, 369 "DevX does not provide UAR offset, can't create queues for packet pacing."); 370 sh->dev_cap.txpp_en = 0; 371 #endif 372 /* Check for LRO support. */ 373 if (mlx5_devx_obj_ops_en(sh) && hca_attr->lro_cap) { 374 /* TBD check tunnel lro caps. */ 375 sh->dev_cap.lro_supported = 1; 376 DRV_LOG(DEBUG, "Device supports LRO."); 377 DRV_LOG(DEBUG, 378 "LRO minimal size of TCP segment required for coalescing is %d bytes.", 379 hca_attr->lro_min_mss_size); 380 } 381 sh->dev_cap.scatter_fcs_w_decap_disable = 382 hca_attr->scatter_fcs_w_decap_disable; 383 sh->dev_cap.rq_delay_drop_en = hca_attr->rq_delay_drop; 384 mlx5_rt_timestamp_config(sh, hca_attr); 385 return 0; 386 } 387 388 /** 389 * Detect misc5 support or not 390 * 391 * @param[in] priv 392 * Device private data pointer 393 */ 394 #ifdef HAVE_MLX5DV_DR 395 static void 396 __mlx5_discovery_misc5_cap(struct mlx5_priv *priv) 397 { 398 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 399 /* Dummy VxLAN matcher to detect rdma-core misc5 cap 400 * Case: IPv4--->UDP--->VxLAN--->vni 401 */ 402 void *tbl; 403 struct mlx5_flow_dv_match_params matcher_mask; 404 void *match_m; 405 void *matcher; 406 void *headers_m; 407 void *misc5_m; 408 uint32_t *tunnel_header_m; 409 struct mlx5dv_flow_matcher_attr dv_attr; 410 411 memset(&matcher_mask, 0, sizeof(matcher_mask)); 412 matcher_mask.size = sizeof(matcher_mask.buf); 413 match_m = matcher_mask.buf; 414 headers_m = MLX5_ADDR_OF(fte_match_param, match_m, outer_headers); 415 misc5_m = MLX5_ADDR_OF(fte_match_param, 416 match_m, misc_parameters_5); 417 tunnel_header_m = (uint32_t *) 418 MLX5_ADDR_OF(fte_match_set_misc5, 419 misc5_m, tunnel_header_1); 420 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff); 421 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 4); 422 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff); 423 *tunnel_header_m = 0xffffff; 424 425 tbl = mlx5_glue->dr_create_flow_tbl(priv->sh->rx_domain, 1); 426 if (!tbl) { 427 DRV_LOG(INFO, "No SW steering support"); 428 return; 429 } 430 dv_attr.type = IBV_FLOW_ATTR_NORMAL, 431 dv_attr.match_mask = (void *)&matcher_mask, 432 dv_attr.match_criteria_enable = 433 (1 << MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT) | 434 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT); 435 dv_attr.priority = 3; 436 #ifdef HAVE_MLX5DV_DR_ESWITCH 437 void *misc2_m; 438 if (priv->sh->config.dv_esw_en) { 439 /* FDB enabled reg_c_0 */ 440 dv_attr.match_criteria_enable |= 441 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT); 442 misc2_m = MLX5_ADDR_OF(fte_match_param, 443 match_m, misc_parameters_2); 444 MLX5_SET(fte_match_set_misc2, misc2_m, 445 metadata_reg_c_0, 0xffff); 446 } 447 #endif 448 matcher = mlx5_glue->dv_create_flow_matcher(priv->sh->cdev->ctx, 449 &dv_attr, tbl); 450 if (matcher) { 451 priv->sh->misc5_cap = 1; 452 mlx5_glue->dv_destroy_flow_matcher(matcher); 453 } 454 mlx5_glue->dr_destroy_flow_tbl(tbl); 455 #else 456 RTE_SET_USED(priv); 457 #endif 458 } 459 #endif 460 461 /** 462 * Initialize DR related data within private structure. 463 * Routine checks the reference counter and does actual 464 * resources creation/initialization only if counter is zero. 465 * 466 * @param[in] priv 467 * Pointer to the private device data structure. 468 * 469 * @return 470 * Zero on success, positive error code otherwise. 471 */ 472 static int 473 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 474 { 475 struct mlx5_dev_ctx_shared *sh = priv->sh; 476 char s[MLX5_NAME_SIZE] __rte_unused; 477 int err; 478 479 MLX5_ASSERT(sh && sh->refcnt); 480 if (sh->refcnt > 1) 481 return 0; 482 err = mlx5_alloc_table_hash_list(priv); 483 if (err) 484 goto error; 485 /* The resources below are only valid with DV support. */ 486 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 487 /* Init port id action list. */ 488 snprintf(s, sizeof(s), "%s_port_id_action_list", sh->ibdev_name); 489 sh->port_id_action_list = mlx5_list_create(s, sh, true, 490 flow_dv_port_id_create_cb, 491 flow_dv_port_id_match_cb, 492 flow_dv_port_id_remove_cb, 493 flow_dv_port_id_clone_cb, 494 flow_dv_port_id_clone_free_cb); 495 if (!sh->port_id_action_list) 496 goto error; 497 /* Init push vlan action list. */ 498 snprintf(s, sizeof(s), "%s_push_vlan_action_list", sh->ibdev_name); 499 sh->push_vlan_action_list = mlx5_list_create(s, sh, true, 500 flow_dv_push_vlan_create_cb, 501 flow_dv_push_vlan_match_cb, 502 flow_dv_push_vlan_remove_cb, 503 flow_dv_push_vlan_clone_cb, 504 flow_dv_push_vlan_clone_free_cb); 505 if (!sh->push_vlan_action_list) 506 goto error; 507 /* Init sample action list. */ 508 snprintf(s, sizeof(s), "%s_sample_action_list", sh->ibdev_name); 509 sh->sample_action_list = mlx5_list_create(s, sh, true, 510 flow_dv_sample_create_cb, 511 flow_dv_sample_match_cb, 512 flow_dv_sample_remove_cb, 513 flow_dv_sample_clone_cb, 514 flow_dv_sample_clone_free_cb); 515 if (!sh->sample_action_list) 516 goto error; 517 /* Init dest array action list. */ 518 snprintf(s, sizeof(s), "%s_dest_array_list", sh->ibdev_name); 519 sh->dest_array_list = mlx5_list_create(s, sh, true, 520 flow_dv_dest_array_create_cb, 521 flow_dv_dest_array_match_cb, 522 flow_dv_dest_array_remove_cb, 523 flow_dv_dest_array_clone_cb, 524 flow_dv_dest_array_clone_free_cb); 525 if (!sh->dest_array_list) 526 goto error; 527 /* Init shared flex parsers list, no need lcore_share */ 528 snprintf(s, sizeof(s), "%s_flex_parsers_list", sh->ibdev_name); 529 sh->flex_parsers_dv = mlx5_list_create(s, sh, false, 530 mlx5_flex_parser_create_cb, 531 mlx5_flex_parser_match_cb, 532 mlx5_flex_parser_remove_cb, 533 mlx5_flex_parser_clone_cb, 534 mlx5_flex_parser_clone_free_cb); 535 if (!sh->flex_parsers_dv) 536 goto error; 537 #endif 538 #ifdef HAVE_MLX5DV_DR 539 void *domain; 540 541 /* Reference counter is zero, we should initialize structures. */ 542 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx, 543 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 544 if (!domain) { 545 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 546 err = errno; 547 goto error; 548 } 549 sh->rx_domain = domain; 550 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx, 551 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 552 if (!domain) { 553 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 554 err = errno; 555 goto error; 556 } 557 sh->tx_domain = domain; 558 #ifdef HAVE_MLX5DV_DR_ESWITCH 559 if (sh->config.dv_esw_en) { 560 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx, 561 MLX5DV_DR_DOMAIN_TYPE_FDB); 562 if (!domain) { 563 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 564 err = errno; 565 goto error; 566 } 567 sh->fdb_domain = domain; 568 } 569 /* 570 * The drop action is just some dummy placeholder in rdma-core. It 571 * does not belong to domains and has no any attributes, and, can be 572 * shared by the entire device. 573 */ 574 sh->dr_drop_action = mlx5_glue->dr_create_flow_action_drop(); 575 if (!sh->dr_drop_action) { 576 DRV_LOG(ERR, "FDB mlx5dv_dr_create_flow_action_drop"); 577 err = errno; 578 goto error; 579 } 580 #endif 581 if (!sh->tunnel_hub && sh->config.dv_miss_info) 582 err = mlx5_alloc_tunnel_hub(sh); 583 if (err) { 584 DRV_LOG(ERR, "mlx5_alloc_tunnel_hub failed err=%d", err); 585 goto error; 586 } 587 if (sh->config.reclaim_mode == MLX5_RCM_AGGR) { 588 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1); 589 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1); 590 if (sh->fdb_domain) 591 mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1); 592 } 593 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); 594 if (!sh->config.allow_duplicate_pattern) { 595 #ifndef HAVE_MLX5_DR_ALLOW_DUPLICATE 596 DRV_LOG(WARNING, "Disallow duplicate pattern is not supported - maybe old rdma-core version?"); 597 #endif 598 mlx5_glue->dr_allow_duplicate_rules(sh->rx_domain, 0); 599 mlx5_glue->dr_allow_duplicate_rules(sh->tx_domain, 0); 600 if (sh->fdb_domain) 601 mlx5_glue->dr_allow_duplicate_rules(sh->fdb_domain, 0); 602 } 603 604 __mlx5_discovery_misc5_cap(priv); 605 #endif /* HAVE_MLX5DV_DR */ 606 sh->default_miss_action = 607 mlx5_glue->dr_create_flow_action_default_miss(); 608 if (!sh->default_miss_action) 609 DRV_LOG(WARNING, "Default miss action is not supported."); 610 LIST_INIT(&sh->shared_rxqs); 611 return 0; 612 error: 613 /* Rollback the created objects. */ 614 if (sh->rx_domain) { 615 mlx5_glue->dr_destroy_domain(sh->rx_domain); 616 sh->rx_domain = NULL; 617 } 618 if (sh->tx_domain) { 619 mlx5_glue->dr_destroy_domain(sh->tx_domain); 620 sh->tx_domain = NULL; 621 } 622 if (sh->fdb_domain) { 623 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 624 sh->fdb_domain = NULL; 625 } 626 if (sh->dr_drop_action) { 627 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 628 sh->dr_drop_action = NULL; 629 } 630 if (sh->pop_vlan_action) { 631 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 632 sh->pop_vlan_action = NULL; 633 } 634 if (sh->encaps_decaps) { 635 mlx5_hlist_destroy(sh->encaps_decaps); 636 sh->encaps_decaps = NULL; 637 } 638 if (sh->modify_cmds) { 639 mlx5_hlist_destroy(sh->modify_cmds); 640 sh->modify_cmds = NULL; 641 } 642 if (sh->tag_table) { 643 /* tags should be destroyed with flow before. */ 644 mlx5_hlist_destroy(sh->tag_table); 645 sh->tag_table = NULL; 646 } 647 if (sh->tunnel_hub) { 648 mlx5_release_tunnel_hub(sh, priv->dev_port); 649 sh->tunnel_hub = NULL; 650 } 651 mlx5_free_table_hash_list(priv); 652 if (sh->port_id_action_list) { 653 mlx5_list_destroy(sh->port_id_action_list); 654 sh->port_id_action_list = NULL; 655 } 656 if (sh->push_vlan_action_list) { 657 mlx5_list_destroy(sh->push_vlan_action_list); 658 sh->push_vlan_action_list = NULL; 659 } 660 if (sh->sample_action_list) { 661 mlx5_list_destroy(sh->sample_action_list); 662 sh->sample_action_list = NULL; 663 } 664 if (sh->dest_array_list) { 665 mlx5_list_destroy(sh->dest_array_list); 666 sh->dest_array_list = NULL; 667 } 668 return err; 669 } 670 671 /** 672 * Destroy DR related data within private structure. 673 * 674 * @param[in] priv 675 * Pointer to the private device data structure. 676 */ 677 void 678 mlx5_os_free_shared_dr(struct mlx5_priv *priv) 679 { 680 struct mlx5_dev_ctx_shared *sh = priv->sh; 681 682 MLX5_ASSERT(sh && sh->refcnt); 683 if (sh->refcnt > 1) 684 return; 685 MLX5_ASSERT(LIST_EMPTY(&sh->shared_rxqs)); 686 #ifdef HAVE_MLX5DV_DR 687 if (sh->rx_domain) { 688 mlx5_glue->dr_destroy_domain(sh->rx_domain); 689 sh->rx_domain = NULL; 690 } 691 if (sh->tx_domain) { 692 mlx5_glue->dr_destroy_domain(sh->tx_domain); 693 sh->tx_domain = NULL; 694 } 695 #ifdef HAVE_MLX5DV_DR_ESWITCH 696 if (sh->fdb_domain) { 697 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 698 sh->fdb_domain = NULL; 699 } 700 if (sh->dr_drop_action) { 701 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 702 sh->dr_drop_action = NULL; 703 } 704 #endif 705 if (sh->pop_vlan_action) { 706 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 707 sh->pop_vlan_action = NULL; 708 } 709 #endif /* HAVE_MLX5DV_DR */ 710 if (sh->default_miss_action) 711 mlx5_glue->destroy_flow_action 712 (sh->default_miss_action); 713 if (sh->encaps_decaps) { 714 mlx5_hlist_destroy(sh->encaps_decaps); 715 sh->encaps_decaps = NULL; 716 } 717 if (sh->modify_cmds) { 718 mlx5_hlist_destroy(sh->modify_cmds); 719 sh->modify_cmds = NULL; 720 } 721 if (sh->tag_table) { 722 /* tags should be destroyed with flow before. */ 723 mlx5_hlist_destroy(sh->tag_table); 724 sh->tag_table = NULL; 725 } 726 if (sh->tunnel_hub) { 727 mlx5_release_tunnel_hub(sh, priv->dev_port); 728 sh->tunnel_hub = NULL; 729 } 730 mlx5_free_table_hash_list(priv); 731 if (sh->port_id_action_list) { 732 mlx5_list_destroy(sh->port_id_action_list); 733 sh->port_id_action_list = NULL; 734 } 735 if (sh->push_vlan_action_list) { 736 mlx5_list_destroy(sh->push_vlan_action_list); 737 sh->push_vlan_action_list = NULL; 738 } 739 if (sh->sample_action_list) { 740 mlx5_list_destroy(sh->sample_action_list); 741 sh->sample_action_list = NULL; 742 } 743 if (sh->dest_array_list) { 744 mlx5_list_destroy(sh->dest_array_list); 745 sh->dest_array_list = NULL; 746 } 747 } 748 749 /** 750 * Initialize shared data between primary and secondary process. 751 * 752 * A memzone is reserved by primary process and secondary processes attach to 753 * the memzone. 754 * 755 * @return 756 * 0 on success, a negative errno value otherwise and rte_errno is set. 757 */ 758 static int 759 mlx5_init_shared_data(void) 760 { 761 const struct rte_memzone *mz; 762 int ret = 0; 763 764 rte_spinlock_lock(&mlx5_shared_data_lock); 765 if (mlx5_shared_data == NULL) { 766 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 767 /* Allocate shared memory. */ 768 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 769 sizeof(*mlx5_shared_data), 770 SOCKET_ID_ANY, 0); 771 if (mz == NULL) { 772 DRV_LOG(ERR, 773 "Cannot allocate mlx5 shared data"); 774 ret = -rte_errno; 775 goto error; 776 } 777 mlx5_shared_data = mz->addr; 778 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 779 rte_spinlock_init(&mlx5_shared_data->lock); 780 } else { 781 /* Lookup allocated shared memory. */ 782 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 783 if (mz == NULL) { 784 DRV_LOG(ERR, 785 "Cannot attach mlx5 shared data"); 786 ret = -rte_errno; 787 goto error; 788 } 789 mlx5_shared_data = mz->addr; 790 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 791 } 792 } 793 error: 794 rte_spinlock_unlock(&mlx5_shared_data_lock); 795 return ret; 796 } 797 798 /** 799 * PMD global initialization. 800 * 801 * Independent from individual device, this function initializes global 802 * per-PMD data structures distinguishing primary and secondary processes. 803 * Hence, each initialization is called once per a process. 804 * 805 * @return 806 * 0 on success, a negative errno value otherwise and rte_errno is set. 807 */ 808 static int 809 mlx5_init_once(void) 810 { 811 struct mlx5_shared_data *sd; 812 struct mlx5_local_data *ld = &mlx5_local_data; 813 int ret = 0; 814 815 if (mlx5_init_shared_data()) 816 return -rte_errno; 817 sd = mlx5_shared_data; 818 MLX5_ASSERT(sd); 819 rte_spinlock_lock(&sd->lock); 820 switch (rte_eal_process_type()) { 821 case RTE_PROC_PRIMARY: 822 if (sd->init_done) 823 break; 824 ret = mlx5_mp_init_primary(MLX5_MP_NAME, 825 mlx5_mp_os_primary_handle); 826 if (ret) 827 goto out; 828 sd->init_done = true; 829 break; 830 case RTE_PROC_SECONDARY: 831 if (ld->init_done) 832 break; 833 ret = mlx5_mp_init_secondary(MLX5_MP_NAME, 834 mlx5_mp_os_secondary_handle); 835 if (ret) 836 goto out; 837 ++sd->secondary_cnt; 838 ld->init_done = true; 839 break; 840 default: 841 break; 842 } 843 out: 844 rte_spinlock_unlock(&sd->lock); 845 return ret; 846 } 847 848 /** 849 * DR flow drop action support detect. 850 * 851 * @param dev 852 * Pointer to rte_eth_dev structure. 853 * 854 */ 855 static void 856 mlx5_flow_drop_action_config(struct rte_eth_dev *dev __rte_unused) 857 { 858 #ifdef HAVE_MLX5DV_DR 859 struct mlx5_priv *priv = dev->data->dev_private; 860 861 if (!priv->sh->config.dv_flow_en || !priv->sh->dr_drop_action) 862 return; 863 /** 864 * DR supports drop action placeholder when it is supported; 865 * otherwise, use the queue drop action. 866 */ 867 if (!priv->sh->drop_action_check_flag) { 868 if (!mlx5_flow_discover_dr_action_support(dev)) 869 priv->sh->dr_drop_action_en = 1; 870 priv->sh->drop_action_check_flag = 1; 871 } 872 if (priv->sh->dr_drop_action_en) 873 priv->root_drop_action = priv->sh->dr_drop_action; 874 else 875 priv->root_drop_action = priv->drop_queue.hrxq->action; 876 #endif 877 } 878 879 static void 880 mlx5_queue_counter_id_prepare(struct rte_eth_dev *dev) 881 { 882 struct mlx5_priv *priv = dev->data->dev_private; 883 void *ctx = priv->sh->cdev->ctx; 884 885 priv->q_counters = mlx5_devx_cmd_queue_counter_alloc(ctx); 886 if (!priv->q_counters) { 887 struct ibv_cq *cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0); 888 struct ibv_wq *wq; 889 890 DRV_LOG(DEBUG, "Port %d queue counter object cannot be created " 891 "by DevX - fall-back to use the kernel driver global " 892 "queue counter.", dev->data->port_id); 893 /* Create WQ by kernel and query its queue counter ID. */ 894 if (cq) { 895 wq = mlx5_glue->create_wq(ctx, 896 &(struct ibv_wq_init_attr){ 897 .wq_type = IBV_WQT_RQ, 898 .max_wr = 1, 899 .max_sge = 1, 900 .pd = priv->sh->cdev->pd, 901 .cq = cq, 902 }); 903 if (wq) { 904 /* Counter is assigned only on RDY state. */ 905 int ret = mlx5_glue->modify_wq(wq, 906 &(struct ibv_wq_attr){ 907 .attr_mask = IBV_WQ_ATTR_STATE, 908 .wq_state = IBV_WQS_RDY, 909 }); 910 911 if (ret == 0) 912 mlx5_devx_cmd_wq_query(wq, 913 &priv->counter_set_id); 914 claim_zero(mlx5_glue->destroy_wq(wq)); 915 } 916 claim_zero(mlx5_glue->destroy_cq(cq)); 917 } 918 } else { 919 priv->counter_set_id = priv->q_counters->id; 920 } 921 if (priv->counter_set_id == 0) 922 DRV_LOG(INFO, "Part of the port %d statistics will not be " 923 "available.", dev->data->port_id); 924 } 925 926 /** 927 * Check if representor spawn info match devargs. 928 * 929 * @param spawn 930 * Verbs device parameters (name, port, switch_info) to spawn. 931 * @param eth_da 932 * Device devargs to probe. 933 * 934 * @return 935 * Match result. 936 */ 937 static bool 938 mlx5_representor_match(struct mlx5_dev_spawn_data *spawn, 939 struct rte_eth_devargs *eth_da) 940 { 941 struct mlx5_switch_info *switch_info = &spawn->info; 942 unsigned int p, f; 943 uint16_t id; 944 uint16_t repr_id = mlx5_representor_id_encode(switch_info, 945 eth_da->type); 946 947 switch (eth_da->type) { 948 case RTE_ETH_REPRESENTOR_SF: 949 if (!(spawn->info.port_name == -1 && 950 switch_info->name_type == 951 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 952 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFSF) { 953 rte_errno = EBUSY; 954 return false; 955 } 956 break; 957 case RTE_ETH_REPRESENTOR_VF: 958 /* Allows HPF representor index -1 as exception. */ 959 if (!(spawn->info.port_name == -1 && 960 switch_info->name_type == 961 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 962 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFVF) { 963 rte_errno = EBUSY; 964 return false; 965 } 966 break; 967 case RTE_ETH_REPRESENTOR_NONE: 968 rte_errno = EBUSY; 969 return false; 970 default: 971 rte_errno = ENOTSUP; 972 DRV_LOG(ERR, "unsupported representor type"); 973 return false; 974 } 975 /* Check representor ID: */ 976 for (p = 0; p < eth_da->nb_ports; ++p) { 977 if (spawn->pf_bond < 0) { 978 /* For non-LAG mode, allow and ignore pf. */ 979 switch_info->pf_num = eth_da->ports[p]; 980 repr_id = mlx5_representor_id_encode(switch_info, 981 eth_da->type); 982 } 983 for (f = 0; f < eth_da->nb_representor_ports; ++f) { 984 id = MLX5_REPRESENTOR_ID 985 (eth_da->ports[p], eth_da->type, 986 eth_da->representor_ports[f]); 987 if (repr_id == id) 988 return true; 989 } 990 } 991 rte_errno = EBUSY; 992 return false; 993 } 994 995 /** 996 * Spawn an Ethernet device from Verbs information. 997 * 998 * @param dpdk_dev 999 * Backing DPDK device. 1000 * @param spawn 1001 * Verbs device parameters (name, port, switch_info) to spawn. 1002 * @param eth_da 1003 * Device arguments. 1004 * @param mkvlist 1005 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. 1006 * 1007 * @return 1008 * A valid Ethernet device object on success, NULL otherwise and rte_errno 1009 * is set. The following errors are defined: 1010 * 1011 * EBUSY: device is not supposed to be spawned. 1012 * EEXIST: device is already spawned 1013 */ 1014 static struct rte_eth_dev * 1015 mlx5_dev_spawn(struct rte_device *dpdk_dev, 1016 struct mlx5_dev_spawn_data *spawn, 1017 struct rte_eth_devargs *eth_da, 1018 struct mlx5_kvargs_ctrl *mkvlist) 1019 { 1020 const struct mlx5_switch_info *switch_info = &spawn->info; 1021 struct mlx5_dev_ctx_shared *sh = NULL; 1022 struct ibv_port_attr port_attr = { .state = IBV_PORT_NOP }; 1023 struct rte_eth_dev *eth_dev = NULL; 1024 struct mlx5_priv *priv = NULL; 1025 int err = 0; 1026 struct rte_ether_addr mac; 1027 char name[RTE_ETH_NAME_MAX_LEN]; 1028 int own_domain_id = 0; 1029 uint16_t port_id; 1030 struct mlx5_port_info vport_info = { .query_flags = 0 }; 1031 int nl_rdma; 1032 int i; 1033 1034 /* Determine if this port representor is supposed to be spawned. */ 1035 if (switch_info->representor && dpdk_dev->devargs && 1036 !mlx5_representor_match(spawn, eth_da)) 1037 return NULL; 1038 /* Build device name. */ 1039 if (spawn->pf_bond < 0) { 1040 /* Single device. */ 1041 if (!switch_info->representor) 1042 strlcpy(name, dpdk_dev->name, sizeof(name)); 1043 else 1044 err = snprintf(name, sizeof(name), "%s_representor_%s%u", 1045 dpdk_dev->name, 1046 switch_info->name_type == 1047 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 1048 switch_info->port_name); 1049 } else { 1050 /* Bonding device. */ 1051 if (!switch_info->representor) { 1052 err = snprintf(name, sizeof(name), "%s_%s", 1053 dpdk_dev->name, spawn->phys_dev_name); 1054 } else { 1055 err = snprintf(name, sizeof(name), "%s_%s_representor_c%dpf%d%s%u", 1056 dpdk_dev->name, spawn->phys_dev_name, 1057 switch_info->ctrl_num, 1058 switch_info->pf_num, 1059 switch_info->name_type == 1060 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 1061 switch_info->port_name); 1062 } 1063 } 1064 if (err >= (int)sizeof(name)) 1065 DRV_LOG(WARNING, "device name overflow %s", name); 1066 /* check if the device is already spawned */ 1067 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 1068 /* 1069 * When device is already spawned, its devargs should be set 1070 * as used. otherwise, mlx5_kvargs_validate() will fail. 1071 */ 1072 if (mkvlist) 1073 mlx5_port_args_set_used(name, port_id, mkvlist); 1074 rte_errno = EEXIST; 1075 return NULL; 1076 } 1077 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 1078 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 1079 struct mlx5_mp_id mp_id; 1080 1081 eth_dev = rte_eth_dev_attach_secondary(name); 1082 if (eth_dev == NULL) { 1083 DRV_LOG(ERR, "can not attach rte ethdev"); 1084 rte_errno = ENOMEM; 1085 return NULL; 1086 } 1087 eth_dev->device = dpdk_dev; 1088 eth_dev->dev_ops = &mlx5_dev_sec_ops; 1089 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1090 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1091 err = mlx5_proc_priv_init(eth_dev); 1092 if (err) 1093 return NULL; 1094 mlx5_mp_id_init(&mp_id, eth_dev->data->port_id); 1095 /* Receive command fd from primary process */ 1096 err = mlx5_mp_req_verbs_cmd_fd(&mp_id); 1097 if (err < 0) 1098 goto err_secondary; 1099 /* Remap UAR for Tx queues. */ 1100 err = mlx5_tx_uar_init_secondary(eth_dev, err); 1101 if (err) 1102 goto err_secondary; 1103 /* 1104 * Ethdev pointer is still required as input since 1105 * the primary device is not accessible from the 1106 * secondary process. 1107 */ 1108 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 1109 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 1110 return eth_dev; 1111 err_secondary: 1112 mlx5_dev_close(eth_dev); 1113 return NULL; 1114 } 1115 sh = mlx5_alloc_shared_dev_ctx(spawn, mkvlist); 1116 if (!sh) 1117 return NULL; 1118 nl_rdma = mlx5_nl_init(NETLINK_RDMA); 1119 /* Check port status. */ 1120 if (spawn->phys_port <= UINT8_MAX) { 1121 /* Legacy Verbs api only support u8 port number. */ 1122 err = mlx5_glue->query_port(sh->cdev->ctx, spawn->phys_port, 1123 &port_attr); 1124 if (err) { 1125 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 1126 goto error; 1127 } 1128 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 1129 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 1130 err = EINVAL; 1131 goto error; 1132 } 1133 } else if (nl_rdma >= 0) { 1134 /* IB doesn't allow more than 255 ports, must be Ethernet. */ 1135 err = mlx5_nl_port_state(nl_rdma, 1136 spawn->phys_dev_name, 1137 spawn->phys_port); 1138 if (err < 0) { 1139 DRV_LOG(INFO, "Failed to get netlink port state: %s", 1140 strerror(rte_errno)); 1141 err = -rte_errno; 1142 goto error; 1143 } 1144 port_attr.state = (enum ibv_port_state)err; 1145 } 1146 if (port_attr.state != IBV_PORT_ACTIVE) 1147 DRV_LOG(INFO, "port is not active: \"%s\" (%d)", 1148 mlx5_glue->port_state_str(port_attr.state), 1149 port_attr.state); 1150 /* Allocate private eth device data. */ 1151 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 1152 sizeof(*priv), 1153 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1154 if (priv == NULL) { 1155 DRV_LOG(ERR, "priv allocation failure"); 1156 err = ENOMEM; 1157 goto error; 1158 } 1159 priv->sh = sh; 1160 priv->dev_port = spawn->phys_port; 1161 priv->pci_dev = spawn->pci_dev; 1162 priv->mtu = RTE_ETHER_MTU; 1163 /* Some internal functions rely on Netlink sockets, open them now. */ 1164 priv->nl_socket_rdma = nl_rdma; 1165 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 1166 priv->representor = !!switch_info->representor; 1167 priv->master = !!switch_info->master; 1168 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 1169 priv->vport_meta_tag = 0; 1170 priv->vport_meta_mask = 0; 1171 priv->pf_bond = spawn->pf_bond; 1172 1173 DRV_LOG(DEBUG, 1174 "dev_port=%u bus=%s pci=%s master=%d representor=%d pf_bond=%d\n", 1175 priv->dev_port, dpdk_dev->bus->name, 1176 priv->pci_dev ? priv->pci_dev->name : "NONE", 1177 priv->master, priv->representor, priv->pf_bond); 1178 1179 /* 1180 * If we have E-Switch we should determine the vport attributes. 1181 * E-Switch may use either source vport field or reg_c[0] metadata 1182 * register to match on vport index. The engaged part of metadata 1183 * register is defined by mask. 1184 */ 1185 if (sh->esw_mode) { 1186 err = mlx5_glue->devx_port_query(sh->cdev->ctx, 1187 spawn->phys_port, 1188 &vport_info); 1189 if (err) { 1190 DRV_LOG(WARNING, 1191 "Cannot query devx port %d on device %s", 1192 spawn->phys_port, spawn->phys_dev_name); 1193 vport_info.query_flags = 0; 1194 } 1195 } 1196 if (vport_info.query_flags & MLX5_PORT_QUERY_REG_C0) { 1197 priv->vport_meta_tag = vport_info.vport_meta_tag; 1198 priv->vport_meta_mask = vport_info.vport_meta_mask; 1199 if (!priv->vport_meta_mask) { 1200 DRV_LOG(ERR, 1201 "vport zero mask for port %d on bonding device %s", 1202 spawn->phys_port, spawn->phys_dev_name); 1203 err = ENOTSUP; 1204 goto error; 1205 } 1206 if (priv->vport_meta_tag & ~priv->vport_meta_mask) { 1207 DRV_LOG(ERR, 1208 "Invalid vport tag for port %d on bonding device %s", 1209 spawn->phys_port, spawn->phys_dev_name); 1210 err = ENOTSUP; 1211 goto error; 1212 } 1213 } 1214 if (vport_info.query_flags & MLX5_PORT_QUERY_VPORT) { 1215 priv->vport_id = vport_info.vport_id; 1216 } else if (spawn->pf_bond >= 0 && sh->esw_mode) { 1217 DRV_LOG(ERR, 1218 "Cannot deduce vport index for port %d on bonding device %s", 1219 spawn->phys_port, spawn->phys_dev_name); 1220 err = ENOTSUP; 1221 goto error; 1222 } else { 1223 /* 1224 * Suppose vport index in compatible way. Kernel/rdma_core 1225 * support single E-Switch per PF configurations only and 1226 * vport_id field contains the vport index for associated VF, 1227 * which is deduced from representor port name. 1228 * For example, let's have the IB device port 10, it has 1229 * attached network device eth0, which has port name attribute 1230 * pf0vf2, we can deduce the VF number as 2, and set vport index 1231 * as 3 (2+1). This assigning schema should be changed if the 1232 * multiple E-Switch instances per PF configurations or/and PCI 1233 * subfunctions are added. 1234 */ 1235 priv->vport_id = switch_info->representor ? 1236 switch_info->port_name + 1 : -1; 1237 } 1238 priv->representor_id = mlx5_representor_id_encode(switch_info, 1239 eth_da->type); 1240 /* 1241 * Look for sibling devices in order to reuse their switch domain 1242 * if any, otherwise allocate one. 1243 */ 1244 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) { 1245 const struct mlx5_priv *opriv = 1246 rte_eth_devices[port_id].data->dev_private; 1247 1248 if (!opriv || 1249 opriv->sh != priv->sh || 1250 opriv->domain_id == 1251 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 1252 continue; 1253 priv->domain_id = opriv->domain_id; 1254 DRV_LOG(DEBUG, "dev_port-%u inherit domain_id=%u\n", 1255 priv->dev_port, priv->domain_id); 1256 break; 1257 } 1258 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1259 err = rte_eth_switch_domain_alloc(&priv->domain_id); 1260 if (err) { 1261 err = rte_errno; 1262 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1263 strerror(rte_errno)); 1264 goto error; 1265 } 1266 own_domain_id = 1; 1267 DRV_LOG(DEBUG, "dev_port-%u new domain_id=%u\n", 1268 priv->dev_port, priv->domain_id); 1269 } 1270 if (sh->cdev->config.devx) { 1271 struct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr; 1272 1273 sh->steering_format_version = hca_attr->steering_format_version; 1274 #if defined(HAVE_MLX5DV_DR) && \ 1275 (defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) || \ 1276 defined(HAVE_MLX5_DR_CREATE_ACTION_ASO)) 1277 if (hca_attr->qos.sup && hca_attr->qos.flow_meter_old && 1278 sh->config.dv_flow_en) { 1279 uint8_t reg_c_mask = hca_attr->qos.flow_meter_reg_c_ids; 1280 /* 1281 * Meter needs two REG_C's for color match and pre-sfx 1282 * flow match. Here get the REG_C for color match. 1283 * REG_C_0 and REG_C_1 is reserved for metadata feature. 1284 */ 1285 reg_c_mask &= 0xfc; 1286 if (__builtin_popcount(reg_c_mask) < 1) { 1287 priv->mtr_en = 0; 1288 DRV_LOG(WARNING, "No available register for" 1289 " meter."); 1290 } else { 1291 /* 1292 * The meter color register is used by the 1293 * flow-hit feature as well. 1294 * The flow-hit feature must use REG_C_3 1295 * Prefer REG_C_3 if it is available. 1296 */ 1297 if (reg_c_mask & (1 << (REG_C_3 - REG_C_0))) 1298 priv->mtr_color_reg = REG_C_3; 1299 else 1300 priv->mtr_color_reg = ffs(reg_c_mask) 1301 - 1 + REG_C_0; 1302 priv->mtr_en = 1; 1303 priv->mtr_reg_share = hca_attr->qos.flow_meter; 1304 DRV_LOG(DEBUG, "The REG_C meter uses is %d", 1305 priv->mtr_color_reg); 1306 } 1307 } 1308 if (hca_attr->qos.sup && hca_attr->qos.flow_meter_aso_sup) { 1309 uint32_t log_obj_size = 1310 rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1); 1311 if (log_obj_size >= 1312 hca_attr->qos.log_meter_aso_granularity && 1313 log_obj_size <= 1314 hca_attr->qos.log_meter_aso_max_alloc) 1315 sh->meter_aso_en = 1; 1316 } 1317 if (priv->mtr_en) { 1318 err = mlx5_aso_flow_mtrs_mng_init(priv->sh); 1319 if (err) { 1320 err = -err; 1321 goto error; 1322 } 1323 } 1324 if (hca_attr->flow.tunnel_header_0_1) 1325 sh->tunnel_header_0_1 = 1; 1326 #endif 1327 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 1328 if (hca_attr->flow_hit_aso && priv->mtr_color_reg == REG_C_3) { 1329 sh->flow_hit_aso_en = 1; 1330 err = mlx5_flow_aso_age_mng_init(sh); 1331 if (err) { 1332 err = -err; 1333 goto error; 1334 } 1335 DRV_LOG(DEBUG, "Flow Hit ASO is supported."); 1336 } 1337 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 1338 #if defined(HAVE_MLX5_DR_CREATE_ACTION_ASO) && \ 1339 defined(HAVE_MLX5_DR_ACTION_ASO_CT) 1340 if (hca_attr->ct_offload && priv->mtr_color_reg == REG_C_3) { 1341 err = mlx5_flow_aso_ct_mng_init(sh); 1342 if (err) { 1343 err = -err; 1344 goto error; 1345 } 1346 DRV_LOG(DEBUG, "CT ASO is supported."); 1347 sh->ct_aso_en = 1; 1348 } 1349 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO && HAVE_MLX5_DR_ACTION_ASO_CT */ 1350 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE) 1351 if (hca_attr->log_max_ft_sampler_num > 0 && 1352 sh->config.dv_flow_en) { 1353 priv->sampler_en = 1; 1354 DRV_LOG(DEBUG, "Sampler enabled!"); 1355 } else { 1356 priv->sampler_en = 0; 1357 if (!hca_attr->log_max_ft_sampler_num) 1358 DRV_LOG(WARNING, 1359 "No available register for sampler."); 1360 else 1361 DRV_LOG(DEBUG, "DV flow is not supported!"); 1362 } 1363 #endif 1364 } 1365 /* Process parameters and store port configuration on priv structure. */ 1366 err = mlx5_port_args_config(priv, mkvlist, &priv->config); 1367 if (err) { 1368 err = rte_errno; 1369 DRV_LOG(ERR, "Failed to process port configure: %s", 1370 strerror(rte_errno)); 1371 goto error; 1372 } 1373 eth_dev = rte_eth_dev_allocate(name); 1374 if (eth_dev == NULL) { 1375 DRV_LOG(ERR, "can not allocate rte ethdev"); 1376 err = ENOMEM; 1377 goto error; 1378 } 1379 if (priv->representor) { 1380 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1381 eth_dev->data->representor_id = priv->representor_id; 1382 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) { 1383 struct mlx5_priv *opriv = 1384 rte_eth_devices[port_id].data->dev_private; 1385 if (opriv && 1386 opriv->master && 1387 opriv->domain_id == priv->domain_id && 1388 opriv->sh == priv->sh) { 1389 eth_dev->data->backer_port_id = port_id; 1390 break; 1391 } 1392 } 1393 if (port_id >= RTE_MAX_ETHPORTS) 1394 eth_dev->data->backer_port_id = eth_dev->data->port_id; 1395 } 1396 priv->mp_id.port_id = eth_dev->data->port_id; 1397 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 1398 /* 1399 * Store associated network device interface index. This index 1400 * is permanent throughout the lifetime of device. So, we may store 1401 * the ifindex here and use the cached value further. 1402 */ 1403 MLX5_ASSERT(spawn->ifindex); 1404 priv->if_index = spawn->ifindex; 1405 priv->lag_affinity_idx = sh->refcnt - 1; 1406 eth_dev->data->dev_private = priv; 1407 priv->dev_data = eth_dev->data; 1408 eth_dev->data->mac_addrs = priv->mac; 1409 eth_dev->device = dpdk_dev; 1410 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1411 /* Configure the first MAC address by default. */ 1412 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1413 DRV_LOG(ERR, 1414 "port %u cannot get MAC address, is mlx5_en" 1415 " loaded? (errno: %s)", 1416 eth_dev->data->port_id, strerror(rte_errno)); 1417 err = ENODEV; 1418 goto error; 1419 } 1420 DRV_LOG(INFO, 1421 "port %u MAC address is " RTE_ETHER_ADDR_PRT_FMT, 1422 eth_dev->data->port_id, RTE_ETHER_ADDR_BYTES(&mac)); 1423 #ifdef RTE_LIBRTE_MLX5_DEBUG 1424 { 1425 char ifname[MLX5_NAMESIZE]; 1426 1427 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1428 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1429 eth_dev->data->port_id, ifname); 1430 else 1431 DRV_LOG(DEBUG, "port %u ifname is unknown", 1432 eth_dev->data->port_id); 1433 } 1434 #endif 1435 /* Get actual MTU if possible. */ 1436 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1437 if (err) { 1438 err = rte_errno; 1439 goto error; 1440 } 1441 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1442 priv->mtu); 1443 /* Initialize burst functions to prevent crashes before link-up. */ 1444 eth_dev->rx_pkt_burst = rte_eth_pkt_burst_dummy; 1445 eth_dev->tx_pkt_burst = rte_eth_pkt_burst_dummy; 1446 eth_dev->dev_ops = &mlx5_dev_ops; 1447 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1448 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1449 eth_dev->rx_queue_count = mlx5_rx_queue_count; 1450 /* Register MAC address. */ 1451 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1452 if (sh->dev_cap.vf && sh->config.vf_nl_en) 1453 mlx5_nl_mac_addr_sync(priv->nl_socket_route, 1454 mlx5_ifindex(eth_dev), 1455 eth_dev->data->mac_addrs, 1456 MLX5_MAX_MAC_ADDRESSES); 1457 priv->ctrl_flows = 0; 1458 rte_spinlock_init(&priv->flow_list_lock); 1459 TAILQ_INIT(&priv->flow_meters); 1460 priv->mtr_profile_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_PTR); 1461 if (!priv->mtr_profile_tbl) 1462 goto error; 1463 /* Bring Ethernet device up. */ 1464 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1465 eth_dev->data->port_id); 1466 mlx5_set_link_up(eth_dev); 1467 /* 1468 * Even though the interrupt handler is not installed yet, 1469 * interrupts will still trigger on the async_fd from 1470 * Verbs context returned by ibv_open_device(). 1471 */ 1472 mlx5_link_update(eth_dev, 0); 1473 for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) { 1474 icfg[i].release_mem_en = !!sh->config.reclaim_mode; 1475 if (sh->config.reclaim_mode) 1476 icfg[i].per_core_cache = 0; 1477 priv->flows[i] = mlx5_ipool_create(&icfg[i]); 1478 if (!priv->flows[i]) 1479 goto error; 1480 } 1481 /* Create context for virtual machine VLAN workaround. */ 1482 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); 1483 if (sh->config.dv_flow_en) { 1484 err = mlx5_alloc_shared_dr(priv); 1485 if (err) 1486 goto error; 1487 if (mlx5_flex_item_port_init(eth_dev) < 0) 1488 goto error; 1489 } 1490 if (mlx5_devx_obj_ops_en(sh)) { 1491 priv->obj_ops = devx_obj_ops; 1492 mlx5_queue_counter_id_prepare(eth_dev); 1493 priv->obj_ops.lb_dummy_queue_create = 1494 mlx5_rxq_ibv_obj_dummy_lb_create; 1495 priv->obj_ops.lb_dummy_queue_release = 1496 mlx5_rxq_ibv_obj_dummy_lb_release; 1497 } else if (spawn->max_port > UINT8_MAX) { 1498 /* Verbs can't support ports larger than 255 by design. */ 1499 DRV_LOG(ERR, "must enable DV and ESW when RDMA link ports > 255"); 1500 err = ENOTSUP; 1501 goto error; 1502 } else { 1503 priv->obj_ops = ibv_obj_ops; 1504 } 1505 if (sh->config.tx_pp && 1506 priv->obj_ops.txq_obj_new != mlx5_txq_devx_obj_new) { 1507 /* 1508 * HAVE_MLX5DV_DEVX_UAR_OFFSET is required to support 1509 * packet pacing and already checked above. 1510 * Hence, we should only make sure the SQs will be created 1511 * with DevX, not with Verbs. 1512 * Verbs allocates the SQ UAR on its own and it can't be shared 1513 * with Clock Queue UAR as required for Tx scheduling. 1514 */ 1515 DRV_LOG(ERR, "Verbs SQs, UAR can't be shared as required for packet pacing"); 1516 err = ENODEV; 1517 goto error; 1518 } 1519 priv->drop_queue.hrxq = mlx5_drop_action_create(eth_dev); 1520 if (!priv->drop_queue.hrxq) 1521 goto error; 1522 /* Port representor shares the same max priority with pf port. */ 1523 if (!priv->sh->flow_priority_check_flag) { 1524 /* Supported Verbs flow priority number detection. */ 1525 err = mlx5_flow_discover_priorities(eth_dev); 1526 priv->sh->flow_max_priority = err; 1527 priv->sh->flow_priority_check_flag = 1; 1528 } else { 1529 err = priv->sh->flow_max_priority; 1530 } 1531 if (err < 0) { 1532 err = -err; 1533 goto error; 1534 } 1535 mlx5_set_metadata_mask(eth_dev); 1536 if (sh->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1537 !priv->sh->dv_regc0_mask) { 1538 DRV_LOG(ERR, "metadata mode %u is not supported " 1539 "(no metadata reg_c[0] is available)", 1540 sh->config.dv_xmeta_en); 1541 err = ENOTSUP; 1542 goto error; 1543 } 1544 priv->hrxqs = mlx5_list_create("hrxq", eth_dev, true, 1545 mlx5_hrxq_create_cb, 1546 mlx5_hrxq_match_cb, 1547 mlx5_hrxq_remove_cb, 1548 mlx5_hrxq_clone_cb, 1549 mlx5_hrxq_clone_free_cb); 1550 if (!priv->hrxqs) 1551 goto error; 1552 rte_rwlock_init(&priv->ind_tbls_lock); 1553 /* Query availability of metadata reg_c's. */ 1554 if (!priv->sh->metadata_regc_check_flag) { 1555 err = mlx5_flow_discover_mreg_c(eth_dev); 1556 if (err < 0) { 1557 err = -err; 1558 goto error; 1559 } 1560 } 1561 if (!mlx5_flow_ext_mreg_supported(eth_dev)) { 1562 DRV_LOG(DEBUG, 1563 "port %u extensive metadata register is not supported", 1564 eth_dev->data->port_id); 1565 if (sh->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1566 DRV_LOG(ERR, "metadata mode %u is not supported " 1567 "(no metadata registers available)", 1568 sh->config.dv_xmeta_en); 1569 err = ENOTSUP; 1570 goto error; 1571 } 1572 } 1573 if (sh->config.dv_flow_en && 1574 sh->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1575 mlx5_flow_ext_mreg_supported(eth_dev) && 1576 priv->sh->dv_regc0_mask) { 1577 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME, 1578 MLX5_FLOW_MREG_HTABLE_SZ, 1579 false, true, eth_dev, 1580 flow_dv_mreg_create_cb, 1581 flow_dv_mreg_match_cb, 1582 flow_dv_mreg_remove_cb, 1583 flow_dv_mreg_clone_cb, 1584 flow_dv_mreg_clone_free_cb); 1585 if (!priv->mreg_cp_tbl) { 1586 err = ENOMEM; 1587 goto error; 1588 } 1589 } 1590 rte_spinlock_init(&priv->shared_act_sl); 1591 mlx5_flow_counter_mode_config(eth_dev); 1592 mlx5_flow_drop_action_config(eth_dev); 1593 if (sh->config.dv_flow_en) 1594 eth_dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 1595 return eth_dev; 1596 error: 1597 if (priv) { 1598 if (priv->mreg_cp_tbl) 1599 mlx5_hlist_destroy(priv->mreg_cp_tbl); 1600 if (priv->sh) 1601 mlx5_os_free_shared_dr(priv); 1602 if (priv->nl_socket_route >= 0) 1603 close(priv->nl_socket_route); 1604 if (priv->vmwa_context) 1605 mlx5_vlan_vmwa_exit(priv->vmwa_context); 1606 if (eth_dev && priv->drop_queue.hrxq) 1607 mlx5_drop_action_destroy(eth_dev); 1608 if (priv->mtr_profile_tbl) 1609 mlx5_l3t_destroy(priv->mtr_profile_tbl); 1610 if (own_domain_id) 1611 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1612 if (priv->hrxqs) 1613 mlx5_list_destroy(priv->hrxqs); 1614 if (eth_dev && priv->flex_item_map) 1615 mlx5_flex_item_port_cleanup(eth_dev); 1616 mlx5_free(priv); 1617 if (eth_dev != NULL) 1618 eth_dev->data->dev_private = NULL; 1619 } 1620 if (eth_dev != NULL) { 1621 /* mac_addrs must not be freed alone because part of 1622 * dev_private 1623 **/ 1624 eth_dev->data->mac_addrs = NULL; 1625 rte_eth_dev_release_port(eth_dev); 1626 } 1627 if (sh) 1628 mlx5_free_shared_dev_ctx(sh); 1629 if (nl_rdma >= 0) 1630 close(nl_rdma); 1631 MLX5_ASSERT(err > 0); 1632 rte_errno = err; 1633 return NULL; 1634 } 1635 1636 /** 1637 * Comparison callback to sort device data. 1638 * 1639 * This is meant to be used with qsort(). 1640 * 1641 * @param a[in] 1642 * Pointer to pointer to first data object. 1643 * @param b[in] 1644 * Pointer to pointer to second data object. 1645 * 1646 * @return 1647 * 0 if both objects are equal, less than 0 if the first argument is less 1648 * than the second, greater than 0 otherwise. 1649 */ 1650 static int 1651 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1652 { 1653 const struct mlx5_switch_info *si_a = 1654 &((const struct mlx5_dev_spawn_data *)a)->info; 1655 const struct mlx5_switch_info *si_b = 1656 &((const struct mlx5_dev_spawn_data *)b)->info; 1657 int ret; 1658 1659 /* Master device first. */ 1660 ret = si_b->master - si_a->master; 1661 if (ret) 1662 return ret; 1663 /* Then representor devices. */ 1664 ret = si_b->representor - si_a->representor; 1665 if (ret) 1666 return ret; 1667 /* Unidentified devices come last in no specific order. */ 1668 if (!si_a->representor) 1669 return 0; 1670 /* Order representors by name. */ 1671 return si_a->port_name - si_b->port_name; 1672 } 1673 1674 /** 1675 * Match PCI information for possible slaves of bonding device. 1676 * 1677 * @param[in] ibdev_name 1678 * Name of Infiniband device. 1679 * @param[in] pci_dev 1680 * Pointer to primary PCI address structure to match. 1681 * @param[in] nl_rdma 1682 * Netlink RDMA group socket handle. 1683 * @param[in] owner 1684 * Representor owner PF index. 1685 * @param[out] bond_info 1686 * Pointer to bonding information. 1687 * 1688 * @return 1689 * negative value if no bonding device found, otherwise 1690 * positive index of slave PF in bonding. 1691 */ 1692 static int 1693 mlx5_device_bond_pci_match(const char *ibdev_name, 1694 const struct rte_pci_addr *pci_dev, 1695 int nl_rdma, uint16_t owner, 1696 struct mlx5_bond_info *bond_info) 1697 { 1698 char ifname[IF_NAMESIZE + 1]; 1699 unsigned int ifindex; 1700 unsigned int np, i; 1701 FILE *bond_file = NULL, *file; 1702 int pf = -1; 1703 int ret; 1704 uint8_t cur_guid[32] = {0}; 1705 uint8_t guid[32] = {0}; 1706 1707 /* 1708 * Try to get master device name. If something goes wrong suppose 1709 * the lack of kernel support and no bonding devices. 1710 */ 1711 memset(bond_info, 0, sizeof(*bond_info)); 1712 if (nl_rdma < 0) 1713 return -1; 1714 if (!strstr(ibdev_name, "bond")) 1715 return -1; 1716 np = mlx5_nl_portnum(nl_rdma, ibdev_name); 1717 if (!np) 1718 return -1; 1719 if (mlx5_get_device_guid(pci_dev, cur_guid, sizeof(cur_guid)) < 0) 1720 return -1; 1721 /* 1722 * The master device might not be on the predefined port(not on port 1723 * index 1, it is not guaranteed), we have to scan all Infiniband 1724 * device ports and find master. 1725 */ 1726 for (i = 1; i <= np; ++i) { 1727 /* Check whether Infiniband port is populated. */ 1728 ifindex = mlx5_nl_ifindex(nl_rdma, ibdev_name, i); 1729 if (!ifindex) 1730 continue; 1731 if (!if_indextoname(ifindex, ifname)) 1732 continue; 1733 /* Try to read bonding slave names from sysfs. */ 1734 MKSTR(slaves, 1735 "/sys/class/net/%s/master/bonding/slaves", ifname); 1736 bond_file = fopen(slaves, "r"); 1737 if (bond_file) 1738 break; 1739 } 1740 if (!bond_file) 1741 return -1; 1742 /* Use safe format to check maximal buffer length. */ 1743 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE); 1744 while (fscanf(bond_file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) { 1745 char tmp_str[IF_NAMESIZE + 32]; 1746 struct rte_pci_addr pci_addr; 1747 struct mlx5_switch_info info; 1748 int ret; 1749 1750 /* Process slave interface names in the loop. */ 1751 snprintf(tmp_str, sizeof(tmp_str), 1752 "/sys/class/net/%s", ifname); 1753 if (mlx5_get_pci_addr(tmp_str, &pci_addr)) { 1754 DRV_LOG(WARNING, 1755 "Cannot get PCI address for netdev \"%s\".", 1756 ifname); 1757 continue; 1758 } 1759 /* Slave interface PCI address match found. */ 1760 snprintf(tmp_str, sizeof(tmp_str), 1761 "/sys/class/net/%s/phys_port_name", ifname); 1762 file = fopen(tmp_str, "rb"); 1763 if (!file) 1764 break; 1765 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET; 1766 if (fscanf(file, "%32s", tmp_str) == 1) 1767 mlx5_translate_port_name(tmp_str, &info); 1768 fclose(file); 1769 /* Only process PF ports. */ 1770 if (info.name_type != MLX5_PHYS_PORT_NAME_TYPE_LEGACY && 1771 info.name_type != MLX5_PHYS_PORT_NAME_TYPE_UPLINK) 1772 continue; 1773 /* Check max bonding member. */ 1774 if (info.port_name >= MLX5_BOND_MAX_PORTS) { 1775 DRV_LOG(WARNING, "bonding index out of range, " 1776 "please increase MLX5_BOND_MAX_PORTS: %s", 1777 tmp_str); 1778 break; 1779 } 1780 /* Get ifindex. */ 1781 snprintf(tmp_str, sizeof(tmp_str), 1782 "/sys/class/net/%s/ifindex", ifname); 1783 file = fopen(tmp_str, "rb"); 1784 if (!file) 1785 break; 1786 ret = fscanf(file, "%u", &ifindex); 1787 fclose(file); 1788 if (ret != 1) 1789 break; 1790 /* Save bonding info. */ 1791 strncpy(bond_info->ports[info.port_name].ifname, ifname, 1792 sizeof(bond_info->ports[0].ifname)); 1793 bond_info->ports[info.port_name].pci_addr = pci_addr; 1794 bond_info->ports[info.port_name].ifindex = ifindex; 1795 bond_info->n_port++; 1796 /* 1797 * Under socket direct mode, bonding will use 1798 * system_image_guid as identification. 1799 * After OFED 5.4, guid is readable (ret >= 0) under sysfs. 1800 * All bonding members should have the same guid even if driver 1801 * is using PCIe BDF. 1802 */ 1803 ret = mlx5_get_device_guid(&pci_addr, guid, sizeof(guid)); 1804 if (ret < 0) 1805 break; 1806 else if (ret > 0) { 1807 if (!memcmp(guid, cur_guid, sizeof(guid)) && 1808 owner == info.port_name && 1809 (owner != 0 || (owner == 0 && 1810 !rte_pci_addr_cmp(pci_dev, &pci_addr)))) 1811 pf = info.port_name; 1812 } else if (pci_dev->domain == pci_addr.domain && 1813 pci_dev->bus == pci_addr.bus && 1814 pci_dev->devid == pci_addr.devid && 1815 ((pci_dev->function == 0 && 1816 pci_dev->function + owner == pci_addr.function) || 1817 (pci_dev->function == owner && 1818 pci_addr.function == owner))) 1819 pf = info.port_name; 1820 } 1821 if (pf >= 0) { 1822 /* Get bond interface info */ 1823 ret = mlx5_sysfs_bond_info(ifindex, &bond_info->ifindex, 1824 bond_info->ifname); 1825 if (ret) 1826 DRV_LOG(ERR, "unable to get bond info: %s", 1827 strerror(rte_errno)); 1828 else 1829 DRV_LOG(INFO, "PF device %u, bond device %u(%s)", 1830 ifindex, bond_info->ifindex, bond_info->ifname); 1831 } 1832 if (owner == 0 && pf != 0) { 1833 DRV_LOG(INFO, "PCIe instance %04x:%02x:%02x.%x isn't bonding owner", 1834 pci_dev->domain, pci_dev->bus, pci_dev->devid, 1835 pci_dev->function); 1836 } 1837 return pf; 1838 } 1839 1840 /** 1841 * Register a PCI device within bonding. 1842 * 1843 * This function spawns Ethernet devices out of a given PCI device and 1844 * bonding owner PF index. 1845 * 1846 * @param[in] cdev 1847 * Pointer to common mlx5 device structure. 1848 * @param[in] req_eth_da 1849 * Requested ethdev device argument. 1850 * @param[in] owner_id 1851 * Requested owner PF port ID within bonding device, default to 0. 1852 * @param[in, out] mkvlist 1853 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. 1854 * 1855 * @return 1856 * 0 on success, a negative errno value otherwise and rte_errno is set. 1857 */ 1858 static int 1859 mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev, 1860 struct rte_eth_devargs *req_eth_da, 1861 uint16_t owner_id, struct mlx5_kvargs_ctrl *mkvlist) 1862 { 1863 struct ibv_device **ibv_list; 1864 /* 1865 * Number of found IB Devices matching with requested PCI BDF. 1866 * nd != 1 means there are multiple IB devices over the same 1867 * PCI device and we have representors and master. 1868 */ 1869 unsigned int nd = 0; 1870 /* 1871 * Number of found IB device Ports. nd = 1 and np = 1..n means 1872 * we have the single multiport IB device, and there may be 1873 * representors attached to some of found ports. 1874 */ 1875 unsigned int np = 0; 1876 /* 1877 * Number of DPDK ethernet devices to Spawn - either over 1878 * multiple IB devices or multiple ports of single IB device. 1879 * Actually this is the number of iterations to spawn. 1880 */ 1881 unsigned int ns = 0; 1882 /* 1883 * Bonding device 1884 * < 0 - no bonding device (single one) 1885 * >= 0 - bonding device (value is slave PF index) 1886 */ 1887 int bd = -1; 1888 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev); 1889 struct mlx5_dev_spawn_data *list = NULL; 1890 struct rte_eth_devargs eth_da = *req_eth_da; 1891 struct rte_pci_addr owner_pci = pci_dev->addr; /* Owner PF. */ 1892 struct mlx5_bond_info bond_info; 1893 int ret = -1; 1894 1895 errno = 0; 1896 ibv_list = mlx5_glue->get_device_list(&ret); 1897 if (!ibv_list) { 1898 rte_errno = errno ? errno : ENOSYS; 1899 DRV_LOG(ERR, "Cannot list devices, is ib_uverbs loaded?"); 1900 return -rte_errno; 1901 } 1902 /* 1903 * First scan the list of all Infiniband devices to find 1904 * matching ones, gathering into the list. 1905 */ 1906 struct ibv_device *ibv_match[ret + 1]; 1907 int nl_route = mlx5_nl_init(NETLINK_ROUTE); 1908 int nl_rdma = mlx5_nl_init(NETLINK_RDMA); 1909 unsigned int i; 1910 1911 while (ret-- > 0) { 1912 struct rte_pci_addr pci_addr; 1913 1914 DRV_LOG(DEBUG, "Checking device \"%s\"", ibv_list[ret]->name); 1915 bd = mlx5_device_bond_pci_match(ibv_list[ret]->name, &owner_pci, 1916 nl_rdma, owner_id, &bond_info); 1917 if (bd >= 0) { 1918 /* 1919 * Bonding device detected. Only one match is allowed, 1920 * the bonding is supported over multi-port IB device, 1921 * there should be no matches on representor PCI 1922 * functions or non VF LAG bonding devices with 1923 * specified address. 1924 */ 1925 if (nd) { 1926 DRV_LOG(ERR, 1927 "multiple PCI match on bonding device" 1928 "\"%s\" found", ibv_list[ret]->name); 1929 rte_errno = ENOENT; 1930 ret = -rte_errno; 1931 goto exit; 1932 } 1933 /* Amend owner pci address if owner PF ID specified. */ 1934 if (eth_da.nb_representor_ports) 1935 owner_pci.function += owner_id; 1936 DRV_LOG(INFO, 1937 "PCI information matches for slave %d bonding device \"%s\"", 1938 bd, ibv_list[ret]->name); 1939 ibv_match[nd++] = ibv_list[ret]; 1940 break; 1941 } else { 1942 /* Bonding device not found. */ 1943 if (mlx5_get_pci_addr(ibv_list[ret]->ibdev_path, 1944 &pci_addr)) 1945 continue; 1946 if (owner_pci.domain != pci_addr.domain || 1947 owner_pci.bus != pci_addr.bus || 1948 owner_pci.devid != pci_addr.devid || 1949 owner_pci.function != pci_addr.function) 1950 continue; 1951 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 1952 ibv_list[ret]->name); 1953 ibv_match[nd++] = ibv_list[ret]; 1954 } 1955 } 1956 ibv_match[nd] = NULL; 1957 if (!nd) { 1958 /* No device matches, just complain and bail out. */ 1959 DRV_LOG(WARNING, 1960 "No Verbs device matches PCI device " PCI_PRI_FMT "," 1961 " are kernel drivers loaded?", 1962 owner_pci.domain, owner_pci.bus, 1963 owner_pci.devid, owner_pci.function); 1964 rte_errno = ENOENT; 1965 ret = -rte_errno; 1966 goto exit; 1967 } 1968 if (nd == 1) { 1969 /* 1970 * Found single matching device may have multiple ports. 1971 * Each port may be representor, we have to check the port 1972 * number and check the representors existence. 1973 */ 1974 if (nl_rdma >= 0) 1975 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 1976 if (!np) 1977 DRV_LOG(WARNING, 1978 "Cannot get IB device \"%s\" ports number.", 1979 ibv_match[0]->name); 1980 if (bd >= 0 && !np) { 1981 DRV_LOG(ERR, "Cannot get ports for bonding device."); 1982 rte_errno = ENOENT; 1983 ret = -rte_errno; 1984 goto exit; 1985 } 1986 } 1987 /* Now we can determine the maximal amount of devices to be spawned. */ 1988 list = mlx5_malloc(MLX5_MEM_ZERO, 1989 sizeof(struct mlx5_dev_spawn_data) * (np ? np : nd), 1990 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1991 if (!list) { 1992 DRV_LOG(ERR, "Spawn data array allocation failure."); 1993 rte_errno = ENOMEM; 1994 ret = -rte_errno; 1995 goto exit; 1996 } 1997 if (bd >= 0 || np > 1) { 1998 /* 1999 * Single IB device with multiple ports found, 2000 * it may be E-Switch master device and representors. 2001 * We have to perform identification through the ports. 2002 */ 2003 MLX5_ASSERT(nl_rdma >= 0); 2004 MLX5_ASSERT(ns == 0); 2005 MLX5_ASSERT(nd == 1); 2006 MLX5_ASSERT(np); 2007 for (i = 1; i <= np; ++i) { 2008 list[ns].bond_info = &bond_info; 2009 list[ns].max_port = np; 2010 list[ns].phys_port = i; 2011 list[ns].phys_dev_name = ibv_match[0]->name; 2012 list[ns].eth_dev = NULL; 2013 list[ns].pci_dev = pci_dev; 2014 list[ns].cdev = cdev; 2015 list[ns].pf_bond = bd; 2016 list[ns].ifindex = mlx5_nl_ifindex(nl_rdma, 2017 ibv_match[0]->name, 2018 i); 2019 if (!list[ns].ifindex) { 2020 /* 2021 * No network interface index found for the 2022 * specified port, it means there is no 2023 * representor on this port. It's OK, 2024 * there can be disabled ports, for example 2025 * if sriov_numvfs < sriov_totalvfs. 2026 */ 2027 continue; 2028 } 2029 ret = -1; 2030 if (nl_route >= 0) 2031 ret = mlx5_nl_switch_info(nl_route, 2032 list[ns].ifindex, 2033 &list[ns].info); 2034 if (ret || (!list[ns].info.representor && 2035 !list[ns].info.master)) { 2036 /* 2037 * We failed to recognize representors with 2038 * Netlink, let's try to perform the task 2039 * with sysfs. 2040 */ 2041 ret = mlx5_sysfs_switch_info(list[ns].ifindex, 2042 &list[ns].info); 2043 } 2044 if (!ret && bd >= 0) { 2045 switch (list[ns].info.name_type) { 2046 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 2047 if (np == 1) { 2048 /* 2049 * Force standalone bonding 2050 * device for ROCE LAG 2051 * configurations. 2052 */ 2053 list[ns].info.master = 0; 2054 list[ns].info.representor = 0; 2055 } 2056 if (list[ns].info.port_name == bd) 2057 ns++; 2058 break; 2059 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF: 2060 /* Fallthrough */ 2061 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 2062 /* Fallthrough */ 2063 case MLX5_PHYS_PORT_NAME_TYPE_PFSF: 2064 if (list[ns].info.pf_num == bd) 2065 ns++; 2066 break; 2067 default: 2068 break; 2069 } 2070 continue; 2071 } 2072 if (!ret && (list[ns].info.representor ^ 2073 list[ns].info.master)) 2074 ns++; 2075 } 2076 if (!ns) { 2077 DRV_LOG(ERR, 2078 "Unable to recognize master/representors on the IB device with multiple ports."); 2079 rte_errno = ENOENT; 2080 ret = -rte_errno; 2081 goto exit; 2082 } 2083 } else { 2084 /* 2085 * The existence of several matching entries (nd > 1) means 2086 * port representors have been instantiated. No existing Verbs 2087 * call nor sysfs entries can tell them apart, this can only 2088 * be done through Netlink calls assuming kernel drivers are 2089 * recent enough to support them. 2090 * 2091 * In the event of identification failure through Netlink, 2092 * try again through sysfs, then: 2093 * 2094 * 1. A single IB device matches (nd == 1) with single 2095 * port (np=0/1) and is not a representor, assume 2096 * no switch support. 2097 * 2098 * 2. Otherwise no safe assumptions can be made; 2099 * complain louder and bail out. 2100 */ 2101 for (i = 0; i != nd; ++i) { 2102 memset(&list[ns].info, 0, sizeof(list[ns].info)); 2103 list[ns].bond_info = NULL; 2104 list[ns].max_port = 1; 2105 list[ns].phys_port = 1; 2106 list[ns].phys_dev_name = ibv_match[i]->name; 2107 list[ns].eth_dev = NULL; 2108 list[ns].pci_dev = pci_dev; 2109 list[ns].cdev = cdev; 2110 list[ns].pf_bond = -1; 2111 list[ns].ifindex = 0; 2112 if (nl_rdma >= 0) 2113 list[ns].ifindex = mlx5_nl_ifindex 2114 (nl_rdma, 2115 ibv_match[i]->name, 2116 1); 2117 if (!list[ns].ifindex) { 2118 char ifname[IF_NAMESIZE]; 2119 2120 /* 2121 * Netlink failed, it may happen with old 2122 * ib_core kernel driver (before 4.16). 2123 * We can assume there is old driver because 2124 * here we are processing single ports IB 2125 * devices. Let's try sysfs to retrieve 2126 * the ifindex. The method works for 2127 * master device only. 2128 */ 2129 if (nd > 1) { 2130 /* 2131 * Multiple devices found, assume 2132 * representors, can not distinguish 2133 * master/representor and retrieve 2134 * ifindex via sysfs. 2135 */ 2136 continue; 2137 } 2138 ret = mlx5_get_ifname_sysfs 2139 (ibv_match[i]->ibdev_path, ifname); 2140 if (!ret) 2141 list[ns].ifindex = 2142 if_nametoindex(ifname); 2143 if (!list[ns].ifindex) { 2144 /* 2145 * No network interface index found 2146 * for the specified device, it means 2147 * there it is neither representor 2148 * nor master. 2149 */ 2150 continue; 2151 } 2152 } 2153 ret = -1; 2154 if (nl_route >= 0) 2155 ret = mlx5_nl_switch_info(nl_route, 2156 list[ns].ifindex, 2157 &list[ns].info); 2158 if (ret || (!list[ns].info.representor && 2159 !list[ns].info.master)) { 2160 /* 2161 * We failed to recognize representors with 2162 * Netlink, let's try to perform the task 2163 * with sysfs. 2164 */ 2165 ret = mlx5_sysfs_switch_info(list[ns].ifindex, 2166 &list[ns].info); 2167 } 2168 if (!ret && (list[ns].info.representor ^ 2169 list[ns].info.master)) { 2170 ns++; 2171 } else if ((nd == 1) && 2172 !list[ns].info.representor && 2173 !list[ns].info.master) { 2174 /* 2175 * Single IB device with one physical port and 2176 * attached network device. 2177 * May be SRIOV is not enabled or there is no 2178 * representors. 2179 */ 2180 DRV_LOG(INFO, "No E-Switch support detected."); 2181 ns++; 2182 break; 2183 } 2184 } 2185 if (!ns) { 2186 DRV_LOG(ERR, 2187 "Unable to recognize master/representors on the multiple IB devices."); 2188 rte_errno = ENOENT; 2189 ret = -rte_errno; 2190 goto exit; 2191 } 2192 /* 2193 * New kernels may add the switch_id attribute for the case 2194 * there is no E-Switch and we wrongly recognized the only 2195 * device as master. Override this if there is the single 2196 * device with single port and new device name format present. 2197 */ 2198 if (nd == 1 && 2199 list[0].info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) { 2200 list[0].info.master = 0; 2201 list[0].info.representor = 0; 2202 } 2203 } 2204 MLX5_ASSERT(ns); 2205 /* 2206 * Sort list to probe devices in natural order for users convenience 2207 * (i.e. master first, then representors from lowest to highest ID). 2208 */ 2209 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 2210 if (eth_da.type != RTE_ETH_REPRESENTOR_NONE) { 2211 /* Set devargs default values. */ 2212 if (eth_da.nb_mh_controllers == 0) { 2213 eth_da.nb_mh_controllers = 1; 2214 eth_da.mh_controllers[0] = 0; 2215 } 2216 if (eth_da.nb_ports == 0 && ns > 0) { 2217 if (list[0].pf_bond >= 0 && list[0].info.representor) 2218 DRV_LOG(WARNING, "Representor on Bonding device should use pf#vf# syntax: %s", 2219 pci_dev->device.devargs->args); 2220 eth_da.nb_ports = 1; 2221 eth_da.ports[0] = list[0].info.pf_num; 2222 } 2223 if (eth_da.nb_representor_ports == 0) { 2224 eth_da.nb_representor_ports = 1; 2225 eth_da.representor_ports[0] = 0; 2226 } 2227 } 2228 for (i = 0; i != ns; ++i) { 2229 uint32_t restore; 2230 2231 list[i].eth_dev = mlx5_dev_spawn(cdev->dev, &list[i], ð_da, 2232 mkvlist); 2233 if (!list[i].eth_dev) { 2234 if (rte_errno != EBUSY && rte_errno != EEXIST) 2235 break; 2236 /* Device is disabled or already spawned. Ignore it. */ 2237 continue; 2238 } 2239 restore = list[i].eth_dev->data->dev_flags; 2240 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 2241 /** 2242 * Each representor has a dedicated interrupts vector. 2243 * rte_eth_copy_pci_info() assigns PF interrupts handle to 2244 * representor eth_dev object because representor and PF 2245 * share the same PCI address. 2246 * Override representor device with a dedicated 2247 * interrupts handle here. 2248 * Representor interrupts handle is released in mlx5_dev_stop(). 2249 */ 2250 if (list[i].info.representor) { 2251 struct rte_intr_handle *intr_handle = 2252 rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); 2253 if (intr_handle == NULL) { 2254 DRV_LOG(ERR, 2255 "port %u failed to allocate memory for interrupt handler " 2256 "Rx interrupts will not be supported", 2257 i); 2258 rte_errno = ENOMEM; 2259 ret = -rte_errno; 2260 goto exit; 2261 } 2262 list[i].eth_dev->intr_handle = intr_handle; 2263 } 2264 /* Restore non-PCI flags cleared by the above call. */ 2265 list[i].eth_dev->data->dev_flags |= restore; 2266 rte_eth_dev_probing_finish(list[i].eth_dev); 2267 } 2268 if (i != ns) { 2269 DRV_LOG(ERR, 2270 "probe of PCI device " PCI_PRI_FMT " aborted after" 2271 " encountering an error: %s", 2272 owner_pci.domain, owner_pci.bus, 2273 owner_pci.devid, owner_pci.function, 2274 strerror(rte_errno)); 2275 ret = -rte_errno; 2276 /* Roll back. */ 2277 while (i--) { 2278 if (!list[i].eth_dev) 2279 continue; 2280 mlx5_dev_close(list[i].eth_dev); 2281 /* mac_addrs must not be freed because in dev_private */ 2282 list[i].eth_dev->data->mac_addrs = NULL; 2283 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 2284 } 2285 /* Restore original error. */ 2286 rte_errno = -ret; 2287 } else { 2288 ret = 0; 2289 } 2290 exit: 2291 /* 2292 * Do the routine cleanup: 2293 * - close opened Netlink sockets 2294 * - free allocated spawn data array 2295 * - free the Infiniband device list 2296 */ 2297 if (nl_rdma >= 0) 2298 close(nl_rdma); 2299 if (nl_route >= 0) 2300 close(nl_route); 2301 if (list) 2302 mlx5_free(list); 2303 MLX5_ASSERT(ibv_list); 2304 mlx5_glue->free_device_list(ibv_list); 2305 return ret; 2306 } 2307 2308 static int 2309 mlx5_os_parse_eth_devargs(struct rte_device *dev, 2310 struct rte_eth_devargs *eth_da) 2311 { 2312 int ret = 0; 2313 2314 if (dev->devargs == NULL) 2315 return 0; 2316 memset(eth_da, 0, sizeof(*eth_da)); 2317 /* Parse representor information first from class argument. */ 2318 if (dev->devargs->cls_str) 2319 ret = rte_eth_devargs_parse(dev->devargs->cls_str, eth_da); 2320 if (ret != 0) { 2321 DRV_LOG(ERR, "failed to parse device arguments: %s", 2322 dev->devargs->cls_str); 2323 return -rte_errno; 2324 } 2325 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE) { 2326 /* Parse legacy device argument */ 2327 ret = rte_eth_devargs_parse(dev->devargs->args, eth_da); 2328 if (ret) { 2329 DRV_LOG(ERR, "failed to parse device arguments: %s", 2330 dev->devargs->args); 2331 return -rte_errno; 2332 } 2333 } 2334 return 0; 2335 } 2336 2337 /** 2338 * Callback to register a PCI device. 2339 * 2340 * This function spawns Ethernet devices out of a given PCI device. 2341 * 2342 * @param[in] cdev 2343 * Pointer to common mlx5 device structure. 2344 * @param[in, out] mkvlist 2345 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. 2346 * 2347 * @return 2348 * 0 on success, a negative errno value otherwise and rte_errno is set. 2349 */ 2350 static int 2351 mlx5_os_pci_probe(struct mlx5_common_device *cdev, 2352 struct mlx5_kvargs_ctrl *mkvlist) 2353 { 2354 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev); 2355 struct rte_eth_devargs eth_da = { .nb_ports = 0 }; 2356 int ret = 0; 2357 uint16_t p; 2358 2359 ret = mlx5_os_parse_eth_devargs(cdev->dev, ð_da); 2360 if (ret != 0) 2361 return ret; 2362 2363 if (eth_da.nb_ports > 0) { 2364 /* Iterate all port if devargs pf is range: "pf[0-1]vf[...]". */ 2365 for (p = 0; p < eth_da.nb_ports; p++) { 2366 ret = mlx5_os_pci_probe_pf(cdev, ð_da, 2367 eth_da.ports[p], mkvlist); 2368 if (ret) 2369 break; 2370 } 2371 if (ret) { 2372 DRV_LOG(ERR, "Probe of PCI device " PCI_PRI_FMT " " 2373 "aborted due to prodding failure of PF %u", 2374 pci_dev->addr.domain, pci_dev->addr.bus, 2375 pci_dev->addr.devid, pci_dev->addr.function, 2376 eth_da.ports[p]); 2377 mlx5_net_remove(cdev); 2378 } 2379 } else { 2380 ret = mlx5_os_pci_probe_pf(cdev, ð_da, 0, mkvlist); 2381 } 2382 return ret; 2383 } 2384 2385 /* Probe a single SF device on auxiliary bus, no representor support. */ 2386 static int 2387 mlx5_os_auxiliary_probe(struct mlx5_common_device *cdev, 2388 struct mlx5_kvargs_ctrl *mkvlist) 2389 { 2390 struct rte_eth_devargs eth_da = { .nb_ports = 0 }; 2391 struct mlx5_dev_spawn_data spawn = { .pf_bond = -1 }; 2392 struct rte_device *dev = cdev->dev; 2393 struct rte_auxiliary_device *adev = RTE_DEV_TO_AUXILIARY(dev); 2394 struct rte_eth_dev *eth_dev; 2395 int ret = 0; 2396 2397 /* Parse ethdev devargs. */ 2398 ret = mlx5_os_parse_eth_devargs(dev, ð_da); 2399 if (ret != 0) 2400 return ret; 2401 /* Init spawn data. */ 2402 spawn.max_port = 1; 2403 spawn.phys_port = 1; 2404 spawn.phys_dev_name = mlx5_os_get_ctx_device_name(cdev->ctx); 2405 ret = mlx5_auxiliary_get_ifindex(dev->name); 2406 if (ret < 0) { 2407 DRV_LOG(ERR, "failed to get ethdev ifindex: %s", dev->name); 2408 return ret; 2409 } 2410 spawn.ifindex = ret; 2411 spawn.cdev = cdev; 2412 /* Spawn device. */ 2413 eth_dev = mlx5_dev_spawn(dev, &spawn, ð_da, mkvlist); 2414 if (eth_dev == NULL) 2415 return -rte_errno; 2416 /* Post create. */ 2417 eth_dev->intr_handle = adev->intr_handle; 2418 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 2419 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2420 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_RMV; 2421 eth_dev->data->numa_node = dev->numa_node; 2422 } 2423 rte_eth_dev_probing_finish(eth_dev); 2424 return 0; 2425 } 2426 2427 /** 2428 * Net class driver callback to probe a device. 2429 * 2430 * This function probe PCI bus device(s) or a single SF on auxiliary bus. 2431 * 2432 * @param[in] cdev 2433 * Pointer to the common mlx5 device. 2434 * @param[in, out] mkvlist 2435 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. 2436 * 2437 * @return 2438 * 0 on success, a negative errno value otherwise and rte_errno is set. 2439 */ 2440 int 2441 mlx5_os_net_probe(struct mlx5_common_device *cdev, 2442 struct mlx5_kvargs_ctrl *mkvlist) 2443 { 2444 int ret; 2445 2446 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 2447 mlx5_pmd_socket_init(); 2448 ret = mlx5_init_once(); 2449 if (ret) { 2450 DRV_LOG(ERR, "Unable to init PMD global data: %s", 2451 strerror(rte_errno)); 2452 return -rte_errno; 2453 } 2454 ret = mlx5_probe_again_args_validate(cdev, mkvlist); 2455 if (ret) { 2456 DRV_LOG(ERR, "Probe again parameters are not compatible : %s", 2457 strerror(rte_errno)); 2458 return -rte_errno; 2459 } 2460 if (mlx5_dev_is_pci(cdev->dev)) 2461 return mlx5_os_pci_probe(cdev, mkvlist); 2462 else 2463 return mlx5_os_auxiliary_probe(cdev, mkvlist); 2464 } 2465 2466 /** 2467 * Cleanup resources when the last device is closed. 2468 */ 2469 void 2470 mlx5_os_net_cleanup(void) 2471 { 2472 mlx5_pmd_socket_uninit(); 2473 } 2474 2475 /** 2476 * Install shared asynchronous device events handler. 2477 * This function is implemented to support event sharing 2478 * between multiple ports of single IB device. 2479 * 2480 * @param sh 2481 * Pointer to mlx5_dev_ctx_shared object. 2482 */ 2483 void 2484 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) 2485 { 2486 int ret; 2487 int flags; 2488 struct ibv_context *ctx = sh->cdev->ctx; 2489 2490 sh->intr_handle = rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); 2491 if (sh->intr_handle == NULL) { 2492 DRV_LOG(ERR, "Fail to allocate intr_handle"); 2493 rte_errno = ENOMEM; 2494 return; 2495 } 2496 rte_intr_fd_set(sh->intr_handle, -1); 2497 2498 flags = fcntl(ctx->async_fd, F_GETFL); 2499 ret = fcntl(ctx->async_fd, F_SETFL, flags | O_NONBLOCK); 2500 if (ret) { 2501 DRV_LOG(INFO, "failed to change file descriptor async event" 2502 " queue"); 2503 } else { 2504 rte_intr_fd_set(sh->intr_handle, ctx->async_fd); 2505 rte_intr_type_set(sh->intr_handle, RTE_INTR_HANDLE_EXT); 2506 if (rte_intr_callback_register(sh->intr_handle, 2507 mlx5_dev_interrupt_handler, sh)) { 2508 DRV_LOG(INFO, "Fail to install the shared interrupt."); 2509 rte_intr_fd_set(sh->intr_handle, -1); 2510 } 2511 } 2512 if (sh->cdev->config.devx) { 2513 #ifdef HAVE_IBV_DEVX_ASYNC 2514 sh->intr_handle_devx = 2515 rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); 2516 if (!sh->intr_handle_devx) { 2517 DRV_LOG(ERR, "Fail to allocate intr_handle"); 2518 rte_errno = ENOMEM; 2519 return; 2520 } 2521 rte_intr_fd_set(sh->intr_handle_devx, -1); 2522 sh->devx_comp = (void *)mlx5_glue->devx_create_cmd_comp(ctx); 2523 struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp; 2524 if (!devx_comp) { 2525 DRV_LOG(INFO, "failed to allocate devx_comp."); 2526 return; 2527 } 2528 flags = fcntl(devx_comp->fd, F_GETFL); 2529 ret = fcntl(devx_comp->fd, F_SETFL, flags | O_NONBLOCK); 2530 if (ret) { 2531 DRV_LOG(INFO, "failed to change file descriptor" 2532 " devx comp"); 2533 return; 2534 } 2535 rte_intr_fd_set(sh->intr_handle_devx, devx_comp->fd); 2536 rte_intr_type_set(sh->intr_handle_devx, 2537 RTE_INTR_HANDLE_EXT); 2538 if (rte_intr_callback_register(sh->intr_handle_devx, 2539 mlx5_dev_interrupt_handler_devx, sh)) { 2540 DRV_LOG(INFO, "Fail to install the devx shared" 2541 " interrupt."); 2542 rte_intr_fd_set(sh->intr_handle_devx, -1); 2543 } 2544 #endif /* HAVE_IBV_DEVX_ASYNC */ 2545 } 2546 } 2547 2548 /** 2549 * Uninstall shared asynchronous device events handler. 2550 * This function is implemented to support event sharing 2551 * between multiple ports of single IB device. 2552 * 2553 * @param dev 2554 * Pointer to mlx5_dev_ctx_shared object. 2555 */ 2556 void 2557 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) 2558 { 2559 if (rte_intr_fd_get(sh->intr_handle) >= 0) 2560 mlx5_intr_callback_unregister(sh->intr_handle, 2561 mlx5_dev_interrupt_handler, sh); 2562 rte_intr_instance_free(sh->intr_handle); 2563 #ifdef HAVE_IBV_DEVX_ASYNC 2564 if (rte_intr_fd_get(sh->intr_handle_devx) >= 0) 2565 rte_intr_callback_unregister(sh->intr_handle_devx, 2566 mlx5_dev_interrupt_handler_devx, sh); 2567 rte_intr_instance_free(sh->intr_handle_devx); 2568 if (sh->devx_comp) 2569 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp); 2570 #endif 2571 } 2572 2573 /** 2574 * Read statistics by a named counter. 2575 * 2576 * @param[in] priv 2577 * Pointer to the private device data structure. 2578 * @param[in] ctr_name 2579 * Pointer to the name of the statistic counter to read 2580 * @param[out] stat 2581 * Pointer to read statistic value. 2582 * @return 2583 * 0 on success and stat is valud, 1 if failed to read the value 2584 * rte_errno is set. 2585 * 2586 */ 2587 int 2588 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name, 2589 uint64_t *stat) 2590 { 2591 int fd; 2592 2593 if (priv->sh) { 2594 if (priv->q_counters != NULL && 2595 strcmp(ctr_name, "out_of_buffer") == 0) 2596 return mlx5_devx_cmd_queue_counter_query 2597 (priv->q_counters, 0, (uint32_t *)stat); 2598 MKSTR(path, "%s/ports/%d/hw_counters/%s", 2599 priv->sh->ibdev_path, 2600 priv->dev_port, 2601 ctr_name); 2602 fd = open(path, O_RDONLY); 2603 /* 2604 * in switchdev the file location is not per port 2605 * but rather in <ibdev_path>/hw_counters/<file_name>. 2606 */ 2607 if (fd == -1) { 2608 MKSTR(path1, "%s/hw_counters/%s", 2609 priv->sh->ibdev_path, 2610 ctr_name); 2611 fd = open(path1, O_RDONLY); 2612 } 2613 if (fd != -1) { 2614 char buf[21] = {'\0'}; 2615 ssize_t n = read(fd, buf, sizeof(buf)); 2616 2617 close(fd); 2618 if (n != -1) { 2619 *stat = strtoull(buf, NULL, 10); 2620 return 0; 2621 } 2622 } 2623 } 2624 *stat = 0; 2625 return 1; 2626 } 2627 2628 /** 2629 * Remove a MAC address from device 2630 * 2631 * @param dev 2632 * Pointer to Ethernet device structure. 2633 * @param index 2634 * MAC address index. 2635 */ 2636 void 2637 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 2638 { 2639 struct mlx5_priv *priv = dev->data->dev_private; 2640 const int vf = priv->sh->dev_cap.vf; 2641 2642 if (vf) 2643 mlx5_nl_mac_addr_remove(priv->nl_socket_route, 2644 mlx5_ifindex(dev), priv->mac_own, 2645 &dev->data->mac_addrs[index], index); 2646 } 2647 2648 /** 2649 * Adds a MAC address to the device 2650 * 2651 * @param dev 2652 * Pointer to Ethernet device structure. 2653 * @param mac_addr 2654 * MAC address to register. 2655 * @param index 2656 * MAC address index. 2657 * 2658 * @return 2659 * 0 on success, a negative errno value otherwise 2660 */ 2661 int 2662 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 2663 uint32_t index) 2664 { 2665 struct mlx5_priv *priv = dev->data->dev_private; 2666 const int vf = priv->sh->dev_cap.vf; 2667 int ret = 0; 2668 2669 if (vf) 2670 ret = mlx5_nl_mac_addr_add(priv->nl_socket_route, 2671 mlx5_ifindex(dev), priv->mac_own, 2672 mac, index); 2673 return ret; 2674 } 2675 2676 /** 2677 * Modify a VF MAC address 2678 * 2679 * @param priv 2680 * Pointer to device private data. 2681 * @param mac_addr 2682 * MAC address to modify into. 2683 * @param iface_idx 2684 * Net device interface index 2685 * @param vf_index 2686 * VF index 2687 * 2688 * @return 2689 * 0 on success, a negative errno value otherwise 2690 */ 2691 int 2692 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, 2693 unsigned int iface_idx, 2694 struct rte_ether_addr *mac_addr, 2695 int vf_index) 2696 { 2697 return mlx5_nl_vf_mac_addr_modify 2698 (priv->nl_socket_route, iface_idx, mac_addr, vf_index); 2699 } 2700 2701 /** 2702 * Set device promiscuous mode 2703 * 2704 * @param dev 2705 * Pointer to Ethernet device structure. 2706 * @param enable 2707 * 0 - promiscuous is disabled, otherwise - enabled 2708 * 2709 * @return 2710 * 0 on success, a negative error value otherwise 2711 */ 2712 int 2713 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable) 2714 { 2715 struct mlx5_priv *priv = dev->data->dev_private; 2716 2717 return mlx5_nl_promisc(priv->nl_socket_route, 2718 mlx5_ifindex(dev), !!enable); 2719 } 2720 2721 /** 2722 * Set device promiscuous mode 2723 * 2724 * @param dev 2725 * Pointer to Ethernet device structure. 2726 * @param enable 2727 * 0 - all multicase is disabled, otherwise - enabled 2728 * 2729 * @return 2730 * 0 on success, a negative error value otherwise 2731 */ 2732 int 2733 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) 2734 { 2735 struct mlx5_priv *priv = dev->data->dev_private; 2736 2737 return mlx5_nl_allmulti(priv->nl_socket_route, 2738 mlx5_ifindex(dev), !!enable); 2739 } 2740 2741 /** 2742 * Flush device MAC addresses 2743 * 2744 * @param dev 2745 * Pointer to Ethernet device structure. 2746 * 2747 */ 2748 void 2749 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev) 2750 { 2751 struct mlx5_priv *priv = dev->data->dev_private; 2752 2753 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev), 2754 dev->data->mac_addrs, 2755 MLX5_MAX_MAC_ADDRESSES, priv->mac_own); 2756 } 2757