1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2020 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 #include <strings.h> 7 #include <stdint.h> 8 #include <sys/mman.h> 9 10 #include <rte_malloc.h> 11 #include <rte_log.h> 12 #include <rte_errno.h> 13 #include <bus_pci_driver.h> 14 #include <rte_pci.h> 15 #include <rte_regexdev_driver.h> 16 #include <rte_mbuf.h> 17 18 #include <infiniband/mlx5dv.h> 19 #include <mlx5_glue.h> 20 #include <mlx5_common.h> 21 #include <mlx5_prm.h> 22 23 #include "mlx5_regex_utils.h" 24 #include "mlx5_rxp.h" 25 #include "mlx5_regex.h" 26 27 #define MLX5_REGEX_MAX_WQE_INDEX 0xffff 28 #define MLX5_REGEX_METADATA_SIZE ((size_t)64) 29 #define MLX5_REGEX_MAX_OUTPUT (((size_t)1) << 11) 30 #define MLX5_REGEX_WQE_CTRL_OFFSET 12 31 #define MLX5_REGEX_WQE_METADATA_OFFSET 16 32 #define MLX5_REGEX_WQE_GATHER_OFFSET 32 33 #define MLX5_REGEX_WQE_SCATTER_OFFSET 48 34 #define MLX5_REGEX_METADATA_OFF 32 35 #define MLX5_REGEX_UMR_WQE_SIZE 192 36 /* The maximum KLMs can be added to one UMR indirect mkey. */ 37 #define MLX5_REGEX_MAX_KLM_NUM 128 38 /* The KLM array size for one job. */ 39 #define MLX5_REGEX_KLMS_SIZE \ 40 ((MLX5_REGEX_MAX_KLM_NUM) * sizeof(struct mlx5_klm)) 41 /* In WQE set mode, the pi should be quarter of the MLX5_REGEX_MAX_WQE_INDEX. */ 42 #define MLX5_REGEX_UMR_QP_PI_IDX(pi, ops) \ 43 (((pi) + (ops)) & (MLX5_REGEX_MAX_WQE_INDEX >> 2)) 44 #ifdef RTE_LIBRTE_MLX5_DEBUG 45 #define MLX5_REGEX_DEBUG 0 46 #endif 47 #ifdef HAVE_MLX5_UMR_IMKEY 48 static uint16_t max_nb_segs = MLX5_REGEX_MAX_KLM_NUM; 49 #else 50 static uint16_t max_nb_segs = 1; 51 #endif 52 53 uint16_t 54 mlx5_regexdev_max_segs_get(void) 55 { 56 return max_nb_segs; 57 } 58 59 #ifdef MLX5_REGEX_DEBUG 60 static inline uint16_t 61 validate_ops(struct rte_regex_ops **ops, uint16_t nb_ops) 62 { 63 uint16_t nb_left = nb_ops; 64 struct rte_mbuf *mbuf; 65 66 while (nb_left--) { 67 mbuf = ops[nb_left]->mbuf; 68 if ((mbuf->pkt_len > MLX5_RXP_MAX_JOB_LENGTH) || 69 (mbuf->nb_segs > max_nb_segs)) { 70 DRV_LOG(ERR, "Failed to validate regex ops"); 71 return 1; 72 } 73 } 74 return 0; 75 } 76 #endif 77 78 static inline uint32_t 79 qp_size_get(struct mlx5_regex_hw_qp *qp) 80 { 81 return (1U << qp->log_nb_desc); 82 } 83 84 static inline uint32_t 85 cq_size_get(struct mlx5_regex_cq *cq) 86 { 87 return (1U << cq->log_nb_desc); 88 } 89 90 struct mlx5_regex_job { 91 uint64_t user_id; 92 volatile uint8_t *output; 93 volatile uint8_t *metadata; 94 struct mlx5_klm *imkey_array; /* Indirect mkey's KLM array. */ 95 struct mlx5_devx_obj *imkey; /* UMR WQE's indirect meky. */ 96 } __rte_cached_aligned; 97 98 static inline void 99 set_data_seg(struct mlx5_wqe_data_seg *seg, 100 uint32_t length, uint32_t lkey, 101 uintptr_t address) 102 { 103 seg->byte_count = rte_cpu_to_be_32(length); 104 seg->lkey = rte_cpu_to_be_32(lkey); 105 seg->addr = rte_cpu_to_be_64(address); 106 } 107 108 static inline void 109 set_metadata_seg(struct mlx5_wqe_metadata_seg *seg, 110 uint32_t mmo_control_31_0, uint32_t lkey, 111 uintptr_t address) 112 { 113 seg->mmo_control_31_0 = htobe32(mmo_control_31_0); 114 seg->lkey = rte_cpu_to_be_32(lkey); 115 seg->addr = rte_cpu_to_be_64(address); 116 } 117 118 static inline void 119 set_regex_ctrl_seg(void *seg, uint8_t le, uint16_t subset_id0, 120 uint16_t subset_id1, uint16_t subset_id2, 121 uint16_t subset_id3, uint8_t ctrl) 122 { 123 MLX5_SET(regexp_mmo_control, seg, le, le); 124 MLX5_SET(regexp_mmo_control, seg, ctrl, ctrl); 125 MLX5_SET(regexp_mmo_control, seg, subset_id_0, subset_id0); 126 MLX5_SET(regexp_mmo_control, seg, subset_id_1, subset_id1); 127 MLX5_SET(regexp_mmo_control, seg, subset_id_2, subset_id2); 128 MLX5_SET(regexp_mmo_control, seg, subset_id_3, subset_id3); 129 } 130 131 static inline void 132 set_wqe_ctrl_seg(struct mlx5_wqe_ctrl_seg *seg, uint16_t pi, uint8_t opcode, 133 uint8_t opmod, uint32_t qp_num, uint8_t fm_ce_se, uint8_t ds, 134 uint8_t signature, uint32_t imm) 135 { 136 seg->opmod_idx_opcode = rte_cpu_to_be_32(((uint32_t)opmod << 24) | 137 ((uint32_t)pi << 8) | 138 opcode); 139 seg->qpn_ds = rte_cpu_to_be_32((qp_num << 8) | ds); 140 seg->fm_ce_se = fm_ce_se; 141 seg->signature = signature; 142 seg->imm = imm; 143 } 144 145 static inline void 146 __prep_one(struct mlx5_regex_priv *priv, struct mlx5_regex_hw_qp *qp_obj, 147 struct rte_regex_ops *op, struct mlx5_regex_job *job, 148 size_t pi, struct mlx5_klm *klm) 149 { 150 size_t wqe_offset = (pi & (qp_size_get(qp_obj) - 1)) * 151 (MLX5_SEND_WQE_BB << (priv->has_umr ? 2 : 0)) + 152 (priv->has_umr ? MLX5_REGEX_UMR_WQE_SIZE : 0); 153 uint16_t group0 = op->req_flags & RTE_REGEX_OPS_REQ_GROUP_ID0_VALID_F ? 154 op->group_id0 : 0; 155 uint16_t group1 = op->req_flags & RTE_REGEX_OPS_REQ_GROUP_ID1_VALID_F ? 156 op->group_id1 : 0; 157 uint16_t group2 = op->req_flags & RTE_REGEX_OPS_REQ_GROUP_ID2_VALID_F ? 158 op->group_id2 : 0; 159 uint16_t group3 = op->req_flags & RTE_REGEX_OPS_REQ_GROUP_ID3_VALID_F ? 160 op->group_id3 : 0; 161 uint8_t control = op->req_flags & 162 RTE_REGEX_OPS_REQ_MATCH_HIGH_PRIORITY_F ? 1 : 0; 163 164 /* For backward compatibility. */ 165 if (!(op->req_flags & (RTE_REGEX_OPS_REQ_GROUP_ID0_VALID_F | 166 RTE_REGEX_OPS_REQ_GROUP_ID1_VALID_F | 167 RTE_REGEX_OPS_REQ_GROUP_ID2_VALID_F | 168 RTE_REGEX_OPS_REQ_GROUP_ID3_VALID_F))) 169 group0 = op->group_id0; 170 uint8_t *wqe = (uint8_t *)(uintptr_t)qp_obj->qp_obj.wqes + wqe_offset; 171 int ds = 4; /* ctrl + meta + input + output */ 172 173 set_wqe_ctrl_seg((struct mlx5_wqe_ctrl_seg *)wqe, 174 (priv->has_umr ? (pi * 4 + 3) : pi), 175 MLX5_OPCODE_MMO, MLX5_OPC_MOD_MMO_REGEX, 176 qp_obj->qp_obj.qp->id, 0, ds, 0, 0); 177 set_regex_ctrl_seg(wqe + 12, 0, group0, group1, group2, group3, 178 control); 179 struct mlx5_wqe_data_seg *input_seg = 180 (struct mlx5_wqe_data_seg *)(wqe + 181 MLX5_REGEX_WQE_GATHER_OFFSET); 182 input_seg->byte_count = rte_cpu_to_be_32(klm->byte_count); 183 input_seg->addr = rte_cpu_to_be_64(klm->address); 184 input_seg->lkey = klm->mkey; 185 job->user_id = op->user_id; 186 } 187 188 static inline void 189 prep_one(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp, 190 struct mlx5_regex_hw_qp *qp_obj, struct rte_regex_ops *op, 191 struct mlx5_regex_job *job) 192 { 193 struct mlx5_klm klm; 194 195 klm.byte_count = rte_pktmbuf_data_len(op->mbuf); 196 klm.mkey = mlx5_mr_mb2mr(&qp->mr_ctrl, op->mbuf); 197 klm.address = rte_pktmbuf_mtod(op->mbuf, uintptr_t); 198 __prep_one(priv, qp_obj, op, job, qp_obj->pi, &klm); 199 qp_obj->db_pi = qp_obj->pi; 200 qp_obj->pi = (qp_obj->pi + 1) & MLX5_REGEX_MAX_WQE_INDEX; 201 } 202 203 static inline void 204 send_doorbell(struct mlx5_regex_priv *priv, struct mlx5_regex_hw_qp *qp) 205 { 206 size_t wqe_offset = (qp->db_pi & (qp_size_get(qp) - 1)) * 207 (MLX5_SEND_WQE_BB << (priv->has_umr ? 2 : 0)) + 208 (priv->has_umr ? MLX5_REGEX_UMR_WQE_SIZE : 0); 209 uint8_t *wqe = (uint8_t *)(uintptr_t)qp->qp_obj.wqes + wqe_offset; 210 uint32_t actual_pi = (priv->has_umr ? (qp->db_pi * 4 + 3) : qp->db_pi) & 211 MLX5_REGEX_MAX_WQE_INDEX; 212 213 /* Or the fm_ce_se instead of set, avoid the fence be cleared. */ 214 ((struct mlx5_wqe_ctrl_seg *)wqe)->fm_ce_se |= MLX5_WQE_CTRL_CQ_UPDATE; 215 mlx5_doorbell_ring(&priv->uar.bf_db, *(volatile uint64_t *)wqe, 216 actual_pi, &qp->qp_obj.db_rec[MLX5_SND_DBR], 217 !priv->uar.dbnc); 218 } 219 220 static inline int 221 get_free(struct mlx5_regex_hw_qp *qp, uint8_t has_umr) { 222 return (qp_size_get(qp) - ((qp->pi - qp->ci) & 223 (has_umr ? (MLX5_REGEX_MAX_WQE_INDEX >> 2) : 224 MLX5_REGEX_MAX_WQE_INDEX))); 225 } 226 227 static inline uint32_t 228 job_id_get(uint32_t qid, size_t qp_size, size_t index) { 229 return qid * qp_size + (index & (qp_size - 1)); 230 } 231 232 #ifdef HAVE_MLX5_UMR_IMKEY 233 static inline int 234 mkey_klm_available(struct mlx5_klm *klm, uint32_t pos, uint32_t new) 235 { 236 return (klm && ((pos + new) <= MLX5_REGEX_MAX_KLM_NUM)); 237 } 238 239 static inline void 240 complete_umr_wqe(struct mlx5_regex_qp *qp, struct mlx5_regex_hw_qp *qp_obj, 241 struct mlx5_regex_job *mkey_job, 242 size_t umr_index, uint32_t klm_size, uint32_t total_len) 243 { 244 size_t wqe_offset = (umr_index & (qp_size_get(qp_obj) - 1)) * 245 (MLX5_SEND_WQE_BB * 4); 246 struct mlx5_wqe_ctrl_seg *wqe = (struct mlx5_wqe_ctrl_seg *)((uint8_t *) 247 (uintptr_t)qp_obj->qp_obj.wqes + wqe_offset); 248 struct mlx5_wqe_umr_ctrl_seg *ucseg = 249 (struct mlx5_wqe_umr_ctrl_seg *)(wqe + 1); 250 struct mlx5_wqe_mkey_context_seg *mkc = 251 (struct mlx5_wqe_mkey_context_seg *)(ucseg + 1); 252 struct mlx5_klm *iklm = (struct mlx5_klm *)(mkc + 1); 253 uint16_t klm_align = RTE_ALIGN(klm_size, 4); 254 255 memset(wqe, 0, MLX5_REGEX_UMR_WQE_SIZE); 256 /* Set WQE control seg. Non-inline KLM UMR WQE size must be 9 WQE_DS. */ 257 set_wqe_ctrl_seg(wqe, (umr_index * 4), MLX5_OPCODE_UMR, 258 0, qp_obj->qp_obj.qp->id, 0, 9, 0, 259 rte_cpu_to_be_32(mkey_job->imkey->id)); 260 /* Set UMR WQE control seg. */ 261 ucseg->mkey_mask |= rte_cpu_to_be_64(MLX5_WQE_UMR_CTRL_MKEY_MASK_LEN | 262 MLX5_WQE_UMR_CTRL_FLAG_TRNSLATION_OFFSET | 263 MLX5_WQE_UMR_CTRL_MKEY_MASK_ACCESS_LOCAL_WRITE); 264 ucseg->klm_octowords = rte_cpu_to_be_16(klm_align); 265 /* Set mkey context seg. */ 266 mkc->len = rte_cpu_to_be_64(total_len); 267 mkc->qpn_mkey = rte_cpu_to_be_32(0xffffff00 | 268 (mkey_job->imkey->id & 0xff)); 269 /* Set UMR pointer to data seg. */ 270 iklm->address = rte_cpu_to_be_64 271 ((uintptr_t)((char *)mkey_job->imkey_array)); 272 iklm->mkey = rte_cpu_to_be_32(qp->imkey_addr->lkey); 273 iklm->byte_count = rte_cpu_to_be_32(klm_align); 274 /* Clear the padding memory. */ 275 memset((uint8_t *)&mkey_job->imkey_array[klm_size], 0, 276 sizeof(struct mlx5_klm) * (klm_align - klm_size)); 277 278 /* Add the following RegEx WQE with fence. */ 279 wqe = (struct mlx5_wqe_ctrl_seg *) 280 (((uint8_t *)wqe) + MLX5_REGEX_UMR_WQE_SIZE); 281 wqe->fm_ce_se |= MLX5_WQE_CTRL_INITIATOR_SMALL_FENCE; 282 } 283 284 static inline void 285 prep_nop_regex_wqe_set(struct mlx5_regex_priv *priv, 286 struct mlx5_regex_hw_qp *qp, struct rte_regex_ops *op, 287 struct mlx5_regex_job *job, size_t pi, struct mlx5_klm *klm) 288 { 289 size_t wqe_offset = (pi & (qp_size_get(qp) - 1)) * 290 (MLX5_SEND_WQE_BB << 2); 291 struct mlx5_wqe_ctrl_seg *wqe = (struct mlx5_wqe_ctrl_seg *)((uint8_t *) 292 (uintptr_t)qp->qp_obj.wqes + wqe_offset); 293 294 /* Clear the WQE memory used as UMR WQE previously. */ 295 if ((rte_be_to_cpu_32(wqe->opmod_idx_opcode) & 0xff) != MLX5_OPCODE_NOP) 296 memset(wqe, 0, MLX5_REGEX_UMR_WQE_SIZE); 297 /* UMR WQE size is 9 DS, align nop WQE to 3 WQEBBS(12 DS). */ 298 set_wqe_ctrl_seg(wqe, pi * 4, MLX5_OPCODE_NOP, 0, qp->qp_obj.qp->id, 299 0, 12, 0, 0); 300 __prep_one(priv, qp, op, job, pi, klm); 301 } 302 303 static inline void 304 prep_regex_umr_wqe_set(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp, 305 struct mlx5_regex_hw_qp *qp_obj, struct rte_regex_ops **op, 306 size_t nb_ops) 307 { 308 struct mlx5_regex_job *job = NULL; 309 size_t hw_qpid = qp_obj->qpn, mkey_job_id = 0; 310 size_t left_ops = nb_ops; 311 uint32_t klm_num = 0; 312 uint32_t len = 0; 313 struct mlx5_klm *mkey_klm = NULL; 314 struct mlx5_klm klm; 315 uintptr_t addr; 316 317 while (left_ops--) 318 rte_prefetch0(op[left_ops]); 319 left_ops = nb_ops; 320 /* 321 * Build the WQE set by reverse. In case the burst may consume 322 * multiple mkeys, build the WQE set as normal will hard to 323 * address the last mkey index, since we will only know the last 324 * RegEx WQE's index when finishes building. 325 */ 326 while (left_ops--) { 327 struct rte_mbuf *mbuf = op[left_ops]->mbuf; 328 size_t pi = MLX5_REGEX_UMR_QP_PI_IDX(qp_obj->pi, left_ops); 329 330 if (mbuf->nb_segs > 1) { 331 size_t scatter_size = 0; 332 333 if (!mkey_klm_available(mkey_klm, klm_num, 334 mbuf->nb_segs)) { 335 /* 336 * The mkey's KLM is full, create the UMR 337 * WQE in the next WQE set. 338 */ 339 if (mkey_klm) 340 complete_umr_wqe(qp, qp_obj, 341 &qp->jobs[mkey_job_id], 342 MLX5_REGEX_UMR_QP_PI_IDX(pi, 1), 343 klm_num, len); 344 /* 345 * Get the indircet mkey and KLM array index 346 * from the last WQE set. 347 */ 348 mkey_job_id = job_id_get(hw_qpid, 349 qp_size_get(qp_obj), pi); 350 mkey_klm = qp->jobs[mkey_job_id].imkey_array; 351 klm_num = 0; 352 len = 0; 353 } 354 /* Build RegEx WQE's data segment KLM. */ 355 klm.address = len; 356 klm.mkey = rte_cpu_to_be_32 357 (qp->jobs[mkey_job_id].imkey->id); 358 while (mbuf) { 359 addr = rte_pktmbuf_mtod(mbuf, uintptr_t); 360 /* Build indirect mkey seg's KLM. */ 361 mkey_klm->mkey = mlx5_mr_mb2mr(&qp->mr_ctrl, 362 mbuf); 363 mkey_klm->address = rte_cpu_to_be_64(addr); 364 mkey_klm->byte_count = rte_cpu_to_be_32 365 (rte_pktmbuf_data_len(mbuf)); 366 /* 367 * Save the mbuf's total size for RegEx data 368 * segment. 369 */ 370 scatter_size += rte_pktmbuf_data_len(mbuf); 371 mkey_klm++; 372 klm_num++; 373 mbuf = mbuf->next; 374 } 375 len += scatter_size; 376 klm.byte_count = scatter_size; 377 } else { 378 /* The single mubf case. Build the KLM directly. */ 379 klm.mkey = mlx5_mr_mb2mr(&qp->mr_ctrl, mbuf); 380 klm.address = rte_pktmbuf_mtod(mbuf, uintptr_t); 381 klm.byte_count = rte_pktmbuf_data_len(mbuf); 382 } 383 job = &qp->jobs[job_id_get(hw_qpid, qp_size_get(qp_obj), pi)]; 384 /* 385 * Build the nop + RegEx WQE set by default. The fist nop WQE 386 * will be updated later as UMR WQE if scattered mubf exist. 387 */ 388 prep_nop_regex_wqe_set(priv, qp_obj, op[left_ops], job, pi, 389 &klm); 390 } 391 /* 392 * Scattered mbuf have been added to the KLM array. Complete the build 393 * of UMR WQE, update the first nop WQE as UMR WQE. 394 */ 395 if (mkey_klm) 396 complete_umr_wqe(qp, qp_obj, &qp->jobs[mkey_job_id], qp_obj->pi, 397 klm_num, len); 398 qp_obj->db_pi = MLX5_REGEX_UMR_QP_PI_IDX(qp_obj->pi, nb_ops - 1); 399 qp_obj->pi = MLX5_REGEX_UMR_QP_PI_IDX(qp_obj->pi, nb_ops); 400 } 401 402 uint16_t 403 mlx5_regexdev_enqueue_gga(struct rte_regexdev *dev, uint16_t qp_id, 404 struct rte_regex_ops **ops, uint16_t nb_ops) 405 { 406 struct mlx5_regex_priv *priv = dev->data->dev_private; 407 struct mlx5_regex_qp *queue = &priv->qps[qp_id]; 408 struct mlx5_regex_hw_qp *qp_obj; 409 size_t hw_qpid, nb_left = nb_ops, nb_desc; 410 411 #ifdef MLX5_REGEX_DEBUG 412 if (validate_ops(ops, nb_ops)) 413 return 0; 414 #endif 415 416 while ((hw_qpid = ffs(queue->free_qps))) { 417 hw_qpid--; /* ffs returns 1 for bit 0 */ 418 qp_obj = &queue->qps[hw_qpid]; 419 nb_desc = get_free(qp_obj, priv->has_umr); 420 if (nb_desc) { 421 /* The ops be handled can't exceed nb_ops. */ 422 if (nb_desc > nb_left) 423 nb_desc = nb_left; 424 else 425 queue->free_qps &= ~(1 << hw_qpid); 426 prep_regex_umr_wqe_set(priv, queue, qp_obj, ops, 427 nb_desc); 428 send_doorbell(priv, qp_obj); 429 nb_left -= nb_desc; 430 } 431 if (!nb_left) 432 break; 433 ops += nb_desc; 434 } 435 nb_ops -= nb_left; 436 queue->pi += nb_ops; 437 return nb_ops; 438 } 439 #endif 440 441 uint16_t 442 mlx5_regexdev_enqueue(struct rte_regexdev *dev, uint16_t qp_id, 443 struct rte_regex_ops **ops, uint16_t nb_ops) 444 { 445 struct mlx5_regex_priv *priv = dev->data->dev_private; 446 struct mlx5_regex_qp *queue = &priv->qps[qp_id]; 447 struct mlx5_regex_hw_qp *qp_obj; 448 size_t hw_qpid, job_id, i = 0; 449 450 #ifdef MLX5_REGEX_DEBUG 451 if (validate_ops(ops, nb_ops)) 452 return 0; 453 #endif 454 455 while ((hw_qpid = ffs(queue->free_qps))) { 456 hw_qpid--; /* ffs returns 1 for bit 0 */ 457 qp_obj = &queue->qps[hw_qpid]; 458 while (get_free(qp_obj, priv->has_umr)) { 459 job_id = job_id_get(hw_qpid, qp_size_get(qp_obj), 460 qp_obj->pi); 461 prep_one(priv, queue, qp_obj, ops[i], 462 &queue->jobs[job_id]); 463 i++; 464 if (unlikely(i == nb_ops)) { 465 send_doorbell(priv, qp_obj); 466 goto out; 467 } 468 } 469 queue->free_qps &= ~(1 << hw_qpid); 470 send_doorbell(priv, qp_obj); 471 } 472 473 out: 474 queue->pi += i; 475 return i; 476 } 477 478 #define MLX5_REGEX_RESP_SZ 8 479 480 static inline void 481 extract_result(struct rte_regex_ops *op, struct mlx5_regex_job *job) 482 { 483 size_t j; 484 size_t offset; 485 uint16_t status; 486 487 op->user_id = job->user_id; 488 op->nb_matches = MLX5_GET_VOLATILE(regexp_metadata, job->metadata + 489 MLX5_REGEX_METADATA_OFF, 490 match_count); 491 op->nb_actual_matches = MLX5_GET_VOLATILE(regexp_metadata, 492 job->metadata + 493 MLX5_REGEX_METADATA_OFF, 494 detected_match_count); 495 for (j = 0; j < op->nb_matches; j++) { 496 offset = MLX5_REGEX_RESP_SZ * j; 497 op->matches[j].rule_id = 498 MLX5_GET_VOLATILE(regexp_match_tuple, 499 (job->output + offset), rule_id); 500 op->matches[j].start_offset = 501 MLX5_GET_VOLATILE(regexp_match_tuple, 502 (job->output + offset), start_ptr); 503 op->matches[j].len = 504 MLX5_GET_VOLATILE(regexp_match_tuple, 505 (job->output + offset), length); 506 } 507 status = MLX5_GET_VOLATILE(regexp_metadata, job->metadata + 508 MLX5_REGEX_METADATA_OFF, 509 status); 510 op->rsp_flags = 0; 511 if (status & MLX5_RXP_RESP_STATUS_PMI_SOJ) 512 op->rsp_flags |= RTE_REGEX_OPS_RSP_PMI_SOJ_F; 513 if (status & MLX5_RXP_RESP_STATUS_PMI_EOJ) 514 op->rsp_flags |= RTE_REGEX_OPS_RSP_PMI_EOJ_F; 515 if (status & MLX5_RXP_RESP_STATUS_MAX_LATENCY) 516 op->rsp_flags |= RTE_REGEX_OPS_RSP_MAX_SCAN_TIMEOUT_F; 517 if (status & MLX5_RXP_RESP_STATUS_MAX_MATCH) 518 op->rsp_flags |= RTE_REGEX_OPS_RSP_MAX_MATCH_F; 519 if (status & MLX5_RXP_RESP_STATUS_MAX_PREFIX) 520 op->rsp_flags |= RTE_REGEX_OPS_RSP_MAX_PREFIX_F; 521 if (status & MLX5_RXP_RESP_STATUS_MAX_PRI_THREADS) 522 op->rsp_flags |= RTE_REGEX_OPS_RSP_RESOURCE_LIMIT_REACHED_F; 523 if (status & MLX5_RXP_RESP_STATUS_MAX_SEC_THREADS) 524 op->rsp_flags |= RTE_REGEX_OPS_RSP_RESOURCE_LIMIT_REACHED_F; 525 } 526 527 static inline volatile struct mlx5_cqe * 528 poll_one(struct mlx5_regex_cq *cq) 529 { 530 volatile struct mlx5_cqe *cqe; 531 size_t next_cqe_offset; 532 533 next_cqe_offset = (cq->ci & (cq_size_get(cq) - 1)); 534 cqe = (volatile struct mlx5_cqe *)(cq->cq_obj.cqes + next_cqe_offset); 535 rte_io_wmb(); 536 537 int ret = check_cqe(cqe, cq_size_get(cq), cq->ci); 538 539 if (unlikely(ret == MLX5_CQE_STATUS_ERR)) { 540 DRV_LOG(ERR, "Completion with error on qp 0x%x", 0); 541 return NULL; 542 } 543 544 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) 545 return NULL; 546 547 return cqe; 548 } 549 550 551 /** 552 * DPDK callback for dequeue. 553 * 554 * @param dev 555 * Pointer to the regex dev structure. 556 * @param qp_id 557 * The queue to enqueue the traffic to. 558 * @param ops 559 * List of regex ops to dequeue. 560 * @param nb_ops 561 * Number of ops in ops parameter. 562 * 563 * @return 564 * Number of packets successfully dequeued (<= pkts_n). 565 */ 566 uint16_t 567 mlx5_regexdev_dequeue(struct rte_regexdev *dev, uint16_t qp_id, 568 struct rte_regex_ops **ops, uint16_t nb_ops) 569 { 570 struct mlx5_regex_priv *priv = dev->data->dev_private; 571 struct mlx5_regex_qp *queue = &priv->qps[qp_id]; 572 struct mlx5_regex_cq *cq = &queue->cq; 573 volatile struct mlx5_cqe *cqe; 574 size_t i = 0; 575 576 while ((cqe = poll_one(cq))) { 577 uint16_t wq_counter 578 = (rte_be_to_cpu_16(cqe->wqe_counter) + 1) & 579 MLX5_REGEX_MAX_WQE_INDEX; 580 size_t hw_qpid = cqe->user_index_bytes[2]; 581 struct mlx5_regex_hw_qp *qp_obj = &queue->qps[hw_qpid]; 582 583 /* UMR mode WQE counter move as WQE set(4 WQEBBS).*/ 584 if (priv->has_umr) 585 wq_counter >>= 2; 586 while (qp_obj->ci != wq_counter) { 587 if (unlikely(i == nb_ops)) { 588 /* Return without updating cq->ci */ 589 goto out; 590 } 591 uint32_t job_id = job_id_get(hw_qpid, 592 qp_size_get(qp_obj), qp_obj->ci); 593 extract_result(ops[i], &queue->jobs[job_id]); 594 qp_obj->ci = (qp_obj->ci + 1) & (priv->has_umr ? 595 (MLX5_REGEX_MAX_WQE_INDEX >> 2) : 596 MLX5_REGEX_MAX_WQE_INDEX); 597 i++; 598 } 599 cq->ci = (cq->ci + 1) & 0xffffff; 600 rte_wmb(); 601 cq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->ci); 602 queue->free_qps |= (1 << hw_qpid); 603 } 604 605 out: 606 queue->ci += i; 607 return i; 608 } 609 610 static void 611 setup_qps(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *queue) 612 { 613 size_t hw_qpid, entry; 614 uint32_t job_id; 615 for (hw_qpid = 0; hw_qpid < queue->nb_obj; hw_qpid++) { 616 struct mlx5_regex_hw_qp *qp_obj = &queue->qps[hw_qpid]; 617 uint8_t *wqe = (uint8_t *)(uintptr_t)qp_obj->qp_obj.wqes; 618 for (entry = 0 ; entry < qp_size_get(qp_obj); entry++) { 619 job_id = hw_qpid * qp_size_get(qp_obj) + entry; 620 struct mlx5_regex_job *job = &queue->jobs[job_id]; 621 622 /* Fill UMR WQE with NOP in advanced. */ 623 if (priv->has_umr) { 624 set_wqe_ctrl_seg 625 ((struct mlx5_wqe_ctrl_seg *)wqe, 626 entry * 2, MLX5_OPCODE_NOP, 0, 627 qp_obj->qp_obj.qp->id, 0, 12, 0, 0); 628 wqe += MLX5_REGEX_UMR_WQE_SIZE; 629 } 630 set_metadata_seg((struct mlx5_wqe_metadata_seg *) 631 (wqe + MLX5_REGEX_WQE_METADATA_OFFSET), 632 0, queue->metadata->lkey, 633 (uintptr_t)job->metadata); 634 set_data_seg((struct mlx5_wqe_data_seg *) 635 (wqe + MLX5_REGEX_WQE_SCATTER_OFFSET), 636 MLX5_REGEX_MAX_OUTPUT, 637 queue->outputs->lkey, 638 (uintptr_t)job->output); 639 wqe += 64; 640 } 641 queue->free_qps |= 1 << hw_qpid; 642 } 643 } 644 645 static int 646 setup_buffers(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp) 647 { 648 struct ibv_pd *pd = priv->cdev->pd; 649 uint32_t i; 650 int err; 651 652 void *ptr = rte_calloc(__func__, qp->nb_desc, 653 MLX5_REGEX_METADATA_SIZE, 654 MLX5_REGEX_METADATA_SIZE); 655 if (!ptr) 656 return -ENOMEM; 657 658 qp->metadata = mlx5_glue->reg_mr(pd, ptr, 659 MLX5_REGEX_METADATA_SIZE * qp->nb_desc, 660 IBV_ACCESS_LOCAL_WRITE); 661 if (!qp->metadata) { 662 DRV_LOG(ERR, "Failed to register metadata"); 663 rte_free(ptr); 664 return -EINVAL; 665 } 666 667 ptr = rte_calloc(__func__, qp->nb_desc, 668 MLX5_REGEX_MAX_OUTPUT, 669 MLX5_REGEX_MAX_OUTPUT); 670 if (!ptr) { 671 err = -ENOMEM; 672 goto err_output; 673 } 674 qp->outputs = mlx5_glue->reg_mr(pd, ptr, 675 MLX5_REGEX_MAX_OUTPUT * qp->nb_desc, 676 IBV_ACCESS_LOCAL_WRITE); 677 if (!qp->outputs) { 678 rte_free(ptr); 679 DRV_LOG(ERR, "Failed to register output"); 680 err = -EINVAL; 681 goto err_output; 682 } 683 684 if (priv->has_umr) { 685 ptr = rte_calloc(__func__, qp->nb_desc, MLX5_REGEX_KLMS_SIZE, 686 MLX5_REGEX_KLMS_SIZE); 687 if (!ptr) { 688 err = -ENOMEM; 689 goto err_imkey; 690 } 691 qp->imkey_addr = mlx5_glue->reg_mr(pd, ptr, 692 MLX5_REGEX_KLMS_SIZE * qp->nb_desc, 693 IBV_ACCESS_LOCAL_WRITE); 694 if (!qp->imkey_addr) { 695 rte_free(ptr); 696 DRV_LOG(ERR, "Failed to register output"); 697 err = -EINVAL; 698 goto err_imkey; 699 } 700 } 701 702 /* distribute buffers to jobs */ 703 for (i = 0; i < qp->nb_desc; i++) { 704 qp->jobs[i].output = 705 (uint8_t *)qp->outputs->addr + 706 (i % qp->nb_desc) * MLX5_REGEX_MAX_OUTPUT; 707 qp->jobs[i].metadata = 708 (uint8_t *)qp->metadata->addr + 709 (i % qp->nb_desc) * MLX5_REGEX_METADATA_SIZE; 710 if (qp->imkey_addr) 711 qp->jobs[i].imkey_array = (struct mlx5_klm *) 712 qp->imkey_addr->addr + 713 (i % qp->nb_desc) * MLX5_REGEX_MAX_KLM_NUM; 714 } 715 716 return 0; 717 718 err_imkey: 719 ptr = qp->outputs->addr; 720 rte_free(ptr); 721 mlx5_glue->dereg_mr(qp->outputs); 722 err_output: 723 ptr = qp->metadata->addr; 724 rte_free(ptr); 725 mlx5_glue->dereg_mr(qp->metadata); 726 return err; 727 } 728 729 int 730 mlx5_regexdev_setup_fastpath(struct mlx5_regex_priv *priv, uint32_t qp_id) 731 { 732 struct mlx5_regex_qp *qp = &priv->qps[qp_id]; 733 struct mlx5_klm klm = { 0 }; 734 struct mlx5_devx_mkey_attr attr = { 735 .klm_array = &klm, 736 .klm_num = 1, 737 .umr_en = 1, 738 }; 739 uint32_t i; 740 int err = 0; 741 742 qp->jobs = rte_calloc(__func__, qp->nb_desc, sizeof(*qp->jobs), 64); 743 if (!qp->jobs) 744 return -ENOMEM; 745 err = setup_buffers(priv, qp); 746 if (err) { 747 rte_free(qp->jobs); 748 qp->jobs = NULL; 749 return err; 750 } 751 752 setup_qps(priv, qp); 753 754 if (priv->has_umr) { 755 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 756 attr.pd = priv->cdev->pdn; 757 #endif 758 for (i = 0; i < qp->nb_desc; i++) { 759 attr.klm_num = MLX5_REGEX_MAX_KLM_NUM; 760 attr.klm_array = qp->jobs[i].imkey_array; 761 qp->jobs[i].imkey = mlx5_devx_cmd_mkey_create 762 (priv->cdev->ctx, &attr); 763 if (!qp->jobs[i].imkey) { 764 err = -rte_errno; 765 DRV_LOG(ERR, "Failed to allocate imkey."); 766 mlx5_regexdev_teardown_fastpath(priv, qp_id); 767 } 768 } 769 } 770 return err; 771 } 772 773 static void 774 free_buffers(struct mlx5_regex_qp *qp) 775 { 776 if (qp->imkey_addr) { 777 mlx5_glue->dereg_mr(qp->imkey_addr); 778 rte_free(qp->imkey_addr->addr); 779 } 780 if (qp->metadata) { 781 mlx5_glue->dereg_mr(qp->metadata); 782 rte_free(qp->metadata->addr); 783 } 784 if (qp->outputs) { 785 mlx5_glue->dereg_mr(qp->outputs); 786 rte_free(qp->outputs->addr); 787 } 788 } 789 790 void 791 mlx5_regexdev_teardown_fastpath(struct mlx5_regex_priv *priv, uint32_t qp_id) 792 { 793 struct mlx5_regex_qp *qp = &priv->qps[qp_id]; 794 uint32_t i; 795 796 if (qp->jobs) { 797 for (i = 0; i < qp->nb_desc; i++) { 798 if (qp->jobs[i].imkey) 799 claim_zero(mlx5_devx_cmd_destroy 800 (qp->jobs[i].imkey)); 801 } 802 free_buffers(qp); 803 rte_free(qp->jobs); 804 qp->jobs = NULL; 805 } 806 } 807