1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2016 Cavium, Inc 3 */ 4 5 #include <assert.h> 6 #include <stdio.h> 7 #include <stdbool.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <unistd.h> 12 #include <stdarg.h> 13 #include <inttypes.h> 14 #include <netinet/in.h> 15 #include <sys/queue.h> 16 17 #include <rte_alarm.h> 18 #include <rte_branch_prediction.h> 19 #include <rte_byteorder.h> 20 #include <rte_common.h> 21 #include <rte_cycles.h> 22 #include <rte_debug.h> 23 #include <rte_dev.h> 24 #include <rte_eal.h> 25 #include <rte_ether.h> 26 #include <ethdev_driver.h> 27 #include <ethdev_pci.h> 28 #include <rte_interrupts.h> 29 #include <rte_log.h> 30 #include <rte_memory.h> 31 #include <rte_memzone.h> 32 #include <rte_malloc.h> 33 #include <rte_random.h> 34 #include <rte_pci.h> 35 #include <rte_bus_pci.h> 36 #include <rte_tailq.h> 37 #include <rte_devargs.h> 38 #include <rte_kvargs.h> 39 40 #include "base/nicvf_plat.h" 41 42 #include "nicvf_ethdev.h" 43 #include "nicvf_rxtx.h" 44 #include "nicvf_svf.h" 45 #include "nicvf_logs.h" 46 47 static int nicvf_dev_stop(struct rte_eth_dev *dev); 48 static void nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup); 49 static void nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, 50 bool cleanup); 51 static int nicvf_vlan_offload_config(struct rte_eth_dev *dev, int mask); 52 static int nicvf_vlan_offload_set(struct rte_eth_dev *dev, int mask); 53 54 RTE_LOG_REGISTER_SUFFIX(nicvf_logtype_mbox, mbox, NOTICE); 55 RTE_LOG_REGISTER_SUFFIX(nicvf_logtype_init, init, NOTICE); 56 RTE_LOG_REGISTER_SUFFIX(nicvf_logtype_driver, driver, NOTICE); 57 58 #define NICVF_QLM_MODE_SGMII 7 59 #define NICVF_QLM_MODE_XFI 12 60 61 enum nicvf_link_speed { 62 NICVF_LINK_SPEED_SGMII, 63 NICVF_LINK_SPEED_XAUI, 64 NICVF_LINK_SPEED_RXAUI, 65 NICVF_LINK_SPEED_10G_R, 66 NICVF_LINK_SPEED_40G_R, 67 NICVF_LINK_SPEED_RESERVE1, 68 NICVF_LINK_SPEED_QSGMII, 69 NICVF_LINK_SPEED_RESERVE2, 70 NICVF_LINK_SPEED_UNKNOWN = 255 71 }; 72 73 static inline uint32_t 74 nicvf_parse_link_speeds(uint32_t link_speeds) 75 { 76 uint32_t link_speed = NICVF_LINK_SPEED_UNKNOWN; 77 78 if (link_speeds & RTE_ETH_LINK_SPEED_40G) 79 link_speed = NICVF_LINK_SPEED_40G_R; 80 81 if (link_speeds & RTE_ETH_LINK_SPEED_10G) { 82 link_speed = NICVF_LINK_SPEED_XAUI; 83 link_speed |= NICVF_LINK_SPEED_RXAUI; 84 link_speed |= NICVF_LINK_SPEED_10G_R; 85 } 86 87 if (link_speeds & RTE_ETH_LINK_SPEED_5G) 88 link_speed = NICVF_LINK_SPEED_QSGMII; 89 90 if (link_speeds & RTE_ETH_LINK_SPEED_1G) 91 link_speed = NICVF_LINK_SPEED_SGMII; 92 93 return link_speed; 94 } 95 96 static inline uint8_t 97 nicvf_parse_eth_link_duplex(uint32_t link_speeds) 98 { 99 if ((link_speeds & RTE_ETH_LINK_SPEED_10M_HD) || 100 (link_speeds & RTE_ETH_LINK_SPEED_100M_HD)) 101 return RTE_ETH_LINK_HALF_DUPLEX; 102 else 103 return RTE_ETH_LINK_FULL_DUPLEX; 104 } 105 106 static int 107 nicvf_apply_link_speed(struct rte_eth_dev *dev) 108 { 109 struct nicvf *nic = nicvf_pmd_priv(dev); 110 struct rte_eth_conf *conf = &dev->data->dev_conf; 111 struct change_link_mode cfg; 112 if (conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) 113 /* TODO: Handle this case */ 114 return 0; 115 116 cfg.speed = nicvf_parse_link_speeds(conf->link_speeds); 117 cfg.autoneg = (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) ? 1 : 0; 118 cfg.duplex = nicvf_parse_eth_link_duplex(conf->link_speeds); 119 cfg.qlm_mode = ((conf->link_speeds & RTE_ETH_LINK_SPEED_1G) ? 120 NICVF_QLM_MODE_SGMII : 121 (conf->link_speeds & RTE_ETH_LINK_SPEED_10G) ? 122 NICVF_QLM_MODE_XFI : 0); 123 124 if (cfg.speed != NICVF_LINK_SPEED_UNKNOWN && 125 (cfg.speed != nic->speed || cfg.duplex != nic->duplex)) { 126 nic->speed = cfg.speed; 127 nic->duplex = cfg.duplex; 128 return nicvf_mbox_change_mode(nic, &cfg); 129 } else { 130 return 0; 131 } 132 } 133 134 static void 135 nicvf_link_status_update(struct nicvf *nic, 136 struct rte_eth_link *link) 137 { 138 memset(link, 0, sizeof(*link)); 139 140 link->link_status = nic->link_up ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN; 141 142 if (nic->duplex == NICVF_HALF_DUPLEX) 143 link->link_duplex = RTE_ETH_LINK_HALF_DUPLEX; 144 else if (nic->duplex == NICVF_FULL_DUPLEX) 145 link->link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 146 link->link_speed = nic->speed; 147 link->link_autoneg = RTE_ETH_LINK_AUTONEG; 148 } 149 150 /*Poll for link status change by sending NIC_MBOX_MSG_BGX_LINK_CHANGE msg 151 * periodically to PF. 152 */ 153 static void 154 nicvf_interrupt(void *arg) 155 { 156 struct rte_eth_dev *dev = arg; 157 struct nicvf *nic = nicvf_pmd_priv(dev); 158 struct rte_eth_link link; 159 160 rte_eth_linkstatus_get(dev, &link); 161 162 nicvf_mbox_link_change(nic); 163 if (nic->link_up != link.link_status) { 164 if (dev->data->dev_conf.intr_conf.lsc) { 165 nicvf_link_status_update(nic, &link); 166 rte_eth_linkstatus_set(dev, &link); 167 168 rte_eth_dev_callback_process(dev, 169 RTE_ETH_EVENT_INTR_LSC, 170 NULL); 171 } 172 } 173 174 rte_eal_alarm_set(NICVF_INTR_LINK_POLL_INTERVAL_MS * 1000, 175 nicvf_interrupt, dev); 176 } 177 178 static void 179 nicvf_vf_interrupt(void *arg) 180 { 181 struct nicvf *nic = arg; 182 183 nicvf_reg_poll_interrupts(nic); 184 185 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, 186 nicvf_vf_interrupt, nic); 187 } 188 189 static int 190 nicvf_periodic_alarm_start(void (fn)(void *), void *arg) 191 { 192 return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, fn, arg); 193 } 194 195 static int 196 nicvf_periodic_alarm_stop(void (fn)(void *), void *arg) 197 { 198 return rte_eal_alarm_cancel(fn, arg); 199 } 200 201 /* 202 * Return 0 means link status changed, -1 means not changed 203 */ 204 static int 205 nicvf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 206 { 207 #define CHECK_INTERVAL 100 /* 100ms */ 208 #define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */ 209 struct rte_eth_link link; 210 struct nicvf *nic = nicvf_pmd_priv(dev); 211 int i; 212 213 PMD_INIT_FUNC_TRACE(); 214 215 if (wait_to_complete) { 216 /* rte_eth_link_get() might need to wait up to 9 seconds */ 217 for (i = 0; i < MAX_CHECK_TIME; i++) { 218 nicvf_link_status_update(nic, &link); 219 if (link.link_status == RTE_ETH_LINK_UP) 220 break; 221 rte_delay_ms(CHECK_INTERVAL); 222 } 223 } else { 224 nicvf_link_status_update(nic, &link); 225 } 226 227 return rte_eth_linkstatus_set(dev, &link); 228 } 229 230 static int 231 nicvf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 232 { 233 struct nicvf *nic = nicvf_pmd_priv(dev); 234 uint32_t buffsz, frame_size = mtu + NIC_HW_L2_OVERHEAD; 235 size_t i; 236 237 PMD_INIT_FUNC_TRACE(); 238 239 buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 240 241 /* 242 * Refuse mtu that requires the support of scattered packets 243 * when this feature has not been enabled before. 244 */ 245 if (dev->data->dev_started && !dev->data->scattered_rx && 246 (frame_size + 2 * VLAN_TAG_SIZE > buffsz)) 247 return -EINVAL; 248 249 /* check <seg size> * <max_seg> >= max_frame */ 250 if (dev->data->scattered_rx && 251 (frame_size + 2 * VLAN_TAG_SIZE > buffsz * NIC_HW_MAX_SEGS)) 252 return -EINVAL; 253 254 if (nicvf_mbox_update_hw_max_frs(nic, mtu)) 255 return -EINVAL; 256 257 nic->mtu = mtu; 258 259 for (i = 0; i < nic->sqs_count; i++) 260 nic->snicvf[i]->mtu = mtu; 261 262 return 0; 263 } 264 265 static int 266 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs) 267 { 268 uint64_t *data = regs->data; 269 struct nicvf *nic = nicvf_pmd_priv(dev); 270 271 if (data == NULL) { 272 regs->length = nicvf_reg_get_count(); 273 regs->width = THUNDERX_REG_BYTES; 274 return 0; 275 } 276 277 /* Support only full register dump */ 278 if ((regs->length == 0) || 279 (regs->length == (uint32_t)nicvf_reg_get_count())) { 280 regs->version = nic->vendor_id << 16 | nic->device_id; 281 nicvf_reg_dump(nic, data); 282 return 0; 283 } 284 return -ENOTSUP; 285 } 286 287 static int 288 nicvf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 289 { 290 uint16_t qidx; 291 struct nicvf_hw_rx_qstats rx_qstats; 292 struct nicvf_hw_tx_qstats tx_qstats; 293 struct nicvf_hw_stats port_stats; 294 struct nicvf *nic = nicvf_pmd_priv(dev); 295 uint16_t rx_start, rx_end; 296 uint16_t tx_start, tx_end; 297 size_t i; 298 299 /* RX queue indices for the first VF */ 300 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 301 302 /* Reading per RX ring stats */ 303 for (qidx = rx_start; qidx <= rx_end; qidx++) { 304 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 305 break; 306 307 nicvf_hw_get_rx_qstats(nic, &rx_qstats, qidx); 308 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes; 309 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets; 310 } 311 312 /* TX queue indices for the first VF */ 313 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 314 315 /* Reading per TX ring stats */ 316 for (qidx = tx_start; qidx <= tx_end; qidx++) { 317 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 318 break; 319 320 nicvf_hw_get_tx_qstats(nic, &tx_qstats, qidx); 321 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes; 322 stats->q_opackets[qidx] = tx_qstats.q_tx_packets; 323 } 324 325 for (i = 0; i < nic->sqs_count; i++) { 326 struct nicvf *snic = nic->snicvf[i]; 327 328 if (snic == NULL) 329 break; 330 331 /* RX queue indices for a secondary VF */ 332 nicvf_rx_range(dev, snic, &rx_start, &rx_end); 333 334 /* Reading per RX ring stats */ 335 for (qidx = rx_start; qidx <= rx_end; qidx++) { 336 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 337 break; 338 339 nicvf_hw_get_rx_qstats(snic, &rx_qstats, 340 qidx % MAX_RCV_QUEUES_PER_QS); 341 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes; 342 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets; 343 } 344 345 /* TX queue indices for a secondary VF */ 346 nicvf_tx_range(dev, snic, &tx_start, &tx_end); 347 /* Reading per TX ring stats */ 348 for (qidx = tx_start; qidx <= tx_end; qidx++) { 349 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 350 break; 351 352 nicvf_hw_get_tx_qstats(snic, &tx_qstats, 353 qidx % MAX_SND_QUEUES_PER_QS); 354 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes; 355 stats->q_opackets[qidx] = tx_qstats.q_tx_packets; 356 } 357 } 358 359 nicvf_hw_get_stats(nic, &port_stats); 360 stats->ibytes = port_stats.rx_bytes; 361 stats->ipackets = port_stats.rx_ucast_frames; 362 stats->ipackets += port_stats.rx_bcast_frames; 363 stats->ipackets += port_stats.rx_mcast_frames; 364 stats->ierrors = port_stats.rx_l2_errors; 365 stats->imissed = port_stats.rx_drop_red; 366 stats->imissed += port_stats.rx_drop_overrun; 367 stats->imissed += port_stats.rx_drop_bcast; 368 stats->imissed += port_stats.rx_drop_mcast; 369 stats->imissed += port_stats.rx_drop_l3_bcast; 370 stats->imissed += port_stats.rx_drop_l3_mcast; 371 372 stats->obytes = port_stats.tx_bytes_ok; 373 stats->opackets = port_stats.tx_ucast_frames_ok; 374 stats->opackets += port_stats.tx_bcast_frames_ok; 375 stats->opackets += port_stats.tx_mcast_frames_ok; 376 stats->oerrors = port_stats.tx_drops; 377 378 return 0; 379 } 380 381 static const uint32_t * 382 nicvf_dev_supported_ptypes_get(struct rte_eth_dev *dev) 383 { 384 size_t copied; 385 static uint32_t ptypes[32]; 386 struct nicvf *nic = nicvf_pmd_priv(dev); 387 static const uint32_t ptypes_common[] = { 388 RTE_PTYPE_L3_IPV4, 389 RTE_PTYPE_L3_IPV4_EXT, 390 RTE_PTYPE_L3_IPV6, 391 RTE_PTYPE_L3_IPV6_EXT, 392 RTE_PTYPE_L4_TCP, 393 RTE_PTYPE_L4_UDP, 394 RTE_PTYPE_L4_FRAG, 395 }; 396 static const uint32_t ptypes_tunnel[] = { 397 RTE_PTYPE_TUNNEL_GRE, 398 RTE_PTYPE_TUNNEL_GENEVE, 399 RTE_PTYPE_TUNNEL_VXLAN, 400 RTE_PTYPE_TUNNEL_NVGRE, 401 }; 402 static const uint32_t ptypes_end = RTE_PTYPE_UNKNOWN; 403 404 copied = sizeof(ptypes_common); 405 memcpy(ptypes, ptypes_common, copied); 406 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) { 407 memcpy((char *)ptypes + copied, ptypes_tunnel, 408 sizeof(ptypes_tunnel)); 409 copied += sizeof(ptypes_tunnel); 410 } 411 412 memcpy((char *)ptypes + copied, &ptypes_end, sizeof(ptypes_end)); 413 414 /* All Ptypes are supported in all Rx functions. */ 415 return ptypes; 416 } 417 418 static int 419 nicvf_dev_stats_reset(struct rte_eth_dev *dev) 420 { 421 int i; 422 uint16_t rxqs = 0, txqs = 0; 423 struct nicvf *nic = nicvf_pmd_priv(dev); 424 uint16_t rx_start, rx_end; 425 uint16_t tx_start, tx_end; 426 int ret; 427 428 /* Reset all primary nic counters */ 429 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 430 for (i = rx_start; i <= rx_end; i++) 431 rxqs |= (0x3 << (i * 2)); 432 433 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 434 for (i = tx_start; i <= tx_end; i++) 435 txqs |= (0x3 << (i * 2)); 436 437 ret = nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, rxqs, txqs); 438 if (ret != 0) 439 return ret; 440 441 /* Reset secondary nic queue counters */ 442 for (i = 0; i < nic->sqs_count; i++) { 443 struct nicvf *snic = nic->snicvf[i]; 444 if (snic == NULL) 445 break; 446 447 nicvf_rx_range(dev, snic, &rx_start, &rx_end); 448 for (i = rx_start; i <= rx_end; i++) 449 rxqs |= (0x3 << ((i % MAX_CMP_QUEUES_PER_QS) * 2)); 450 451 nicvf_tx_range(dev, snic, &tx_start, &tx_end); 452 for (i = tx_start; i <= tx_end; i++) 453 txqs |= (0x3 << ((i % MAX_SND_QUEUES_PER_QS) * 2)); 454 455 ret = nicvf_mbox_reset_stat_counters(snic, 0, 0, rxqs, txqs); 456 if (ret != 0) 457 return ret; 458 } 459 460 return 0; 461 } 462 463 /* Promiscuous mode enabled by default in LMAC to VF 1:1 map configuration */ 464 static int 465 nicvf_dev_promisc_enable(struct rte_eth_dev *dev __rte_unused) 466 { 467 return 0; 468 } 469 470 static inline uint64_t 471 nicvf_rss_ethdev_to_nic(struct nicvf *nic, uint64_t ethdev_rss) 472 { 473 uint64_t nic_rss = 0; 474 475 if (ethdev_rss & RTE_ETH_RSS_IPV4) 476 nic_rss |= RSS_IP_ENA; 477 478 if (ethdev_rss & RTE_ETH_RSS_IPV6) 479 nic_rss |= RSS_IP_ENA; 480 481 if (ethdev_rss & RTE_ETH_RSS_NONFRAG_IPV4_UDP) 482 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA); 483 484 if (ethdev_rss & RTE_ETH_RSS_NONFRAG_IPV4_TCP) 485 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA); 486 487 if (ethdev_rss & RTE_ETH_RSS_NONFRAG_IPV6_UDP) 488 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA); 489 490 if (ethdev_rss & RTE_ETH_RSS_NONFRAG_IPV6_TCP) 491 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA); 492 493 if (ethdev_rss & RTE_ETH_RSS_PORT) 494 nic_rss |= RSS_L2_EXTENDED_HASH_ENA; 495 496 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) { 497 if (ethdev_rss & RTE_ETH_RSS_VXLAN) 498 nic_rss |= RSS_TUN_VXLAN_ENA; 499 500 if (ethdev_rss & RTE_ETH_RSS_GENEVE) 501 nic_rss |= RSS_TUN_GENEVE_ENA; 502 503 if (ethdev_rss & RTE_ETH_RSS_NVGRE) 504 nic_rss |= RSS_TUN_NVGRE_ENA; 505 } 506 507 return nic_rss; 508 } 509 510 static inline uint64_t 511 nicvf_rss_nic_to_ethdev(struct nicvf *nic, uint64_t nic_rss) 512 { 513 uint64_t ethdev_rss = 0; 514 515 if (nic_rss & RSS_IP_ENA) 516 ethdev_rss |= (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_IPV6); 517 518 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_TCP_ENA)) 519 ethdev_rss |= (RTE_ETH_RSS_NONFRAG_IPV4_TCP | 520 RTE_ETH_RSS_NONFRAG_IPV6_TCP); 521 522 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_UDP_ENA)) 523 ethdev_rss |= (RTE_ETH_RSS_NONFRAG_IPV4_UDP | 524 RTE_ETH_RSS_NONFRAG_IPV6_UDP); 525 526 if (nic_rss & RSS_L2_EXTENDED_HASH_ENA) 527 ethdev_rss |= RTE_ETH_RSS_PORT; 528 529 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) { 530 if (nic_rss & RSS_TUN_VXLAN_ENA) 531 ethdev_rss |= RTE_ETH_RSS_VXLAN; 532 533 if (nic_rss & RSS_TUN_GENEVE_ENA) 534 ethdev_rss |= RTE_ETH_RSS_GENEVE; 535 536 if (nic_rss & RSS_TUN_NVGRE_ENA) 537 ethdev_rss |= RTE_ETH_RSS_NVGRE; 538 } 539 return ethdev_rss; 540 } 541 542 static int 543 nicvf_dev_reta_query(struct rte_eth_dev *dev, 544 struct rte_eth_rss_reta_entry64 *reta_conf, 545 uint16_t reta_size) 546 { 547 struct nicvf *nic = nicvf_pmd_priv(dev); 548 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; 549 int ret, i, j; 550 551 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) { 552 PMD_DRV_LOG(ERR, 553 "The size of hash lookup table configured " 554 "(%u) doesn't match the number hardware can supported " 555 "(%u)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE); 556 return -EINVAL; 557 } 558 559 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE); 560 if (ret) 561 return ret; 562 563 /* Copy RETA table */ 564 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_ETH_RETA_GROUP_SIZE); i++) { 565 for (j = 0; j < RTE_ETH_RETA_GROUP_SIZE; j++) 566 if ((reta_conf[i].mask >> j) & 0x01) 567 reta_conf[i].reta[j] = tbl[j]; 568 } 569 570 return 0; 571 } 572 573 static int 574 nicvf_dev_reta_update(struct rte_eth_dev *dev, 575 struct rte_eth_rss_reta_entry64 *reta_conf, 576 uint16_t reta_size) 577 { 578 struct nicvf *nic = nicvf_pmd_priv(dev); 579 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; 580 int ret, i, j; 581 582 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) { 583 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 584 "(%u) doesn't match the number hardware can supported " 585 "(%u)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE); 586 return -EINVAL; 587 } 588 589 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE); 590 if (ret) 591 return ret; 592 593 /* Copy RETA table */ 594 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_ETH_RETA_GROUP_SIZE); i++) { 595 for (j = 0; j < RTE_ETH_RETA_GROUP_SIZE; j++) 596 if ((reta_conf[i].mask >> j) & 0x01) 597 tbl[j] = reta_conf[i].reta[j]; 598 } 599 600 return nicvf_rss_reta_update(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE); 601 } 602 603 static int 604 nicvf_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 605 struct rte_eth_rss_conf *rss_conf) 606 { 607 struct nicvf *nic = nicvf_pmd_priv(dev); 608 609 if (rss_conf->rss_key) 610 nicvf_rss_get_key(nic, rss_conf->rss_key); 611 612 rss_conf->rss_key_len = RSS_HASH_KEY_BYTE_SIZE; 613 rss_conf->rss_hf = nicvf_rss_nic_to_ethdev(nic, nicvf_rss_get_cfg(nic)); 614 return 0; 615 } 616 617 static int 618 nicvf_dev_rss_hash_update(struct rte_eth_dev *dev, 619 struct rte_eth_rss_conf *rss_conf) 620 { 621 struct nicvf *nic = nicvf_pmd_priv(dev); 622 uint64_t nic_rss; 623 624 if (rss_conf->rss_key && 625 rss_conf->rss_key_len != RSS_HASH_KEY_BYTE_SIZE) { 626 PMD_DRV_LOG(ERR, "Hash key size mismatch %u", 627 rss_conf->rss_key_len); 628 return -EINVAL; 629 } 630 631 if (rss_conf->rss_key) 632 nicvf_rss_set_key(nic, rss_conf->rss_key); 633 634 nic_rss = nicvf_rss_ethdev_to_nic(nic, rss_conf->rss_hf); 635 nicvf_rss_set_cfg(nic, nic_rss); 636 return 0; 637 } 638 639 static int 640 nicvf_qset_cq_alloc(struct rte_eth_dev *dev, struct nicvf *nic, 641 struct nicvf_rxq *rxq, uint16_t qidx, uint32_t desc_cnt) 642 { 643 const struct rte_memzone *rz; 644 uint32_t ring_size = CMP_QUEUE_SZ_MAX * sizeof(union cq_entry_t); 645 646 rz = rte_eth_dma_zone_reserve(dev, "cq_ring", 647 nicvf_netdev_qidx(nic, qidx), ring_size, 648 NICVF_CQ_BASE_ALIGN_BYTES, nic->node); 649 if (rz == NULL) { 650 PMD_INIT_LOG(ERR, "Failed to allocate mem for cq hw ring"); 651 return -ENOMEM; 652 } 653 654 memset(rz->addr, 0, ring_size); 655 656 rxq->phys = rz->iova; 657 rxq->desc = rz->addr; 658 rxq->qlen_mask = desc_cnt - 1; 659 660 return 0; 661 } 662 663 static int 664 nicvf_qset_sq_alloc(struct rte_eth_dev *dev, struct nicvf *nic, 665 struct nicvf_txq *sq, uint16_t qidx, uint32_t desc_cnt) 666 { 667 const struct rte_memzone *rz; 668 uint32_t ring_size = SND_QUEUE_SZ_MAX * sizeof(union sq_entry_t); 669 670 rz = rte_eth_dma_zone_reserve(dev, "sq", 671 nicvf_netdev_qidx(nic, qidx), ring_size, 672 NICVF_SQ_BASE_ALIGN_BYTES, nic->node); 673 if (rz == NULL) { 674 PMD_INIT_LOG(ERR, "Failed allocate mem for sq hw ring"); 675 return -ENOMEM; 676 } 677 678 memset(rz->addr, 0, ring_size); 679 680 sq->phys = rz->iova; 681 sq->desc = rz->addr; 682 sq->qlen_mask = desc_cnt - 1; 683 684 return 0; 685 } 686 687 static int 688 nicvf_qset_rbdr_alloc(struct rte_eth_dev *dev, struct nicvf *nic, 689 uint32_t desc_cnt, uint32_t buffsz) 690 { 691 struct nicvf_rbdr *rbdr; 692 const struct rte_memzone *rz; 693 uint32_t ring_size; 694 695 assert(nic->rbdr == NULL); 696 rbdr = rte_zmalloc_socket("rbdr", sizeof(struct nicvf_rbdr), 697 RTE_CACHE_LINE_SIZE, nic->node); 698 if (rbdr == NULL) { 699 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr"); 700 return -ENOMEM; 701 } 702 703 ring_size = sizeof(struct rbdr_entry_t) * RBDR_QUEUE_SZ_MAX; 704 rz = rte_eth_dma_zone_reserve(dev, "rbdr", 705 nicvf_netdev_qidx(nic, 0), ring_size, 706 NICVF_RBDR_BASE_ALIGN_BYTES, nic->node); 707 if (rz == NULL) { 708 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr desc ring"); 709 rte_free(rbdr); 710 return -ENOMEM; 711 } 712 713 memset(rz->addr, 0, ring_size); 714 715 rbdr->phys = rz->iova; 716 rbdr->tail = 0; 717 rbdr->next_tail = 0; 718 rbdr->desc = rz->addr; 719 rbdr->buffsz = buffsz; 720 rbdr->qlen_mask = desc_cnt - 1; 721 rbdr->rbdr_status = 722 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_STATUS0; 723 rbdr->rbdr_door = 724 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_DOOR; 725 726 nic->rbdr = rbdr; 727 return 0; 728 } 729 730 static void 731 nicvf_rbdr_release_mbuf(struct rte_eth_dev *dev, struct nicvf *nic, 732 nicvf_iova_addr_t phy) 733 { 734 uint16_t qidx; 735 void *obj; 736 struct nicvf_rxq *rxq; 737 uint16_t rx_start, rx_end; 738 739 /* Get queue ranges for this VF */ 740 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 741 742 for (qidx = rx_start; qidx <= rx_end; qidx++) { 743 rxq = dev->data->rx_queues[qidx]; 744 if (rxq->precharge_cnt) { 745 obj = (void *)nicvf_mbuff_phy2virt(phy, 746 rxq->mbuf_phys_off); 747 rte_mempool_put(rxq->pool, obj); 748 rxq->precharge_cnt--; 749 break; 750 } 751 } 752 } 753 754 static inline void 755 nicvf_rbdr_release_mbufs(struct rte_eth_dev *dev, struct nicvf *nic) 756 { 757 uint32_t qlen_mask, head; 758 struct rbdr_entry_t *entry; 759 struct nicvf_rbdr *rbdr = nic->rbdr; 760 761 qlen_mask = rbdr->qlen_mask; 762 head = rbdr->head; 763 while (head != rbdr->tail) { 764 entry = rbdr->desc + head; 765 nicvf_rbdr_release_mbuf(dev, nic, entry->full_addr); 766 head++; 767 head = head & qlen_mask; 768 } 769 } 770 771 static inline void 772 nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq) 773 { 774 uint32_t head; 775 776 head = txq->head; 777 while (head != txq->tail) { 778 if (txq->txbuffs[head]) { 779 rte_pktmbuf_free_seg(txq->txbuffs[head]); 780 txq->txbuffs[head] = NULL; 781 } 782 head++; 783 head = head & txq->qlen_mask; 784 } 785 } 786 787 static void 788 nicvf_tx_queue_reset(struct nicvf_txq *txq) 789 { 790 uint32_t txq_desc_cnt = txq->qlen_mask + 1; 791 792 memset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt); 793 memset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt); 794 txq->tail = 0; 795 txq->head = 0; 796 txq->xmit_bufs = 0; 797 } 798 799 static inline int 800 nicvf_vf_start_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 801 uint16_t qidx) 802 { 803 struct nicvf_txq *txq; 804 int ret; 805 806 assert(qidx < MAX_SND_QUEUES_PER_QS); 807 808 if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 809 RTE_ETH_QUEUE_STATE_STARTED) 810 return 0; 811 812 txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]; 813 txq->pool = NULL; 814 ret = nicvf_qset_sq_config(nic, qidx, txq); 815 if (ret) { 816 PMD_INIT_LOG(ERR, "Failed to configure sq VF%d %d %d", 817 nic->vf_id, qidx, ret); 818 goto config_sq_error; 819 } 820 821 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 822 RTE_ETH_QUEUE_STATE_STARTED; 823 return ret; 824 825 config_sq_error: 826 nicvf_qset_sq_reclaim(nic, qidx); 827 return ret; 828 } 829 830 static inline int 831 nicvf_vf_stop_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 832 uint16_t qidx) 833 { 834 struct nicvf_txq *txq; 835 int ret; 836 837 assert(qidx < MAX_SND_QUEUES_PER_QS); 838 839 if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 840 RTE_ETH_QUEUE_STATE_STOPPED) 841 return 0; 842 843 ret = nicvf_qset_sq_reclaim(nic, qidx); 844 if (ret) 845 PMD_INIT_LOG(ERR, "Failed to reclaim sq VF%d %d %d", 846 nic->vf_id, qidx, ret); 847 848 txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]; 849 nicvf_tx_queue_release_mbufs(txq); 850 nicvf_tx_queue_reset(txq); 851 852 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 853 RTE_ETH_QUEUE_STATE_STOPPED; 854 return ret; 855 } 856 857 static inline int 858 nicvf_configure_cpi(struct rte_eth_dev *dev) 859 { 860 struct nicvf *nic = nicvf_pmd_priv(dev); 861 uint16_t qidx, qcnt; 862 int ret; 863 864 /* Count started rx queues */ 865 for (qidx = qcnt = 0; qidx < dev->data->nb_rx_queues; qidx++) 866 if (dev->data->rx_queue_state[qidx] == 867 RTE_ETH_QUEUE_STATE_STARTED) 868 qcnt++; 869 870 nic->cpi_alg = CPI_ALG_NONE; 871 ret = nicvf_mbox_config_cpi(nic, qcnt); 872 if (ret) 873 PMD_INIT_LOG(ERR, "Failed to configure CPI %d", ret); 874 875 return ret; 876 } 877 878 static inline int 879 nicvf_configure_rss(struct rte_eth_dev *dev) 880 { 881 struct nicvf *nic = nicvf_pmd_priv(dev); 882 uint64_t rsshf; 883 int ret = -EINVAL; 884 885 rsshf = nicvf_rss_ethdev_to_nic(nic, 886 dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf); 887 PMD_DRV_LOG(INFO, "mode=%d rx_queues=%d loopback=%d rsshf=0x%" PRIx64, 888 dev->data->dev_conf.rxmode.mq_mode, 889 dev->data->nb_rx_queues, 890 dev->data->dev_conf.lpbk_mode, rsshf); 891 892 if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_NONE) 893 ret = nicvf_rss_term(nic); 894 else if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) 895 ret = nicvf_rss_config(nic, dev->data->nb_rx_queues, rsshf); 896 if (ret) 897 PMD_INIT_LOG(ERR, "Failed to configure RSS %d", ret); 898 899 return ret; 900 } 901 902 static int 903 nicvf_configure_rss_reta(struct rte_eth_dev *dev) 904 { 905 struct nicvf *nic = nicvf_pmd_priv(dev); 906 unsigned int idx, qmap_size; 907 uint8_t qmap[RTE_MAX_QUEUES_PER_PORT]; 908 uint8_t default_reta[NIC_MAX_RSS_IDR_TBL_SIZE]; 909 910 if (nic->cpi_alg != CPI_ALG_NONE) 911 return -EINVAL; 912 913 /* Prepare queue map */ 914 for (idx = 0, qmap_size = 0; idx < dev->data->nb_rx_queues; idx++) { 915 if (dev->data->rx_queue_state[idx] == 916 RTE_ETH_QUEUE_STATE_STARTED) 917 qmap[qmap_size++] = idx; 918 } 919 920 /* Update default RSS RETA */ 921 for (idx = 0; idx < NIC_MAX_RSS_IDR_TBL_SIZE; idx++) 922 default_reta[idx] = qmap[idx % qmap_size]; 923 924 return nicvf_rss_reta_update(nic, default_reta, 925 NIC_MAX_RSS_IDR_TBL_SIZE); 926 } 927 928 static void 929 nicvf_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid) 930 { 931 struct nicvf_txq *txq = dev->data->tx_queues[qid]; 932 933 PMD_INIT_FUNC_TRACE(); 934 935 if (txq) { 936 if (txq->txbuffs != NULL) { 937 nicvf_tx_queue_release_mbufs(txq); 938 rte_free(txq->txbuffs); 939 txq->txbuffs = NULL; 940 } 941 rte_free(txq); 942 dev->data->tx_queues[qid] = NULL; 943 } 944 } 945 946 static void 947 nicvf_set_tx_function(struct rte_eth_dev *dev) 948 { 949 struct nicvf_txq *txq = NULL; 950 size_t i; 951 bool multiseg = false; 952 953 for (i = 0; i < dev->data->nb_tx_queues; i++) { 954 txq = dev->data->tx_queues[i]; 955 if (txq->offloads & RTE_ETH_TX_OFFLOAD_MULTI_SEGS) { 956 multiseg = true; 957 break; 958 } 959 } 960 961 /* Use a simple Tx queue (no offloads, no multi segs) if possible */ 962 if (multiseg) { 963 PMD_DRV_LOG(DEBUG, "Using multi-segment tx callback"); 964 dev->tx_pkt_burst = nicvf_xmit_pkts_multiseg; 965 } else { 966 PMD_DRV_LOG(DEBUG, "Using single-segment tx callback"); 967 dev->tx_pkt_burst = nicvf_xmit_pkts; 968 } 969 970 if (!txq) 971 return; 972 973 if (txq->pool_free == nicvf_single_pool_free_xmited_buffers) 974 PMD_DRV_LOG(DEBUG, "Using single-mempool tx free method"); 975 else 976 PMD_DRV_LOG(DEBUG, "Using multi-mempool tx free method"); 977 } 978 979 static void 980 nicvf_set_rx_function(struct rte_eth_dev *dev) 981 { 982 struct nicvf *nic = nicvf_pmd_priv(dev); 983 984 const eth_rx_burst_t rx_burst_func[2][2][2] = { 985 /* [NORMAL/SCATTER] [CKSUM/NO_CKSUM] [VLAN_STRIP/NO_VLAN_STRIP] */ 986 [0][0][0] = nicvf_recv_pkts_no_offload, 987 [0][0][1] = nicvf_recv_pkts_vlan_strip, 988 [0][1][0] = nicvf_recv_pkts_cksum, 989 [0][1][1] = nicvf_recv_pkts_cksum_vlan_strip, 990 [1][0][0] = nicvf_recv_pkts_multiseg_no_offload, 991 [1][0][1] = nicvf_recv_pkts_multiseg_vlan_strip, 992 [1][1][0] = nicvf_recv_pkts_multiseg_cksum, 993 [1][1][1] = nicvf_recv_pkts_multiseg_cksum_vlan_strip, 994 }; 995 996 dev->rx_pkt_burst = 997 rx_burst_func[dev->data->scattered_rx] 998 [nic->offload_cksum][nic->vlan_strip]; 999 } 1000 1001 static int 1002 nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx, 1003 uint16_t nb_desc, unsigned int socket_id, 1004 const struct rte_eth_txconf *tx_conf) 1005 { 1006 uint16_t tx_free_thresh; 1007 bool is_single_pool; 1008 struct nicvf_txq *txq; 1009 struct nicvf *nic = nicvf_pmd_priv(dev); 1010 uint64_t offloads; 1011 1012 PMD_INIT_FUNC_TRACE(); 1013 1014 if (qidx >= MAX_SND_QUEUES_PER_QS) 1015 nic = nic->snicvf[qidx / MAX_SND_QUEUES_PER_QS - 1]; 1016 1017 qidx = qidx % MAX_SND_QUEUES_PER_QS; 1018 1019 /* Socket id check */ 1020 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node) 1021 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d", 1022 socket_id, nic->node); 1023 1024 /* Tx deferred start is not supported */ 1025 if (tx_conf->tx_deferred_start) { 1026 PMD_INIT_LOG(ERR, "Tx deferred start not supported"); 1027 return -EINVAL; 1028 } 1029 1030 /* Roundup nb_desc to available qsize and validate max number of desc */ 1031 nb_desc = nicvf_qsize_sq_roundup(nb_desc); 1032 if (nb_desc == 0) { 1033 PMD_INIT_LOG(ERR, "Value of nb_desc beyond available sq qsize"); 1034 return -EINVAL; 1035 } 1036 1037 /* Validate tx_free_thresh */ 1038 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ? 1039 tx_conf->tx_free_thresh : 1040 NICVF_DEFAULT_TX_FREE_THRESH); 1041 1042 if (tx_free_thresh > (nb_desc) || 1043 tx_free_thresh > NICVF_MAX_TX_FREE_THRESH) { 1044 PMD_INIT_LOG(ERR, 1045 "tx_free_thresh must be less than the number of TX " 1046 "descriptors. (tx_free_thresh=%u port=%d " 1047 "queue=%d)", (unsigned int)tx_free_thresh, 1048 (int)dev->data->port_id, (int)qidx); 1049 return -EINVAL; 1050 } 1051 1052 /* Free memory prior to re-allocation if needed. */ 1053 if (dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) { 1054 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d", 1055 nicvf_netdev_qidx(nic, qidx)); 1056 nicvf_dev_tx_queue_release(dev, nicvf_netdev_qidx(nic, qidx)); 1057 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL; 1058 } 1059 1060 /* Allocating tx queue data structure */ 1061 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nicvf_txq), 1062 RTE_CACHE_LINE_SIZE, nic->node); 1063 if (txq == NULL) { 1064 PMD_INIT_LOG(ERR, "Failed to allocate txq=%d", 1065 nicvf_netdev_qidx(nic, qidx)); 1066 return -ENOMEM; 1067 } 1068 1069 txq->nic = nic; 1070 txq->queue_id = qidx; 1071 txq->tx_free_thresh = tx_free_thresh; 1072 txq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD; 1073 txq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR; 1074 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads; 1075 txq->offloads = offloads; 1076 1077 is_single_pool = !!(offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE); 1078 1079 /* Choose optimum free threshold value for multipool case */ 1080 if (!is_single_pool) { 1081 txq->tx_free_thresh = (uint16_t) 1082 (tx_conf->tx_free_thresh == NICVF_DEFAULT_TX_FREE_THRESH ? 1083 NICVF_TX_FREE_MPOOL_THRESH : 1084 tx_conf->tx_free_thresh); 1085 txq->pool_free = nicvf_multi_pool_free_xmited_buffers; 1086 } else { 1087 txq->pool_free = nicvf_single_pool_free_xmited_buffers; 1088 } 1089 1090 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = txq; 1091 1092 /* Allocate software ring */ 1093 txq->txbuffs = rte_zmalloc_socket("txq->txbuffs", 1094 nb_desc * sizeof(struct rte_mbuf *), 1095 RTE_CACHE_LINE_SIZE, nic->node); 1096 1097 if (txq->txbuffs == NULL) { 1098 nicvf_dev_tx_queue_release(dev, nicvf_netdev_qidx(nic, qidx)); 1099 return -ENOMEM; 1100 } 1101 1102 if (nicvf_qset_sq_alloc(dev, nic, txq, qidx, nb_desc)) { 1103 PMD_INIT_LOG(ERR, "Failed to allocate mem for sq %d", qidx); 1104 nicvf_dev_tx_queue_release(dev, nicvf_netdev_qidx(nic, qidx)); 1105 return -ENOMEM; 1106 } 1107 1108 nicvf_tx_queue_reset(txq); 1109 1110 PMD_INIT_LOG(DEBUG, "[%d] txq=%p nb_desc=%d desc=%p" 1111 " phys=0x%" PRIx64 " offloads=0x%" PRIx64, 1112 nicvf_netdev_qidx(nic, qidx), txq, nb_desc, txq->desc, 1113 txq->phys, txq->offloads); 1114 1115 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1116 RTE_ETH_QUEUE_STATE_STOPPED; 1117 return 0; 1118 } 1119 1120 static inline void 1121 nicvf_rx_queue_release_mbufs(struct rte_eth_dev *dev, struct nicvf_rxq *rxq) 1122 { 1123 uint32_t rxq_cnt; 1124 uint32_t nb_pkts, released_pkts = 0; 1125 uint32_t refill_cnt = 0; 1126 struct rte_mbuf *rx_pkts[NICVF_MAX_RX_FREE_THRESH]; 1127 1128 if (dev->rx_pkt_burst == NULL) 1129 return; 1130 1131 while ((rxq_cnt = nicvf_dev_rx_queue_count(rxq))) { 1132 nb_pkts = dev->rx_pkt_burst(rxq, rx_pkts, 1133 NICVF_MAX_RX_FREE_THRESH); 1134 PMD_DRV_LOG(INFO, "nb_pkts=%d rxq_cnt=%d", nb_pkts, rxq_cnt); 1135 while (nb_pkts) { 1136 rte_pktmbuf_free_seg(rx_pkts[--nb_pkts]); 1137 released_pkts++; 1138 } 1139 } 1140 1141 1142 refill_cnt += nicvf_dev_rbdr_refill(dev, 1143 nicvf_netdev_qidx(rxq->nic, rxq->queue_id)); 1144 1145 PMD_DRV_LOG(INFO, "free_cnt=%d refill_cnt=%d", 1146 released_pkts, refill_cnt); 1147 } 1148 1149 static void 1150 nicvf_rx_queue_reset(struct nicvf_rxq *rxq) 1151 { 1152 rxq->head = 0; 1153 rxq->available_space = 0; 1154 rxq->recv_buffers = 0; 1155 } 1156 1157 static inline int 1158 nicvf_vf_start_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 1159 uint16_t qidx) 1160 { 1161 struct nicvf_rxq *rxq; 1162 int ret; 1163 1164 assert(qidx < MAX_RCV_QUEUES_PER_QS); 1165 1166 if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 1167 RTE_ETH_QUEUE_STATE_STARTED) 1168 return 0; 1169 1170 /* Update rbdr pointer to all rxq */ 1171 rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]; 1172 rxq->shared_rbdr = nic->rbdr; 1173 1174 ret = nicvf_qset_rq_config(nic, qidx, rxq); 1175 if (ret) { 1176 PMD_INIT_LOG(ERR, "Failed to configure rq VF%d %d %d", 1177 nic->vf_id, qidx, ret); 1178 goto config_rq_error; 1179 } 1180 ret = nicvf_qset_cq_config(nic, qidx, rxq); 1181 if (ret) { 1182 PMD_INIT_LOG(ERR, "Failed to configure cq VF%d %d %d", 1183 nic->vf_id, qidx, ret); 1184 goto config_cq_error; 1185 } 1186 1187 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1188 RTE_ETH_QUEUE_STATE_STARTED; 1189 return 0; 1190 1191 config_cq_error: 1192 nicvf_qset_cq_reclaim(nic, qidx); 1193 config_rq_error: 1194 nicvf_qset_rq_reclaim(nic, qidx); 1195 return ret; 1196 } 1197 1198 static inline int 1199 nicvf_vf_stop_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 1200 uint16_t qidx) 1201 { 1202 struct nicvf_rxq *rxq; 1203 int ret, other_error; 1204 1205 if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 1206 RTE_ETH_QUEUE_STATE_STOPPED) 1207 return 0; 1208 1209 ret = nicvf_qset_rq_reclaim(nic, qidx); 1210 if (ret) 1211 PMD_INIT_LOG(ERR, "Failed to reclaim rq VF%d %d %d", 1212 nic->vf_id, qidx, ret); 1213 1214 other_error = ret; 1215 rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]; 1216 nicvf_rx_queue_release_mbufs(dev, rxq); 1217 nicvf_rx_queue_reset(rxq); 1218 1219 ret = nicvf_qset_cq_reclaim(nic, qidx); 1220 if (ret) 1221 PMD_INIT_LOG(ERR, "Failed to reclaim cq VF%d %d %d", 1222 nic->vf_id, qidx, ret); 1223 1224 other_error |= ret; 1225 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1226 RTE_ETH_QUEUE_STATE_STOPPED; 1227 return other_error; 1228 } 1229 1230 static void 1231 nicvf_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid) 1232 { 1233 PMD_INIT_FUNC_TRACE(); 1234 1235 rte_free(dev->data->rx_queues[qid]); 1236 } 1237 1238 static int 1239 nicvf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx) 1240 { 1241 struct nicvf *nic = nicvf_pmd_priv(dev); 1242 int ret; 1243 1244 if (qidx >= MAX_RCV_QUEUES_PER_QS) 1245 nic = nic->snicvf[(qidx / MAX_RCV_QUEUES_PER_QS - 1)]; 1246 1247 qidx = qidx % MAX_RCV_QUEUES_PER_QS; 1248 1249 ret = nicvf_vf_start_rx_queue(dev, nic, qidx); 1250 if (ret) 1251 return ret; 1252 1253 ret = nicvf_configure_cpi(dev); 1254 if (ret) 1255 return ret; 1256 1257 return nicvf_configure_rss_reta(dev); 1258 } 1259 1260 static int 1261 nicvf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx) 1262 { 1263 int ret; 1264 struct nicvf *nic = nicvf_pmd_priv(dev); 1265 1266 if (qidx >= MAX_SND_QUEUES_PER_QS) 1267 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)]; 1268 1269 qidx = qidx % MAX_RCV_QUEUES_PER_QS; 1270 1271 ret = nicvf_vf_stop_rx_queue(dev, nic, qidx); 1272 ret |= nicvf_configure_cpi(dev); 1273 ret |= nicvf_configure_rss_reta(dev); 1274 return ret; 1275 } 1276 1277 static int 1278 nicvf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx) 1279 { 1280 struct nicvf *nic = nicvf_pmd_priv(dev); 1281 1282 if (qidx >= MAX_SND_QUEUES_PER_QS) 1283 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)]; 1284 1285 qidx = qidx % MAX_SND_QUEUES_PER_QS; 1286 1287 return nicvf_vf_start_tx_queue(dev, nic, qidx); 1288 } 1289 1290 static int 1291 nicvf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx) 1292 { 1293 struct nicvf *nic = nicvf_pmd_priv(dev); 1294 1295 if (qidx >= MAX_SND_QUEUES_PER_QS) 1296 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)]; 1297 1298 qidx = qidx % MAX_SND_QUEUES_PER_QS; 1299 1300 return nicvf_vf_stop_tx_queue(dev, nic, qidx); 1301 } 1302 1303 static inline void 1304 nicvf_rxq_mbuf_setup(struct nicvf_rxq *rxq) 1305 { 1306 uintptr_t p; 1307 struct rte_mbuf mb_def; 1308 struct nicvf *nic = rxq->nic; 1309 1310 RTE_BUILD_BUG_ON(sizeof(union mbuf_initializer) != 8); 1311 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0); 1312 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) - 1313 offsetof(struct rte_mbuf, data_off) != 2); 1314 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) - 1315 offsetof(struct rte_mbuf, data_off) != 4); 1316 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) - 1317 offsetof(struct rte_mbuf, data_off) != 6); 1318 RTE_BUILD_BUG_ON(offsetof(struct nicvf_rxq, rxq_fastpath_data_end) - 1319 offsetof(struct nicvf_rxq, 1320 rxq_fastpath_data_start) > 128); 1321 mb_def.nb_segs = 1; 1322 mb_def.data_off = RTE_PKTMBUF_HEADROOM + (nic->skip_bytes); 1323 mb_def.port = rxq->port_id; 1324 rte_mbuf_refcnt_set(&mb_def, 1); 1325 1326 /* Prevent compiler reordering: rearm_data covers previous fields */ 1327 rte_compiler_barrier(); 1328 p = (uintptr_t)&mb_def.rearm_data; 1329 rxq->mbuf_initializer.value = *(uint64_t *)p; 1330 } 1331 1332 static int 1333 nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx, 1334 uint16_t nb_desc, unsigned int socket_id, 1335 const struct rte_eth_rxconf *rx_conf, 1336 struct rte_mempool *mp) 1337 { 1338 uint16_t rx_free_thresh; 1339 struct nicvf_rxq *rxq; 1340 struct nicvf *nic = nicvf_pmd_priv(dev); 1341 uint64_t offloads; 1342 uint32_t buffsz; 1343 struct rte_pktmbuf_pool_private *mbp_priv; 1344 1345 PMD_INIT_FUNC_TRACE(); 1346 1347 /* First skip check */ 1348 mbp_priv = rte_mempool_get_priv(mp); 1349 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM; 1350 if (buffsz < (uint32_t)(nic->skip_bytes)) { 1351 PMD_INIT_LOG(ERR, "First skip is more than configured buffer size"); 1352 return -EINVAL; 1353 } 1354 1355 if (qidx >= MAX_RCV_QUEUES_PER_QS) 1356 nic = nic->snicvf[qidx / MAX_RCV_QUEUES_PER_QS - 1]; 1357 1358 qidx = qidx % MAX_RCV_QUEUES_PER_QS; 1359 1360 /* Socket id check */ 1361 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node) 1362 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d", 1363 socket_id, nic->node); 1364 1365 /* Mempool memory must be contiguous, so must be one memory segment*/ 1366 if (mp->nb_mem_chunks != 1) { 1367 PMD_INIT_LOG(ERR, "Non-contiguous mempool, add more huge pages"); 1368 return -EINVAL; 1369 } 1370 1371 /* Mempool memory must be physically contiguous */ 1372 if (mp->flags & RTE_MEMPOOL_F_NO_IOVA_CONTIG) { 1373 PMD_INIT_LOG(ERR, "Mempool memory must be physically contiguous"); 1374 return -EINVAL; 1375 } 1376 1377 /* Rx deferred start is not supported */ 1378 if (rx_conf->rx_deferred_start) { 1379 PMD_INIT_LOG(ERR, "Rx deferred start not supported"); 1380 return -EINVAL; 1381 } 1382 1383 /* Roundup nb_desc to available qsize and validate max number of desc */ 1384 nb_desc = nicvf_qsize_cq_roundup(nb_desc); 1385 if (nb_desc == 0) { 1386 PMD_INIT_LOG(ERR, "Value nb_desc beyond available hw cq qsize"); 1387 return -EINVAL; 1388 } 1389 1390 1391 /* Check rx_free_thresh upper bound */ 1392 rx_free_thresh = (uint16_t)((rx_conf->rx_free_thresh) ? 1393 rx_conf->rx_free_thresh : 1394 NICVF_DEFAULT_RX_FREE_THRESH); 1395 if (rx_free_thresh > NICVF_MAX_RX_FREE_THRESH || 1396 rx_free_thresh >= nb_desc * .75) { 1397 PMD_INIT_LOG(ERR, "rx_free_thresh greater than expected %d", 1398 rx_free_thresh); 1399 return -EINVAL; 1400 } 1401 1402 /* Free memory prior to re-allocation if needed */ 1403 if (dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) { 1404 PMD_RX_LOG(DEBUG, "Freeing memory prior to re-allocation %d", 1405 nicvf_netdev_qidx(nic, qidx)); 1406 nicvf_dev_rx_queue_release(dev, nicvf_netdev_qidx(nic, qidx)); 1407 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL; 1408 } 1409 1410 /* Allocate rxq memory */ 1411 rxq = rte_zmalloc_socket("ethdev rx queue", sizeof(struct nicvf_rxq), 1412 RTE_CACHE_LINE_SIZE, nic->node); 1413 if (rxq == NULL) { 1414 PMD_INIT_LOG(ERR, "Failed to allocate rxq=%d", 1415 nicvf_netdev_qidx(nic, qidx)); 1416 return -ENOMEM; 1417 } 1418 1419 rxq->nic = nic; 1420 rxq->pool = mp; 1421 rxq->queue_id = qidx; 1422 rxq->port_id = dev->data->port_id; 1423 rxq->rx_free_thresh = rx_free_thresh; 1424 rxq->rx_drop_en = rx_conf->rx_drop_en; 1425 rxq->cq_status = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_STATUS; 1426 rxq->cq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_DOOR; 1427 rxq->precharge_cnt = 0; 1428 1429 if (nicvf_hw_cap(nic) & NICVF_CAP_CQE_RX2) 1430 rxq->rbptr_offset = NICVF_CQE_RX2_RBPTR_WORD; 1431 else 1432 rxq->rbptr_offset = NICVF_CQE_RBPTR_WORD; 1433 1434 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = rxq; 1435 1436 nicvf_rxq_mbuf_setup(rxq); 1437 1438 /* Alloc completion queue */ 1439 if (nicvf_qset_cq_alloc(dev, nic, rxq, rxq->queue_id, nb_desc)) { 1440 PMD_INIT_LOG(ERR, "failed to allocate cq %u", rxq->queue_id); 1441 nicvf_dev_rx_queue_release(dev, nicvf_netdev_qidx(nic, qidx)); 1442 return -ENOMEM; 1443 } 1444 1445 nicvf_rx_queue_reset(rxq); 1446 1447 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads; 1448 PMD_INIT_LOG(DEBUG, "[%d] rxq=%p pool=%s nb_desc=(%d/%d)" 1449 " phy=0x%" PRIx64 " offloads=0x%" PRIx64, 1450 nicvf_netdev_qidx(nic, qidx), rxq, mp->name, nb_desc, 1451 rte_mempool_avail_count(mp), rxq->phys, offloads); 1452 1453 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1454 RTE_ETH_QUEUE_STATE_STOPPED; 1455 return 0; 1456 } 1457 1458 static int 1459 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 1460 { 1461 struct nicvf *nic = nicvf_pmd_priv(dev); 1462 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1463 1464 PMD_INIT_FUNC_TRACE(); 1465 1466 /* Autonegotiation may be disabled */ 1467 dev_info->speed_capa = RTE_ETH_LINK_SPEED_FIXED; 1468 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_10M | RTE_ETH_LINK_SPEED_100M | 1469 RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_10G; 1470 if (nicvf_hw_version(nic) != PCI_SUB_DEVICE_ID_CN81XX_NICVF) 1471 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_40G; 1472 1473 dev_info->min_rx_bufsize = RTE_ETHER_MIN_MTU; 1474 dev_info->max_rx_pktlen = NIC_HW_MAX_MTU + RTE_ETHER_HDR_LEN; 1475 dev_info->max_rx_queues = 1476 (uint16_t)MAX_RCV_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1); 1477 dev_info->max_tx_queues = 1478 (uint16_t)MAX_SND_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1); 1479 dev_info->max_mac_addrs = 1; 1480 dev_info->max_vfs = pci_dev->max_vfs; 1481 1482 dev_info->max_mtu = dev_info->max_rx_pktlen - 1483 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN); 1484 dev_info->min_mtu = dev_info->min_rx_bufsize - NIC_HW_L2_OVERHEAD; 1485 1486 dev_info->rx_offload_capa = NICVF_RX_OFFLOAD_CAPA; 1487 dev_info->tx_offload_capa = NICVF_TX_OFFLOAD_CAPA; 1488 dev_info->rx_queue_offload_capa = NICVF_RX_OFFLOAD_CAPA; 1489 dev_info->tx_queue_offload_capa = NICVF_TX_OFFLOAD_CAPA; 1490 1491 dev_info->reta_size = nic->rss_info.rss_size; 1492 dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE; 1493 dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1; 1494 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) 1495 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL; 1496 1497 dev_info->default_rxconf = (struct rte_eth_rxconf) { 1498 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH, 1499 .rx_drop_en = 0, 1500 }; 1501 1502 dev_info->default_txconf = (struct rte_eth_txconf) { 1503 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH, 1504 .offloads = RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE | 1505 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | 1506 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | 1507 RTE_ETH_TX_OFFLOAD_TCP_CKSUM, 1508 }; 1509 1510 return 0; 1511 } 1512 1513 static nicvf_iova_addr_t 1514 rbdr_rte_mempool_get(void *dev, void *opaque) 1515 { 1516 uint16_t qidx; 1517 uintptr_t mbuf; 1518 struct nicvf_rxq *rxq; 1519 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)dev; 1520 struct nicvf *nic = (struct nicvf *)opaque; 1521 uint16_t rx_start, rx_end; 1522 1523 /* Get queue ranges for this VF */ 1524 nicvf_rx_range(eth_dev, nic, &rx_start, &rx_end); 1525 1526 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1527 rxq = eth_dev->data->rx_queues[qidx]; 1528 /* Maintain equal buffer count across all pools */ 1529 if (rxq->precharge_cnt >= rxq->qlen_mask) 1530 continue; 1531 rxq->precharge_cnt++; 1532 mbuf = (uintptr_t)rte_pktmbuf_alloc(rxq->pool); 1533 if (mbuf) 1534 return nicvf_mbuff_virt2phy(mbuf, rxq->mbuf_phys_off); 1535 } 1536 return 0; 1537 } 1538 1539 static int 1540 nicvf_vf_start(struct rte_eth_dev *dev, struct nicvf *nic, uint32_t rbdrsz) 1541 { 1542 int ret; 1543 uint16_t qidx, data_off; 1544 uint32_t total_rxq_desc, nb_rbdr_desc, exp_buffs; 1545 uint64_t mbuf_phys_off = 0; 1546 struct nicvf_rxq *rxq; 1547 struct rte_mbuf *mbuf; 1548 uint16_t rx_start, rx_end; 1549 uint16_t tx_start, tx_end; 1550 int mask; 1551 1552 PMD_INIT_FUNC_TRACE(); 1553 1554 /* Userspace process exited without proper shutdown in last run */ 1555 if (nicvf_qset_rbdr_active(nic, 0)) 1556 nicvf_vf_stop(dev, nic, false); 1557 1558 /* Get queue ranges for this VF */ 1559 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 1560 1561 /* 1562 * Thunderx nicvf PMD can support more than one pool per port only when 1563 * 1) Data payload size is same across all the pools in given port 1564 * AND 1565 * 2) All mbuffs in the pools are from the same hugepage 1566 * AND 1567 * 3) Mbuff metadata size is same across all the pools in given port 1568 * 1569 * This is to support existing application that uses multiple pool/port. 1570 * But, the purpose of using multipool for QoS will not be addressed. 1571 * 1572 */ 1573 1574 /* Validate mempool attributes */ 1575 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1576 rxq = dev->data->rx_queues[qidx]; 1577 rxq->mbuf_phys_off = nicvf_mempool_phy_offset(rxq->pool); 1578 mbuf = rte_pktmbuf_alloc(rxq->pool); 1579 if (mbuf == NULL) { 1580 PMD_INIT_LOG(ERR, "Failed allocate mbuf VF%d qid=%d " 1581 "pool=%s", 1582 nic->vf_id, qidx, rxq->pool->name); 1583 return -ENOMEM; 1584 } 1585 data_off = nicvf_mbuff_meta_length(mbuf); 1586 data_off += RTE_PKTMBUF_HEADROOM; 1587 rte_pktmbuf_free(mbuf); 1588 1589 if (data_off % RTE_CACHE_LINE_SIZE) { 1590 PMD_INIT_LOG(ERR, "%s: unaligned data_off=%d delta=%d", 1591 rxq->pool->name, data_off, 1592 data_off % RTE_CACHE_LINE_SIZE); 1593 return -EINVAL; 1594 } 1595 rxq->mbuf_phys_off -= data_off; 1596 rxq->mbuf_phys_off -= nic->skip_bytes; 1597 1598 if (mbuf_phys_off == 0) 1599 mbuf_phys_off = rxq->mbuf_phys_off; 1600 if (mbuf_phys_off != rxq->mbuf_phys_off) { 1601 PMD_INIT_LOG(ERR, "pool params not same,%s VF%d %" 1602 PRIx64, rxq->pool->name, nic->vf_id, 1603 mbuf_phys_off); 1604 return -EINVAL; 1605 } 1606 } 1607 1608 /* Check the level of buffers in the pool */ 1609 total_rxq_desc = 0; 1610 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1611 rxq = dev->data->rx_queues[qidx]; 1612 /* Count total numbers of rxq descs */ 1613 total_rxq_desc += rxq->qlen_mask + 1; 1614 exp_buffs = RTE_MEMPOOL_CACHE_MAX_SIZE + rxq->rx_free_thresh; 1615 exp_buffs *= dev->data->nb_rx_queues; 1616 if (rte_mempool_avail_count(rxq->pool) < exp_buffs) { 1617 PMD_INIT_LOG(ERR, "Buff shortage in pool=%s (%d/%d)", 1618 rxq->pool->name, 1619 rte_mempool_avail_count(rxq->pool), 1620 exp_buffs); 1621 return -ENOENT; 1622 } 1623 } 1624 1625 /* Check RBDR desc overflow */ 1626 ret = nicvf_qsize_rbdr_roundup(total_rxq_desc); 1627 if (ret == 0) { 1628 PMD_INIT_LOG(ERR, "Reached RBDR desc limit, reduce nr desc " 1629 "VF%d", nic->vf_id); 1630 return -ENOMEM; 1631 } 1632 1633 /* Enable qset */ 1634 ret = nicvf_qset_config(nic); 1635 if (ret) { 1636 PMD_INIT_LOG(ERR, "Failed to enable qset %d VF%d", ret, 1637 nic->vf_id); 1638 return ret; 1639 } 1640 1641 /* Allocate RBDR and RBDR ring desc */ 1642 nb_rbdr_desc = nicvf_qsize_rbdr_roundup(total_rxq_desc); 1643 ret = nicvf_qset_rbdr_alloc(dev, nic, nb_rbdr_desc, rbdrsz); 1644 if (ret) { 1645 PMD_INIT_LOG(ERR, "Failed to allocate memory for rbdr alloc " 1646 "VF%d", nic->vf_id); 1647 goto qset_reclaim; 1648 } 1649 1650 /* Enable and configure RBDR registers */ 1651 ret = nicvf_qset_rbdr_config(nic, 0); 1652 if (ret) { 1653 PMD_INIT_LOG(ERR, "Failed to configure rbdr %d VF%d", ret, 1654 nic->vf_id); 1655 goto qset_rbdr_free; 1656 } 1657 1658 /* Fill rte_mempool buffers in RBDR pool and precharge it */ 1659 ret = nicvf_qset_rbdr_precharge(dev, nic, 0, rbdr_rte_mempool_get, 1660 total_rxq_desc); 1661 if (ret) { 1662 PMD_INIT_LOG(ERR, "Failed to fill rbdr %d VF%d", ret, 1663 nic->vf_id); 1664 goto qset_rbdr_reclaim; 1665 } 1666 1667 PMD_DRV_LOG(INFO, "Filled %d out of %d entries in RBDR VF%d", 1668 nic->rbdr->tail, nb_rbdr_desc, nic->vf_id); 1669 1670 /* Configure VLAN Strip */ 1671 mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK | 1672 RTE_ETH_VLAN_EXTEND_MASK; 1673 ret = nicvf_vlan_offload_config(dev, mask); 1674 1675 /* Based on the packet type(IPv4 or IPv6), the nicvf HW aligns L3 data 1676 * to the 64bit memory address. 1677 * The alignment creates a hole in mbuf(between the end of headroom and 1678 * packet data start). The new revision of the HW provides an option to 1679 * disable the L3 alignment feature and make mbuf layout looks 1680 * more like other NICs. For better application compatibility, disabling 1681 * l3 alignment feature on the hardware revisions it supports 1682 */ 1683 nicvf_apad_config(nic, false); 1684 1685 /* Get queue ranges for this VF */ 1686 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 1687 1688 /* Configure TX queues */ 1689 for (qidx = tx_start; qidx <= tx_end; qidx++) { 1690 ret = nicvf_vf_start_tx_queue(dev, nic, 1691 qidx % MAX_SND_QUEUES_PER_QS); 1692 if (ret) 1693 goto start_txq_error; 1694 } 1695 1696 /* Configure RX queues */ 1697 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1698 ret = nicvf_vf_start_rx_queue(dev, nic, 1699 qidx % MAX_RCV_QUEUES_PER_QS); 1700 if (ret) 1701 goto start_rxq_error; 1702 } 1703 1704 if (!nic->sqs_mode) { 1705 /* Configure CPI algorithm */ 1706 ret = nicvf_configure_cpi(dev); 1707 if (ret) 1708 goto start_txq_error; 1709 1710 ret = nicvf_mbox_get_rss_size(nic); 1711 if (ret) { 1712 PMD_INIT_LOG(ERR, "Failed to get rss table size"); 1713 goto qset_rss_error; 1714 } 1715 1716 /* Configure RSS */ 1717 ret = nicvf_configure_rss(dev); 1718 if (ret) 1719 goto qset_rss_error; 1720 } 1721 1722 /* Done; Let PF make the BGX's RX and TX switches to ON position */ 1723 nicvf_mbox_cfg_done(nic); 1724 return 0; 1725 1726 qset_rss_error: 1727 nicvf_rss_term(nic); 1728 start_rxq_error: 1729 for (qidx = rx_start; qidx <= rx_end; qidx++) 1730 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS); 1731 start_txq_error: 1732 for (qidx = tx_start; qidx <= tx_end; qidx++) 1733 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS); 1734 qset_rbdr_reclaim: 1735 nicvf_qset_rbdr_reclaim(nic, 0); 1736 nicvf_rbdr_release_mbufs(dev, nic); 1737 qset_rbdr_free: 1738 if (nic->rbdr) { 1739 rte_free(nic->rbdr); 1740 nic->rbdr = NULL; 1741 } 1742 qset_reclaim: 1743 nicvf_qset_reclaim(nic); 1744 return ret; 1745 } 1746 1747 static int 1748 nicvf_dev_start(struct rte_eth_dev *dev) 1749 { 1750 uint16_t qidx; 1751 int ret; 1752 size_t i; 1753 struct nicvf *nic = nicvf_pmd_priv(dev); 1754 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode; 1755 uint16_t mtu; 1756 uint32_t buffsz = 0, rbdrsz = 0; 1757 struct rte_pktmbuf_pool_private *mbp_priv; 1758 struct nicvf_rxq *rxq; 1759 1760 PMD_INIT_FUNC_TRACE(); 1761 1762 /* This function must be called for a primary device */ 1763 assert_primary(nic); 1764 1765 /* Validate RBDR buff size */ 1766 for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) { 1767 rxq = dev->data->rx_queues[qidx]; 1768 mbp_priv = rte_mempool_get_priv(rxq->pool); 1769 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM; 1770 if (buffsz % 128) { 1771 PMD_INIT_LOG(ERR, "rxbuf size must be multiply of 128"); 1772 return -EINVAL; 1773 } 1774 if (rbdrsz == 0) 1775 rbdrsz = buffsz; 1776 if (rbdrsz != buffsz) { 1777 PMD_INIT_LOG(ERR, "buffsz not same, qidx=%d (%d/%d)", 1778 qidx, rbdrsz, buffsz); 1779 return -EINVAL; 1780 } 1781 } 1782 1783 /* Configure loopback */ 1784 ret = nicvf_loopback_config(nic, dev->data->dev_conf.lpbk_mode); 1785 if (ret) { 1786 PMD_INIT_LOG(ERR, "Failed to configure loopback %d", ret); 1787 return ret; 1788 } 1789 1790 /* Reset all statistics counters attached to this port */ 1791 ret = nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, 0xFFFF, 0xFFFF); 1792 if (ret) { 1793 PMD_INIT_LOG(ERR, "Failed to reset stat counters %d", ret); 1794 return ret; 1795 } 1796 1797 /* Setup scatter mode if needed by jumbo */ 1798 if (dev->data->mtu + (uint32_t)NIC_HW_L2_OVERHEAD + 2 * VLAN_TAG_SIZE > buffsz) 1799 dev->data->scattered_rx = 1; 1800 if ((rx_conf->offloads & RTE_ETH_RX_OFFLOAD_SCATTER) != 0) 1801 dev->data->scattered_rx = 1; 1802 1803 /* Setup MTU */ 1804 mtu = dev->data->mtu; 1805 1806 if (nicvf_dev_set_mtu(dev, mtu)) { 1807 PMD_INIT_LOG(ERR, "Failed to set default mtu size"); 1808 return -EBUSY; 1809 } 1810 1811 /* Apply new link configurations if changed */ 1812 ret = nicvf_apply_link_speed(dev); 1813 if (ret) { 1814 PMD_INIT_LOG(ERR, "Failed to set link configuration\n"); 1815 return ret; 1816 } 1817 1818 ret = nicvf_vf_start(dev, nic, rbdrsz); 1819 if (ret != 0) 1820 return ret; 1821 1822 for (i = 0; i < nic->sqs_count; i++) { 1823 assert(nic->snicvf[i]); 1824 1825 ret = nicvf_vf_start(dev, nic->snicvf[i], rbdrsz); 1826 if (ret != 0) 1827 return ret; 1828 } 1829 1830 /* Configure callbacks based on offloads */ 1831 nicvf_set_tx_function(dev); 1832 nicvf_set_rx_function(dev); 1833 1834 return 0; 1835 } 1836 1837 static void 1838 nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup) 1839 { 1840 size_t i; 1841 int ret; 1842 struct nicvf *nic = nicvf_pmd_priv(dev); 1843 1844 PMD_INIT_FUNC_TRACE(); 1845 dev->data->dev_started = 0; 1846 1847 /* Teardown secondary vf first */ 1848 for (i = 0; i < nic->sqs_count; i++) { 1849 if (!nic->snicvf[i]) 1850 continue; 1851 1852 nicvf_vf_stop(dev, nic->snicvf[i], cleanup); 1853 } 1854 1855 /* Stop the primary VF now */ 1856 nicvf_vf_stop(dev, nic, cleanup); 1857 1858 /* Disable loopback */ 1859 ret = nicvf_loopback_config(nic, 0); 1860 if (ret) 1861 PMD_INIT_LOG(ERR, "Failed to disable loopback %d", ret); 1862 1863 /* Reclaim CPI configuration */ 1864 ret = nicvf_mbox_config_cpi(nic, 0); 1865 if (ret) 1866 PMD_INIT_LOG(ERR, "Failed to reclaim CPI config %d", ret); 1867 } 1868 1869 static int 1870 nicvf_dev_stop(struct rte_eth_dev *dev) 1871 { 1872 PMD_INIT_FUNC_TRACE(); 1873 1874 nicvf_dev_stop_cleanup(dev, false); 1875 1876 return 0; 1877 } 1878 1879 static void 1880 nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, bool cleanup) 1881 { 1882 int ret; 1883 uint16_t qidx; 1884 uint16_t tx_start, tx_end; 1885 uint16_t rx_start, rx_end; 1886 1887 PMD_INIT_FUNC_TRACE(); 1888 1889 if (cleanup) { 1890 /* Let PF make the BGX's RX and TX switches to OFF position */ 1891 nicvf_mbox_shutdown(nic); 1892 } 1893 1894 /* Disable VLAN Strip */ 1895 nicvf_vlan_hw_strip(nic, 0); 1896 1897 /* Get queue ranges for this VF */ 1898 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 1899 1900 for (qidx = tx_start; qidx <= tx_end; qidx++) 1901 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS); 1902 1903 /* Get queue ranges for this VF */ 1904 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 1905 1906 /* Reclaim rq */ 1907 for (qidx = rx_start; qidx <= rx_end; qidx++) 1908 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS); 1909 1910 /* Reclaim RBDR */ 1911 ret = nicvf_qset_rbdr_reclaim(nic, 0); 1912 if (ret) 1913 PMD_INIT_LOG(ERR, "Failed to reclaim RBDR %d", ret); 1914 1915 /* Move all charged buffers in RBDR back to pool */ 1916 if (nic->rbdr != NULL) 1917 nicvf_rbdr_release_mbufs(dev, nic); 1918 1919 /* Disable qset */ 1920 ret = nicvf_qset_reclaim(nic); 1921 if (ret) 1922 PMD_INIT_LOG(ERR, "Failed to disable qset %d", ret); 1923 1924 /* Disable all interrupts */ 1925 nicvf_disable_all_interrupts(nic); 1926 1927 /* Free RBDR SW structure */ 1928 if (nic->rbdr) { 1929 rte_free(nic->rbdr); 1930 nic->rbdr = NULL; 1931 } 1932 } 1933 1934 static int 1935 nicvf_dev_close(struct rte_eth_dev *dev) 1936 { 1937 struct nicvf *nic = nicvf_pmd_priv(dev); 1938 1939 PMD_INIT_FUNC_TRACE(); 1940 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1941 return 0; 1942 1943 nicvf_dev_stop_cleanup(dev, true); 1944 nicvf_periodic_alarm_stop(nicvf_interrupt, dev); 1945 nicvf_periodic_alarm_stop(nicvf_vf_interrupt, nic); 1946 1947 rte_intr_instance_free(nic->intr_handle); 1948 1949 return 0; 1950 } 1951 1952 static int 1953 nicvf_request_sqs(struct nicvf *nic) 1954 { 1955 size_t i; 1956 1957 assert_primary(nic); 1958 assert(nic->sqs_count > 0); 1959 assert(nic->sqs_count <= MAX_SQS_PER_VF); 1960 1961 /* Set no of Rx/Tx queues in each of the SQsets */ 1962 for (i = 0; i < nic->sqs_count; i++) { 1963 if (nicvf_svf_empty()) 1964 rte_panic("Cannot assign sufficient number of " 1965 "secondary queues to primary VF%" PRIu8 "\n", 1966 nic->vf_id); 1967 1968 nic->snicvf[i] = nicvf_svf_pop(); 1969 nic->snicvf[i]->sqs_id = i; 1970 } 1971 1972 return nicvf_mbox_request_sqs(nic); 1973 } 1974 1975 static int 1976 nicvf_dev_configure(struct rte_eth_dev *dev) 1977 { 1978 struct rte_eth_dev_data *data = dev->data; 1979 struct rte_eth_conf *conf = &data->dev_conf; 1980 struct rte_eth_rxmode *rxmode = &conf->rxmode; 1981 struct rte_eth_txmode *txmode = &conf->txmode; 1982 struct nicvf *nic = nicvf_pmd_priv(dev); 1983 uint8_t cqcount; 1984 1985 PMD_INIT_FUNC_TRACE(); 1986 1987 if (rxmode->mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) 1988 rxmode->offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH; 1989 1990 if (!rte_eal_has_hugepages()) { 1991 PMD_INIT_LOG(INFO, "Huge page is not configured"); 1992 return -EINVAL; 1993 } 1994 1995 if (txmode->mq_mode) { 1996 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported"); 1997 return -EINVAL; 1998 } 1999 2000 if (rxmode->mq_mode != RTE_ETH_MQ_RX_NONE && 2001 rxmode->mq_mode != RTE_ETH_MQ_RX_RSS) { 2002 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode); 2003 return -EINVAL; 2004 } 2005 2006 if (rxmode->split_hdr_size) { 2007 PMD_INIT_LOG(INFO, "Rxmode does not support split header"); 2008 return -EINVAL; 2009 } 2010 2011 if (conf->dcb_capability_en) { 2012 PMD_INIT_LOG(INFO, "DCB enable not supported"); 2013 return -EINVAL; 2014 } 2015 2016 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) { 2017 PMD_INIT_LOG(INFO, "Flow director not supported"); 2018 return -EINVAL; 2019 } 2020 2021 assert_primary(nic); 2022 NICVF_STATIC_ASSERT(MAX_RCV_QUEUES_PER_QS == MAX_SND_QUEUES_PER_QS); 2023 cqcount = RTE_MAX(data->nb_tx_queues, data->nb_rx_queues); 2024 if (cqcount > MAX_RCV_QUEUES_PER_QS) { 2025 nic->sqs_count = RTE_ALIGN_CEIL(cqcount, MAX_RCV_QUEUES_PER_QS); 2026 nic->sqs_count = (nic->sqs_count / MAX_RCV_QUEUES_PER_QS) - 1; 2027 } else { 2028 nic->sqs_count = 0; 2029 } 2030 2031 assert(nic->sqs_count <= MAX_SQS_PER_VF); 2032 2033 if (nic->sqs_count > 0) { 2034 if (nicvf_request_sqs(nic)) { 2035 rte_panic("Cannot assign sufficient number of " 2036 "secondary queues to PORT%d VF%" PRIu8 "\n", 2037 dev->data->port_id, nic->vf_id); 2038 } 2039 } 2040 2041 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_CHECKSUM) 2042 nic->offload_cksum = 1; 2043 2044 PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64, 2045 dev->data->port_id, nicvf_hw_cap(nic)); 2046 2047 return 0; 2048 } 2049 2050 static int 2051 nicvf_dev_set_link_up(struct rte_eth_dev *dev) 2052 { 2053 struct nicvf *nic = nicvf_pmd_priv(dev); 2054 int rc, i; 2055 2056 rc = nicvf_mbox_set_link_up_down(nic, true); 2057 if (rc) 2058 goto done; 2059 2060 /* Start tx queues */ 2061 for (i = 0; i < dev->data->nb_tx_queues; i++) 2062 nicvf_dev_tx_queue_start(dev, i); 2063 2064 done: 2065 return rc; 2066 } 2067 2068 static int 2069 nicvf_dev_set_link_down(struct rte_eth_dev *dev) 2070 { 2071 struct nicvf *nic = nicvf_pmd_priv(dev); 2072 int i; 2073 2074 /* Stop tx queues */ 2075 for (i = 0; i < dev->data->nb_tx_queues; i++) 2076 nicvf_dev_tx_queue_stop(dev, i); 2077 2078 return nicvf_mbox_set_link_up_down(nic, false); 2079 } 2080 2081 /* Initialize and register driver with DPDK Application */ 2082 static const struct eth_dev_ops nicvf_eth_dev_ops = { 2083 .dev_configure = nicvf_dev_configure, 2084 .dev_start = nicvf_dev_start, 2085 .dev_stop = nicvf_dev_stop, 2086 .link_update = nicvf_dev_link_update, 2087 .dev_close = nicvf_dev_close, 2088 .stats_get = nicvf_dev_stats_get, 2089 .stats_reset = nicvf_dev_stats_reset, 2090 .promiscuous_enable = nicvf_dev_promisc_enable, 2091 .dev_infos_get = nicvf_dev_info_get, 2092 .dev_supported_ptypes_get = nicvf_dev_supported_ptypes_get, 2093 .mtu_set = nicvf_dev_set_mtu, 2094 .vlan_offload_set = nicvf_vlan_offload_set, 2095 .reta_update = nicvf_dev_reta_update, 2096 .reta_query = nicvf_dev_reta_query, 2097 .rss_hash_update = nicvf_dev_rss_hash_update, 2098 .rss_hash_conf_get = nicvf_dev_rss_hash_conf_get, 2099 .rx_queue_start = nicvf_dev_rx_queue_start, 2100 .rx_queue_stop = nicvf_dev_rx_queue_stop, 2101 .tx_queue_start = nicvf_dev_tx_queue_start, 2102 .tx_queue_stop = nicvf_dev_tx_queue_stop, 2103 .rx_queue_setup = nicvf_dev_rx_queue_setup, 2104 .rx_queue_release = nicvf_dev_rx_queue_release, 2105 .tx_queue_setup = nicvf_dev_tx_queue_setup, 2106 .tx_queue_release = nicvf_dev_tx_queue_release, 2107 .dev_set_link_up = nicvf_dev_set_link_up, 2108 .dev_set_link_down = nicvf_dev_set_link_down, 2109 .get_reg = nicvf_dev_get_regs, 2110 }; 2111 2112 static int 2113 nicvf_vlan_offload_config(struct rte_eth_dev *dev, int mask) 2114 { 2115 struct rte_eth_rxmode *rxmode; 2116 struct nicvf *nic = nicvf_pmd_priv(dev); 2117 rxmode = &dev->data->dev_conf.rxmode; 2118 if (mask & RTE_ETH_VLAN_STRIP_MASK) { 2119 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) 2120 nicvf_vlan_hw_strip(nic, true); 2121 else 2122 nicvf_vlan_hw_strip(nic, false); 2123 } 2124 2125 return 0; 2126 } 2127 2128 static int 2129 nicvf_vlan_offload_set(struct rte_eth_dev *dev, int mask) 2130 { 2131 nicvf_vlan_offload_config(dev, mask); 2132 2133 return 0; 2134 } 2135 2136 static inline int 2137 nicvf_set_first_skip(struct rte_eth_dev *dev) 2138 { 2139 int bytes_to_skip = 0; 2140 int ret = 0; 2141 unsigned int i; 2142 struct rte_kvargs *kvlist; 2143 static const char *const skip[] = { 2144 SKIP_DATA_BYTES, 2145 NULL}; 2146 struct nicvf *nic = nicvf_pmd_priv(dev); 2147 2148 if (!dev->device->devargs) { 2149 nicvf_first_skip_config(nic, 0); 2150 return ret; 2151 } 2152 2153 kvlist = rte_kvargs_parse(dev->device->devargs->args, skip); 2154 if (!kvlist) 2155 return -EINVAL; 2156 2157 if (kvlist->count == 0) 2158 goto exit; 2159 2160 for (i = 0; i != kvlist->count; ++i) { 2161 const struct rte_kvargs_pair *pair = &kvlist->pairs[i]; 2162 2163 if (!strcmp(pair->key, SKIP_DATA_BYTES)) 2164 bytes_to_skip = atoi(pair->value); 2165 } 2166 2167 /*128 bytes amounts to one cache line*/ 2168 if (bytes_to_skip >= 0 && bytes_to_skip < 128) { 2169 if (!(bytes_to_skip % 8)) { 2170 nicvf_first_skip_config(nic, (bytes_to_skip / 8)); 2171 nic->skip_bytes = bytes_to_skip; 2172 goto kvlist_free; 2173 } else { 2174 PMD_INIT_LOG(ERR, "skip_data_bytes should be multiple of 8"); 2175 ret = -EINVAL; 2176 goto exit; 2177 } 2178 } else { 2179 PMD_INIT_LOG(ERR, "skip_data_bytes should be less than 128"); 2180 ret = -EINVAL; 2181 goto exit; 2182 } 2183 exit: 2184 nicvf_first_skip_config(nic, 0); 2185 kvlist_free: 2186 rte_kvargs_free(kvlist); 2187 return ret; 2188 } 2189 static int 2190 nicvf_eth_dev_uninit(struct rte_eth_dev *dev) 2191 { 2192 PMD_INIT_FUNC_TRACE(); 2193 nicvf_dev_close(dev); 2194 return 0; 2195 } 2196 static int 2197 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev) 2198 { 2199 int ret; 2200 struct rte_pci_device *pci_dev; 2201 struct nicvf *nic = nicvf_pmd_priv(eth_dev); 2202 2203 PMD_INIT_FUNC_TRACE(); 2204 2205 eth_dev->dev_ops = &nicvf_eth_dev_ops; 2206 eth_dev->rx_queue_count = nicvf_dev_rx_queue_count; 2207 2208 /* For secondary processes, the primary has done all the work */ 2209 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2210 if (nic) { 2211 /* Setup callbacks for secondary process */ 2212 nicvf_set_tx_function(eth_dev); 2213 nicvf_set_rx_function(eth_dev); 2214 return 0; 2215 } else { 2216 /* If nic == NULL than it is secondary function 2217 * so ethdev need to be released by caller */ 2218 return ENOTSUP; 2219 } 2220 } 2221 2222 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 2223 rte_eth_copy_pci_info(eth_dev, pci_dev); 2224 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 2225 2226 nic->device_id = pci_dev->id.device_id; 2227 nic->vendor_id = pci_dev->id.vendor_id; 2228 nic->subsystem_device_id = pci_dev->id.subsystem_device_id; 2229 nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id; 2230 2231 PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) %u:%u:%u:%u", 2232 pci_dev->id.vendor_id, pci_dev->id.device_id, 2233 pci_dev->addr.domain, pci_dev->addr.bus, 2234 pci_dev->addr.devid, pci_dev->addr.function); 2235 2236 nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr; 2237 if (!nic->reg_base) { 2238 PMD_INIT_LOG(ERR, "Failed to map BAR0"); 2239 ret = -ENODEV; 2240 goto fail; 2241 } 2242 2243 /* Allocate interrupt instance */ 2244 nic->intr_handle = rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); 2245 if (nic->intr_handle == NULL) { 2246 PMD_INIT_LOG(ERR, "Failed to allocate intr handle"); 2247 ret = -ENODEV; 2248 goto fail; 2249 } 2250 2251 nicvf_disable_all_interrupts(nic); 2252 2253 /* To read mbox messages */ 2254 ret = nicvf_periodic_alarm_start(nicvf_vf_interrupt, nic); 2255 if (ret) { 2256 PMD_INIT_LOG(ERR, "Failed to start period alarm"); 2257 goto fail; 2258 } 2259 2260 /* To poll link status change*/ 2261 ret = nicvf_periodic_alarm_start(nicvf_interrupt, eth_dev); 2262 if (ret) { 2263 PMD_INIT_LOG(ERR, "Failed to start period alarm"); 2264 goto fail; 2265 } 2266 2267 ret = nicvf_mbox_check_pf_ready(nic); 2268 if (ret) { 2269 PMD_INIT_LOG(ERR, "Failed to get ready message from PF"); 2270 goto alarm_fail; 2271 } else { 2272 PMD_INIT_LOG(INFO, 2273 "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s", 2274 nic->node, nic->vf_id, 2275 nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass", 2276 nic->sqs_mode ? "true" : "false", 2277 nic->loopback_supported ? "true" : "false" 2278 ); 2279 } 2280 2281 /* To make sure RX DMAC register is set to default value (0x3) */ 2282 nicvf_mbox_reset_xcast(nic); 2283 2284 ret = nicvf_base_init(nic); 2285 if (ret) { 2286 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init"); 2287 goto malloc_fail; 2288 } 2289 2290 if (nic->sqs_mode) { 2291 /* Push nic to stack of secondary vfs */ 2292 nicvf_svf_push(nic); 2293 2294 /* Steal nic pointer from the device for further reuse */ 2295 eth_dev->data->dev_private = NULL; 2296 2297 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev); 2298 2299 /* Detach port by returning positive error number */ 2300 return ENOTSUP; 2301 } 2302 2303 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", 2304 RTE_ETHER_ADDR_LEN, 0); 2305 if (eth_dev->data->mac_addrs == NULL) { 2306 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr"); 2307 ret = -ENOMEM; 2308 goto alarm_fail; 2309 } 2310 if (rte_is_zero_ether_addr((struct rte_ether_addr *)nic->mac_addr)) 2311 rte_eth_random_addr(&nic->mac_addr[0]); 2312 2313 rte_ether_addr_copy((struct rte_ether_addr *)nic->mac_addr, 2314 ð_dev->data->mac_addrs[0]); 2315 2316 ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr); 2317 if (ret) { 2318 PMD_INIT_LOG(ERR, "Failed to set mac addr"); 2319 goto malloc_fail; 2320 } 2321 2322 ret = nicvf_set_first_skip(eth_dev); 2323 if (ret) { 2324 PMD_INIT_LOG(ERR, "Failed to configure first skip"); 2325 goto malloc_fail; 2326 } 2327 PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=" RTE_ETHER_ADDR_PRT_FMT, 2328 eth_dev->data->port_id, nic->vendor_id, nic->device_id, 2329 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2], 2330 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]); 2331 2332 return 0; 2333 2334 malloc_fail: 2335 rte_free(eth_dev->data->mac_addrs); 2336 eth_dev->data->mac_addrs = NULL; 2337 alarm_fail: 2338 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev); 2339 fail: 2340 return ret; 2341 } 2342 2343 static const struct rte_pci_id pci_id_nicvf_map[] = { 2344 { 2345 .class_id = RTE_CLASS_ANY_ID, 2346 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2347 .device_id = PCI_DEVICE_ID_THUNDERX_CN88XX_PASS1_NICVF, 2348 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2349 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS1_NICVF, 2350 }, 2351 { 2352 .class_id = RTE_CLASS_ANY_ID, 2353 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2354 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF, 2355 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2356 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS2_NICVF, 2357 }, 2358 { 2359 .class_id = RTE_CLASS_ANY_ID, 2360 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2361 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF, 2362 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2363 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN81XX_NICVF, 2364 }, 2365 { 2366 .class_id = RTE_CLASS_ANY_ID, 2367 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2368 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF, 2369 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2370 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN83XX_NICVF, 2371 }, 2372 { 2373 .vendor_id = 0, 2374 }, 2375 }; 2376 2377 static int nicvf_eth_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2378 struct rte_pci_device *pci_dev) 2379 { 2380 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct nicvf), 2381 nicvf_eth_dev_init); 2382 } 2383 2384 static int nicvf_eth_pci_remove(struct rte_pci_device *pci_dev) 2385 { 2386 return rte_eth_dev_pci_generic_remove(pci_dev, nicvf_eth_dev_uninit); 2387 } 2388 2389 static struct rte_pci_driver rte_nicvf_pmd = { 2390 .id_table = pci_id_nicvf_map, 2391 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_KEEP_MAPPED_RES | 2392 RTE_PCI_DRV_INTR_LSC, 2393 .probe = nicvf_eth_pci_probe, 2394 .remove = nicvf_eth_pci_remove, 2395 }; 2396 2397 RTE_PMD_REGISTER_PCI(net_thunderx, rte_nicvf_pmd); 2398 RTE_PMD_REGISTER_PCI_TABLE(net_thunderx, pci_id_nicvf_map); 2399 RTE_PMD_REGISTER_KMOD_DEP(net_thunderx, "* igb_uio | uio_pci_generic | vfio-pci"); 2400 RTE_PMD_REGISTER_PARAM_STRING(net_thunderx, SKIP_DATA_BYTES "=<int>"); 2401