1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2021 HiSilicon Limited. 3 */ 4 5 #include <rte_alarm.h> 6 #include <rte_bus_pci.h> 7 #include <ethdev_pci.h> 8 9 #include "hns3_ethdev.h" 10 #include "hns3_common.h" 11 #include "hns3_logs.h" 12 #include "hns3_rxtx.h" 13 #include "hns3_intr.h" 14 #include "hns3_regs.h" 15 #include "hns3_dcb.h" 16 #include "hns3_mp.h" 17 #include "hns3_flow.h" 18 19 #define HNS3_SERVICE_INTERVAL 1000000 /* us */ 20 #define HNS3_SERVICE_QUICK_INTERVAL 10 21 #define HNS3_INVALID_PVID 0xFFFF 22 23 #define HNS3_FILTER_TYPE_VF 0 24 #define HNS3_FILTER_TYPE_PORT 1 25 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0) 26 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0) 27 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1) 28 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2) 29 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3) 30 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \ 31 | HNS3_FILTER_FE_ROCE_EGRESS_B) 32 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \ 33 | HNS3_FILTER_FE_ROCE_INGRESS_B) 34 35 /* Reset related Registers */ 36 #define HNS3_GLOBAL_RESET_BIT 0 37 #define HNS3_CORE_RESET_BIT 1 38 #define HNS3_IMP_RESET_BIT 2 39 #define HNS3_FUN_RST_ING_B 0 40 41 #define HNS3_VECTOR0_IMP_RESET_INT_B 1 42 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U 43 #define HNS3_VECTOR0_IMP_RD_POISON_B 5U 44 #define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U 45 46 #define HNS3_RESET_WAIT_MS 100 47 #define HNS3_RESET_WAIT_CNT 200 48 49 /* FEC mode order defined in HNS3 hardware */ 50 #define HNS3_HW_FEC_MODE_NOFEC 0 51 #define HNS3_HW_FEC_MODE_BASER 1 52 #define HNS3_HW_FEC_MODE_RS 2 53 54 enum hns3_evt_cause { 55 HNS3_VECTOR0_EVENT_RST, 56 HNS3_VECTOR0_EVENT_MBX, 57 HNS3_VECTOR0_EVENT_ERR, 58 HNS3_VECTOR0_EVENT_PTP, 59 HNS3_VECTOR0_EVENT_OTHER, 60 }; 61 62 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = { 63 { RTE_ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 64 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 65 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) }, 66 67 { RTE_ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 68 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 69 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) | 70 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }, 71 72 { RTE_ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 73 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 74 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) }, 75 76 { RTE_ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 77 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 78 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) | 79 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }, 80 81 { RTE_ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 82 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 83 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }, 84 85 { RTE_ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 86 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 87 RTE_ETH_FEC_MODE_CAPA_MASK(RS) } 88 }; 89 90 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns, 91 uint64_t *levels); 92 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 93 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, 94 int on); 95 static int hns3_update_link_info(struct rte_eth_dev *eth_dev); 96 static bool hns3_update_link_status(struct hns3_hw *hw); 97 98 static int hns3_add_mc_mac_addr(struct hns3_hw *hw, 99 struct rte_ether_addr *mac_addr); 100 static int hns3_remove_mc_mac_addr(struct hns3_hw *hw, 101 struct rte_ether_addr *mac_addr); 102 static int hns3_restore_fec(struct hns3_hw *hw); 103 static int hns3_query_dev_fec_info(struct hns3_hw *hw); 104 static int hns3_do_stop(struct hns3_adapter *hns); 105 static int hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds); 106 static int hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable); 107 108 109 static void 110 hns3_pf_disable_irq0(struct hns3_hw *hw) 111 { 112 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0); 113 } 114 115 static void 116 hns3_pf_enable_irq0(struct hns3_hw *hw) 117 { 118 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1); 119 } 120 121 static enum hns3_evt_cause 122 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay, 123 uint32_t *vec_val) 124 { 125 struct hns3_hw *hw = &hns->hw; 126 127 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); 128 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); 129 *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B); 130 if (!is_delay) { 131 hw->reset.stats.imp_cnt++; 132 hns3_warn(hw, "IMP reset detected, clear reset status"); 133 } else { 134 hns3_schedule_delayed_reset(hns); 135 hns3_warn(hw, "IMP reset detected, don't clear reset status"); 136 } 137 138 return HNS3_VECTOR0_EVENT_RST; 139 } 140 141 static enum hns3_evt_cause 142 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay, 143 uint32_t *vec_val) 144 { 145 struct hns3_hw *hw = &hns->hw; 146 147 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); 148 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending); 149 *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B); 150 if (!is_delay) { 151 hw->reset.stats.global_cnt++; 152 hns3_warn(hw, "Global reset detected, clear reset status"); 153 } else { 154 hns3_schedule_delayed_reset(hns); 155 hns3_warn(hw, 156 "Global reset detected, don't clear reset status"); 157 } 158 159 return HNS3_VECTOR0_EVENT_RST; 160 } 161 162 static enum hns3_evt_cause 163 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) 164 { 165 struct hns3_hw *hw = &hns->hw; 166 uint32_t vector0_int_stats; 167 uint32_t cmdq_src_val; 168 uint32_t hw_err_src_reg; 169 uint32_t val; 170 enum hns3_evt_cause ret; 171 bool is_delay; 172 173 /* fetch the events from their corresponding regs */ 174 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); 175 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); 176 hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG); 177 178 is_delay = clearval == NULL ? true : false; 179 /* 180 * Assumption: If by any chance reset and mailbox events are reported 181 * together then we will only process reset event and defer the 182 * processing of the mailbox events. Since, we would have not cleared 183 * RX CMDQ event this time we would receive again another interrupt 184 * from H/W just for the mailbox. 185 */ 186 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */ 187 ret = hns3_proc_imp_reset_event(hns, is_delay, &val); 188 goto out; 189 } 190 191 /* Global reset */ 192 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) { 193 ret = hns3_proc_global_reset_event(hns, is_delay, &val); 194 goto out; 195 } 196 197 /* Check for vector0 1588 event source */ 198 if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) { 199 val = BIT(HNS3_VECTOR0_1588_INT_B); 200 ret = HNS3_VECTOR0_EVENT_PTP; 201 goto out; 202 } 203 204 /* check for vector0 msix event source */ 205 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK || 206 hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) { 207 val = vector0_int_stats | hw_err_src_reg; 208 ret = HNS3_VECTOR0_EVENT_ERR; 209 goto out; 210 } 211 212 /* check for vector0 mailbox(=CMDQ RX) event source */ 213 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) { 214 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B); 215 val = cmdq_src_val; 216 ret = HNS3_VECTOR0_EVENT_MBX; 217 goto out; 218 } 219 220 val = vector0_int_stats; 221 ret = HNS3_VECTOR0_EVENT_OTHER; 222 out: 223 224 if (clearval) 225 *clearval = val; 226 return ret; 227 } 228 229 static void 230 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr) 231 { 232 if (event_type == HNS3_VECTOR0_EVENT_RST || 233 event_type == HNS3_VECTOR0_EVENT_PTP) 234 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr); 235 else if (event_type == HNS3_VECTOR0_EVENT_MBX) 236 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr); 237 } 238 239 static void 240 hns3_clear_all_event_cause(struct hns3_hw *hw) 241 { 242 uint32_t vector0_int_stats; 243 244 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); 245 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) 246 hns3_warn(hw, "Probe during IMP reset interrupt"); 247 248 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) 249 hns3_warn(hw, "Probe during Global reset interrupt"); 250 251 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST, 252 BIT(HNS3_VECTOR0_IMPRESET_INT_B) | 253 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | 254 BIT(HNS3_VECTOR0_CORERESET_INT_B)); 255 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0); 256 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP, 257 BIT(HNS3_VECTOR0_1588_INT_B)); 258 } 259 260 static void 261 hns3_handle_mac_tnl(struct hns3_hw *hw) 262 { 263 struct hns3_cmd_desc desc; 264 uint32_t status; 265 int ret; 266 267 /* query and clear mac tnl interrupt */ 268 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true); 269 ret = hns3_cmd_send(hw, &desc, 1); 270 if (ret) { 271 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret); 272 return; 273 } 274 275 status = rte_le_to_cpu_32(desc.data[0]); 276 if (status) { 277 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status); 278 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT, 279 false); 280 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR); 281 ret = hns3_cmd_send(hw, &desc, 1); 282 if (ret) 283 hns3_err(hw, "failed to clear mac tnl int, ret = %d.", 284 ret); 285 } 286 } 287 288 static void 289 hns3_interrupt_handler(void *param) 290 { 291 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 292 struct hns3_adapter *hns = dev->data->dev_private; 293 struct hns3_hw *hw = &hns->hw; 294 enum hns3_evt_cause event_cause; 295 uint32_t clearval = 0; 296 uint32_t vector0_int; 297 uint32_t ras_int; 298 uint32_t cmdq_int; 299 300 /* Disable interrupt */ 301 hns3_pf_disable_irq0(hw); 302 303 event_cause = hns3_check_event_cause(hns, &clearval); 304 vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); 305 ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG); 306 cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); 307 hns3_clear_event_cause(hw, event_cause, clearval); 308 /* vector 0 interrupt is shared with reset and mailbox source events. */ 309 if (event_cause == HNS3_VECTOR0_EVENT_ERR) { 310 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x " 311 "ras_int_stat:0x%x cmdq_int_stat:0x%x", 312 vector0_int, ras_int, cmdq_int); 313 hns3_handle_mac_tnl(hw); 314 hns3_handle_error(hns); 315 } else if (event_cause == HNS3_VECTOR0_EVENT_RST) { 316 hns3_warn(hw, "received reset interrupt"); 317 hns3_schedule_reset(hns); 318 } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) { 319 hns3_dev_handle_mbx_msg(hw); 320 } else if (event_cause != HNS3_VECTOR0_EVENT_PTP) { 321 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x " 322 "ras_int_stat:0x%x cmdq_int_stat:0x%x", 323 vector0_int, ras_int, cmdq_int); 324 } 325 326 /* Enable interrupt if it is not cause by reset */ 327 hns3_pf_enable_irq0(hw); 328 } 329 330 static int 331 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on) 332 { 333 #define HNS3_VLAN_ID_OFFSET_STEP 160 334 #define HNS3_VLAN_BYTE_SIZE 8 335 struct hns3_vlan_filter_pf_cfg_cmd *req; 336 struct hns3_hw *hw = &hns->hw; 337 uint8_t vlan_offset_byte_val; 338 struct hns3_cmd_desc desc; 339 uint8_t vlan_offset_byte; 340 uint8_t vlan_offset_base; 341 int ret; 342 343 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false); 344 345 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP; 346 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) / 347 HNS3_VLAN_BYTE_SIZE; 348 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE); 349 350 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data; 351 req->vlan_offset = vlan_offset_base; 352 req->vlan_cfg = on ? 0 : 1; 353 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 354 355 ret = hns3_cmd_send(hw, &desc, 1); 356 if (ret) 357 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d", 358 vlan_id, ret); 359 360 return ret; 361 } 362 363 static void 364 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id) 365 { 366 struct hns3_user_vlan_table *vlan_entry; 367 struct hns3_pf *pf = &hns->pf; 368 369 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 370 if (vlan_entry->vlan_id == vlan_id) { 371 if (vlan_entry->hd_tbl_status) 372 hns3_set_port_vlan_filter(hns, vlan_id, 0); 373 LIST_REMOVE(vlan_entry, next); 374 rte_free(vlan_entry); 375 break; 376 } 377 } 378 } 379 380 static void 381 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id, 382 bool writen_to_tbl) 383 { 384 struct hns3_user_vlan_table *vlan_entry; 385 struct hns3_hw *hw = &hns->hw; 386 struct hns3_pf *pf = &hns->pf; 387 388 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 389 if (vlan_entry->vlan_id == vlan_id) 390 return; 391 } 392 393 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0); 394 if (vlan_entry == NULL) { 395 hns3_err(hw, "Failed to malloc hns3 vlan table"); 396 return; 397 } 398 399 vlan_entry->hd_tbl_status = writen_to_tbl; 400 vlan_entry->vlan_id = vlan_id; 401 402 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next); 403 } 404 405 static int 406 hns3_restore_vlan_table(struct hns3_adapter *hns) 407 { 408 struct hns3_user_vlan_table *vlan_entry; 409 struct hns3_hw *hw = &hns->hw; 410 struct hns3_pf *pf = &hns->pf; 411 uint16_t vlan_id; 412 int ret = 0; 413 414 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE) 415 return hns3_vlan_pvid_configure(hns, 416 hw->port_base_vlan_cfg.pvid, 1); 417 418 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 419 if (vlan_entry->hd_tbl_status) { 420 vlan_id = vlan_entry->vlan_id; 421 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1); 422 if (ret) 423 break; 424 } 425 } 426 427 return ret; 428 } 429 430 static int 431 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on) 432 { 433 struct hns3_hw *hw = &hns->hw; 434 bool writen_to_tbl = false; 435 int ret = 0; 436 437 /* 438 * When vlan filter is enabled, hardware regards packets without vlan 439 * as packets with vlan 0. So, to receive packets without vlan, vlan id 440 * 0 is not allowed to be removed by rte_eth_dev_vlan_filter. 441 */ 442 if (on == 0 && vlan_id == 0) 443 return 0; 444 445 /* 446 * When port base vlan enabled, we use port base vlan as the vlan 447 * filter condition. In this case, we don't update vlan filter table 448 * when user add new vlan or remove exist vlan, just update the 449 * vlan list. The vlan id in vlan list will be written in vlan filter 450 * table until port base vlan disabled 451 */ 452 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) { 453 ret = hns3_set_port_vlan_filter(hns, vlan_id, on); 454 writen_to_tbl = true; 455 } 456 457 if (ret == 0) { 458 if (on) 459 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl); 460 else 461 hns3_rm_dev_vlan_table(hns, vlan_id); 462 } 463 return ret; 464 } 465 466 static int 467 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 468 { 469 struct hns3_adapter *hns = dev->data->dev_private; 470 struct hns3_hw *hw = &hns->hw; 471 int ret; 472 473 rte_spinlock_lock(&hw->lock); 474 ret = hns3_vlan_filter_configure(hns, vlan_id, on); 475 rte_spinlock_unlock(&hw->lock); 476 return ret; 477 } 478 479 static int 480 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type, 481 uint16_t tpid) 482 { 483 struct hns3_rx_vlan_type_cfg_cmd *rx_req; 484 struct hns3_tx_vlan_type_cfg_cmd *tx_req; 485 struct hns3_hw *hw = &hns->hw; 486 struct hns3_cmd_desc desc; 487 int ret; 488 489 if ((vlan_type != RTE_ETH_VLAN_TYPE_INNER && 490 vlan_type != RTE_ETH_VLAN_TYPE_OUTER)) { 491 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type); 492 return -EINVAL; 493 } 494 495 if (tpid != RTE_ETHER_TYPE_VLAN) { 496 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type); 497 return -EINVAL; 498 } 499 500 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false); 501 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data; 502 503 if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER) { 504 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid); 505 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid); 506 } else if (vlan_type == RTE_ETH_VLAN_TYPE_INNER) { 507 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid); 508 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid); 509 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid); 510 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid); 511 } 512 513 ret = hns3_cmd_send(hw, &desc, 1); 514 if (ret) { 515 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d", 516 ret); 517 return ret; 518 } 519 520 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false); 521 522 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data; 523 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid); 524 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid); 525 526 ret = hns3_cmd_send(hw, &desc, 1); 527 if (ret) 528 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d", 529 ret); 530 return ret; 531 } 532 533 static int 534 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, 535 uint16_t tpid) 536 { 537 struct hns3_adapter *hns = dev->data->dev_private; 538 struct hns3_hw *hw = &hns->hw; 539 int ret; 540 541 rte_spinlock_lock(&hw->lock); 542 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid); 543 rte_spinlock_unlock(&hw->lock); 544 return ret; 545 } 546 547 static int 548 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns, 549 struct hns3_rx_vtag_cfg *vcfg) 550 { 551 struct hns3_vport_vtag_rx_cfg_cmd *req; 552 struct hns3_hw *hw = &hns->hw; 553 struct hns3_cmd_desc desc; 554 uint16_t vport_id; 555 uint8_t bitmap; 556 int ret; 557 558 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false); 559 560 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data; 561 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B, 562 vcfg->strip_tag1_en ? 1 : 0); 563 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B, 564 vcfg->strip_tag2_en ? 1 : 0); 565 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B, 566 vcfg->vlan1_vlan_prionly ? 1 : 0); 567 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B, 568 vcfg->vlan2_vlan_prionly ? 1 : 0); 569 570 /* firmware will ignore this configuration for PCI_REVISION_ID_HIP08 */ 571 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B, 572 vcfg->strip_tag1_discard_en ? 1 : 0); 573 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B, 574 vcfg->strip_tag2_discard_en ? 1 : 0); 575 /* 576 * In current version VF is not supported when PF is driven by DPDK 577 * driver, just need to configure parameters for PF vport. 578 */ 579 vport_id = HNS3_PF_FUNC_ID; 580 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD; 581 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE); 582 req->vf_bitmap[req->vf_offset] = bitmap; 583 584 ret = hns3_cmd_send(hw, &desc, 1); 585 if (ret) 586 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret); 587 return ret; 588 } 589 590 static int 591 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable) 592 { 593 struct hns3_rx_vtag_cfg rxvlan_cfg; 594 struct hns3_hw *hw = &hns->hw; 595 int ret; 596 597 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) { 598 rxvlan_cfg.strip_tag1_en = false; 599 rxvlan_cfg.strip_tag2_en = enable; 600 rxvlan_cfg.strip_tag2_discard_en = false; 601 } else { 602 rxvlan_cfg.strip_tag1_en = enable; 603 rxvlan_cfg.strip_tag2_en = true; 604 rxvlan_cfg.strip_tag2_discard_en = true; 605 } 606 607 rxvlan_cfg.strip_tag1_discard_en = false; 608 rxvlan_cfg.vlan1_vlan_prionly = false; 609 rxvlan_cfg.vlan2_vlan_prionly = false; 610 rxvlan_cfg.rx_vlan_offload_en = enable; 611 612 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg); 613 if (ret) { 614 hns3_err(hw, "%s strip rx vtag failed, ret = %d.", 615 enable ? "enable" : "disable", ret); 616 return ret; 617 } 618 619 memcpy(&hns->pf.vtag_config.rx_vcfg, &rxvlan_cfg, 620 sizeof(struct hns3_rx_vtag_cfg)); 621 622 return ret; 623 } 624 625 static int 626 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type, 627 uint8_t fe_type, bool filter_en, uint8_t vf_id) 628 { 629 struct hns3_vlan_filter_ctrl_cmd *req; 630 struct hns3_cmd_desc desc; 631 int ret; 632 633 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false); 634 635 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data; 636 req->vlan_type = vlan_type; 637 req->vlan_fe = filter_en ? fe_type : 0; 638 req->vf_id = vf_id; 639 640 ret = hns3_cmd_send(hw, &desc, 1); 641 if (ret) 642 hns3_err(hw, "set vlan filter fail, ret =%d", ret); 643 644 return ret; 645 } 646 647 static int 648 hns3_vlan_filter_init(struct hns3_adapter *hns) 649 { 650 struct hns3_hw *hw = &hns->hw; 651 int ret; 652 653 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF, 654 HNS3_FILTER_FE_EGRESS, false, 655 HNS3_PF_FUNC_ID); 656 if (ret) { 657 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret); 658 return ret; 659 } 660 661 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT, 662 HNS3_FILTER_FE_INGRESS, false, 663 HNS3_PF_FUNC_ID); 664 if (ret) 665 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret); 666 667 return ret; 668 } 669 670 static int 671 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable) 672 { 673 struct hns3_hw *hw = &hns->hw; 674 int ret; 675 676 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT, 677 HNS3_FILTER_FE_INGRESS, enable, 678 HNS3_PF_FUNC_ID); 679 if (ret) 680 hns3_err(hw, "failed to %s port vlan filter, ret = %d", 681 enable ? "enable" : "disable", ret); 682 683 return ret; 684 } 685 686 static int 687 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask) 688 { 689 struct hns3_adapter *hns = dev->data->dev_private; 690 struct hns3_hw *hw = &hns->hw; 691 struct rte_eth_rxmode *rxmode; 692 unsigned int tmp_mask; 693 bool enable; 694 int ret = 0; 695 696 rte_spinlock_lock(&hw->lock); 697 rxmode = &dev->data->dev_conf.rxmode; 698 tmp_mask = (unsigned int)mask; 699 if (tmp_mask & RTE_ETH_VLAN_FILTER_MASK) { 700 /* ignore vlan filter configuration during promiscuous mode */ 701 if (!dev->data->promiscuous) { 702 /* Enable or disable VLAN filter */ 703 enable = rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER ? 704 true : false; 705 706 ret = hns3_enable_vlan_filter(hns, enable); 707 if (ret) { 708 rte_spinlock_unlock(&hw->lock); 709 hns3_err(hw, "failed to %s rx filter, ret = %d", 710 enable ? "enable" : "disable", ret); 711 return ret; 712 } 713 } 714 } 715 716 if (tmp_mask & RTE_ETH_VLAN_STRIP_MASK) { 717 /* Enable or disable VLAN stripping */ 718 enable = rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP ? 719 true : false; 720 721 ret = hns3_en_hw_strip_rxvtag(hns, enable); 722 if (ret) { 723 rte_spinlock_unlock(&hw->lock); 724 hns3_err(hw, "failed to %s rx strip, ret = %d", 725 enable ? "enable" : "disable", ret); 726 return ret; 727 } 728 } 729 730 rte_spinlock_unlock(&hw->lock); 731 732 return ret; 733 } 734 735 static int 736 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns, 737 struct hns3_tx_vtag_cfg *vcfg) 738 { 739 struct hns3_vport_vtag_tx_cfg_cmd *req; 740 struct hns3_cmd_desc desc; 741 struct hns3_hw *hw = &hns->hw; 742 uint16_t vport_id; 743 uint8_t bitmap; 744 int ret; 745 746 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false); 747 748 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data; 749 req->def_vlan_tag1 = vcfg->default_tag1; 750 req->def_vlan_tag2 = vcfg->default_tag2; 751 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B, 752 vcfg->accept_tag1 ? 1 : 0); 753 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B, 754 vcfg->accept_untag1 ? 1 : 0); 755 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B, 756 vcfg->accept_tag2 ? 1 : 0); 757 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B, 758 vcfg->accept_untag2 ? 1 : 0); 759 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B, 760 vcfg->insert_tag1_en ? 1 : 0); 761 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B, 762 vcfg->insert_tag2_en ? 1 : 0); 763 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0); 764 765 /* firmware will ignore this configuration for PCI_REVISION_ID_HIP08 */ 766 hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B, 767 vcfg->tag_shift_mode_en ? 1 : 0); 768 769 /* 770 * In current version VF is not supported when PF is driven by DPDK 771 * driver, just need to configure parameters for PF vport. 772 */ 773 vport_id = HNS3_PF_FUNC_ID; 774 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD; 775 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE); 776 req->vf_bitmap[req->vf_offset] = bitmap; 777 778 ret = hns3_cmd_send(hw, &desc, 1); 779 if (ret) 780 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret); 781 782 return ret; 783 } 784 785 static int 786 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state, 787 uint16_t pvid) 788 { 789 struct hns3_hw *hw = &hns->hw; 790 struct hns3_tx_vtag_cfg txvlan_cfg; 791 int ret; 792 793 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) { 794 txvlan_cfg.accept_tag1 = true; 795 txvlan_cfg.insert_tag1_en = false; 796 txvlan_cfg.default_tag1 = 0; 797 } else { 798 txvlan_cfg.accept_tag1 = 799 hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE; 800 txvlan_cfg.insert_tag1_en = true; 801 txvlan_cfg.default_tag1 = pvid; 802 } 803 804 txvlan_cfg.accept_untag1 = true; 805 txvlan_cfg.accept_tag2 = true; 806 txvlan_cfg.accept_untag2 = true; 807 txvlan_cfg.insert_tag2_en = false; 808 txvlan_cfg.default_tag2 = 0; 809 txvlan_cfg.tag_shift_mode_en = true; 810 811 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg); 812 if (ret) { 813 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid, 814 ret); 815 return ret; 816 } 817 818 memcpy(&hns->pf.vtag_config.tx_vcfg, &txvlan_cfg, 819 sizeof(struct hns3_tx_vtag_cfg)); 820 821 return ret; 822 } 823 824 825 static void 826 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list) 827 { 828 struct hns3_user_vlan_table *vlan_entry; 829 struct hns3_pf *pf = &hns->pf; 830 831 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 832 if (vlan_entry->hd_tbl_status) { 833 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0); 834 vlan_entry->hd_tbl_status = false; 835 } 836 } 837 838 if (is_del_list) { 839 vlan_entry = LIST_FIRST(&pf->vlan_list); 840 while (vlan_entry) { 841 LIST_REMOVE(vlan_entry, next); 842 rte_free(vlan_entry); 843 vlan_entry = LIST_FIRST(&pf->vlan_list); 844 } 845 } 846 } 847 848 static void 849 hns3_add_all_vlan_table(struct hns3_adapter *hns) 850 { 851 struct hns3_user_vlan_table *vlan_entry; 852 struct hns3_pf *pf = &hns->pf; 853 854 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 855 if (!vlan_entry->hd_tbl_status) { 856 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1); 857 vlan_entry->hd_tbl_status = true; 858 } 859 } 860 } 861 862 static void 863 hns3_remove_all_vlan_table(struct hns3_adapter *hns) 864 { 865 struct hns3_hw *hw = &hns->hw; 866 int ret; 867 868 hns3_rm_all_vlan_table(hns, true); 869 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) { 870 ret = hns3_set_port_vlan_filter(hns, 871 hw->port_base_vlan_cfg.pvid, 0); 872 if (ret) { 873 hns3_err(hw, "Failed to remove all vlan table, ret =%d", 874 ret); 875 return; 876 } 877 } 878 } 879 880 static int 881 hns3_update_vlan_filter_entries(struct hns3_adapter *hns, 882 uint16_t port_base_vlan_state, uint16_t new_pvid) 883 { 884 struct hns3_hw *hw = &hns->hw; 885 uint16_t old_pvid; 886 int ret; 887 888 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) { 889 old_pvid = hw->port_base_vlan_cfg.pvid; 890 if (old_pvid != HNS3_INVALID_PVID) { 891 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0); 892 if (ret) { 893 hns3_err(hw, "failed to remove old pvid %u, " 894 "ret = %d", old_pvid, ret); 895 return ret; 896 } 897 } 898 899 hns3_rm_all_vlan_table(hns, false); 900 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1); 901 if (ret) { 902 hns3_err(hw, "failed to add new pvid %u, ret = %d", 903 new_pvid, ret); 904 return ret; 905 } 906 } else { 907 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0); 908 if (ret) { 909 hns3_err(hw, "failed to remove pvid %u, ret = %d", 910 new_pvid, ret); 911 return ret; 912 } 913 914 hns3_add_all_vlan_table(hns); 915 } 916 return 0; 917 } 918 919 static int 920 hns3_en_pvid_strip(struct hns3_adapter *hns, int on) 921 { 922 struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg; 923 struct hns3_rx_vtag_cfg rx_vlan_cfg; 924 bool rx_strip_en; 925 int ret; 926 927 rx_strip_en = old_cfg->rx_vlan_offload_en; 928 if (on) { 929 rx_vlan_cfg.strip_tag1_en = rx_strip_en; 930 rx_vlan_cfg.strip_tag2_en = true; 931 rx_vlan_cfg.strip_tag2_discard_en = true; 932 } else { 933 rx_vlan_cfg.strip_tag1_en = false; 934 rx_vlan_cfg.strip_tag2_en = rx_strip_en; 935 rx_vlan_cfg.strip_tag2_discard_en = false; 936 } 937 rx_vlan_cfg.strip_tag1_discard_en = false; 938 rx_vlan_cfg.vlan1_vlan_prionly = false; 939 rx_vlan_cfg.vlan2_vlan_prionly = false; 940 rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en; 941 942 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg); 943 if (ret) 944 return ret; 945 946 memcpy(&hns->pf.vtag_config.rx_vcfg, &rx_vlan_cfg, 947 sizeof(struct hns3_rx_vtag_cfg)); 948 949 return ret; 950 } 951 952 static int 953 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on) 954 { 955 struct hns3_hw *hw = &hns->hw; 956 uint16_t port_base_vlan_state; 957 int ret, err; 958 959 if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) { 960 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) 961 hns3_warn(hw, "Invalid operation! As current pvid set " 962 "is %u, disable pvid %u is invalid", 963 hw->port_base_vlan_cfg.pvid, pvid); 964 return 0; 965 } 966 967 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE : 968 HNS3_PORT_BASE_VLAN_DISABLE; 969 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid); 970 if (ret) { 971 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d", 972 ret); 973 return ret; 974 } 975 976 ret = hns3_en_pvid_strip(hns, on); 977 if (ret) { 978 hns3_err(hw, "failed to config rx vlan strip for pvid, " 979 "ret = %d", ret); 980 goto pvid_vlan_strip_fail; 981 } 982 983 if (pvid == HNS3_INVALID_PVID) 984 goto out; 985 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid); 986 if (ret) { 987 hns3_err(hw, "failed to update vlan filter entries, ret = %d", 988 ret); 989 goto vlan_filter_set_fail; 990 } 991 992 out: 993 hw->port_base_vlan_cfg.state = port_base_vlan_state; 994 hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID; 995 return ret; 996 997 vlan_filter_set_fail: 998 err = hns3_en_pvid_strip(hns, hw->port_base_vlan_cfg.state == 999 HNS3_PORT_BASE_VLAN_ENABLE); 1000 if (err) 1001 hns3_err(hw, "fail to rollback pvid strip, ret = %d", err); 1002 1003 pvid_vlan_strip_fail: 1004 err = hns3_vlan_txvlan_cfg(hns, hw->port_base_vlan_cfg.state, 1005 hw->port_base_vlan_cfg.pvid); 1006 if (err) 1007 hns3_err(hw, "fail to rollback txvlan status, ret = %d", err); 1008 1009 return ret; 1010 } 1011 1012 static int 1013 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on) 1014 { 1015 struct hns3_adapter *hns = dev->data->dev_private; 1016 struct hns3_hw *hw = &hns->hw; 1017 bool pvid_en_state_change; 1018 uint16_t pvid_state; 1019 int ret; 1020 1021 if (pvid > RTE_ETHER_MAX_VLAN_ID) { 1022 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid, 1023 RTE_ETHER_MAX_VLAN_ID); 1024 return -EINVAL; 1025 } 1026 1027 /* 1028 * If PVID configuration state change, should refresh the PVID 1029 * configuration state in struct hns3_tx_queue/hns3_rx_queue. 1030 */ 1031 pvid_state = hw->port_base_vlan_cfg.state; 1032 if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) || 1033 (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE)) 1034 pvid_en_state_change = false; 1035 else 1036 pvid_en_state_change = true; 1037 1038 rte_spinlock_lock(&hw->lock); 1039 ret = hns3_vlan_pvid_configure(hns, pvid, on); 1040 rte_spinlock_unlock(&hw->lock); 1041 if (ret) 1042 return ret; 1043 /* 1044 * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx 1045 * need be processed by PMD. 1046 */ 1047 if (pvid_en_state_change && 1048 hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE) 1049 hns3_update_all_queues_pvid_proc_en(hw); 1050 1051 return 0; 1052 } 1053 1054 static int 1055 hns3_default_vlan_config(struct hns3_adapter *hns) 1056 { 1057 struct hns3_hw *hw = &hns->hw; 1058 int ret; 1059 1060 /* 1061 * When vlan filter is enabled, hardware regards packets without vlan 1062 * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan 1063 * table, packets without vlan won't be received. So, add vlan 0 as 1064 * the default vlan. 1065 */ 1066 ret = hns3_vlan_filter_configure(hns, 0, 1); 1067 if (ret) 1068 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret); 1069 return ret; 1070 } 1071 1072 static int 1073 hns3_init_vlan_config(struct hns3_adapter *hns) 1074 { 1075 struct hns3_hw *hw = &hns->hw; 1076 int ret; 1077 1078 /* 1079 * This function can be called in the initialization and reset process, 1080 * when in reset process, it means that hardware had been reseted 1081 * successfully and we need to restore the hardware configuration to 1082 * ensure that the hardware configuration remains unchanged before and 1083 * after reset. 1084 */ 1085 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) { 1086 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE; 1087 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID; 1088 } 1089 1090 ret = hns3_vlan_filter_init(hns); 1091 if (ret) { 1092 hns3_err(hw, "vlan init fail in pf, ret =%d", ret); 1093 return ret; 1094 } 1095 1096 ret = hns3_vlan_tpid_configure(hns, RTE_ETH_VLAN_TYPE_INNER, 1097 RTE_ETHER_TYPE_VLAN); 1098 if (ret) { 1099 hns3_err(hw, "tpid set fail in pf, ret =%d", ret); 1100 return ret; 1101 } 1102 1103 /* 1104 * When in the reinit dev stage of the reset process, the following 1105 * vlan-related configurations may differ from those at initialization, 1106 * we will restore configurations to hardware in hns3_restore_vlan_table 1107 * and hns3_restore_vlan_conf later. 1108 */ 1109 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) { 1110 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0); 1111 if (ret) { 1112 hns3_err(hw, "pvid set fail in pf, ret =%d", ret); 1113 return ret; 1114 } 1115 1116 ret = hns3_en_hw_strip_rxvtag(hns, false); 1117 if (ret) { 1118 hns3_err(hw, "rx strip configure fail in pf, ret =%d", 1119 ret); 1120 return ret; 1121 } 1122 } 1123 1124 return hns3_default_vlan_config(hns); 1125 } 1126 1127 static int 1128 hns3_restore_vlan_conf(struct hns3_adapter *hns) 1129 { 1130 struct hns3_pf *pf = &hns->pf; 1131 struct hns3_hw *hw = &hns->hw; 1132 uint64_t offloads; 1133 bool enable; 1134 int ret; 1135 1136 if (!hw->data->promiscuous) { 1137 /* restore vlan filter states */ 1138 offloads = hw->data->dev_conf.rxmode.offloads; 1139 enable = offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER ? true : false; 1140 ret = hns3_enable_vlan_filter(hns, enable); 1141 if (ret) { 1142 hns3_err(hw, "failed to restore vlan rx filter conf, " 1143 "ret = %d", ret); 1144 return ret; 1145 } 1146 } 1147 1148 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg); 1149 if (ret) { 1150 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret); 1151 return ret; 1152 } 1153 1154 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg); 1155 if (ret) 1156 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret); 1157 1158 return ret; 1159 } 1160 1161 static int 1162 hns3_dev_configure_vlan(struct rte_eth_dev *dev) 1163 { 1164 struct hns3_adapter *hns = dev->data->dev_private; 1165 struct rte_eth_dev_data *data = dev->data; 1166 struct rte_eth_txmode *txmode; 1167 struct hns3_hw *hw = &hns->hw; 1168 int mask; 1169 int ret; 1170 1171 txmode = &data->dev_conf.txmode; 1172 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged) 1173 hns3_warn(hw, 1174 "hw_vlan_reject_tagged or hw_vlan_reject_untagged " 1175 "configuration is not supported! Ignore these two " 1176 "parameters: hw_vlan_reject_tagged(%u), " 1177 "hw_vlan_reject_untagged(%u)", 1178 txmode->hw_vlan_reject_tagged, 1179 txmode->hw_vlan_reject_untagged); 1180 1181 /* Apply vlan offload setting */ 1182 mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK; 1183 ret = hns3_vlan_offload_set(dev, mask); 1184 if (ret) { 1185 hns3_err(hw, "dev config rx vlan offload failed, ret = %d", 1186 ret); 1187 return ret; 1188 } 1189 1190 /* 1191 * If pvid config is not set in rte_eth_conf, driver needn't to set 1192 * VLAN pvid related configuration to hardware. 1193 */ 1194 if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0) 1195 return 0; 1196 1197 /* Apply pvid setting */ 1198 ret = hns3_vlan_pvid_set(dev, txmode->pvid, 1199 txmode->hw_vlan_insert_pvid); 1200 if (ret) 1201 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d", 1202 txmode->pvid, ret); 1203 1204 return ret; 1205 } 1206 1207 static int 1208 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min, 1209 unsigned int tso_mss_max) 1210 { 1211 struct hns3_cfg_tso_status_cmd *req; 1212 struct hns3_cmd_desc desc; 1213 uint16_t tso_mss; 1214 1215 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false); 1216 1217 req = (struct hns3_cfg_tso_status_cmd *)desc.data; 1218 1219 tso_mss = 0; 1220 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S, 1221 tso_mss_min); 1222 req->tso_mss_min = rte_cpu_to_le_16(tso_mss); 1223 1224 tso_mss = 0; 1225 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S, 1226 tso_mss_max); 1227 req->tso_mss_max = rte_cpu_to_le_16(tso_mss); 1228 1229 return hns3_cmd_send(hw, &desc, 1); 1230 } 1231 1232 static int 1233 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size, 1234 uint16_t *allocated_size, bool is_alloc) 1235 { 1236 struct hns3_umv_spc_alc_cmd *req; 1237 struct hns3_cmd_desc desc; 1238 int ret; 1239 1240 req = (struct hns3_umv_spc_alc_cmd *)desc.data; 1241 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false); 1242 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1); 1243 req->space_size = rte_cpu_to_le_32(space_size); 1244 1245 ret = hns3_cmd_send(hw, &desc, 1); 1246 if (ret) { 1247 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d", 1248 is_alloc ? "allocate" : "free", ret); 1249 return ret; 1250 } 1251 1252 if (is_alloc && allocated_size) 1253 *allocated_size = rte_le_to_cpu_32(desc.data[1]); 1254 1255 return 0; 1256 } 1257 1258 static int 1259 hns3_init_umv_space(struct hns3_hw *hw) 1260 { 1261 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1262 struct hns3_pf *pf = &hns->pf; 1263 uint16_t allocated_size = 0; 1264 int ret; 1265 1266 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size, 1267 true); 1268 if (ret) 1269 return ret; 1270 1271 if (allocated_size < pf->wanted_umv_size) 1272 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u", 1273 pf->wanted_umv_size, allocated_size); 1274 1275 pf->max_umv_size = (!!allocated_size) ? allocated_size : 1276 pf->wanted_umv_size; 1277 pf->used_umv_size = 0; 1278 return 0; 1279 } 1280 1281 static int 1282 hns3_uninit_umv_space(struct hns3_hw *hw) 1283 { 1284 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1285 struct hns3_pf *pf = &hns->pf; 1286 int ret; 1287 1288 if (pf->max_umv_size == 0) 1289 return 0; 1290 1291 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false); 1292 if (ret) 1293 return ret; 1294 1295 pf->max_umv_size = 0; 1296 1297 return 0; 1298 } 1299 1300 static bool 1301 hns3_is_umv_space_full(struct hns3_hw *hw) 1302 { 1303 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1304 struct hns3_pf *pf = &hns->pf; 1305 bool is_full; 1306 1307 is_full = (pf->used_umv_size >= pf->max_umv_size); 1308 1309 return is_full; 1310 } 1311 1312 static void 1313 hns3_update_umv_space(struct hns3_hw *hw, bool is_free) 1314 { 1315 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1316 struct hns3_pf *pf = &hns->pf; 1317 1318 if (is_free) { 1319 if (pf->used_umv_size > 0) 1320 pf->used_umv_size--; 1321 } else 1322 pf->used_umv_size++; 1323 } 1324 1325 static void 1326 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req, 1327 const uint8_t *addr, bool is_mc) 1328 { 1329 const unsigned char *mac_addr = addr; 1330 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) | 1331 ((uint32_t)mac_addr[2] << 16) | 1332 ((uint32_t)mac_addr[1] << 8) | 1333 (uint32_t)mac_addr[0]; 1334 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4]; 1335 1336 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1); 1337 if (is_mc) { 1338 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1339 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1); 1340 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1); 1341 } 1342 1343 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val); 1344 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff); 1345 } 1346 1347 static int 1348 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp, 1349 uint8_t resp_code, 1350 enum hns3_mac_vlan_tbl_opcode op) 1351 { 1352 if (cmdq_resp) { 1353 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u", 1354 cmdq_resp); 1355 return -EIO; 1356 } 1357 1358 if (op == HNS3_MAC_VLAN_ADD) { 1359 if (resp_code == 0 || resp_code == 1) { 1360 return 0; 1361 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) { 1362 hns3_err(hw, "add mac addr failed for uc_overflow"); 1363 return -ENOSPC; 1364 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) { 1365 hns3_err(hw, "add mac addr failed for mc_overflow"); 1366 return -ENOSPC; 1367 } 1368 1369 hns3_err(hw, "add mac addr failed for undefined, code=%u", 1370 resp_code); 1371 return -EIO; 1372 } else if (op == HNS3_MAC_VLAN_REMOVE) { 1373 if (resp_code == 0) { 1374 return 0; 1375 } else if (resp_code == 1) { 1376 hns3_dbg(hw, "remove mac addr failed for miss"); 1377 return -ENOENT; 1378 } 1379 1380 hns3_err(hw, "remove mac addr failed for undefined, code=%u", 1381 resp_code); 1382 return -EIO; 1383 } else if (op == HNS3_MAC_VLAN_LKUP) { 1384 if (resp_code == 0) { 1385 return 0; 1386 } else if (resp_code == 1) { 1387 hns3_dbg(hw, "lookup mac addr failed for miss"); 1388 return -ENOENT; 1389 } 1390 1391 hns3_err(hw, "lookup mac addr failed for undefined, code=%u", 1392 resp_code); 1393 return -EIO; 1394 } 1395 1396 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u", 1397 op); 1398 1399 return -EINVAL; 1400 } 1401 1402 static int 1403 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw, 1404 struct hns3_mac_vlan_tbl_entry_cmd *req, 1405 struct hns3_cmd_desc *desc, uint8_t desc_num) 1406 { 1407 uint8_t resp_code; 1408 uint16_t retval; 1409 int ret; 1410 int i; 1411 1412 if (desc_num == HNS3_MC_MAC_VLAN_OPS_DESC_NUM) { 1413 for (i = 0; i < desc_num - 1; i++) { 1414 hns3_cmd_setup_basic_desc(&desc[i], 1415 HNS3_OPC_MAC_VLAN_ADD, true); 1416 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1417 if (i == 0) 1418 memcpy(desc[i].data, req, 1419 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1420 } 1421 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_MAC_VLAN_ADD, 1422 true); 1423 } else { 1424 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, 1425 true); 1426 memcpy(desc[0].data, req, 1427 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1428 } 1429 ret = hns3_cmd_send(hw, desc, desc_num); 1430 if (ret) { 1431 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.", 1432 ret); 1433 return ret; 1434 } 1435 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff; 1436 retval = rte_le_to_cpu_16(desc[0].retval); 1437 1438 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1439 HNS3_MAC_VLAN_LKUP); 1440 } 1441 1442 static int 1443 hns3_add_mac_vlan_tbl(struct hns3_hw *hw, 1444 struct hns3_mac_vlan_tbl_entry_cmd *req, 1445 struct hns3_cmd_desc *desc, uint8_t desc_num) 1446 { 1447 uint8_t resp_code; 1448 uint16_t retval; 1449 int cfg_status; 1450 int ret; 1451 int i; 1452 1453 if (desc_num == HNS3_UC_MAC_VLAN_OPS_DESC_NUM) { 1454 hns3_cmd_setup_basic_desc(desc, HNS3_OPC_MAC_VLAN_ADD, false); 1455 memcpy(desc->data, req, 1456 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1457 ret = hns3_cmd_send(hw, desc, desc_num); 1458 resp_code = (rte_le_to_cpu_32(desc->data[0]) >> 8) & 0xff; 1459 retval = rte_le_to_cpu_16(desc->retval); 1460 1461 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1462 HNS3_MAC_VLAN_ADD); 1463 } else { 1464 for (i = 0; i < desc_num; i++) { 1465 hns3_cmd_reuse_desc(&desc[i], false); 1466 if (i == desc_num - 1) 1467 desc[i].flag &= 1468 rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT); 1469 else 1470 desc[i].flag |= 1471 rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1472 } 1473 memcpy(desc[0].data, req, 1474 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1475 desc[0].retval = 0; 1476 ret = hns3_cmd_send(hw, desc, desc_num); 1477 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff; 1478 retval = rte_le_to_cpu_16(desc[0].retval); 1479 1480 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1481 HNS3_MAC_VLAN_ADD); 1482 } 1483 1484 if (ret) { 1485 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret); 1486 return ret; 1487 } 1488 1489 return cfg_status; 1490 } 1491 1492 static int 1493 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw, 1494 struct hns3_mac_vlan_tbl_entry_cmd *req) 1495 { 1496 struct hns3_cmd_desc desc; 1497 uint8_t resp_code; 1498 uint16_t retval; 1499 int ret; 1500 1501 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false); 1502 1503 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1504 1505 ret = hns3_cmd_send(hw, &desc, 1); 1506 if (ret) { 1507 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret); 1508 return ret; 1509 } 1510 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff; 1511 retval = rte_le_to_cpu_16(desc.retval); 1512 1513 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1514 HNS3_MAC_VLAN_REMOVE); 1515 } 1516 1517 static int 1518 hns3_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1519 { 1520 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1521 struct hns3_mac_vlan_tbl_entry_cmd req; 1522 struct hns3_pf *pf = &hns->pf; 1523 struct hns3_cmd_desc desc; 1524 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1525 uint16_t egress_port = 0; 1526 uint8_t vf_id; 1527 int ret; 1528 1529 /* check if mac addr is valid */ 1530 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 1531 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1532 mac_addr); 1533 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid", 1534 mac_str); 1535 return -EINVAL; 1536 } 1537 1538 memset(&req, 0, sizeof(req)); 1539 1540 /* 1541 * In current version VF is not supported when PF is driven by DPDK 1542 * driver, just need to configure parameters for PF vport. 1543 */ 1544 vf_id = HNS3_PF_FUNC_ID; 1545 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M, 1546 HNS3_MAC_EPORT_VFID_S, vf_id); 1547 1548 req.egress_port = rte_cpu_to_le_16(egress_port); 1549 1550 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false); 1551 1552 /* 1553 * Lookup the mac address in the mac_vlan table, and add 1554 * it if the entry is inexistent. Repeated unicast entry 1555 * is not allowed in the mac vlan table. 1556 */ 1557 ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, 1558 HNS3_UC_MAC_VLAN_OPS_DESC_NUM); 1559 if (ret == -ENOENT) { 1560 if (!hns3_is_umv_space_full(hw)) { 1561 ret = hns3_add_mac_vlan_tbl(hw, &req, &desc, 1562 HNS3_UC_MAC_VLAN_OPS_DESC_NUM); 1563 if (!ret) 1564 hns3_update_umv_space(hw, false); 1565 return ret; 1566 } 1567 1568 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size); 1569 1570 return -ENOSPC; 1571 } 1572 1573 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr); 1574 1575 /* check if we just hit the duplicate */ 1576 if (ret == 0) { 1577 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str); 1578 return 0; 1579 } 1580 1581 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table", 1582 mac_str); 1583 1584 return ret; 1585 } 1586 1587 static int 1588 hns3_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1589 { 1590 struct hns3_mac_vlan_tbl_entry_cmd req; 1591 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1592 int ret; 1593 1594 /* check if mac addr is valid */ 1595 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 1596 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1597 mac_addr); 1598 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid", 1599 mac_str); 1600 return -EINVAL; 1601 } 1602 1603 memset(&req, 0, sizeof(req)); 1604 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1605 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false); 1606 ret = hns3_remove_mac_vlan_tbl(hw, &req); 1607 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */ 1608 return 0; 1609 else if (ret == 0) 1610 hns3_update_umv_space(hw, true); 1611 1612 return ret; 1613 } 1614 1615 static int 1616 hns3_set_default_mac_addr(struct rte_eth_dev *dev, 1617 struct rte_ether_addr *mac_addr) 1618 { 1619 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1620 struct rte_ether_addr *oaddr; 1621 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1622 int ret, ret_val; 1623 1624 rte_spinlock_lock(&hw->lock); 1625 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr; 1626 ret = hw->ops.del_uc_mac_addr(hw, oaddr); 1627 if (ret) { 1628 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1629 oaddr); 1630 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d", 1631 mac_str, ret); 1632 1633 rte_spinlock_unlock(&hw->lock); 1634 return ret; 1635 } 1636 1637 ret = hw->ops.add_uc_mac_addr(hw, mac_addr); 1638 if (ret) { 1639 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1640 mac_addr); 1641 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret); 1642 goto err_add_uc_addr; 1643 } 1644 1645 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes); 1646 if (ret) { 1647 hns3_err(hw, "Failed to configure mac pause address: %d", ret); 1648 goto err_pause_addr_cfg; 1649 } 1650 1651 rte_ether_addr_copy(mac_addr, 1652 (struct rte_ether_addr *)hw->mac.mac_addr); 1653 rte_spinlock_unlock(&hw->lock); 1654 1655 return 0; 1656 1657 err_pause_addr_cfg: 1658 ret_val = hw->ops.del_uc_mac_addr(hw, mac_addr); 1659 if (ret_val) { 1660 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1661 mac_addr); 1662 hns3_warn(hw, 1663 "Failed to roll back to del setted mac addr(%s): %d", 1664 mac_str, ret_val); 1665 } 1666 1667 err_add_uc_addr: 1668 ret_val = hw->ops.add_uc_mac_addr(hw, oaddr); 1669 if (ret_val) { 1670 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, oaddr); 1671 hns3_warn(hw, "Failed to restore old uc mac addr(%s): %d", 1672 mac_str, ret_val); 1673 } 1674 rte_spinlock_unlock(&hw->lock); 1675 1676 return ret; 1677 } 1678 1679 static void 1680 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr) 1681 { 1682 #define HNS3_VF_NUM_IN_FIRST_DESC 192 1683 uint8_t word_num; 1684 uint8_t bit_num; 1685 1686 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) { 1687 word_num = vfid / 32; 1688 bit_num = vfid % 32; 1689 if (clr) 1690 desc[1].data[word_num] &= 1691 rte_cpu_to_le_32(~(1UL << bit_num)); 1692 else 1693 desc[1].data[word_num] |= 1694 rte_cpu_to_le_32(1UL << bit_num); 1695 } else { 1696 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32; 1697 bit_num = vfid % 32; 1698 if (clr) 1699 desc[2].data[word_num] &= 1700 rte_cpu_to_le_32(~(1UL << bit_num)); 1701 else 1702 desc[2].data[word_num] |= 1703 rte_cpu_to_le_32(1UL << bit_num); 1704 } 1705 } 1706 1707 static int 1708 hns3_add_mc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1709 { 1710 struct hns3_cmd_desc desc[HNS3_MC_MAC_VLAN_OPS_DESC_NUM]; 1711 struct hns3_mac_vlan_tbl_entry_cmd req; 1712 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1713 uint8_t vf_id; 1714 int ret; 1715 1716 /* Check if mac addr is valid */ 1717 if (!rte_is_multicast_ether_addr(mac_addr)) { 1718 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1719 mac_addr); 1720 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid", 1721 mac_str); 1722 return -EINVAL; 1723 } 1724 1725 memset(&req, 0, sizeof(req)); 1726 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1727 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true); 1728 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, 1729 HNS3_MC_MAC_VLAN_OPS_DESC_NUM); 1730 if (ret) { 1731 /* This mac addr do not exist, add new entry for it */ 1732 memset(desc[0].data, 0, sizeof(desc[0].data)); 1733 memset(desc[1].data, 0, sizeof(desc[0].data)); 1734 memset(desc[2].data, 0, sizeof(desc[0].data)); 1735 } 1736 1737 /* 1738 * In current version VF is not supported when PF is driven by DPDK 1739 * driver, just need to configure parameters for PF vport. 1740 */ 1741 vf_id = HNS3_PF_FUNC_ID; 1742 hns3_update_desc_vfid(desc, vf_id, false); 1743 ret = hns3_add_mac_vlan_tbl(hw, &req, desc, 1744 HNS3_MC_MAC_VLAN_OPS_DESC_NUM); 1745 if (ret) { 1746 if (ret == -ENOSPC) 1747 hns3_err(hw, "mc mac vlan table is full"); 1748 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1749 mac_addr); 1750 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret); 1751 } 1752 1753 return ret; 1754 } 1755 1756 static int 1757 hns3_remove_mc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1758 { 1759 struct hns3_mac_vlan_tbl_entry_cmd req; 1760 struct hns3_cmd_desc desc[3]; 1761 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1762 uint8_t vf_id; 1763 int ret; 1764 1765 /* Check if mac addr is valid */ 1766 if (!rte_is_multicast_ether_addr(mac_addr)) { 1767 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1768 mac_addr); 1769 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid", 1770 mac_str); 1771 return -EINVAL; 1772 } 1773 1774 memset(&req, 0, sizeof(req)); 1775 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1776 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true); 1777 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, 1778 HNS3_MC_MAC_VLAN_OPS_DESC_NUM); 1779 if (ret == 0) { 1780 /* 1781 * This mac addr exist, remove this handle's VFID for it. 1782 * In current version VF is not supported when PF is driven by 1783 * DPDK driver, just need to configure parameters for PF vport. 1784 */ 1785 vf_id = HNS3_PF_FUNC_ID; 1786 hns3_update_desc_vfid(desc, vf_id, true); 1787 1788 /* All the vfid is zero, so need to delete this entry */ 1789 ret = hns3_remove_mac_vlan_tbl(hw, &req); 1790 } else if (ret == -ENOENT) { 1791 /* This mac addr doesn't exist. */ 1792 return 0; 1793 } 1794 1795 if (ret) { 1796 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1797 mac_addr); 1798 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret); 1799 } 1800 1801 return ret; 1802 } 1803 1804 static int 1805 hns3_check_mq_mode(struct rte_eth_dev *dev) 1806 { 1807 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode; 1808 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode; 1809 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1810 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1811 struct rte_eth_dcb_rx_conf *dcb_rx_conf; 1812 struct rte_eth_dcb_tx_conf *dcb_tx_conf; 1813 uint8_t num_tc; 1814 int max_tc = 0; 1815 int i; 1816 1817 if (((uint32_t)rx_mq_mode & RTE_ETH_MQ_RX_VMDQ_FLAG) || 1818 (tx_mq_mode == RTE_ETH_MQ_TX_VMDQ_DCB || 1819 tx_mq_mode == RTE_ETH_MQ_TX_VMDQ_ONLY)) { 1820 hns3_err(hw, "VMDQ is not supported, rx_mq_mode = %d, tx_mq_mode = %d.", 1821 rx_mq_mode, tx_mq_mode); 1822 return -EOPNOTSUPP; 1823 } 1824 1825 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 1826 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf; 1827 if ((uint32_t)rx_mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) { 1828 if (dcb_rx_conf->nb_tcs > pf->tc_max) { 1829 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.", 1830 dcb_rx_conf->nb_tcs, pf->tc_max); 1831 return -EINVAL; 1832 } 1833 1834 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS || 1835 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) { 1836 hns3_err(hw, "on RTE_ETH_MQ_RX_DCB_RSS mode, " 1837 "nb_tcs(%d) != %d or %d in rx direction.", 1838 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS); 1839 return -EINVAL; 1840 } 1841 1842 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) { 1843 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)", 1844 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs); 1845 return -EINVAL; 1846 } 1847 1848 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) { 1849 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) { 1850 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, " 1851 "is not equal to one in tx direction.", 1852 i, dcb_rx_conf->dcb_tc[i]); 1853 return -EINVAL; 1854 } 1855 if (dcb_rx_conf->dcb_tc[i] > max_tc) 1856 max_tc = dcb_rx_conf->dcb_tc[i]; 1857 } 1858 1859 num_tc = max_tc + 1; 1860 if (num_tc > dcb_rx_conf->nb_tcs) { 1861 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)", 1862 num_tc, dcb_rx_conf->nb_tcs); 1863 return -EINVAL; 1864 } 1865 } 1866 1867 return 0; 1868 } 1869 1870 static int 1871 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en, 1872 enum hns3_ring_type queue_type, uint16_t queue_id) 1873 { 1874 struct hns3_cmd_desc desc; 1875 struct hns3_ctrl_vector_chain_cmd *req = 1876 (struct hns3_ctrl_vector_chain_cmd *)desc.data; 1877 enum hns3_opcode_type op; 1878 uint16_t tqp_type_and_id = 0; 1879 uint16_t type; 1880 uint16_t gl; 1881 int ret; 1882 1883 op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR; 1884 hns3_cmd_setup_basic_desc(&desc, op, false); 1885 req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M, 1886 HNS3_TQP_INT_ID_L_S); 1887 req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M, 1888 HNS3_TQP_INT_ID_H_S); 1889 1890 if (queue_type == HNS3_RING_TYPE_RX) 1891 gl = HNS3_RING_GL_RX; 1892 else 1893 gl = HNS3_RING_GL_TX; 1894 1895 type = queue_type; 1896 1897 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S, 1898 type); 1899 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id); 1900 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S, 1901 gl); 1902 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id); 1903 req->int_cause_num = 1; 1904 ret = hns3_cmd_send(hw, &desc, 1); 1905 if (ret) { 1906 hns3_err(hw, "%s TQP %u fail, vector_id = %u, ret = %d.", 1907 en ? "Map" : "Unmap", queue_id, vector_id, ret); 1908 return ret; 1909 } 1910 1911 return 0; 1912 } 1913 1914 static int 1915 hns3_setup_dcb(struct rte_eth_dev *dev) 1916 { 1917 struct hns3_adapter *hns = dev->data->dev_private; 1918 struct hns3_hw *hw = &hns->hw; 1919 int ret; 1920 1921 if (!hns3_dev_get_support(hw, DCB)) { 1922 hns3_err(hw, "this port does not support dcb configurations."); 1923 return -EOPNOTSUPP; 1924 } 1925 1926 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) { 1927 hns3_err(hw, "MAC pause enabled, cannot config dcb info."); 1928 return -EOPNOTSUPP; 1929 } 1930 1931 ret = hns3_dcb_configure(hns); 1932 if (ret) 1933 hns3_err(hw, "failed to config dcb: %d", ret); 1934 1935 return ret; 1936 } 1937 1938 static int 1939 hns3_check_link_speed(struct hns3_hw *hw, uint32_t link_speeds) 1940 { 1941 int ret; 1942 1943 /* 1944 * Some hardware doesn't support auto-negotiation, but users may not 1945 * configure link_speeds (default 0), which means auto-negotiation. 1946 * In this case, it should return success. 1947 */ 1948 if (link_speeds == RTE_ETH_LINK_SPEED_AUTONEG && 1949 hw->mac.support_autoneg == 0) 1950 return 0; 1951 1952 if (link_speeds != RTE_ETH_LINK_SPEED_AUTONEG) { 1953 ret = hns3_check_port_speed(hw, link_speeds); 1954 if (ret) 1955 return ret; 1956 } 1957 1958 return 0; 1959 } 1960 1961 static int 1962 hns3_check_dev_conf(struct rte_eth_dev *dev) 1963 { 1964 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1965 struct rte_eth_conf *conf = &dev->data->dev_conf; 1966 int ret; 1967 1968 ret = hns3_check_mq_mode(dev); 1969 if (ret) 1970 return ret; 1971 1972 return hns3_check_link_speed(hw, conf->link_speeds); 1973 } 1974 1975 static int 1976 hns3_dev_configure(struct rte_eth_dev *dev) 1977 { 1978 struct hns3_adapter *hns = dev->data->dev_private; 1979 struct rte_eth_conf *conf = &dev->data->dev_conf; 1980 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode; 1981 struct hns3_hw *hw = &hns->hw; 1982 uint16_t nb_rx_q = dev->data->nb_rx_queues; 1983 uint16_t nb_tx_q = dev->data->nb_tx_queues; 1984 struct rte_eth_rss_conf rss_conf; 1985 bool gro_en; 1986 int ret; 1987 1988 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q); 1989 1990 /* 1991 * Some versions of hardware network engine does not support 1992 * individually enable/disable/reset the Tx or Rx queue. These devices 1993 * must enable/disable/reset Tx and Rx queues at the same time. When the 1994 * numbers of Tx queues allocated by upper applications are not equal to 1995 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues 1996 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not 1997 * work as usual. But these fake queues are imperceptible, and can not 1998 * be used by upper applications. 1999 */ 2000 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q); 2001 if (ret) { 2002 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret); 2003 hw->cfg_max_queues = 0; 2004 return ret; 2005 } 2006 2007 hw->adapter_state = HNS3_NIC_CONFIGURING; 2008 ret = hns3_check_dev_conf(dev); 2009 if (ret) 2010 goto cfg_err; 2011 2012 if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) { 2013 ret = hns3_setup_dcb(dev); 2014 if (ret) 2015 goto cfg_err; 2016 } 2017 2018 if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) { 2019 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH; 2020 rss_conf = conf->rx_adv_conf.rss_conf; 2021 ret = hns3_dev_rss_hash_update(dev, &rss_conf); 2022 if (ret) 2023 goto cfg_err; 2024 } 2025 2026 ret = hns3_dev_mtu_set(dev, conf->rxmode.mtu); 2027 if (ret != 0) 2028 goto cfg_err; 2029 2030 ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf); 2031 if (ret) 2032 goto cfg_err; 2033 2034 ret = hns3_dev_configure_vlan(dev); 2035 if (ret) 2036 goto cfg_err; 2037 2038 /* config hardware GRO */ 2039 gro_en = conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO ? true : false; 2040 ret = hns3_config_gro(hw, gro_en); 2041 if (ret) 2042 goto cfg_err; 2043 2044 hns3_init_rx_ptype_tble(dev); 2045 hw->adapter_state = HNS3_NIC_CONFIGURED; 2046 2047 return 0; 2048 2049 cfg_err: 2050 hw->cfg_max_queues = 0; 2051 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0); 2052 hw->adapter_state = HNS3_NIC_INITIALIZED; 2053 2054 return ret; 2055 } 2056 2057 static int 2058 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps) 2059 { 2060 struct hns3_config_max_frm_size_cmd *req; 2061 struct hns3_cmd_desc desc; 2062 2063 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false); 2064 2065 req = (struct hns3_config_max_frm_size_cmd *)desc.data; 2066 req->max_frm_size = rte_cpu_to_le_16(new_mps); 2067 req->min_frm_size = RTE_ETHER_MIN_LEN; 2068 2069 return hns3_cmd_send(hw, &desc, 1); 2070 } 2071 2072 static int 2073 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps) 2074 { 2075 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2076 int err; 2077 int ret; 2078 2079 ret = hns3_set_mac_mtu(hw, mps); 2080 if (ret) { 2081 hns3_err(hw, "failed to set mtu, ret = %d", ret); 2082 return ret; 2083 } 2084 2085 ret = hns3_buffer_alloc(hw); 2086 if (ret) { 2087 hns3_err(hw, "failed to allocate buffer, ret = %d", ret); 2088 goto rollback; 2089 } 2090 2091 hns->pf.mps = mps; 2092 2093 return 0; 2094 2095 rollback: 2096 err = hns3_set_mac_mtu(hw, hns->pf.mps); 2097 if (err) 2098 hns3_err(hw, "fail to rollback MTU, err = %d", err); 2099 2100 return ret; 2101 } 2102 2103 static int 2104 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 2105 { 2106 struct hns3_adapter *hns = dev->data->dev_private; 2107 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD; 2108 struct hns3_hw *hw = &hns->hw; 2109 int ret; 2110 2111 if (dev->data->dev_started) { 2112 hns3_err(hw, "Failed to set mtu, port %u must be stopped " 2113 "before configuration", dev->data->port_id); 2114 return -EBUSY; 2115 } 2116 2117 rte_spinlock_lock(&hw->lock); 2118 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN); 2119 2120 /* 2121 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely 2122 * assign to "uint16_t" type variable. 2123 */ 2124 ret = hns3_config_mtu(hw, (uint16_t)frame_size); 2125 if (ret) { 2126 rte_spinlock_unlock(&hw->lock); 2127 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d", 2128 dev->data->port_id, mtu, ret); 2129 return ret; 2130 } 2131 2132 rte_spinlock_unlock(&hw->lock); 2133 2134 return 0; 2135 } 2136 2137 static uint32_t 2138 hns3_get_copper_port_speed_capa(uint32_t supported_speed) 2139 { 2140 uint32_t speed_capa = 0; 2141 2142 if (supported_speed & HNS3_PHY_LINK_SPEED_10M_HD_BIT) 2143 speed_capa |= RTE_ETH_LINK_SPEED_10M_HD; 2144 if (supported_speed & HNS3_PHY_LINK_SPEED_10M_BIT) 2145 speed_capa |= RTE_ETH_LINK_SPEED_10M; 2146 if (supported_speed & HNS3_PHY_LINK_SPEED_100M_HD_BIT) 2147 speed_capa |= RTE_ETH_LINK_SPEED_100M_HD; 2148 if (supported_speed & HNS3_PHY_LINK_SPEED_100M_BIT) 2149 speed_capa |= RTE_ETH_LINK_SPEED_100M; 2150 if (supported_speed & HNS3_PHY_LINK_SPEED_1000M_BIT) 2151 speed_capa |= RTE_ETH_LINK_SPEED_1G; 2152 2153 return speed_capa; 2154 } 2155 2156 static uint32_t 2157 hns3_get_firber_port_speed_capa(uint32_t supported_speed) 2158 { 2159 uint32_t speed_capa = 0; 2160 2161 if (supported_speed & HNS3_FIBER_LINK_SPEED_1G_BIT) 2162 speed_capa |= RTE_ETH_LINK_SPEED_1G; 2163 if (supported_speed & HNS3_FIBER_LINK_SPEED_10G_BIT) 2164 speed_capa |= RTE_ETH_LINK_SPEED_10G; 2165 if (supported_speed & HNS3_FIBER_LINK_SPEED_25G_BIT) 2166 speed_capa |= RTE_ETH_LINK_SPEED_25G; 2167 if (supported_speed & HNS3_FIBER_LINK_SPEED_40G_BIT) 2168 speed_capa |= RTE_ETH_LINK_SPEED_40G; 2169 if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_BIT) 2170 speed_capa |= RTE_ETH_LINK_SPEED_50G; 2171 if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_BIT) 2172 speed_capa |= RTE_ETH_LINK_SPEED_100G; 2173 if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_BIT) 2174 speed_capa |= RTE_ETH_LINK_SPEED_200G; 2175 2176 return speed_capa; 2177 } 2178 2179 uint32_t 2180 hns3_get_speed_capa(struct hns3_hw *hw) 2181 { 2182 struct hns3_mac *mac = &hw->mac; 2183 uint32_t speed_capa; 2184 2185 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) 2186 speed_capa = 2187 hns3_get_copper_port_speed_capa(mac->supported_speed); 2188 else 2189 speed_capa = 2190 hns3_get_firber_port_speed_capa(mac->supported_speed); 2191 2192 if (mac->support_autoneg == 0) 2193 speed_capa |= RTE_ETH_LINK_SPEED_FIXED; 2194 2195 return speed_capa; 2196 } 2197 2198 static int 2199 hns3_update_port_link_info(struct rte_eth_dev *eth_dev) 2200 { 2201 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 2202 int ret; 2203 2204 (void)hns3_update_link_status(hw); 2205 2206 ret = hns3_update_link_info(eth_dev); 2207 if (ret) 2208 hw->mac.link_status = RTE_ETH_LINK_DOWN; 2209 2210 return ret; 2211 } 2212 2213 static void 2214 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev, 2215 struct rte_eth_link *new_link) 2216 { 2217 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 2218 struct hns3_mac *mac = &hw->mac; 2219 2220 switch (mac->link_speed) { 2221 case RTE_ETH_SPEED_NUM_10M: 2222 case RTE_ETH_SPEED_NUM_100M: 2223 case RTE_ETH_SPEED_NUM_1G: 2224 case RTE_ETH_SPEED_NUM_10G: 2225 case RTE_ETH_SPEED_NUM_25G: 2226 case RTE_ETH_SPEED_NUM_40G: 2227 case RTE_ETH_SPEED_NUM_50G: 2228 case RTE_ETH_SPEED_NUM_100G: 2229 case RTE_ETH_SPEED_NUM_200G: 2230 if (mac->link_status) 2231 new_link->link_speed = mac->link_speed; 2232 break; 2233 default: 2234 if (mac->link_status) 2235 new_link->link_speed = RTE_ETH_SPEED_NUM_UNKNOWN; 2236 break; 2237 } 2238 2239 if (!mac->link_status) 2240 new_link->link_speed = RTE_ETH_SPEED_NUM_NONE; 2241 2242 new_link->link_duplex = mac->link_duplex; 2243 new_link->link_status = mac->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN; 2244 new_link->link_autoneg = mac->link_autoneg; 2245 } 2246 2247 static int 2248 hns3_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete) 2249 { 2250 #define HNS3_LINK_CHECK_INTERVAL 100 /* 100ms */ 2251 #define HNS3_MAX_LINK_CHECK_TIMES 20 /* 2s (100 * 20ms) in total */ 2252 2253 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 2254 uint32_t retry_cnt = HNS3_MAX_LINK_CHECK_TIMES; 2255 struct hns3_mac *mac = &hw->mac; 2256 struct rte_eth_link new_link; 2257 int ret; 2258 2259 /* When port is stopped, report link down. */ 2260 if (eth_dev->data->dev_started == 0) { 2261 new_link.link_autoneg = mac->link_autoneg; 2262 new_link.link_duplex = mac->link_duplex; 2263 new_link.link_speed = RTE_ETH_SPEED_NUM_NONE; 2264 new_link.link_status = RTE_ETH_LINK_DOWN; 2265 goto out; 2266 } 2267 2268 do { 2269 ret = hns3_update_port_link_info(eth_dev); 2270 if (ret) { 2271 hns3_err(hw, "failed to get port link info, ret = %d.", 2272 ret); 2273 break; 2274 } 2275 2276 if (!wait_to_complete || mac->link_status == RTE_ETH_LINK_UP) 2277 break; 2278 2279 rte_delay_ms(HNS3_LINK_CHECK_INTERVAL); 2280 } while (retry_cnt--); 2281 2282 memset(&new_link, 0, sizeof(new_link)); 2283 hns3_setup_linkstatus(eth_dev, &new_link); 2284 2285 out: 2286 return rte_eth_linkstatus_set(eth_dev, &new_link); 2287 } 2288 2289 static int 2290 hns3_dev_set_link_up(struct rte_eth_dev *dev) 2291 { 2292 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2293 int ret; 2294 2295 /* 2296 * The "tx_pkt_burst" will be restored. But the secondary process does 2297 * not support the mechanism for notifying the primary process. 2298 */ 2299 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2300 hns3_err(hw, "secondary process does not support to set link up."); 2301 return -ENOTSUP; 2302 } 2303 2304 /* 2305 * If device isn't started Rx/Tx function is still disabled, setting 2306 * link up is not allowed. But it is probably better to return success 2307 * to reduce the impact on the upper layer. 2308 */ 2309 if (hw->adapter_state != HNS3_NIC_STARTED) { 2310 hns3_info(hw, "device isn't started, can't set link up."); 2311 return 0; 2312 } 2313 2314 if (!hw->set_link_down) 2315 return 0; 2316 2317 rte_spinlock_lock(&hw->lock); 2318 ret = hns3_cfg_mac_mode(hw, true); 2319 if (ret) { 2320 rte_spinlock_unlock(&hw->lock); 2321 hns3_err(hw, "failed to set link up, ret = %d", ret); 2322 return ret; 2323 } 2324 2325 hw->set_link_down = false; 2326 hns3_start_tx_datapath(dev); 2327 rte_spinlock_unlock(&hw->lock); 2328 2329 return 0; 2330 } 2331 2332 static int 2333 hns3_dev_set_link_down(struct rte_eth_dev *dev) 2334 { 2335 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2336 int ret; 2337 2338 /* 2339 * The "tx_pkt_burst" will be set to dummy function. But the secondary 2340 * process does not support the mechanism for notifying the primary 2341 * process. 2342 */ 2343 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2344 hns3_err(hw, "secondary process does not support to set link down."); 2345 return -ENOTSUP; 2346 } 2347 2348 /* 2349 * If device isn't started or the API has been called, link status is 2350 * down, return success. 2351 */ 2352 if (hw->adapter_state != HNS3_NIC_STARTED || hw->set_link_down) 2353 return 0; 2354 2355 rte_spinlock_lock(&hw->lock); 2356 hns3_stop_tx_datapath(dev); 2357 ret = hns3_cfg_mac_mode(hw, false); 2358 if (ret) { 2359 hns3_start_tx_datapath(dev); 2360 rte_spinlock_unlock(&hw->lock); 2361 hns3_err(hw, "failed to set link down, ret = %d", ret); 2362 return ret; 2363 } 2364 2365 hw->set_link_down = true; 2366 rte_spinlock_unlock(&hw->lock); 2367 2368 return 0; 2369 } 2370 2371 static int 2372 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status) 2373 { 2374 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2375 struct hns3_pf *pf = &hns->pf; 2376 2377 if (!(status->pf_state & HNS3_PF_STATE_DONE)) 2378 return -EINVAL; 2379 2380 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false; 2381 2382 return 0; 2383 } 2384 2385 static int 2386 hns3_query_function_status(struct hns3_hw *hw) 2387 { 2388 #define HNS3_QUERY_MAX_CNT 10 2389 #define HNS3_QUERY_SLEEP_MSCOEND 1 2390 struct hns3_func_status_cmd *req; 2391 struct hns3_cmd_desc desc; 2392 int timeout = 0; 2393 int ret; 2394 2395 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true); 2396 req = (struct hns3_func_status_cmd *)desc.data; 2397 2398 do { 2399 ret = hns3_cmd_send(hw, &desc, 1); 2400 if (ret) { 2401 PMD_INIT_LOG(ERR, "query function status failed %d", 2402 ret); 2403 return ret; 2404 } 2405 2406 /* Check pf reset is done */ 2407 if (req->pf_state) 2408 break; 2409 2410 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND); 2411 } while (timeout++ < HNS3_QUERY_MAX_CNT); 2412 2413 return hns3_parse_func_status(hw, req); 2414 } 2415 2416 static int 2417 hns3_get_pf_max_tqp_num(struct hns3_hw *hw) 2418 { 2419 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2420 struct hns3_pf *pf = &hns->pf; 2421 2422 if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) { 2423 /* 2424 * The total_tqps_num obtained from firmware is maximum tqp 2425 * numbers of this port, which should be used for PF and VFs. 2426 * There is no need for pf to have so many tqp numbers in 2427 * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF, 2428 * coming from config file, is assigned to maximum queue number 2429 * for the PF of this port by user. So users can modify the 2430 * maximum queue number of PF according to their own application 2431 * scenarios, which is more flexible to use. In addition, many 2432 * memories can be saved due to allocating queue statistics 2433 * room according to the actual number of queues required. The 2434 * maximum queue number of PF for network engine with 2435 * revision_id greater than 0x30 is assigned by config file. 2436 */ 2437 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) { 2438 hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) " 2439 "must be greater than 0.", 2440 RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF); 2441 return -EINVAL; 2442 } 2443 2444 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF, 2445 hw->total_tqps_num); 2446 } else { 2447 /* 2448 * Due to the limitation on the number of PF interrupts 2449 * available, the maximum queue number assigned to PF on 2450 * the network engine with revision_id 0x21 is 64. 2451 */ 2452 hw->tqps_num = RTE_MIN(hw->total_tqps_num, 2453 HNS3_MAX_TQP_NUM_HIP08_PF); 2454 } 2455 2456 return 0; 2457 } 2458 2459 static int 2460 hns3_query_pf_resource(struct hns3_hw *hw) 2461 { 2462 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2463 struct hns3_pf *pf = &hns->pf; 2464 struct hns3_pf_res_cmd *req; 2465 struct hns3_cmd_desc desc; 2466 int ret; 2467 2468 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true); 2469 ret = hns3_cmd_send(hw, &desc, 1); 2470 if (ret) { 2471 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret); 2472 return ret; 2473 } 2474 2475 req = (struct hns3_pf_res_cmd *)desc.data; 2476 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) + 2477 rte_le_to_cpu_16(req->ext_tqp_num); 2478 ret = hns3_get_pf_max_tqp_num(hw); 2479 if (ret) 2480 return ret; 2481 2482 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S; 2483 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number); 2484 2485 if (req->tx_buf_size) 2486 pf->tx_buf_size = 2487 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S; 2488 else 2489 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF; 2490 2491 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT); 2492 2493 if (req->dv_buf_size) 2494 pf->dv_buf_size = 2495 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S; 2496 else 2497 pf->dv_buf_size = HNS3_DEFAULT_DV; 2498 2499 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT); 2500 2501 hw->num_msi = 2502 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number), 2503 HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S); 2504 2505 return 0; 2506 } 2507 2508 static void 2509 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc) 2510 { 2511 struct hns3_cfg_param_cmd *req; 2512 uint64_t mac_addr_tmp_high; 2513 uint8_t ext_rss_size_max; 2514 uint64_t mac_addr_tmp; 2515 uint32_t i; 2516 2517 req = (struct hns3_cfg_param_cmd *)desc[0].data; 2518 2519 /* get the configuration */ 2520 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]), 2521 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S); 2522 2523 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2524 HNS3_CFG_PHY_ADDR_M, 2525 HNS3_CFG_PHY_ADDR_S); 2526 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2527 HNS3_CFG_MEDIA_TP_M, 2528 HNS3_CFG_MEDIA_TP_S); 2529 /* get mac address */ 2530 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]); 2531 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 2532 HNS3_CFG_MAC_ADDR_H_M, 2533 HNS3_CFG_MAC_ADDR_H_S); 2534 2535 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 2536 2537 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 2538 HNS3_CFG_DEFAULT_SPEED_M, 2539 HNS3_CFG_DEFAULT_SPEED_S); 2540 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 2541 HNS3_CFG_RSS_SIZE_M, 2542 HNS3_CFG_RSS_SIZE_S); 2543 2544 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++) 2545 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 2546 2547 req = (struct hns3_cfg_param_cmd *)desc[1].data; 2548 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]); 2549 2550 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2551 HNS3_CFG_SPEED_ABILITY_M, 2552 HNS3_CFG_SPEED_ABILITY_S); 2553 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2554 HNS3_CFG_UMV_TBL_SPACE_M, 2555 HNS3_CFG_UMV_TBL_SPACE_S); 2556 if (!cfg->umv_space) 2557 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF; 2558 2559 ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]), 2560 HNS3_CFG_EXT_RSS_SIZE_M, 2561 HNS3_CFG_EXT_RSS_SIZE_S); 2562 /* 2563 * Field ext_rss_size_max obtained from firmware will be more flexible 2564 * for future changes and expansions, which is an exponent of 2, instead 2565 * of reading out directly. If this field is not zero, hns3 PF PMD 2566 * uses it as rss_size_max under one TC. Device, whose revision 2567 * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the 2568 * maximum number of queues supported under a TC through this field. 2569 */ 2570 if (ext_rss_size_max) 2571 cfg->rss_size_max = 1U << ext_rss_size_max; 2572 } 2573 2574 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash 2575 * @hw: pointer to struct hns3_hw 2576 * @hcfg: the config structure to be getted 2577 */ 2578 static int 2579 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg) 2580 { 2581 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM]; 2582 struct hns3_cfg_param_cmd *req; 2583 uint32_t offset; 2584 uint32_t i; 2585 int ret; 2586 2587 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) { 2588 offset = 0; 2589 req = (struct hns3_cfg_param_cmd *)desc[i].data; 2590 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM, 2591 true); 2592 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S, 2593 i * HNS3_CFG_RD_LEN_BYTES); 2594 /* Len should be divided by 4 when send to hardware */ 2595 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S, 2596 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT); 2597 req->offset = rte_cpu_to_le_32(offset); 2598 } 2599 2600 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM); 2601 if (ret) { 2602 PMD_INIT_LOG(ERR, "get config failed %d.", ret); 2603 return ret; 2604 } 2605 2606 hns3_parse_cfg(hcfg, desc); 2607 2608 return 0; 2609 } 2610 2611 static int 2612 hns3_parse_speed(int speed_cmd, uint32_t *speed) 2613 { 2614 switch (speed_cmd) { 2615 case HNS3_CFG_SPEED_10M: 2616 *speed = RTE_ETH_SPEED_NUM_10M; 2617 break; 2618 case HNS3_CFG_SPEED_100M: 2619 *speed = RTE_ETH_SPEED_NUM_100M; 2620 break; 2621 case HNS3_CFG_SPEED_1G: 2622 *speed = RTE_ETH_SPEED_NUM_1G; 2623 break; 2624 case HNS3_CFG_SPEED_10G: 2625 *speed = RTE_ETH_SPEED_NUM_10G; 2626 break; 2627 case HNS3_CFG_SPEED_25G: 2628 *speed = RTE_ETH_SPEED_NUM_25G; 2629 break; 2630 case HNS3_CFG_SPEED_40G: 2631 *speed = RTE_ETH_SPEED_NUM_40G; 2632 break; 2633 case HNS3_CFG_SPEED_50G: 2634 *speed = RTE_ETH_SPEED_NUM_50G; 2635 break; 2636 case HNS3_CFG_SPEED_100G: 2637 *speed = RTE_ETH_SPEED_NUM_100G; 2638 break; 2639 case HNS3_CFG_SPEED_200G: 2640 *speed = RTE_ETH_SPEED_NUM_200G; 2641 break; 2642 default: 2643 return -EINVAL; 2644 } 2645 2646 return 0; 2647 } 2648 2649 static void 2650 hns3_set_default_dev_specifications(struct hns3_hw *hw) 2651 { 2652 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT; 2653 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE; 2654 hw->rss_key_size = HNS3_RSS_KEY_SIZE; 2655 hw->max_tm_rate = HNS3_ETHER_MAX_RATE; 2656 hw->intr.int_ql_max = HNS3_INTR_QL_NONE; 2657 } 2658 2659 static void 2660 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc) 2661 { 2662 struct hns3_dev_specs_0_cmd *req0; 2663 2664 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data; 2665 2666 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num; 2667 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size); 2668 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size); 2669 hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate); 2670 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max); 2671 } 2672 2673 static int 2674 hns3_check_dev_specifications(struct hns3_hw *hw) 2675 { 2676 if (hw->rss_ind_tbl_size == 0 || 2677 hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) { 2678 hns3_err(hw, "the size of hash lookup table configured (%u) exceeds the maximum(%u)", 2679 hw->rss_ind_tbl_size, HNS3_RSS_IND_TBL_SIZE_MAX); 2680 return -EINVAL; 2681 } 2682 2683 return 0; 2684 } 2685 2686 static int 2687 hns3_query_dev_specifications(struct hns3_hw *hw) 2688 { 2689 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM]; 2690 int ret; 2691 int i; 2692 2693 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 2694 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, 2695 true); 2696 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 2697 } 2698 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true); 2699 2700 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM); 2701 if (ret) 2702 return ret; 2703 2704 hns3_parse_dev_specifications(hw, desc); 2705 2706 return hns3_check_dev_specifications(hw); 2707 } 2708 2709 static int 2710 hns3_get_capability(struct hns3_hw *hw) 2711 { 2712 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2713 struct rte_pci_device *pci_dev; 2714 struct hns3_pf *pf = &hns->pf; 2715 struct rte_eth_dev *eth_dev; 2716 uint16_t device_id; 2717 int ret; 2718 2719 eth_dev = &rte_eth_devices[hw->data->port_id]; 2720 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 2721 device_id = pci_dev->id.device_id; 2722 2723 if (device_id == HNS3_DEV_ID_25GE_RDMA || 2724 device_id == HNS3_DEV_ID_50GE_RDMA || 2725 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC || 2726 device_id == HNS3_DEV_ID_200G_RDMA) 2727 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1); 2728 2729 ret = hns3_get_pci_revision_id(hw, &hw->revision); 2730 if (ret) 2731 return ret; 2732 2733 ret = hns3_query_mac_stats_reg_num(hw); 2734 if (ret) 2735 return ret; 2736 2737 if (hw->revision < PCI_REVISION_ID_HIP09_A) { 2738 hns3_set_default_dev_specifications(hw); 2739 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE; 2740 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US; 2741 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM; 2742 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE; 2743 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1; 2744 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN; 2745 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE; 2746 hw->rss_info.ipv6_sctp_offload_supported = false; 2747 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE; 2748 pf->support_multi_tc_pause = false; 2749 return 0; 2750 } 2751 2752 ret = hns3_query_dev_specifications(hw); 2753 if (ret) { 2754 PMD_INIT_LOG(ERR, 2755 "failed to query dev specifications, ret = %d", 2756 ret); 2757 return ret; 2758 } 2759 2760 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL; 2761 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US; 2762 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM; 2763 hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE; 2764 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2; 2765 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN; 2766 pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE; 2767 hw->rss_info.ipv6_sctp_offload_supported = true; 2768 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE; 2769 pf->support_multi_tc_pause = true; 2770 2771 return 0; 2772 } 2773 2774 static int 2775 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type) 2776 { 2777 int ret; 2778 2779 switch (media_type) { 2780 case HNS3_MEDIA_TYPE_COPPER: 2781 if (!hns3_dev_get_support(hw, COPPER)) { 2782 PMD_INIT_LOG(ERR, 2783 "Media type is copper, not supported."); 2784 ret = -EOPNOTSUPP; 2785 } else { 2786 ret = 0; 2787 } 2788 break; 2789 case HNS3_MEDIA_TYPE_FIBER: 2790 case HNS3_MEDIA_TYPE_BACKPLANE: 2791 ret = 0; 2792 break; 2793 default: 2794 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type); 2795 ret = -EINVAL; 2796 break; 2797 } 2798 2799 return ret; 2800 } 2801 2802 static int 2803 hns3_get_board_configuration(struct hns3_hw *hw) 2804 { 2805 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2806 struct hns3_pf *pf = &hns->pf; 2807 struct hns3_cfg cfg; 2808 int ret; 2809 2810 ret = hns3_get_board_cfg(hw, &cfg); 2811 if (ret) { 2812 PMD_INIT_LOG(ERR, "get board config failed %d", ret); 2813 return ret; 2814 } 2815 2816 ret = hns3_check_media_type(hw, cfg.media_type); 2817 if (ret) 2818 return ret; 2819 2820 hw->mac.media_type = cfg.media_type; 2821 hw->rss_size_max = cfg.rss_size_max; 2822 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN); 2823 hw->mac.phy_addr = cfg.phy_addr; 2824 hw->dcb_info.num_pg = 1; 2825 hw->dcb_info.hw_pfc_map = 0; 2826 2827 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed); 2828 if (ret) { 2829 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d", 2830 cfg.default_speed, ret); 2831 return ret; 2832 } 2833 2834 pf->tc_max = cfg.tc_num; 2835 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) { 2836 PMD_INIT_LOG(WARNING, 2837 "Get TC num(%u) from flash, set TC num to 1", 2838 pf->tc_max); 2839 pf->tc_max = 1; 2840 } 2841 2842 /* Dev does not support DCB */ 2843 if (!hns3_dev_get_support(hw, DCB)) { 2844 pf->tc_max = 1; 2845 pf->pfc_max = 0; 2846 } else 2847 pf->pfc_max = pf->tc_max; 2848 2849 hw->dcb_info.num_tc = 1; 2850 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, 2851 hw->tqps_num / hw->dcb_info.num_tc); 2852 hns3_set_bit(hw->hw_tc_map, 0, 1); 2853 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE; 2854 2855 pf->wanted_umv_size = cfg.umv_space; 2856 2857 return ret; 2858 } 2859 2860 static int 2861 hns3_get_configuration(struct hns3_hw *hw) 2862 { 2863 int ret; 2864 2865 ret = hns3_query_function_status(hw); 2866 if (ret) { 2867 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret); 2868 return ret; 2869 } 2870 2871 /* Get device capability */ 2872 ret = hns3_get_capability(hw); 2873 if (ret) { 2874 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret); 2875 return ret; 2876 } 2877 2878 /* Get pf resource */ 2879 ret = hns3_query_pf_resource(hw); 2880 if (ret) { 2881 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret); 2882 return ret; 2883 } 2884 2885 ret = hns3_get_board_configuration(hw); 2886 if (ret) { 2887 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret); 2888 return ret; 2889 } 2890 2891 ret = hns3_query_dev_fec_info(hw); 2892 if (ret) 2893 PMD_INIT_LOG(ERR, 2894 "failed to query FEC information, ret = %d", ret); 2895 2896 return ret; 2897 } 2898 2899 static int 2900 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid, 2901 uint16_t tqp_vid, bool is_pf) 2902 { 2903 struct hns3_tqp_map_cmd *req; 2904 struct hns3_cmd_desc desc; 2905 int ret; 2906 2907 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false); 2908 2909 req = (struct hns3_tqp_map_cmd *)desc.data; 2910 req->tqp_id = rte_cpu_to_le_16(tqp_pid); 2911 req->tqp_vf = func_id; 2912 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B; 2913 if (!is_pf) 2914 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B); 2915 req->tqp_vid = rte_cpu_to_le_16(tqp_vid); 2916 2917 ret = hns3_cmd_send(hw, &desc, 1); 2918 if (ret) 2919 PMD_INIT_LOG(ERR, "TQP map failed %d", ret); 2920 2921 return ret; 2922 } 2923 2924 static int 2925 hns3_map_tqp(struct hns3_hw *hw) 2926 { 2927 uint16_t i; 2928 int ret; 2929 2930 /* 2931 * In current version, VF is not supported when PF is driven by DPDK 2932 * driver, so we assign total tqps_num tqps allocated to this port 2933 * to PF. 2934 */ 2935 for (i = 0; i < hw->total_tqps_num; i++) { 2936 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true); 2937 if (ret) 2938 return ret; 2939 } 2940 2941 return 0; 2942 } 2943 2944 static int 2945 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex) 2946 { 2947 struct hns3_config_mac_speed_dup_cmd *req; 2948 struct hns3_cmd_desc desc; 2949 int ret; 2950 2951 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data; 2952 2953 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false); 2954 2955 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0); 2956 2957 switch (speed) { 2958 case RTE_ETH_SPEED_NUM_10M: 2959 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2960 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M); 2961 break; 2962 case RTE_ETH_SPEED_NUM_100M: 2963 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2964 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M); 2965 break; 2966 case RTE_ETH_SPEED_NUM_1G: 2967 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2968 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G); 2969 break; 2970 case RTE_ETH_SPEED_NUM_10G: 2971 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2972 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G); 2973 break; 2974 case RTE_ETH_SPEED_NUM_25G: 2975 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2976 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G); 2977 break; 2978 case RTE_ETH_SPEED_NUM_40G: 2979 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2980 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G); 2981 break; 2982 case RTE_ETH_SPEED_NUM_50G: 2983 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2984 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G); 2985 break; 2986 case RTE_ETH_SPEED_NUM_100G: 2987 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2988 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G); 2989 break; 2990 case RTE_ETH_SPEED_NUM_200G: 2991 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2992 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G); 2993 break; 2994 default: 2995 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed); 2996 return -EINVAL; 2997 } 2998 2999 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1); 3000 3001 ret = hns3_cmd_send(hw, &desc, 1); 3002 if (ret) 3003 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret); 3004 3005 return ret; 3006 } 3007 3008 static int 3009 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3010 { 3011 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3012 struct hns3_pf *pf = &hns->pf; 3013 struct hns3_priv_buf *priv; 3014 uint32_t i, total_size; 3015 3016 total_size = pf->pkt_buf_size; 3017 3018 /* alloc tx buffer for all enabled tc */ 3019 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3020 priv = &buf_alloc->priv_buf[i]; 3021 3022 if (hw->hw_tc_map & BIT(i)) { 3023 if (total_size < pf->tx_buf_size) 3024 return -ENOMEM; 3025 3026 priv->tx_buf_size = pf->tx_buf_size; 3027 } else 3028 priv->tx_buf_size = 0; 3029 3030 total_size -= priv->tx_buf_size; 3031 } 3032 3033 return 0; 3034 } 3035 3036 static int 3037 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3038 { 3039 /* TX buffer size is unit by 128 byte */ 3040 #define HNS3_BUF_SIZE_UNIT_SHIFT 7 3041 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15) 3042 struct hns3_tx_buff_alloc_cmd *req; 3043 struct hns3_cmd_desc desc; 3044 uint32_t buf_size; 3045 uint32_t i; 3046 int ret; 3047 3048 req = (struct hns3_tx_buff_alloc_cmd *)desc.data; 3049 3050 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0); 3051 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3052 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 3053 3054 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT; 3055 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size | 3056 HNS3_BUF_SIZE_UPDATE_EN_MSK); 3057 } 3058 3059 ret = hns3_cmd_send(hw, &desc, 1); 3060 if (ret) 3061 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret); 3062 3063 return ret; 3064 } 3065 3066 static int 3067 hns3_get_tc_num(struct hns3_hw *hw) 3068 { 3069 int cnt = 0; 3070 uint8_t i; 3071 3072 for (i = 0; i < HNS3_MAX_TC_NUM; i++) 3073 if (hw->hw_tc_map & BIT(i)) 3074 cnt++; 3075 return cnt; 3076 } 3077 3078 static uint32_t 3079 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc) 3080 { 3081 struct hns3_priv_buf *priv; 3082 uint32_t rx_priv = 0; 3083 int i; 3084 3085 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3086 priv = &buf_alloc->priv_buf[i]; 3087 if (priv->enable) 3088 rx_priv += priv->buf_size; 3089 } 3090 return rx_priv; 3091 } 3092 3093 static uint32_t 3094 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc) 3095 { 3096 uint32_t total_tx_size = 0; 3097 uint32_t i; 3098 3099 for (i = 0; i < HNS3_MAX_TC_NUM; i++) 3100 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 3101 3102 return total_tx_size; 3103 } 3104 3105 /* Get the number of pfc enabled TCs, which have private buffer */ 3106 static int 3107 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3108 { 3109 struct hns3_priv_buf *priv; 3110 int cnt = 0; 3111 uint8_t i; 3112 3113 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3114 priv = &buf_alloc->priv_buf[i]; 3115 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable) 3116 cnt++; 3117 } 3118 3119 return cnt; 3120 } 3121 3122 /* Get the number of pfc disabled TCs, which have private buffer */ 3123 static int 3124 hns3_get_no_pfc_priv_num(struct hns3_hw *hw, 3125 struct hns3_pkt_buf_alloc *buf_alloc) 3126 { 3127 struct hns3_priv_buf *priv; 3128 int cnt = 0; 3129 uint8_t i; 3130 3131 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3132 priv = &buf_alloc->priv_buf[i]; 3133 if (hw->hw_tc_map & BIT(i) && 3134 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable) 3135 cnt++; 3136 } 3137 3138 return cnt; 3139 } 3140 3141 static bool 3142 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc, 3143 uint32_t rx_all) 3144 { 3145 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd; 3146 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3147 struct hns3_pf *pf = &hns->pf; 3148 uint32_t shared_buf, aligned_mps; 3149 uint32_t rx_priv; 3150 uint8_t tc_num; 3151 uint8_t i; 3152 3153 tc_num = hns3_get_tc_num(hw); 3154 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT); 3155 3156 if (hns3_dev_get_support(hw, DCB)) 3157 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps + 3158 pf->dv_buf_size; 3159 else 3160 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF 3161 + pf->dv_buf_size; 3162 3163 shared_buf_tc = tc_num * aligned_mps + aligned_mps; 3164 shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc), 3165 HNS3_BUF_SIZE_UNIT); 3166 3167 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc); 3168 if (rx_all < rx_priv + shared_std) 3169 return false; 3170 3171 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT); 3172 buf_alloc->s_buf.buf_size = shared_buf; 3173 if (hns3_dev_get_support(hw, DCB)) { 3174 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size; 3175 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high 3176 - roundup(aligned_mps / HNS3_BUF_DIV_BY, 3177 HNS3_BUF_SIZE_UNIT); 3178 } else { 3179 buf_alloc->s_buf.self.high = 3180 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF; 3181 buf_alloc->s_buf.self.low = aligned_mps; 3182 } 3183 3184 if (hns3_dev_get_support(hw, DCB)) { 3185 hi_thrd = shared_buf - pf->dv_buf_size; 3186 3187 if (tc_num <= NEED_RESERVE_TC_NUM) 3188 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT / 3189 BUF_MAX_PERCENT; 3190 3191 if (tc_num) 3192 hi_thrd = hi_thrd / tc_num; 3193 3194 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps); 3195 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT); 3196 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY; 3197 } else { 3198 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF; 3199 lo_thrd = aligned_mps; 3200 } 3201 3202 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3203 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd; 3204 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd; 3205 } 3206 3207 return true; 3208 } 3209 3210 static bool 3211 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max, 3212 struct hns3_pkt_buf_alloc *buf_alloc) 3213 { 3214 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3215 struct hns3_pf *pf = &hns->pf; 3216 struct hns3_priv_buf *priv; 3217 uint32_t aligned_mps; 3218 uint32_t rx_all; 3219 uint8_t i; 3220 3221 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3222 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT); 3223 3224 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3225 priv = &buf_alloc->priv_buf[i]; 3226 3227 priv->enable = 0; 3228 priv->wl.low = 0; 3229 priv->wl.high = 0; 3230 priv->buf_size = 0; 3231 3232 if (!(hw->hw_tc_map & BIT(i))) 3233 continue; 3234 3235 priv->enable = 1; 3236 if (hw->dcb_info.hw_pfc_map & BIT(i)) { 3237 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT; 3238 priv->wl.high = roundup(priv->wl.low + aligned_mps, 3239 HNS3_BUF_SIZE_UNIT); 3240 } else { 3241 priv->wl.low = 0; 3242 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) : 3243 aligned_mps; 3244 } 3245 3246 priv->buf_size = priv->wl.high + pf->dv_buf_size; 3247 } 3248 3249 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3250 } 3251 3252 static bool 3253 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw, 3254 struct hns3_pkt_buf_alloc *buf_alloc) 3255 { 3256 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3257 struct hns3_pf *pf = &hns->pf; 3258 struct hns3_priv_buf *priv; 3259 int no_pfc_priv_num; 3260 uint32_t rx_all; 3261 uint8_t mask; 3262 int i; 3263 3264 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3265 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc); 3266 3267 /* let the last to be cleared first */ 3268 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) { 3269 priv = &buf_alloc->priv_buf[i]; 3270 mask = BIT((uint8_t)i); 3271 if (hw->hw_tc_map & mask && 3272 !(hw->dcb_info.hw_pfc_map & mask)) { 3273 /* Clear the no pfc TC private buffer */ 3274 priv->wl.low = 0; 3275 priv->wl.high = 0; 3276 priv->buf_size = 0; 3277 priv->enable = 0; 3278 no_pfc_priv_num--; 3279 } 3280 3281 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) || 3282 no_pfc_priv_num == 0) 3283 break; 3284 } 3285 3286 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3287 } 3288 3289 static bool 3290 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw, 3291 struct hns3_pkt_buf_alloc *buf_alloc) 3292 { 3293 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3294 struct hns3_pf *pf = &hns->pf; 3295 struct hns3_priv_buf *priv; 3296 uint32_t rx_all; 3297 int pfc_priv_num; 3298 uint8_t mask; 3299 int i; 3300 3301 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3302 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc); 3303 3304 /* let the last to be cleared first */ 3305 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) { 3306 priv = &buf_alloc->priv_buf[i]; 3307 mask = BIT((uint8_t)i); 3308 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) { 3309 /* Reduce the number of pfc TC with private buffer */ 3310 priv->wl.low = 0; 3311 priv->enable = 0; 3312 priv->wl.high = 0; 3313 priv->buf_size = 0; 3314 pfc_priv_num--; 3315 } 3316 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) || 3317 pfc_priv_num == 0) 3318 break; 3319 } 3320 3321 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3322 } 3323 3324 static bool 3325 hns3_only_alloc_priv_buff(struct hns3_hw *hw, 3326 struct hns3_pkt_buf_alloc *buf_alloc) 3327 { 3328 #define COMPENSATE_BUFFER 0x3C00 3329 #define COMPENSATE_HALF_MPS_NUM 5 3330 #define PRIV_WL_GAP 0x1800 3331 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3332 struct hns3_pf *pf = &hns->pf; 3333 uint32_t tc_num = hns3_get_tc_num(hw); 3334 uint32_t half_mps = pf->mps >> 1; 3335 struct hns3_priv_buf *priv; 3336 uint32_t min_rx_priv; 3337 uint32_t rx_priv; 3338 uint8_t i; 3339 3340 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3341 if (tc_num) 3342 rx_priv = rx_priv / tc_num; 3343 3344 if (tc_num <= NEED_RESERVE_TC_NUM) 3345 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT; 3346 3347 /* 3348 * Minimum value of private buffer in rx direction (min_rx_priv) is 3349 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private 3350 * buffer if rx_priv is greater than min_rx_priv. 3351 */ 3352 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER + 3353 COMPENSATE_HALF_MPS_NUM * half_mps; 3354 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT); 3355 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT); 3356 if (rx_priv < min_rx_priv) 3357 return false; 3358 3359 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3360 priv = &buf_alloc->priv_buf[i]; 3361 priv->enable = 0; 3362 priv->wl.low = 0; 3363 priv->wl.high = 0; 3364 priv->buf_size = 0; 3365 3366 if (!(hw->hw_tc_map & BIT(i))) 3367 continue; 3368 3369 priv->enable = 1; 3370 priv->buf_size = rx_priv; 3371 priv->wl.high = rx_priv - pf->dv_buf_size; 3372 priv->wl.low = priv->wl.high - PRIV_WL_GAP; 3373 } 3374 3375 buf_alloc->s_buf.buf_size = 0; 3376 3377 return true; 3378 } 3379 3380 /* 3381 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs 3382 * @hw: pointer to struct hns3_hw 3383 * @buf_alloc: pointer to buffer calculation data 3384 * @return: 0: calculate successful, negative: fail 3385 */ 3386 static int 3387 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3388 { 3389 /* When DCB is not supported, rx private buffer is not allocated. */ 3390 if (!hns3_dev_get_support(hw, DCB)) { 3391 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3392 struct hns3_pf *pf = &hns->pf; 3393 uint32_t rx_all = pf->pkt_buf_size; 3394 3395 rx_all -= hns3_get_tx_buff_alloced(buf_alloc); 3396 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all)) 3397 return -ENOMEM; 3398 3399 return 0; 3400 } 3401 3402 /* 3403 * Try to allocate privated packet buffer for all TCs without share 3404 * buffer. 3405 */ 3406 if (hns3_only_alloc_priv_buff(hw, buf_alloc)) 3407 return 0; 3408 3409 /* 3410 * Try to allocate privated packet buffer for all TCs with share 3411 * buffer. 3412 */ 3413 if (hns3_rx_buf_calc_all(hw, true, buf_alloc)) 3414 return 0; 3415 3416 /* 3417 * For different application scenes, the enabled port number, TC number 3418 * and no_drop TC number are different. In order to obtain the better 3419 * performance, software could allocate the buffer size and configure 3420 * the waterline by trying to decrease the private buffer size according 3421 * to the order, namely, waterline of valid tc, pfc disabled tc, pfc 3422 * enabled tc. 3423 */ 3424 if (hns3_rx_buf_calc_all(hw, false, buf_alloc)) 3425 return 0; 3426 3427 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc)) 3428 return 0; 3429 3430 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc)) 3431 return 0; 3432 3433 return -ENOMEM; 3434 } 3435 3436 static int 3437 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3438 { 3439 struct hns3_rx_priv_buff_cmd *req; 3440 struct hns3_cmd_desc desc; 3441 uint32_t buf_size; 3442 int ret; 3443 int i; 3444 3445 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false); 3446 req = (struct hns3_rx_priv_buff_cmd *)desc.data; 3447 3448 /* Alloc private buffer TCs */ 3449 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3450 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i]; 3451 3452 req->buf_num[i] = 3453 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S); 3454 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B); 3455 } 3456 3457 buf_size = buf_alloc->s_buf.buf_size; 3458 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) | 3459 (1 << HNS3_TC0_PRI_BUF_EN_B)); 3460 3461 ret = hns3_cmd_send(hw, &desc, 1); 3462 if (ret) 3463 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret); 3464 3465 return ret; 3466 } 3467 3468 static int 3469 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3470 { 3471 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2 3472 struct hns3_rx_priv_wl_buf *req; 3473 struct hns3_priv_buf *priv; 3474 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM]; 3475 int i, j; 3476 int ret; 3477 3478 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) { 3479 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC, 3480 false); 3481 req = (struct hns3_rx_priv_wl_buf *)desc[i].data; 3482 3483 /* The first descriptor set the NEXT bit to 1 */ 3484 if (i == 0) 3485 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3486 else 3487 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3488 3489 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) { 3490 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j; 3491 3492 priv = &buf_alloc->priv_buf[idx]; 3493 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >> 3494 HNS3_BUF_UNIT_S); 3495 req->tc_wl[j].high |= 3496 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3497 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >> 3498 HNS3_BUF_UNIT_S); 3499 req->tc_wl[j].low |= 3500 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3501 } 3502 } 3503 3504 /* Send 2 descriptor at one time */ 3505 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM); 3506 if (ret) 3507 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d", 3508 ret); 3509 return ret; 3510 } 3511 3512 static int 3513 hns3_common_thrd_config(struct hns3_hw *hw, 3514 struct hns3_pkt_buf_alloc *buf_alloc) 3515 { 3516 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2 3517 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf; 3518 struct hns3_rx_com_thrd *req; 3519 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM]; 3520 struct hns3_tc_thrd *tc; 3521 int tc_idx; 3522 int i, j; 3523 int ret; 3524 3525 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) { 3526 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC, 3527 false); 3528 req = (struct hns3_rx_com_thrd *)&desc[i].data; 3529 3530 /* The first descriptor set the NEXT bit to 1 */ 3531 if (i == 0) 3532 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3533 else 3534 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3535 3536 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) { 3537 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j; 3538 tc = &s_buf->tc_thrd[tc_idx]; 3539 3540 req->com_thrd[j].high = 3541 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S); 3542 req->com_thrd[j].high |= 3543 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3544 req->com_thrd[j].low = 3545 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S); 3546 req->com_thrd[j].low |= 3547 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3548 } 3549 } 3550 3551 /* Send 2 descriptors at one time */ 3552 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM); 3553 if (ret) 3554 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret); 3555 3556 return ret; 3557 } 3558 3559 static int 3560 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3561 { 3562 struct hns3_shared_buf *buf = &buf_alloc->s_buf; 3563 struct hns3_rx_com_wl *req; 3564 struct hns3_cmd_desc desc; 3565 int ret; 3566 3567 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false); 3568 3569 req = (struct hns3_rx_com_wl *)desc.data; 3570 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S); 3571 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3572 3573 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S); 3574 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3575 3576 ret = hns3_cmd_send(hw, &desc, 1); 3577 if (ret) 3578 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret); 3579 3580 return ret; 3581 } 3582 3583 int 3584 hns3_buffer_alloc(struct hns3_hw *hw) 3585 { 3586 struct hns3_pkt_buf_alloc pkt_buf; 3587 int ret; 3588 3589 memset(&pkt_buf, 0, sizeof(pkt_buf)); 3590 ret = hns3_tx_buffer_calc(hw, &pkt_buf); 3591 if (ret) { 3592 PMD_INIT_LOG(ERR, 3593 "could not calc tx buffer size for all TCs %d", 3594 ret); 3595 return ret; 3596 } 3597 3598 ret = hns3_tx_buffer_alloc(hw, &pkt_buf); 3599 if (ret) { 3600 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret); 3601 return ret; 3602 } 3603 3604 ret = hns3_rx_buffer_calc(hw, &pkt_buf); 3605 if (ret) { 3606 PMD_INIT_LOG(ERR, 3607 "could not calc rx priv buffer size for all TCs %d", 3608 ret); 3609 return ret; 3610 } 3611 3612 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf); 3613 if (ret) { 3614 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret); 3615 return ret; 3616 } 3617 3618 if (hns3_dev_get_support(hw, DCB)) { 3619 ret = hns3_rx_priv_wl_config(hw, &pkt_buf); 3620 if (ret) { 3621 PMD_INIT_LOG(ERR, 3622 "could not configure rx private waterline %d", 3623 ret); 3624 return ret; 3625 } 3626 3627 ret = hns3_common_thrd_config(hw, &pkt_buf); 3628 if (ret) { 3629 PMD_INIT_LOG(ERR, 3630 "could not configure common threshold %d", 3631 ret); 3632 return ret; 3633 } 3634 } 3635 3636 ret = hns3_common_wl_config(hw, &pkt_buf); 3637 if (ret) 3638 PMD_INIT_LOG(ERR, "could not configure common waterline %d", 3639 ret); 3640 3641 return ret; 3642 } 3643 3644 static int 3645 hns3_mac_init(struct hns3_hw *hw) 3646 { 3647 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3648 struct hns3_mac *mac = &hw->mac; 3649 struct hns3_pf *pf = &hns->pf; 3650 int ret; 3651 3652 pf->support_sfp_query = true; 3653 mac->link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 3654 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex); 3655 if (ret) { 3656 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret); 3657 return ret; 3658 } 3659 3660 mac->link_status = RTE_ETH_LINK_DOWN; 3661 3662 return hns3_config_mtu(hw, pf->mps); 3663 } 3664 3665 static int 3666 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code) 3667 { 3668 #define HNS3_ETHERTYPE_SUCCESS_ADD 0 3669 #define HNS3_ETHERTYPE_ALREADY_ADD 1 3670 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2 3671 #define HNS3_ETHERTYPE_KEY_CONFLICT 3 3672 int return_status; 3673 3674 if (cmdq_resp) { 3675 PMD_INIT_LOG(ERR, 3676 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n", 3677 cmdq_resp); 3678 return -EIO; 3679 } 3680 3681 switch (resp_code) { 3682 case HNS3_ETHERTYPE_SUCCESS_ADD: 3683 case HNS3_ETHERTYPE_ALREADY_ADD: 3684 return_status = 0; 3685 break; 3686 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW: 3687 PMD_INIT_LOG(ERR, 3688 "add mac ethertype failed for manager table overflow."); 3689 return_status = -EIO; 3690 break; 3691 case HNS3_ETHERTYPE_KEY_CONFLICT: 3692 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict."); 3693 return_status = -EIO; 3694 break; 3695 default: 3696 PMD_INIT_LOG(ERR, 3697 "add mac ethertype failed for undefined, code=%u.", 3698 resp_code); 3699 return_status = -EIO; 3700 break; 3701 } 3702 3703 return return_status; 3704 } 3705 3706 static int 3707 hns3_add_mgr_tbl(struct hns3_hw *hw, 3708 const struct hns3_mac_mgr_tbl_entry_cmd *req) 3709 { 3710 struct hns3_cmd_desc desc; 3711 uint8_t resp_code; 3712 uint16_t retval; 3713 int ret; 3714 3715 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false); 3716 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd)); 3717 3718 ret = hns3_cmd_send(hw, &desc, 1); 3719 if (ret) { 3720 PMD_INIT_LOG(ERR, 3721 "add mac ethertype failed for cmd_send, ret =%d.", 3722 ret); 3723 return ret; 3724 } 3725 3726 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff; 3727 retval = rte_le_to_cpu_16(desc.retval); 3728 3729 return hns3_get_mac_ethertype_cmd_status(retval, resp_code); 3730 } 3731 3732 static void 3733 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table, 3734 int *table_item_num) 3735 { 3736 struct hns3_mac_mgr_tbl_entry_cmd *tbl; 3737 3738 /* 3739 * In current version, we add one item in management table as below: 3740 * 0x0180C200000E -- LLDP MC address 3741 */ 3742 tbl = mgr_table; 3743 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B; 3744 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP); 3745 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200)); 3746 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E)); 3747 tbl->i_port_bitmap = 0x1; 3748 *table_item_num = 1; 3749 } 3750 3751 static int 3752 hns3_init_mgr_tbl(struct hns3_hw *hw) 3753 { 3754 #define HNS_MAC_MGR_TBL_MAX_SIZE 16 3755 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE]; 3756 int table_item_num; 3757 int ret; 3758 int i; 3759 3760 memset(mgr_table, 0, sizeof(mgr_table)); 3761 hns3_prepare_mgr_tbl(mgr_table, &table_item_num); 3762 for (i = 0; i < table_item_num; i++) { 3763 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]); 3764 if (ret) { 3765 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d", 3766 ret); 3767 return ret; 3768 } 3769 } 3770 3771 return 0; 3772 } 3773 3774 static void 3775 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc, 3776 bool en_mc, bool en_bc, int vport_id) 3777 { 3778 if (!param) 3779 return; 3780 3781 memset(param, 0, sizeof(struct hns3_promisc_param)); 3782 if (en_uc) 3783 param->enable = HNS3_PROMISC_EN_UC; 3784 if (en_mc) 3785 param->enable |= HNS3_PROMISC_EN_MC; 3786 if (en_bc) 3787 param->enable |= HNS3_PROMISC_EN_BC; 3788 param->vf_id = vport_id; 3789 } 3790 3791 static int 3792 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param) 3793 { 3794 struct hns3_promisc_cfg_cmd *req; 3795 struct hns3_cmd_desc desc; 3796 int ret; 3797 3798 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false); 3799 3800 req = (struct hns3_promisc_cfg_cmd *)desc.data; 3801 req->vf_id = param->vf_id; 3802 req->flag = (param->enable << HNS3_PROMISC_EN_B) | 3803 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B; 3804 3805 ret = hns3_cmd_send(hw, &desc, 1); 3806 if (ret) 3807 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret); 3808 3809 return ret; 3810 } 3811 3812 static int 3813 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc) 3814 { 3815 struct hns3_promisc_param param; 3816 bool en_bc_pmc = true; 3817 uint8_t vf_id; 3818 3819 /* 3820 * In current version VF is not supported when PF is driven by DPDK 3821 * driver, just need to configure parameters for PF vport. 3822 */ 3823 vf_id = HNS3_PF_FUNC_ID; 3824 3825 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id); 3826 return hns3_cmd_set_promisc_mode(hw, ¶m); 3827 } 3828 3829 static int 3830 hns3_promisc_init(struct hns3_hw *hw) 3831 { 3832 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3833 struct hns3_pf *pf = &hns->pf; 3834 struct hns3_promisc_param param; 3835 uint16_t func_id; 3836 int ret; 3837 3838 ret = hns3_set_promisc_mode(hw, false, false); 3839 if (ret) { 3840 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret); 3841 return ret; 3842 } 3843 3844 /* 3845 * In current version VFs are not supported when PF is driven by DPDK 3846 * driver. After PF has been taken over by DPDK, the original VF will 3847 * be invalid. So, there is a possibility of entry residues. It should 3848 * clear VFs's promisc mode to avoid unnecessary bandwidth usage 3849 * during init. 3850 */ 3851 for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) { 3852 hns3_promisc_param_init(¶m, false, false, false, func_id); 3853 ret = hns3_cmd_set_promisc_mode(hw, ¶m); 3854 if (ret) { 3855 PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode," 3856 " ret = %d", func_id, ret); 3857 return ret; 3858 } 3859 } 3860 3861 return 0; 3862 } 3863 3864 static void 3865 hns3_promisc_uninit(struct hns3_hw *hw) 3866 { 3867 struct hns3_promisc_param param; 3868 uint16_t func_id; 3869 int ret; 3870 3871 func_id = HNS3_PF_FUNC_ID; 3872 3873 /* 3874 * In current version VFs are not supported when PF is driven by 3875 * DPDK driver, and VFs' promisc mode status has been cleared during 3876 * init and their status will not change. So just clear PF's promisc 3877 * mode status during uninit. 3878 */ 3879 hns3_promisc_param_init(¶m, false, false, false, func_id); 3880 ret = hns3_cmd_set_promisc_mode(hw, ¶m); 3881 if (ret) 3882 PMD_INIT_LOG(ERR, "failed to clear promisc status during" 3883 " uninit, ret = %d", ret); 3884 } 3885 3886 static int 3887 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev) 3888 { 3889 bool allmulti = dev->data->all_multicast ? true : false; 3890 struct hns3_adapter *hns = dev->data->dev_private; 3891 struct hns3_hw *hw = &hns->hw; 3892 uint64_t offloads; 3893 int err; 3894 int ret; 3895 3896 rte_spinlock_lock(&hw->lock); 3897 ret = hns3_set_promisc_mode(hw, true, true); 3898 if (ret) { 3899 rte_spinlock_unlock(&hw->lock); 3900 hns3_err(hw, "failed to enable promiscuous mode, ret = %d", 3901 ret); 3902 return ret; 3903 } 3904 3905 /* 3906 * When promiscuous mode was enabled, disable the vlan filter to let 3907 * all packets coming in in the receiving direction. 3908 */ 3909 offloads = dev->data->dev_conf.rxmode.offloads; 3910 if (offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) { 3911 ret = hns3_enable_vlan_filter(hns, false); 3912 if (ret) { 3913 hns3_err(hw, "failed to enable promiscuous mode due to " 3914 "failure to disable vlan filter, ret = %d", 3915 ret); 3916 err = hns3_set_promisc_mode(hw, false, allmulti); 3917 if (err) 3918 hns3_err(hw, "failed to restore promiscuous " 3919 "status after disable vlan filter " 3920 "failed during enabling promiscuous " 3921 "mode, ret = %d", ret); 3922 } 3923 } 3924 3925 rte_spinlock_unlock(&hw->lock); 3926 3927 return ret; 3928 } 3929 3930 static int 3931 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev) 3932 { 3933 bool allmulti = dev->data->all_multicast ? true : false; 3934 struct hns3_adapter *hns = dev->data->dev_private; 3935 struct hns3_hw *hw = &hns->hw; 3936 uint64_t offloads; 3937 int err; 3938 int ret; 3939 3940 /* If now in all_multicast mode, must remain in all_multicast mode. */ 3941 rte_spinlock_lock(&hw->lock); 3942 ret = hns3_set_promisc_mode(hw, false, allmulti); 3943 if (ret) { 3944 rte_spinlock_unlock(&hw->lock); 3945 hns3_err(hw, "failed to disable promiscuous mode, ret = %d", 3946 ret); 3947 return ret; 3948 } 3949 /* when promiscuous mode was disabled, restore the vlan filter status */ 3950 offloads = dev->data->dev_conf.rxmode.offloads; 3951 if (offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) { 3952 ret = hns3_enable_vlan_filter(hns, true); 3953 if (ret) { 3954 hns3_err(hw, "failed to disable promiscuous mode due to" 3955 " failure to restore vlan filter, ret = %d", 3956 ret); 3957 err = hns3_set_promisc_mode(hw, true, true); 3958 if (err) 3959 hns3_err(hw, "failed to restore promiscuous " 3960 "status after enabling vlan filter " 3961 "failed during disabling promiscuous " 3962 "mode, ret = %d", ret); 3963 } 3964 } 3965 rte_spinlock_unlock(&hw->lock); 3966 3967 return ret; 3968 } 3969 3970 static int 3971 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev) 3972 { 3973 struct hns3_adapter *hns = dev->data->dev_private; 3974 struct hns3_hw *hw = &hns->hw; 3975 int ret; 3976 3977 if (dev->data->promiscuous) 3978 return 0; 3979 3980 rte_spinlock_lock(&hw->lock); 3981 ret = hns3_set_promisc_mode(hw, false, true); 3982 rte_spinlock_unlock(&hw->lock); 3983 if (ret) 3984 hns3_err(hw, "failed to enable allmulticast mode, ret = %d", 3985 ret); 3986 3987 return ret; 3988 } 3989 3990 static int 3991 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev) 3992 { 3993 struct hns3_adapter *hns = dev->data->dev_private; 3994 struct hns3_hw *hw = &hns->hw; 3995 int ret; 3996 3997 /* If now in promiscuous mode, must remain in all_multicast mode. */ 3998 if (dev->data->promiscuous) 3999 return 0; 4000 4001 rte_spinlock_lock(&hw->lock); 4002 ret = hns3_set_promisc_mode(hw, false, false); 4003 rte_spinlock_unlock(&hw->lock); 4004 if (ret) 4005 hns3_err(hw, "failed to disable allmulticast mode, ret = %d", 4006 ret); 4007 4008 return ret; 4009 } 4010 4011 static int 4012 hns3_dev_promisc_restore(struct hns3_adapter *hns) 4013 { 4014 struct hns3_hw *hw = &hns->hw; 4015 bool allmulti = hw->data->all_multicast ? true : false; 4016 int ret; 4017 4018 if (hw->data->promiscuous) { 4019 ret = hns3_set_promisc_mode(hw, true, true); 4020 if (ret) 4021 hns3_err(hw, "failed to restore promiscuous mode, " 4022 "ret = %d", ret); 4023 return ret; 4024 } 4025 4026 ret = hns3_set_promisc_mode(hw, false, allmulti); 4027 if (ret) 4028 hns3_err(hw, "failed to restore allmulticast mode, ret = %d", 4029 ret); 4030 return ret; 4031 } 4032 4033 static int 4034 hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info) 4035 { 4036 struct hns3_sfp_info_cmd *resp; 4037 struct hns3_cmd_desc desc; 4038 int ret; 4039 4040 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true); 4041 resp = (struct hns3_sfp_info_cmd *)desc.data; 4042 resp->query_type = HNS3_ACTIVE_QUERY; 4043 4044 ret = hns3_cmd_send(hw, &desc, 1); 4045 if (ret == -EOPNOTSUPP) { 4046 hns3_warn(hw, "firmware does not support get SFP info," 4047 " ret = %d.", ret); 4048 return ret; 4049 } else if (ret) { 4050 hns3_err(hw, "get sfp info failed, ret = %d.", ret); 4051 return ret; 4052 } 4053 4054 /* 4055 * In some case, the speed of MAC obtained from firmware may be 0, it 4056 * shouldn't be set to mac->speed. 4057 */ 4058 if (!rte_le_to_cpu_32(resp->sfp_speed)) 4059 return 0; 4060 4061 mac_info->link_speed = rte_le_to_cpu_32(resp->sfp_speed); 4062 /* 4063 * if resp->supported_speed is 0, it means it's an old version 4064 * firmware, do not update these params. 4065 */ 4066 if (resp->supported_speed) { 4067 mac_info->query_type = HNS3_ACTIVE_QUERY; 4068 mac_info->supported_speed = 4069 rte_le_to_cpu_32(resp->supported_speed); 4070 mac_info->support_autoneg = resp->autoneg_ability; 4071 mac_info->link_autoneg = (resp->autoneg == 0) ? RTE_ETH_LINK_FIXED 4072 : RTE_ETH_LINK_AUTONEG; 4073 } else { 4074 mac_info->query_type = HNS3_DEFAULT_QUERY; 4075 } 4076 4077 return 0; 4078 } 4079 4080 static uint8_t 4081 hns3_check_speed_dup(uint8_t duplex, uint32_t speed) 4082 { 4083 if (!(speed == RTE_ETH_SPEED_NUM_10M || speed == RTE_ETH_SPEED_NUM_100M)) 4084 duplex = RTE_ETH_LINK_FULL_DUPLEX; 4085 4086 return duplex; 4087 } 4088 4089 static int 4090 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex) 4091 { 4092 struct hns3_mac *mac = &hw->mac; 4093 int ret; 4094 4095 duplex = hns3_check_speed_dup(duplex, speed); 4096 if (mac->link_speed == speed && mac->link_duplex == duplex) 4097 return 0; 4098 4099 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex); 4100 if (ret) 4101 return ret; 4102 4103 ret = hns3_port_shaper_update(hw, speed); 4104 if (ret) 4105 return ret; 4106 4107 mac->link_speed = speed; 4108 mac->link_duplex = duplex; 4109 4110 return 0; 4111 } 4112 4113 static int 4114 hns3_update_fiber_link_info(struct hns3_hw *hw) 4115 { 4116 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw); 4117 struct hns3_mac *mac = &hw->mac; 4118 struct hns3_mac mac_info; 4119 int ret; 4120 4121 /* If firmware do not support get SFP/qSFP speed, return directly */ 4122 if (!pf->support_sfp_query) 4123 return 0; 4124 4125 memset(&mac_info, 0, sizeof(struct hns3_mac)); 4126 ret = hns3_get_sfp_info(hw, &mac_info); 4127 if (ret == -EOPNOTSUPP) { 4128 pf->support_sfp_query = false; 4129 return ret; 4130 } else if (ret) 4131 return ret; 4132 4133 /* Do nothing if no SFP */ 4134 if (mac_info.link_speed == RTE_ETH_SPEED_NUM_NONE) 4135 return 0; 4136 4137 /* 4138 * If query_type is HNS3_ACTIVE_QUERY, it is no need 4139 * to reconfigure the speed of MAC. Otherwise, it indicates 4140 * that the current firmware only supports to obtain the 4141 * speed of the SFP, and the speed of MAC needs to reconfigure. 4142 */ 4143 mac->query_type = mac_info.query_type; 4144 if (mac->query_type == HNS3_ACTIVE_QUERY) { 4145 if (mac_info.link_speed != mac->link_speed) { 4146 ret = hns3_port_shaper_update(hw, mac_info.link_speed); 4147 if (ret) 4148 return ret; 4149 } 4150 4151 mac->link_speed = mac_info.link_speed; 4152 mac->supported_speed = mac_info.supported_speed; 4153 mac->support_autoneg = mac_info.support_autoneg; 4154 mac->link_autoneg = mac_info.link_autoneg; 4155 4156 return 0; 4157 } 4158 4159 /* Config full duplex for SFP */ 4160 return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed, 4161 RTE_ETH_LINK_FULL_DUPLEX); 4162 } 4163 4164 static void 4165 hns3_parse_copper_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac) 4166 { 4167 #define HNS3_PHY_SUPPORTED_SPEED_MASK 0x2f 4168 4169 struct hns3_phy_params_bd0_cmd *req; 4170 uint32_t supported; 4171 4172 req = (struct hns3_phy_params_bd0_cmd *)desc[0].data; 4173 mac->link_speed = rte_le_to_cpu_32(req->speed); 4174 mac->link_duplex = hns3_get_bit(req->duplex, 4175 HNS3_PHY_DUPLEX_CFG_B); 4176 mac->link_autoneg = hns3_get_bit(req->autoneg, 4177 HNS3_PHY_AUTONEG_CFG_B); 4178 mac->advertising = rte_le_to_cpu_32(req->advertising); 4179 mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising); 4180 supported = rte_le_to_cpu_32(req->supported); 4181 mac->supported_speed = supported & HNS3_PHY_SUPPORTED_SPEED_MASK; 4182 mac->support_autoneg = !!(supported & HNS3_PHY_LINK_MODE_AUTONEG_BIT); 4183 } 4184 4185 static int 4186 hns3_get_copper_phy_params(struct hns3_hw *hw, struct hns3_mac *mac) 4187 { 4188 struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM]; 4189 uint16_t i; 4190 int ret; 4191 4192 for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) { 4193 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, 4194 true); 4195 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 4196 } 4197 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true); 4198 4199 ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM); 4200 if (ret) { 4201 hns3_err(hw, "get phy parameters failed, ret = %d.", ret); 4202 return ret; 4203 } 4204 4205 hns3_parse_copper_phy_params(desc, mac); 4206 4207 return 0; 4208 } 4209 4210 static int 4211 hns3_update_copper_link_info(struct hns3_hw *hw) 4212 { 4213 struct hns3_mac *mac = &hw->mac; 4214 struct hns3_mac mac_info; 4215 int ret; 4216 4217 memset(&mac_info, 0, sizeof(struct hns3_mac)); 4218 ret = hns3_get_copper_phy_params(hw, &mac_info); 4219 if (ret) 4220 return ret; 4221 4222 if (mac_info.link_speed != mac->link_speed) { 4223 ret = hns3_port_shaper_update(hw, mac_info.link_speed); 4224 if (ret) 4225 return ret; 4226 } 4227 4228 mac->link_speed = mac_info.link_speed; 4229 mac->link_duplex = mac_info.link_duplex; 4230 mac->link_autoneg = mac_info.link_autoneg; 4231 mac->supported_speed = mac_info.supported_speed; 4232 mac->advertising = mac_info.advertising; 4233 mac->lp_advertising = mac_info.lp_advertising; 4234 mac->support_autoneg = mac_info.support_autoneg; 4235 4236 return 0; 4237 } 4238 4239 static int 4240 hns3_update_link_info(struct rte_eth_dev *eth_dev) 4241 { 4242 struct hns3_adapter *hns = eth_dev->data->dev_private; 4243 struct hns3_hw *hw = &hns->hw; 4244 4245 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) 4246 return hns3_update_copper_link_info(hw); 4247 4248 return hns3_update_fiber_link_info(hw); 4249 } 4250 4251 static int 4252 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable) 4253 { 4254 struct hns3_config_mac_mode_cmd *req; 4255 struct hns3_cmd_desc desc; 4256 uint32_t loop_en = 0; 4257 uint8_t val = 0; 4258 int ret; 4259 4260 req = (struct hns3_config_mac_mode_cmd *)desc.data; 4261 4262 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false); 4263 if (enable) 4264 val = 1; 4265 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val); 4266 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val); 4267 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val); 4268 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val); 4269 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0); 4270 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0); 4271 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0); 4272 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0); 4273 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val); 4274 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val); 4275 4276 /* 4277 * If RTE_ETH_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC 4278 * when receiving frames. Otherwise, CRC will be stripped. 4279 */ 4280 if (hw->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC) 4281 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0); 4282 else 4283 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val); 4284 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val); 4285 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val); 4286 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val); 4287 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en); 4288 4289 ret = hns3_cmd_send(hw, &desc, 1); 4290 if (ret) 4291 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret); 4292 4293 return ret; 4294 } 4295 4296 static int 4297 hns3_get_mac_link_status(struct hns3_hw *hw) 4298 { 4299 struct hns3_link_status_cmd *req; 4300 struct hns3_cmd_desc desc; 4301 int link_status; 4302 int ret; 4303 4304 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true); 4305 ret = hns3_cmd_send(hw, &desc, 1); 4306 if (ret) { 4307 hns3_err(hw, "get link status cmd failed %d", ret); 4308 return RTE_ETH_LINK_DOWN; 4309 } 4310 4311 req = (struct hns3_link_status_cmd *)desc.data; 4312 link_status = req->status & HNS3_LINK_STATUS_UP_M; 4313 4314 return !!link_status; 4315 } 4316 4317 static bool 4318 hns3_update_link_status(struct hns3_hw *hw) 4319 { 4320 int state; 4321 4322 state = hns3_get_mac_link_status(hw); 4323 if (state != hw->mac.link_status) { 4324 hw->mac.link_status = state; 4325 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down"); 4326 return true; 4327 } 4328 4329 return false; 4330 } 4331 4332 void 4333 hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query) 4334 { 4335 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; 4336 struct rte_eth_link new_link; 4337 int ret; 4338 4339 if (query) 4340 hns3_update_port_link_info(dev); 4341 4342 memset(&new_link, 0, sizeof(new_link)); 4343 hns3_setup_linkstatus(dev, &new_link); 4344 4345 ret = rte_eth_linkstatus_set(dev, &new_link); 4346 if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0) 4347 hns3_start_report_lse(dev); 4348 } 4349 4350 static void 4351 hns3_service_handler(void *param) 4352 { 4353 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 4354 struct hns3_adapter *hns = eth_dev->data->dev_private; 4355 struct hns3_hw *hw = &hns->hw; 4356 4357 if (!hns3_is_reset_pending(hns)) { 4358 hns3_update_linkstatus_and_event(hw, true); 4359 hns3_update_hw_stats(hw); 4360 } else { 4361 hns3_warn(hw, "Cancel the query when reset is pending"); 4362 } 4363 4364 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev); 4365 } 4366 4367 static int 4368 hns3_init_hardware(struct hns3_adapter *hns) 4369 { 4370 struct hns3_hw *hw = &hns->hw; 4371 int ret; 4372 4373 /* 4374 * All queue-related HW operations must be performed after the TCAM 4375 * table is configured. 4376 */ 4377 ret = hns3_map_tqp(hw); 4378 if (ret) { 4379 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret); 4380 return ret; 4381 } 4382 4383 ret = hns3_init_umv_space(hw); 4384 if (ret) { 4385 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret); 4386 return ret; 4387 } 4388 4389 ret = hns3_mac_init(hw); 4390 if (ret) { 4391 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret); 4392 goto err_mac_init; 4393 } 4394 4395 ret = hns3_init_mgr_tbl(hw); 4396 if (ret) { 4397 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret); 4398 goto err_mac_init; 4399 } 4400 4401 ret = hns3_promisc_init(hw); 4402 if (ret) { 4403 PMD_INIT_LOG(ERR, "Failed to init promisc: %d", 4404 ret); 4405 goto err_mac_init; 4406 } 4407 4408 ret = hns3_init_vlan_config(hns); 4409 if (ret) { 4410 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret); 4411 goto err_mac_init; 4412 } 4413 4414 ret = hns3_dcb_init(hw); 4415 if (ret) { 4416 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret); 4417 goto err_mac_init; 4418 } 4419 4420 ret = hns3_init_fd_config(hns); 4421 if (ret) { 4422 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret); 4423 goto err_mac_init; 4424 } 4425 4426 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX); 4427 if (ret) { 4428 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret); 4429 goto err_mac_init; 4430 } 4431 4432 ret = hns3_config_gro(hw, false); 4433 if (ret) { 4434 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret); 4435 goto err_mac_init; 4436 } 4437 4438 /* 4439 * In the initialization clearing the all hardware mapping relationship 4440 * configurations between queues and interrupt vectors is needed, so 4441 * some error caused by the residual configurations, such as the 4442 * unexpected interrupt, can be avoid. 4443 */ 4444 ret = hns3_init_ring_with_vector(hw); 4445 if (ret) { 4446 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret); 4447 goto err_mac_init; 4448 } 4449 4450 return 0; 4451 4452 err_mac_init: 4453 hns3_uninit_umv_space(hw); 4454 return ret; 4455 } 4456 4457 static int 4458 hns3_clear_hw(struct hns3_hw *hw) 4459 { 4460 struct hns3_cmd_desc desc; 4461 int ret; 4462 4463 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false); 4464 4465 ret = hns3_cmd_send(hw, &desc, 1); 4466 if (ret && ret != -EOPNOTSUPP) 4467 return ret; 4468 4469 return 0; 4470 } 4471 4472 static void 4473 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable) 4474 { 4475 uint32_t val; 4476 4477 /* 4478 * The new firmware support report more hardware error types by 4479 * msix mode. These errors are defined as RAS errors in hardware 4480 * and belong to a different type from the MSI-x errors processed 4481 * by the network driver. 4482 * 4483 * Network driver should open the new error report on initialization. 4484 */ 4485 val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); 4486 hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0); 4487 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val); 4488 } 4489 4490 static uint32_t 4491 hns3_set_firber_default_support_speed(struct hns3_hw *hw) 4492 { 4493 struct hns3_mac *mac = &hw->mac; 4494 4495 switch (mac->link_speed) { 4496 case RTE_ETH_SPEED_NUM_1G: 4497 return HNS3_FIBER_LINK_SPEED_1G_BIT; 4498 case RTE_ETH_SPEED_NUM_10G: 4499 return HNS3_FIBER_LINK_SPEED_10G_BIT; 4500 case RTE_ETH_SPEED_NUM_25G: 4501 return HNS3_FIBER_LINK_SPEED_25G_BIT; 4502 case RTE_ETH_SPEED_NUM_40G: 4503 return HNS3_FIBER_LINK_SPEED_40G_BIT; 4504 case RTE_ETH_SPEED_NUM_50G: 4505 return HNS3_FIBER_LINK_SPEED_50G_BIT; 4506 case RTE_ETH_SPEED_NUM_100G: 4507 return HNS3_FIBER_LINK_SPEED_100G_BIT; 4508 case RTE_ETH_SPEED_NUM_200G: 4509 return HNS3_FIBER_LINK_SPEED_200G_BIT; 4510 default: 4511 hns3_warn(hw, "invalid speed %u Mbps.", mac->link_speed); 4512 return 0; 4513 } 4514 } 4515 4516 /* 4517 * Validity of supported_speed for fiber and copper media type can be 4518 * guaranteed by the following policy: 4519 * Copper: 4520 * Although the initialization of the phy in the firmware may not be 4521 * completed, the firmware can guarantees that the supported_speed is 4522 * an valid value. 4523 * Firber: 4524 * If the version of firmware supports the active query way of the 4525 * HNS3_OPC_GET_SFP_INFO opcode, the supported_speed can be obtained 4526 * through it. If unsupported, use the SFP's speed as the value of the 4527 * supported_speed. 4528 */ 4529 static int 4530 hns3_get_port_supported_speed(struct rte_eth_dev *eth_dev) 4531 { 4532 struct hns3_adapter *hns = eth_dev->data->dev_private; 4533 struct hns3_hw *hw = &hns->hw; 4534 struct hns3_mac *mac = &hw->mac; 4535 int ret; 4536 4537 ret = hns3_update_link_info(eth_dev); 4538 if (ret) 4539 return ret; 4540 4541 if (mac->media_type == HNS3_MEDIA_TYPE_FIBER || 4542 mac->media_type == HNS3_MEDIA_TYPE_BACKPLANE) { 4543 /* 4544 * Some firmware does not support the report of supported_speed, 4545 * and only report the effective speed of SFP/backplane. In this 4546 * case, it is necessary to use the SFP/backplane's speed as the 4547 * supported_speed. 4548 */ 4549 if (mac->supported_speed == 0) 4550 mac->supported_speed = 4551 hns3_set_firber_default_support_speed(hw); 4552 } 4553 4554 return 0; 4555 } 4556 4557 static void 4558 hns3_get_fc_autoneg_capability(struct hns3_adapter *hns) 4559 { 4560 struct hns3_mac *mac = &hns->hw.mac; 4561 4562 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) { 4563 hns->pf.support_fc_autoneg = true; 4564 return; 4565 } 4566 4567 /* 4568 * Flow control auto-negotiation requires the cooperation of the driver 4569 * and firmware. Currently, the optical port does not support flow 4570 * control auto-negotiation. 4571 */ 4572 hns->pf.support_fc_autoneg = false; 4573 } 4574 4575 static int 4576 hns3_init_pf(struct rte_eth_dev *eth_dev) 4577 { 4578 struct rte_device *dev = eth_dev->device; 4579 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev); 4580 struct hns3_adapter *hns = eth_dev->data->dev_private; 4581 struct hns3_hw *hw = &hns->hw; 4582 int ret; 4583 4584 PMD_INIT_FUNC_TRACE(); 4585 4586 /* Get hardware io base address from pcie BAR2 IO space */ 4587 hw->io_base = pci_dev->mem_resource[2].addr; 4588 4589 /* Firmware command queue initialize */ 4590 ret = hns3_cmd_init_queue(hw); 4591 if (ret) { 4592 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret); 4593 goto err_cmd_init_queue; 4594 } 4595 4596 hns3_clear_all_event_cause(hw); 4597 4598 /* Firmware command initialize */ 4599 ret = hns3_cmd_init(hw); 4600 if (ret) { 4601 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret); 4602 goto err_cmd_init; 4603 } 4604 4605 hns3_tx_push_init(eth_dev); 4606 4607 /* 4608 * To ensure that the hardware environment is clean during 4609 * initialization, the driver actively clear the hardware environment 4610 * during initialization, including PF and corresponding VFs' vlan, mac, 4611 * flow table configurations, etc. 4612 */ 4613 ret = hns3_clear_hw(hw); 4614 if (ret) { 4615 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret); 4616 goto err_cmd_init; 4617 } 4618 4619 hns3_config_all_msix_error(hw, true); 4620 4621 ret = rte_intr_callback_register(pci_dev->intr_handle, 4622 hns3_interrupt_handler, 4623 eth_dev); 4624 if (ret) { 4625 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret); 4626 goto err_intr_callback_register; 4627 } 4628 4629 ret = hns3_ptp_init(hw); 4630 if (ret) 4631 goto err_get_config; 4632 4633 /* Enable interrupt */ 4634 rte_intr_enable(pci_dev->intr_handle); 4635 hns3_pf_enable_irq0(hw); 4636 4637 /* Get configuration */ 4638 ret = hns3_get_configuration(hw); 4639 if (ret) { 4640 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret); 4641 goto err_get_config; 4642 } 4643 4644 ret = hns3_stats_init(hw); 4645 if (ret) 4646 goto err_get_config; 4647 4648 ret = hns3_init_hardware(hns); 4649 if (ret) { 4650 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret); 4651 goto err_init_hw; 4652 } 4653 4654 /* Initialize flow director filter list & hash */ 4655 ret = hns3_fdir_filter_init(hns); 4656 if (ret) { 4657 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret); 4658 goto err_fdir; 4659 } 4660 4661 hns3_rss_set_default_args(hw); 4662 4663 ret = hns3_enable_hw_error_intr(hns, true); 4664 if (ret) { 4665 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d", 4666 ret); 4667 goto err_enable_intr; 4668 } 4669 4670 ret = hns3_get_port_supported_speed(eth_dev); 4671 if (ret) { 4672 PMD_INIT_LOG(ERR, "failed to get speed capabilities supported " 4673 "by device, ret = %d.", ret); 4674 goto err_supported_speed; 4675 } 4676 4677 hns3_get_fc_autoneg_capability(hns); 4678 4679 hns3_tm_conf_init(eth_dev); 4680 4681 return 0; 4682 4683 err_supported_speed: 4684 (void)hns3_enable_hw_error_intr(hns, false); 4685 err_enable_intr: 4686 hns3_fdir_filter_uninit(hns); 4687 err_fdir: 4688 hns3_uninit_umv_space(hw); 4689 err_init_hw: 4690 hns3_stats_uninit(hw); 4691 err_get_config: 4692 hns3_pf_disable_irq0(hw); 4693 rte_intr_disable(pci_dev->intr_handle); 4694 hns3_intr_unregister(pci_dev->intr_handle, hns3_interrupt_handler, 4695 eth_dev); 4696 err_intr_callback_register: 4697 err_cmd_init: 4698 hns3_cmd_uninit(hw); 4699 hns3_cmd_destroy_queue(hw); 4700 err_cmd_init_queue: 4701 hw->io_base = NULL; 4702 4703 return ret; 4704 } 4705 4706 static void 4707 hns3_uninit_pf(struct rte_eth_dev *eth_dev) 4708 { 4709 struct hns3_adapter *hns = eth_dev->data->dev_private; 4710 struct rte_device *dev = eth_dev->device; 4711 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev); 4712 struct hns3_hw *hw = &hns->hw; 4713 4714 PMD_INIT_FUNC_TRACE(); 4715 4716 hns3_tm_conf_uninit(eth_dev); 4717 hns3_enable_hw_error_intr(hns, false); 4718 hns3_rss_uninit(hns); 4719 (void)hns3_config_gro(hw, false); 4720 hns3_promisc_uninit(hw); 4721 hns3_flow_uninit(eth_dev); 4722 hns3_fdir_filter_uninit(hns); 4723 hns3_uninit_umv_space(hw); 4724 hns3_stats_uninit(hw); 4725 hns3_config_mac_tnl_int(hw, false); 4726 hns3_pf_disable_irq0(hw); 4727 rte_intr_disable(pci_dev->intr_handle); 4728 hns3_intr_unregister(pci_dev->intr_handle, hns3_interrupt_handler, 4729 eth_dev); 4730 hns3_config_all_msix_error(hw, false); 4731 hns3_cmd_uninit(hw); 4732 hns3_cmd_destroy_queue(hw); 4733 hw->io_base = NULL; 4734 } 4735 4736 static uint32_t 4737 hns3_convert_link_speeds2bitmap_copper(uint32_t link_speeds) 4738 { 4739 uint32_t speed_bit; 4740 4741 switch (link_speeds & ~RTE_ETH_LINK_SPEED_FIXED) { 4742 case RTE_ETH_LINK_SPEED_10M: 4743 speed_bit = HNS3_PHY_LINK_SPEED_10M_BIT; 4744 break; 4745 case RTE_ETH_LINK_SPEED_10M_HD: 4746 speed_bit = HNS3_PHY_LINK_SPEED_10M_HD_BIT; 4747 break; 4748 case RTE_ETH_LINK_SPEED_100M: 4749 speed_bit = HNS3_PHY_LINK_SPEED_100M_BIT; 4750 break; 4751 case RTE_ETH_LINK_SPEED_100M_HD: 4752 speed_bit = HNS3_PHY_LINK_SPEED_100M_HD_BIT; 4753 break; 4754 case RTE_ETH_LINK_SPEED_1G: 4755 speed_bit = HNS3_PHY_LINK_SPEED_1000M_BIT; 4756 break; 4757 default: 4758 speed_bit = 0; 4759 break; 4760 } 4761 4762 return speed_bit; 4763 } 4764 4765 static uint32_t 4766 hns3_convert_link_speeds2bitmap_fiber(uint32_t link_speeds) 4767 { 4768 uint32_t speed_bit; 4769 4770 switch (link_speeds & ~RTE_ETH_LINK_SPEED_FIXED) { 4771 case RTE_ETH_LINK_SPEED_1G: 4772 speed_bit = HNS3_FIBER_LINK_SPEED_1G_BIT; 4773 break; 4774 case RTE_ETH_LINK_SPEED_10G: 4775 speed_bit = HNS3_FIBER_LINK_SPEED_10G_BIT; 4776 break; 4777 case RTE_ETH_LINK_SPEED_25G: 4778 speed_bit = HNS3_FIBER_LINK_SPEED_25G_BIT; 4779 break; 4780 case RTE_ETH_LINK_SPEED_40G: 4781 speed_bit = HNS3_FIBER_LINK_SPEED_40G_BIT; 4782 break; 4783 case RTE_ETH_LINK_SPEED_50G: 4784 speed_bit = HNS3_FIBER_LINK_SPEED_50G_BIT; 4785 break; 4786 case RTE_ETH_LINK_SPEED_100G: 4787 speed_bit = HNS3_FIBER_LINK_SPEED_100G_BIT; 4788 break; 4789 case RTE_ETH_LINK_SPEED_200G: 4790 speed_bit = HNS3_FIBER_LINK_SPEED_200G_BIT; 4791 break; 4792 default: 4793 speed_bit = 0; 4794 break; 4795 } 4796 4797 return speed_bit; 4798 } 4799 4800 static int 4801 hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds) 4802 { 4803 struct hns3_mac *mac = &hw->mac; 4804 uint32_t supported_speed = mac->supported_speed; 4805 uint32_t speed_bit = 0; 4806 4807 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) 4808 speed_bit = hns3_convert_link_speeds2bitmap_copper(link_speeds); 4809 else 4810 speed_bit = hns3_convert_link_speeds2bitmap_fiber(link_speeds); 4811 4812 if (!(speed_bit & supported_speed)) { 4813 hns3_err(hw, "link_speeds(0x%x) exceeds the supported speed capability or is incorrect.", 4814 link_speeds); 4815 return -EINVAL; 4816 } 4817 4818 return 0; 4819 } 4820 4821 static uint32_t 4822 hns3_get_link_speed(uint32_t link_speeds) 4823 { 4824 uint32_t speed = RTE_ETH_SPEED_NUM_NONE; 4825 4826 if (link_speeds & RTE_ETH_LINK_SPEED_10M || 4827 link_speeds & RTE_ETH_LINK_SPEED_10M_HD) 4828 speed = RTE_ETH_SPEED_NUM_10M; 4829 if (link_speeds & RTE_ETH_LINK_SPEED_100M || 4830 link_speeds & RTE_ETH_LINK_SPEED_100M_HD) 4831 speed = RTE_ETH_SPEED_NUM_100M; 4832 if (link_speeds & RTE_ETH_LINK_SPEED_1G) 4833 speed = RTE_ETH_SPEED_NUM_1G; 4834 if (link_speeds & RTE_ETH_LINK_SPEED_10G) 4835 speed = RTE_ETH_SPEED_NUM_10G; 4836 if (link_speeds & RTE_ETH_LINK_SPEED_25G) 4837 speed = RTE_ETH_SPEED_NUM_25G; 4838 if (link_speeds & RTE_ETH_LINK_SPEED_40G) 4839 speed = RTE_ETH_SPEED_NUM_40G; 4840 if (link_speeds & RTE_ETH_LINK_SPEED_50G) 4841 speed = RTE_ETH_SPEED_NUM_50G; 4842 if (link_speeds & RTE_ETH_LINK_SPEED_100G) 4843 speed = RTE_ETH_SPEED_NUM_100G; 4844 if (link_speeds & RTE_ETH_LINK_SPEED_200G) 4845 speed = RTE_ETH_SPEED_NUM_200G; 4846 4847 return speed; 4848 } 4849 4850 static uint8_t 4851 hns3_get_link_duplex(uint32_t link_speeds) 4852 { 4853 if ((link_speeds & RTE_ETH_LINK_SPEED_10M_HD) || 4854 (link_speeds & RTE_ETH_LINK_SPEED_100M_HD)) 4855 return RTE_ETH_LINK_HALF_DUPLEX; 4856 else 4857 return RTE_ETH_LINK_FULL_DUPLEX; 4858 } 4859 4860 static int 4861 hns3_set_copper_port_link_speed(struct hns3_hw *hw, 4862 struct hns3_set_link_speed_cfg *cfg) 4863 { 4864 struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM]; 4865 struct hns3_phy_params_bd0_cmd *req; 4866 uint16_t i; 4867 4868 for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) { 4869 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, 4870 false); 4871 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 4872 } 4873 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, false); 4874 req = (struct hns3_phy_params_bd0_cmd *)desc[0].data; 4875 req->autoneg = cfg->autoneg; 4876 4877 /* 4878 * The full speed capability is used to negotiate when 4879 * auto-negotiation is enabled. 4880 */ 4881 if (cfg->autoneg) { 4882 req->advertising = HNS3_PHY_LINK_SPEED_10M_BIT | 4883 HNS3_PHY_LINK_SPEED_10M_HD_BIT | 4884 HNS3_PHY_LINK_SPEED_100M_BIT | 4885 HNS3_PHY_LINK_SPEED_100M_HD_BIT | 4886 HNS3_PHY_LINK_SPEED_1000M_BIT; 4887 } else { 4888 req->speed = cfg->speed; 4889 req->duplex = cfg->duplex; 4890 } 4891 4892 return hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM); 4893 } 4894 4895 static int 4896 hns3_set_autoneg(struct hns3_hw *hw, bool enable) 4897 { 4898 struct hns3_config_auto_neg_cmd *req; 4899 struct hns3_cmd_desc desc; 4900 uint32_t flag = 0; 4901 int ret; 4902 4903 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_AN_MODE, false); 4904 4905 req = (struct hns3_config_auto_neg_cmd *)desc.data; 4906 if (enable) 4907 hns3_set_bit(flag, HNS3_MAC_CFG_AN_EN_B, 1); 4908 req->cfg_an_cmd_flag = rte_cpu_to_le_32(flag); 4909 4910 ret = hns3_cmd_send(hw, &desc, 1); 4911 if (ret) 4912 hns3_err(hw, "autoneg set cmd failed, ret = %d.", ret); 4913 4914 return ret; 4915 } 4916 4917 static int 4918 hns3_set_fiber_port_link_speed(struct hns3_hw *hw, 4919 struct hns3_set_link_speed_cfg *cfg) 4920 { 4921 int ret; 4922 4923 if (hw->mac.support_autoneg) { 4924 ret = hns3_set_autoneg(hw, cfg->autoneg); 4925 if (ret) { 4926 hns3_err(hw, "failed to configure auto-negotiation."); 4927 return ret; 4928 } 4929 4930 /* 4931 * To enable auto-negotiation, we only need to open the switch 4932 * of auto-negotiation, then firmware sets all speed 4933 * capabilities. 4934 */ 4935 if (cfg->autoneg) 4936 return 0; 4937 } 4938 4939 /* 4940 * Some hardware doesn't support auto-negotiation, but users may not 4941 * configure link_speeds (default 0), which means auto-negotiation. 4942 * In this case, a warning message need to be printed, instead of 4943 * an error. 4944 */ 4945 if (cfg->autoneg) { 4946 hns3_warn(hw, "auto-negotiation is not supported, use default fixed speed!"); 4947 return 0; 4948 } 4949 4950 return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->duplex); 4951 } 4952 4953 static const char * 4954 hns3_get_media_type_name(uint8_t media_type) 4955 { 4956 if (media_type == HNS3_MEDIA_TYPE_FIBER) 4957 return "fiber"; 4958 else if (media_type == HNS3_MEDIA_TYPE_COPPER) 4959 return "copper"; 4960 else if (media_type == HNS3_MEDIA_TYPE_BACKPLANE) 4961 return "backplane"; 4962 else 4963 return "unknown"; 4964 } 4965 4966 static int 4967 hns3_set_port_link_speed(struct hns3_hw *hw, 4968 struct hns3_set_link_speed_cfg *cfg) 4969 { 4970 int ret; 4971 4972 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) 4973 ret = hns3_set_copper_port_link_speed(hw, cfg); 4974 else 4975 ret = hns3_set_fiber_port_link_speed(hw, cfg); 4976 4977 if (ret) { 4978 hns3_err(hw, "failed to set %s port link speed, ret = %d.", 4979 hns3_get_media_type_name(hw->mac.media_type), 4980 ret); 4981 return ret; 4982 } 4983 4984 return 0; 4985 } 4986 4987 static int 4988 hns3_apply_link_speed(struct hns3_hw *hw) 4989 { 4990 struct rte_eth_conf *conf = &hw->data->dev_conf; 4991 struct hns3_set_link_speed_cfg cfg; 4992 4993 memset(&cfg, 0, sizeof(struct hns3_set_link_speed_cfg)); 4994 cfg.autoneg = (conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) ? 4995 RTE_ETH_LINK_AUTONEG : RTE_ETH_LINK_FIXED; 4996 if (cfg.autoneg != RTE_ETH_LINK_AUTONEG) { 4997 cfg.speed = hns3_get_link_speed(conf->link_speeds); 4998 cfg.duplex = hns3_get_link_duplex(conf->link_speeds); 4999 } 5000 5001 return hns3_set_port_link_speed(hw, &cfg); 5002 } 5003 5004 static int 5005 hns3_do_start(struct hns3_adapter *hns, bool reset_queue) 5006 { 5007 struct hns3_hw *hw = &hns->hw; 5008 bool link_en; 5009 int ret; 5010 5011 ret = hns3_update_queue_map_configure(hns); 5012 if (ret) { 5013 hns3_err(hw, "failed to update queue mapping configuration, ret = %d", 5014 ret); 5015 return ret; 5016 } 5017 5018 /* Note: hns3_tm_conf_update must be called after configuring DCB. */ 5019 ret = hns3_tm_conf_update(hw); 5020 if (ret) { 5021 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret); 5022 return ret; 5023 } 5024 5025 hns3_enable_rxd_adv_layout(hw); 5026 5027 ret = hns3_init_queues(hns, reset_queue); 5028 if (ret) { 5029 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret); 5030 return ret; 5031 } 5032 5033 link_en = hw->set_link_down ? false : true; 5034 ret = hns3_cfg_mac_mode(hw, link_en); 5035 if (ret) { 5036 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret); 5037 goto err_config_mac_mode; 5038 } 5039 5040 ret = hns3_apply_link_speed(hw); 5041 if (ret) 5042 goto err_set_link_speed; 5043 5044 return 0; 5045 5046 err_set_link_speed: 5047 (void)hns3_cfg_mac_mode(hw, false); 5048 5049 err_config_mac_mode: 5050 hns3_dev_release_mbufs(hns); 5051 /* 5052 * Here is exception handling, hns3_reset_all_tqps will have the 5053 * corresponding error message if it is handled incorrectly, so it is 5054 * not necessary to check hns3_reset_all_tqps return value, here keep 5055 * ret as the error code causing the exception. 5056 */ 5057 (void)hns3_reset_all_tqps(hns); 5058 return ret; 5059 } 5060 5061 static void 5062 hns3_restore_filter(struct rte_eth_dev *dev) 5063 { 5064 hns3_restore_rss_filter(dev); 5065 } 5066 5067 static int 5068 hns3_dev_start(struct rte_eth_dev *dev) 5069 { 5070 struct hns3_adapter *hns = dev->data->dev_private; 5071 struct hns3_hw *hw = &hns->hw; 5072 bool old_state = hw->set_link_down; 5073 int ret; 5074 5075 PMD_INIT_FUNC_TRACE(); 5076 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) 5077 return -EBUSY; 5078 5079 rte_spinlock_lock(&hw->lock); 5080 hw->adapter_state = HNS3_NIC_STARTING; 5081 5082 /* 5083 * If the dev_set_link_down() API has been called, the "set_link_down" 5084 * flag can be cleared by dev_start() API. In addition, the flag should 5085 * also be cleared before calling hns3_do_start() so that MAC can be 5086 * enabled in dev_start stage. 5087 */ 5088 hw->set_link_down = false; 5089 ret = hns3_do_start(hns, true); 5090 if (ret) 5091 goto do_start_fail; 5092 5093 ret = hns3_map_rx_interrupt(dev); 5094 if (ret) 5095 goto map_rx_inter_err; 5096 5097 /* 5098 * There are three register used to control the status of a TQP 5099 * (contains a pair of Tx queue and Rx queue) in the new version network 5100 * engine. One is used to control the enabling of Tx queue, the other is 5101 * used to control the enabling of Rx queue, and the last is the master 5102 * switch used to control the enabling of the tqp. The Tx register and 5103 * TQP register must be enabled at the same time to enable a Tx queue. 5104 * The same applies to the Rx queue. For the older network engine, this 5105 * function only refresh the enabled flag, and it is used to update the 5106 * status of queue in the dpdk framework. 5107 */ 5108 ret = hns3_start_all_txqs(dev); 5109 if (ret) 5110 goto map_rx_inter_err; 5111 5112 ret = hns3_start_all_rxqs(dev); 5113 if (ret) 5114 goto start_all_rxqs_fail; 5115 5116 hw->adapter_state = HNS3_NIC_STARTED; 5117 rte_spinlock_unlock(&hw->lock); 5118 5119 hns3_rx_scattered_calc(dev); 5120 hns3_set_rxtx_function(dev); 5121 hns3_mp_req_start_rxtx(dev); 5122 5123 hns3_restore_filter(dev); 5124 5125 /* Enable interrupt of all rx queues before enabling queues */ 5126 hns3_dev_all_rx_queue_intr_enable(hw, true); 5127 5128 /* 5129 * After finished the initialization, enable tqps to receive/transmit 5130 * packets and refresh all queue status. 5131 */ 5132 hns3_start_tqps(hw); 5133 5134 hns3_tm_dev_start_proc(hw); 5135 5136 if (dev->data->dev_conf.intr_conf.lsc != 0) 5137 hns3_dev_link_update(dev, 0); 5138 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev); 5139 5140 hns3_info(hw, "hns3 dev start successful!"); 5141 5142 return 0; 5143 5144 start_all_rxqs_fail: 5145 hns3_stop_all_txqs(dev); 5146 map_rx_inter_err: 5147 (void)hns3_do_stop(hns); 5148 do_start_fail: 5149 hw->set_link_down = old_state; 5150 hw->adapter_state = HNS3_NIC_CONFIGURED; 5151 rte_spinlock_unlock(&hw->lock); 5152 5153 return ret; 5154 } 5155 5156 static int 5157 hns3_do_stop(struct hns3_adapter *hns) 5158 { 5159 struct hns3_hw *hw = &hns->hw; 5160 int ret; 5161 5162 /* 5163 * The "hns3_do_stop" function will also be called by .stop_service to 5164 * prepare reset. At the time of global or IMP reset, the command cannot 5165 * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be 5166 * accessed during the reset process. So the mbuf can not be released 5167 * during reset and is required to be released after the reset is 5168 * completed. 5169 */ 5170 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) 5171 hns3_dev_release_mbufs(hns); 5172 5173 ret = hns3_cfg_mac_mode(hw, false); 5174 if (ret) 5175 return ret; 5176 hw->mac.link_status = RTE_ETH_LINK_DOWN; 5177 5178 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) { 5179 hns3_configure_all_mac_addr(hns, true); 5180 ret = hns3_reset_all_tqps(hns); 5181 if (ret) { 5182 hns3_err(hw, "failed to reset all queues ret = %d.", 5183 ret); 5184 return ret; 5185 } 5186 } 5187 5188 return 0; 5189 } 5190 5191 static int 5192 hns3_dev_stop(struct rte_eth_dev *dev) 5193 { 5194 struct hns3_adapter *hns = dev->data->dev_private; 5195 struct hns3_hw *hw = &hns->hw; 5196 5197 PMD_INIT_FUNC_TRACE(); 5198 dev->data->dev_started = 0; 5199 5200 hw->adapter_state = HNS3_NIC_STOPPING; 5201 hns3_set_rxtx_function(dev); 5202 rte_wmb(); 5203 /* Disable datapath on secondary process. */ 5204 hns3_mp_req_stop_rxtx(dev); 5205 /* Prevent crashes when queues are still in use. */ 5206 rte_delay_ms(hw->cfg_max_queues); 5207 5208 rte_spinlock_lock(&hw->lock); 5209 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) { 5210 hns3_tm_dev_stop_proc(hw); 5211 hns3_config_mac_tnl_int(hw, false); 5212 hns3_stop_tqps(hw); 5213 hns3_do_stop(hns); 5214 hns3_unmap_rx_interrupt(dev); 5215 hw->adapter_state = HNS3_NIC_CONFIGURED; 5216 } 5217 hns3_rx_scattered_reset(dev); 5218 rte_eal_alarm_cancel(hns3_service_handler, dev); 5219 hns3_stop_report_lse(dev); 5220 rte_spinlock_unlock(&hw->lock); 5221 5222 return 0; 5223 } 5224 5225 static int 5226 hns3_dev_close(struct rte_eth_dev *eth_dev) 5227 { 5228 struct hns3_adapter *hns = eth_dev->data->dev_private; 5229 struct hns3_hw *hw = &hns->hw; 5230 int ret = 0; 5231 5232 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 5233 hns3_mp_uninit(eth_dev); 5234 return 0; 5235 } 5236 5237 if (hw->adapter_state == HNS3_NIC_STARTED) 5238 ret = hns3_dev_stop(eth_dev); 5239 5240 hw->adapter_state = HNS3_NIC_CLOSING; 5241 hns3_reset_abort(hns); 5242 hw->adapter_state = HNS3_NIC_CLOSED; 5243 5244 hns3_configure_all_mc_mac_addr(hns, true); 5245 hns3_remove_all_vlan_table(hns); 5246 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0); 5247 hns3_uninit_pf(eth_dev); 5248 hns3_free_all_queues(eth_dev); 5249 rte_free(hw->reset.wait_data); 5250 hns3_mp_uninit(eth_dev); 5251 hns3_warn(hw, "Close port %u finished", hw->data->port_id); 5252 5253 return ret; 5254 } 5255 5256 static void 5257 hns3_get_autoneg_rxtx_pause_copper(struct hns3_hw *hw, bool *rx_pause, 5258 bool *tx_pause) 5259 { 5260 struct hns3_mac *mac = &hw->mac; 5261 uint32_t advertising = mac->advertising; 5262 uint32_t lp_advertising = mac->lp_advertising; 5263 *rx_pause = false; 5264 *tx_pause = false; 5265 5266 if (advertising & lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) { 5267 *rx_pause = true; 5268 *tx_pause = true; 5269 } else if (advertising & lp_advertising & 5270 HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT) { 5271 if (advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) 5272 *rx_pause = true; 5273 else if (lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) 5274 *tx_pause = true; 5275 } 5276 } 5277 5278 static enum hns3_fc_mode 5279 hns3_get_autoneg_fc_mode(struct hns3_hw *hw) 5280 { 5281 enum hns3_fc_mode current_mode; 5282 bool rx_pause = false; 5283 bool tx_pause = false; 5284 5285 switch (hw->mac.media_type) { 5286 case HNS3_MEDIA_TYPE_COPPER: 5287 hns3_get_autoneg_rxtx_pause_copper(hw, &rx_pause, &tx_pause); 5288 break; 5289 5290 /* 5291 * Flow control auto-negotiation is not supported for fiber and 5292 * backplane media type. 5293 */ 5294 case HNS3_MEDIA_TYPE_FIBER: 5295 case HNS3_MEDIA_TYPE_BACKPLANE: 5296 hns3_err(hw, "autoneg FC mode can't be obtained, but flow control auto-negotiation is enabled."); 5297 current_mode = hw->requested_fc_mode; 5298 goto out; 5299 default: 5300 hns3_err(hw, "autoneg FC mode can't be obtained for unknown media type(%u).", 5301 hw->mac.media_type); 5302 current_mode = HNS3_FC_NONE; 5303 goto out; 5304 } 5305 5306 if (rx_pause && tx_pause) 5307 current_mode = HNS3_FC_FULL; 5308 else if (rx_pause) 5309 current_mode = HNS3_FC_RX_PAUSE; 5310 else if (tx_pause) 5311 current_mode = HNS3_FC_TX_PAUSE; 5312 else 5313 current_mode = HNS3_FC_NONE; 5314 5315 out: 5316 return current_mode; 5317 } 5318 5319 static enum hns3_fc_mode 5320 hns3_get_current_fc_mode(struct rte_eth_dev *dev) 5321 { 5322 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5323 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5324 struct hns3_mac *mac = &hw->mac; 5325 5326 /* 5327 * When the flow control mode is obtained, the device may not complete 5328 * auto-negotiation. It is necessary to wait for link establishment. 5329 */ 5330 (void)hns3_dev_link_update(dev, 1); 5331 5332 /* 5333 * If the link auto-negotiation of the nic is disabled, or the flow 5334 * control auto-negotiation is not supported, the forced flow control 5335 * mode is used. 5336 */ 5337 if (mac->link_autoneg == 0 || !pf->support_fc_autoneg) 5338 return hw->requested_fc_mode; 5339 5340 return hns3_get_autoneg_fc_mode(hw); 5341 } 5342 5343 int 5344 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 5345 { 5346 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5347 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5348 enum hns3_fc_mode current_mode; 5349 5350 current_mode = hns3_get_current_fc_mode(dev); 5351 switch (current_mode) { 5352 case HNS3_FC_FULL: 5353 fc_conf->mode = RTE_ETH_FC_FULL; 5354 break; 5355 case HNS3_FC_TX_PAUSE: 5356 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 5357 break; 5358 case HNS3_FC_RX_PAUSE: 5359 fc_conf->mode = RTE_ETH_FC_RX_PAUSE; 5360 break; 5361 case HNS3_FC_NONE: 5362 default: 5363 fc_conf->mode = RTE_ETH_FC_NONE; 5364 break; 5365 } 5366 5367 fc_conf->pause_time = pf->pause_time; 5368 fc_conf->autoneg = pf->support_fc_autoneg ? hw->mac.link_autoneg : 0; 5369 5370 return 0; 5371 } 5372 5373 static int 5374 hns3_check_fc_autoneg_valid(struct hns3_hw *hw, uint8_t autoneg) 5375 { 5376 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw); 5377 5378 if (!pf->support_fc_autoneg) { 5379 if (autoneg != 0) { 5380 hns3_err(hw, "unsupported fc auto-negotiation setting."); 5381 return -EOPNOTSUPP; 5382 } 5383 5384 /* 5385 * Flow control auto-negotiation of the NIC is not supported, 5386 * but other auto-negotiation features may be supported. 5387 */ 5388 if (autoneg != hw->mac.link_autoneg) { 5389 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to disable autoneg!"); 5390 return -EOPNOTSUPP; 5391 } 5392 5393 return 0; 5394 } 5395 5396 /* 5397 * If flow control auto-negotiation of the NIC is supported, all 5398 * auto-negotiation features are supported. 5399 */ 5400 if (autoneg != hw->mac.link_autoneg) { 5401 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to change autoneg!"); 5402 return -EOPNOTSUPP; 5403 } 5404 5405 return 0; 5406 } 5407 5408 static int 5409 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 5410 { 5411 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5412 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5413 int ret; 5414 5415 if (fc_conf->high_water || fc_conf->low_water || 5416 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) { 5417 hns3_err(hw, "Unsupported flow control settings specified, " 5418 "high_water(%u), low_water(%u), send_xon(%u) and " 5419 "mac_ctrl_frame_fwd(%u) must be set to '0'", 5420 fc_conf->high_water, fc_conf->low_water, 5421 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd); 5422 return -EINVAL; 5423 } 5424 5425 ret = hns3_check_fc_autoneg_valid(hw, fc_conf->autoneg); 5426 if (ret) 5427 return ret; 5428 5429 if (!fc_conf->pause_time) { 5430 hns3_err(hw, "Invalid pause time %u setting.", 5431 fc_conf->pause_time); 5432 return -EINVAL; 5433 } 5434 5435 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE || 5436 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) { 5437 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. " 5438 "current_fc_status = %d", hw->current_fc_status); 5439 return -EOPNOTSUPP; 5440 } 5441 5442 if (hw->num_tc > 1 && !pf->support_multi_tc_pause) { 5443 hns3_err(hw, "in multi-TC scenarios, MAC pause is not supported."); 5444 return -EOPNOTSUPP; 5445 } 5446 5447 rte_spinlock_lock(&hw->lock); 5448 ret = hns3_fc_enable(dev, fc_conf); 5449 rte_spinlock_unlock(&hw->lock); 5450 5451 return ret; 5452 } 5453 5454 static int 5455 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev, 5456 struct rte_eth_pfc_conf *pfc_conf) 5457 { 5458 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5459 int ret; 5460 5461 if (!hns3_dev_get_support(hw, DCB)) { 5462 hns3_err(hw, "This port does not support dcb configurations."); 5463 return -EOPNOTSUPP; 5464 } 5465 5466 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water || 5467 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) { 5468 hns3_err(hw, "Unsupported flow control settings specified, " 5469 "high_water(%u), low_water(%u), send_xon(%u) and " 5470 "mac_ctrl_frame_fwd(%u) must be set to '0'", 5471 pfc_conf->fc.high_water, pfc_conf->fc.low_water, 5472 pfc_conf->fc.send_xon, 5473 pfc_conf->fc.mac_ctrl_frame_fwd); 5474 return -EINVAL; 5475 } 5476 if (pfc_conf->fc.autoneg) { 5477 hns3_err(hw, "Unsupported fc auto-negotiation setting."); 5478 return -EINVAL; 5479 } 5480 if (pfc_conf->fc.pause_time == 0) { 5481 hns3_err(hw, "Invalid pause time %u setting.", 5482 pfc_conf->fc.pause_time); 5483 return -EINVAL; 5484 } 5485 5486 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE || 5487 hw->current_fc_status == HNS3_FC_STATUS_PFC)) { 5488 hns3_err(hw, "MAC pause is enabled. Cannot set PFC." 5489 "current_fc_status = %d", hw->current_fc_status); 5490 return -EOPNOTSUPP; 5491 } 5492 5493 rte_spinlock_lock(&hw->lock); 5494 ret = hns3_dcb_pfc_enable(dev, pfc_conf); 5495 rte_spinlock_unlock(&hw->lock); 5496 5497 return ret; 5498 } 5499 5500 static int 5501 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info) 5502 { 5503 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5504 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5505 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode; 5506 int i; 5507 5508 rte_spinlock_lock(&hw->lock); 5509 if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) 5510 dcb_info->nb_tcs = pf->local_max_tc; 5511 else 5512 dcb_info->nb_tcs = 1; 5513 5514 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) 5515 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i]; 5516 for (i = 0; i < dcb_info->nb_tcs; i++) 5517 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i]; 5518 5519 for (i = 0; i < hw->num_tc; i++) { 5520 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i; 5521 dcb_info->tc_queue.tc_txq[0][i].base = 5522 hw->tc_queue[i].tqp_offset; 5523 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size; 5524 dcb_info->tc_queue.tc_txq[0][i].nb_queue = 5525 hw->tc_queue[i].tqp_count; 5526 } 5527 rte_spinlock_unlock(&hw->lock); 5528 5529 return 0; 5530 } 5531 5532 static int 5533 hns3_reinit_dev(struct hns3_adapter *hns) 5534 { 5535 struct hns3_hw *hw = &hns->hw; 5536 int ret; 5537 5538 ret = hns3_cmd_init(hw); 5539 if (ret) { 5540 hns3_err(hw, "Failed to init cmd: %d", ret); 5541 return ret; 5542 } 5543 5544 ret = hns3_init_hardware(hns); 5545 if (ret) { 5546 hns3_err(hw, "Failed to init hardware: %d", ret); 5547 return ret; 5548 } 5549 5550 ret = hns3_reset_all_tqps(hns); 5551 if (ret) { 5552 hns3_err(hw, "Failed to reset all queues: %d", ret); 5553 return ret; 5554 } 5555 5556 ret = hns3_enable_hw_error_intr(hns, true); 5557 if (ret) { 5558 hns3_err(hw, "fail to enable hw error interrupts: %d", 5559 ret); 5560 return ret; 5561 } 5562 hns3_info(hw, "Reset done, driver initialization finished."); 5563 5564 return 0; 5565 } 5566 5567 static bool 5568 is_pf_reset_done(struct hns3_hw *hw) 5569 { 5570 uint32_t val, reg, reg_bit; 5571 5572 switch (hw->reset.level) { 5573 case HNS3_IMP_RESET: 5574 reg = HNS3_GLOBAL_RESET_REG; 5575 reg_bit = HNS3_IMP_RESET_BIT; 5576 break; 5577 case HNS3_GLOBAL_RESET: 5578 reg = HNS3_GLOBAL_RESET_REG; 5579 reg_bit = HNS3_GLOBAL_RESET_BIT; 5580 break; 5581 case HNS3_FUNC_RESET: 5582 reg = HNS3_FUN_RST_ING; 5583 reg_bit = HNS3_FUN_RST_ING_B; 5584 break; 5585 case HNS3_FLR_RESET: 5586 default: 5587 hns3_err(hw, "Wait for unsupported reset level: %d", 5588 hw->reset.level); 5589 return true; 5590 } 5591 val = hns3_read_dev(hw, reg); 5592 if (hns3_get_bit(val, reg_bit)) 5593 return false; 5594 else 5595 return true; 5596 } 5597 5598 bool 5599 hns3_is_reset_pending(struct hns3_adapter *hns) 5600 { 5601 struct hns3_hw *hw = &hns->hw; 5602 enum hns3_reset_level reset; 5603 5604 hns3_check_event_cause(hns, NULL); 5605 reset = hns3_get_reset_level(hns, &hw->reset.pending); 5606 if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET && 5607 hw->reset.level < reset) { 5608 hns3_warn(hw, "High level reset %d is pending", reset); 5609 return true; 5610 } 5611 reset = hns3_get_reset_level(hns, &hw->reset.request); 5612 if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET && 5613 hw->reset.level < reset) { 5614 hns3_warn(hw, "High level reset %d is request", reset); 5615 return true; 5616 } 5617 return false; 5618 } 5619 5620 static int 5621 hns3_wait_hardware_ready(struct hns3_adapter *hns) 5622 { 5623 struct hns3_hw *hw = &hns->hw; 5624 struct hns3_wait_data *wait_data = hw->reset.wait_data; 5625 struct timeval tv; 5626 5627 if (wait_data->result == HNS3_WAIT_SUCCESS) 5628 return 0; 5629 else if (wait_data->result == HNS3_WAIT_TIMEOUT) { 5630 hns3_clock_gettime(&tv); 5631 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld", 5632 tv.tv_sec, tv.tv_usec); 5633 return -ETIME; 5634 } else if (wait_data->result == HNS3_WAIT_REQUEST) 5635 return -EAGAIN; 5636 5637 wait_data->hns = hns; 5638 wait_data->check_completion = is_pf_reset_done; 5639 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT * 5640 HNS3_RESET_WAIT_MS + hns3_clock_gettime_ms(); 5641 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC; 5642 wait_data->count = HNS3_RESET_WAIT_CNT; 5643 wait_data->result = HNS3_WAIT_REQUEST; 5644 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data); 5645 return -EAGAIN; 5646 } 5647 5648 static int 5649 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id) 5650 { 5651 struct hns3_cmd_desc desc; 5652 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data; 5653 5654 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false); 5655 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1); 5656 req->fun_reset_vfid = func_id; 5657 5658 return hns3_cmd_send(hw, &desc, 1); 5659 } 5660 5661 static int 5662 hns3_imp_reset_cmd(struct hns3_hw *hw) 5663 { 5664 struct hns3_cmd_desc desc; 5665 5666 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false); 5667 desc.data[0] = 0xeedd; 5668 5669 return hns3_cmd_send(hw, &desc, 1); 5670 } 5671 5672 static void 5673 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level) 5674 { 5675 struct hns3_hw *hw = &hns->hw; 5676 struct timeval tv; 5677 uint32_t val; 5678 5679 hns3_clock_gettime(&tv); 5680 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) || 5681 hns3_read_dev(hw, HNS3_FUN_RST_ING)) { 5682 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld", 5683 tv.tv_sec, tv.tv_usec); 5684 return; 5685 } 5686 5687 switch (reset_level) { 5688 case HNS3_IMP_RESET: 5689 hns3_imp_reset_cmd(hw); 5690 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld", 5691 tv.tv_sec, tv.tv_usec); 5692 break; 5693 case HNS3_GLOBAL_RESET: 5694 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG); 5695 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1); 5696 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val); 5697 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld", 5698 tv.tv_sec, tv.tv_usec); 5699 break; 5700 case HNS3_FUNC_RESET: 5701 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld", 5702 tv.tv_sec, tv.tv_usec); 5703 /* schedule again to check later */ 5704 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending); 5705 hns3_schedule_reset(hns); 5706 break; 5707 default: 5708 hns3_warn(hw, "Unsupported reset level: %d", reset_level); 5709 return; 5710 } 5711 hns3_atomic_clear_bit(reset_level, &hw->reset.request); 5712 } 5713 5714 static enum hns3_reset_level 5715 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels) 5716 { 5717 struct hns3_hw *hw = &hns->hw; 5718 enum hns3_reset_level reset_level = HNS3_NONE_RESET; 5719 5720 /* Return the highest priority reset level amongst all */ 5721 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels)) 5722 reset_level = HNS3_IMP_RESET; 5723 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels)) 5724 reset_level = HNS3_GLOBAL_RESET; 5725 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels)) 5726 reset_level = HNS3_FUNC_RESET; 5727 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels)) 5728 reset_level = HNS3_FLR_RESET; 5729 5730 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level) 5731 return HNS3_NONE_RESET; 5732 5733 return reset_level; 5734 } 5735 5736 static void 5737 hns3_record_imp_error(struct hns3_adapter *hns) 5738 { 5739 struct hns3_hw *hw = &hns->hw; 5740 uint32_t reg_val; 5741 5742 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); 5743 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) { 5744 hns3_warn(hw, "Detected IMP RD poison!"); 5745 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0); 5746 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); 5747 } 5748 5749 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) { 5750 hns3_warn(hw, "Detected IMP CMDQ error!"); 5751 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0); 5752 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); 5753 } 5754 } 5755 5756 static int 5757 hns3_prepare_reset(struct hns3_adapter *hns) 5758 { 5759 struct hns3_hw *hw = &hns->hw; 5760 uint32_t reg_val; 5761 int ret; 5762 5763 switch (hw->reset.level) { 5764 case HNS3_FUNC_RESET: 5765 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID); 5766 if (ret) 5767 return ret; 5768 5769 /* 5770 * After performaning pf reset, it is not necessary to do the 5771 * mailbox handling or send any command to firmware, because 5772 * any mailbox handling or command to firmware is only valid 5773 * after hns3_cmd_init is called. 5774 */ 5775 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); 5776 hw->reset.stats.request_cnt++; 5777 break; 5778 case HNS3_IMP_RESET: 5779 hns3_record_imp_error(hns); 5780 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); 5781 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val | 5782 BIT(HNS3_VECTOR0_IMP_RESET_INT_B)); 5783 break; 5784 default: 5785 break; 5786 } 5787 return 0; 5788 } 5789 5790 static int 5791 hns3_set_rst_done(struct hns3_hw *hw) 5792 { 5793 struct hns3_pf_rst_done_cmd *req; 5794 struct hns3_cmd_desc desc; 5795 5796 req = (struct hns3_pf_rst_done_cmd *)desc.data; 5797 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false); 5798 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT; 5799 return hns3_cmd_send(hw, &desc, 1); 5800 } 5801 5802 static int 5803 hns3_stop_service(struct hns3_adapter *hns) 5804 { 5805 struct hns3_hw *hw = &hns->hw; 5806 struct rte_eth_dev *eth_dev; 5807 5808 eth_dev = &rte_eth_devices[hw->data->port_id]; 5809 hw->mac.link_status = RTE_ETH_LINK_DOWN; 5810 if (hw->adapter_state == HNS3_NIC_STARTED) { 5811 rte_eal_alarm_cancel(hns3_service_handler, eth_dev); 5812 hns3_update_linkstatus_and_event(hw, false); 5813 } 5814 5815 hns3_set_rxtx_function(eth_dev); 5816 rte_wmb(); 5817 /* Disable datapath on secondary process. */ 5818 hns3_mp_req_stop_rxtx(eth_dev); 5819 rte_delay_ms(hw->cfg_max_queues); 5820 5821 rte_spinlock_lock(&hw->lock); 5822 if (hns->hw.adapter_state == HNS3_NIC_STARTED || 5823 hw->adapter_state == HNS3_NIC_STOPPING) { 5824 hns3_enable_all_queues(hw, false); 5825 hns3_do_stop(hns); 5826 hw->reset.mbuf_deferred_free = true; 5827 } else 5828 hw->reset.mbuf_deferred_free = false; 5829 5830 /* 5831 * It is cumbersome for hardware to pick-and-choose entries for deletion 5832 * from table space. Hence, for function reset software intervention is 5833 * required to delete the entries 5834 */ 5835 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) 5836 hns3_configure_all_mc_mac_addr(hns, true); 5837 rte_spinlock_unlock(&hw->lock); 5838 5839 return 0; 5840 } 5841 5842 static int 5843 hns3_start_service(struct hns3_adapter *hns) 5844 { 5845 struct hns3_hw *hw = &hns->hw; 5846 struct rte_eth_dev *eth_dev; 5847 5848 if (hw->reset.level == HNS3_IMP_RESET || 5849 hw->reset.level == HNS3_GLOBAL_RESET) 5850 hns3_set_rst_done(hw); 5851 eth_dev = &rte_eth_devices[hw->data->port_id]; 5852 hns3_set_rxtx_function(eth_dev); 5853 hns3_mp_req_start_rxtx(eth_dev); 5854 if (hw->adapter_state == HNS3_NIC_STARTED) { 5855 /* 5856 * This API parent function already hold the hns3_hw.lock, the 5857 * hns3_service_handler may report lse, in bonding application 5858 * it will call driver's ops which may acquire the hns3_hw.lock 5859 * again, thus lead to deadlock. 5860 * We defer calls hns3_service_handler to avoid the deadlock. 5861 */ 5862 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL, 5863 hns3_service_handler, eth_dev); 5864 5865 /* Enable interrupt of all rx queues before enabling queues */ 5866 hns3_dev_all_rx_queue_intr_enable(hw, true); 5867 /* 5868 * Enable state of each rxq and txq will be recovered after 5869 * reset, so we need to restore them before enable all tqps; 5870 */ 5871 hns3_restore_tqp_enable_state(hw); 5872 /* 5873 * When finished the initialization, enable queues to receive 5874 * and transmit packets. 5875 */ 5876 hns3_enable_all_queues(hw, true); 5877 } 5878 5879 return 0; 5880 } 5881 5882 static int 5883 hns3_restore_conf(struct hns3_adapter *hns) 5884 { 5885 struct hns3_hw *hw = &hns->hw; 5886 int ret; 5887 5888 ret = hns3_configure_all_mac_addr(hns, false); 5889 if (ret) 5890 return ret; 5891 5892 ret = hns3_configure_all_mc_mac_addr(hns, false); 5893 if (ret) 5894 goto err_mc_mac; 5895 5896 ret = hns3_dev_promisc_restore(hns); 5897 if (ret) 5898 goto err_promisc; 5899 5900 ret = hns3_restore_vlan_table(hns); 5901 if (ret) 5902 goto err_promisc; 5903 5904 ret = hns3_restore_vlan_conf(hns); 5905 if (ret) 5906 goto err_promisc; 5907 5908 ret = hns3_restore_all_fdir_filter(hns); 5909 if (ret) 5910 goto err_promisc; 5911 5912 ret = hns3_restore_ptp(hns); 5913 if (ret) 5914 goto err_promisc; 5915 5916 ret = hns3_restore_rx_interrupt(hw); 5917 if (ret) 5918 goto err_promisc; 5919 5920 ret = hns3_restore_gro_conf(hw); 5921 if (ret) 5922 goto err_promisc; 5923 5924 ret = hns3_restore_fec(hw); 5925 if (ret) 5926 goto err_promisc; 5927 5928 if (hns->hw.adapter_state == HNS3_NIC_STARTED) { 5929 ret = hns3_do_start(hns, false); 5930 if (ret) 5931 goto err_promisc; 5932 hns3_info(hw, "hns3 dev restart successful!"); 5933 } else if (hw->adapter_state == HNS3_NIC_STOPPING) 5934 hw->adapter_state = HNS3_NIC_CONFIGURED; 5935 return 0; 5936 5937 err_promisc: 5938 hns3_configure_all_mc_mac_addr(hns, true); 5939 err_mc_mac: 5940 hns3_configure_all_mac_addr(hns, true); 5941 return ret; 5942 } 5943 5944 static void 5945 hns3_reset_service(void *param) 5946 { 5947 struct hns3_adapter *hns = (struct hns3_adapter *)param; 5948 struct hns3_hw *hw = &hns->hw; 5949 enum hns3_reset_level reset_level; 5950 struct timeval tv_delta; 5951 struct timeval tv_start; 5952 struct timeval tv; 5953 uint64_t msec; 5954 int ret; 5955 5956 /* 5957 * The interrupt is not triggered within the delay time. 5958 * The interrupt may have been lost. It is necessary to handle 5959 * the interrupt to recover from the error. 5960 */ 5961 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) == 5962 SCHEDULE_DEFERRED) { 5963 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED, 5964 __ATOMIC_RELAXED); 5965 hns3_err(hw, "Handling interrupts in delayed tasks"); 5966 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]); 5967 reset_level = hns3_get_reset_level(hns, &hw->reset.pending); 5968 if (reset_level == HNS3_NONE_RESET) { 5969 hns3_err(hw, "No reset level is set, try IMP reset"); 5970 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); 5971 } 5972 } 5973 __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED); 5974 5975 /* 5976 * Check if there is any ongoing reset in the hardware. This status can 5977 * be checked from reset_pending. If there is then, we need to wait for 5978 * hardware to complete reset. 5979 * a. If we are able to figure out in reasonable time that hardware 5980 * has fully resetted then, we can proceed with driver, client 5981 * reset. 5982 * b. else, we can come back later to check this status so re-sched 5983 * now. 5984 */ 5985 reset_level = hns3_get_reset_level(hns, &hw->reset.pending); 5986 if (reset_level != HNS3_NONE_RESET) { 5987 hns3_clock_gettime(&tv_start); 5988 ret = hns3_reset_process(hns, reset_level); 5989 hns3_clock_gettime(&tv); 5990 timersub(&tv, &tv_start, &tv_delta); 5991 msec = hns3_clock_calctime_ms(&tv_delta); 5992 if (msec > HNS3_RESET_PROCESS_MS) 5993 hns3_err(hw, "%d handle long time delta %" PRIu64 " ms time=%ld.%.6ld", 5994 hw->reset.level, msec, 5995 tv.tv_sec, tv.tv_usec); 5996 if (ret == -EAGAIN) 5997 return; 5998 } 5999 6000 /* Check if we got any *new* reset requests to be honored */ 6001 reset_level = hns3_get_reset_level(hns, &hw->reset.request); 6002 if (reset_level != HNS3_NONE_RESET) 6003 hns3_msix_process(hns, reset_level); 6004 } 6005 6006 static unsigned int 6007 hns3_get_speed_capa_num(uint16_t device_id) 6008 { 6009 unsigned int num; 6010 6011 switch (device_id) { 6012 case HNS3_DEV_ID_25GE: 6013 case HNS3_DEV_ID_25GE_RDMA: 6014 num = 2; 6015 break; 6016 case HNS3_DEV_ID_100G_RDMA_MACSEC: 6017 case HNS3_DEV_ID_200G_RDMA: 6018 num = 1; 6019 break; 6020 default: 6021 num = 0; 6022 break; 6023 } 6024 6025 return num; 6026 } 6027 6028 static int 6029 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa, 6030 uint16_t device_id) 6031 { 6032 switch (device_id) { 6033 case HNS3_DEV_ID_25GE: 6034 /* fallthrough */ 6035 case HNS3_DEV_ID_25GE_RDMA: 6036 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed; 6037 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa; 6038 6039 /* In HNS3 device, the 25G NIC is compatible with 10G rate */ 6040 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed; 6041 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa; 6042 break; 6043 case HNS3_DEV_ID_100G_RDMA_MACSEC: 6044 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed; 6045 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa; 6046 break; 6047 case HNS3_DEV_ID_200G_RDMA: 6048 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed; 6049 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa; 6050 break; 6051 default: 6052 return -ENOTSUP; 6053 } 6054 6055 return 0; 6056 } 6057 6058 static int 6059 hns3_fec_get_capability(struct rte_eth_dev *dev, 6060 struct rte_eth_fec_capa *speed_fec_capa, 6061 unsigned int num) 6062 { 6063 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6064 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 6065 uint16_t device_id = pci_dev->id.device_id; 6066 unsigned int capa_num; 6067 int ret; 6068 6069 capa_num = hns3_get_speed_capa_num(device_id); 6070 if (capa_num == 0) { 6071 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD", 6072 device_id); 6073 return -ENOTSUP; 6074 } 6075 6076 if (speed_fec_capa == NULL || num < capa_num) 6077 return capa_num; 6078 6079 ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id); 6080 if (ret) 6081 return -ENOTSUP; 6082 6083 return capa_num; 6084 } 6085 6086 static int 6087 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state) 6088 { 6089 struct hns3_config_fec_cmd *req; 6090 struct hns3_cmd_desc desc; 6091 int ret; 6092 6093 /* 6094 * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported 6095 * in device of link speed 6096 * below 10 Gbps. 6097 */ 6098 if (hw->mac.link_speed < RTE_ETH_SPEED_NUM_10G) { 6099 *state = 0; 6100 return 0; 6101 } 6102 6103 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true); 6104 req = (struct hns3_config_fec_cmd *)desc.data; 6105 ret = hns3_cmd_send(hw, &desc, 1); 6106 if (ret) { 6107 hns3_err(hw, "get current fec auto state failed, ret = %d", 6108 ret); 6109 return ret; 6110 } 6111 6112 *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B); 6113 return 0; 6114 } 6115 6116 static int 6117 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa) 6118 { 6119 struct hns3_sfp_info_cmd *resp; 6120 uint32_t tmp_fec_capa; 6121 uint8_t auto_state; 6122 struct hns3_cmd_desc desc; 6123 int ret; 6124 6125 /* 6126 * If link is down and AUTO is enabled, AUTO is returned, otherwise, 6127 * configured FEC mode is returned. 6128 * If link is up, current FEC mode is returned. 6129 */ 6130 if (hw->mac.link_status == RTE_ETH_LINK_DOWN) { 6131 ret = get_current_fec_auto_state(hw, &auto_state); 6132 if (ret) 6133 return ret; 6134 6135 if (auto_state == 0x1) { 6136 *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO); 6137 return 0; 6138 } 6139 } 6140 6141 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true); 6142 resp = (struct hns3_sfp_info_cmd *)desc.data; 6143 resp->query_type = HNS3_ACTIVE_QUERY; 6144 6145 ret = hns3_cmd_send(hw, &desc, 1); 6146 if (ret == -EOPNOTSUPP) { 6147 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret); 6148 return ret; 6149 } else if (ret) { 6150 hns3_err(hw, "get FEC failed, ret = %d", ret); 6151 return ret; 6152 } 6153 6154 /* 6155 * FEC mode order defined in hns3 hardware is inconsistent with 6156 * that defined in the ethdev library. So the sequence needs 6157 * to be converted. 6158 */ 6159 switch (resp->active_fec) { 6160 case HNS3_HW_FEC_MODE_NOFEC: 6161 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC); 6162 break; 6163 case HNS3_HW_FEC_MODE_BASER: 6164 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 6165 break; 6166 case HNS3_HW_FEC_MODE_RS: 6167 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS); 6168 break; 6169 default: 6170 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC); 6171 break; 6172 } 6173 6174 *fec_capa = tmp_fec_capa; 6175 return 0; 6176 } 6177 6178 static int 6179 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa) 6180 { 6181 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6182 6183 return hns3_fec_get_internal(hw, fec_capa); 6184 } 6185 6186 static int 6187 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode) 6188 { 6189 struct hns3_config_fec_cmd *req; 6190 struct hns3_cmd_desc desc; 6191 int ret; 6192 6193 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false); 6194 6195 req = (struct hns3_config_fec_cmd *)desc.data; 6196 switch (mode) { 6197 case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC): 6198 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M, 6199 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF); 6200 break; 6201 case RTE_ETH_FEC_MODE_CAPA_MASK(BASER): 6202 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M, 6203 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER); 6204 break; 6205 case RTE_ETH_FEC_MODE_CAPA_MASK(RS): 6206 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M, 6207 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS); 6208 break; 6209 case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO): 6210 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1); 6211 break; 6212 default: 6213 return 0; 6214 } 6215 ret = hns3_cmd_send(hw, &desc, 1); 6216 if (ret) 6217 hns3_err(hw, "set fec mode failed, ret = %d", ret); 6218 6219 return ret; 6220 } 6221 6222 static uint32_t 6223 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa) 6224 { 6225 struct hns3_mac *mac = &hw->mac; 6226 uint32_t cur_capa; 6227 6228 switch (mac->link_speed) { 6229 case RTE_ETH_SPEED_NUM_10G: 6230 cur_capa = fec_capa[1].capa; 6231 break; 6232 case RTE_ETH_SPEED_NUM_25G: 6233 case RTE_ETH_SPEED_NUM_100G: 6234 case RTE_ETH_SPEED_NUM_200G: 6235 cur_capa = fec_capa[0].capa; 6236 break; 6237 default: 6238 cur_capa = 0; 6239 break; 6240 } 6241 6242 return cur_capa; 6243 } 6244 6245 static bool 6246 is_fec_mode_one_bit_set(uint32_t mode) 6247 { 6248 int cnt = 0; 6249 uint8_t i; 6250 6251 for (i = 0; i < sizeof(mode); i++) 6252 if (mode >> i & 0x1) 6253 cnt++; 6254 6255 return cnt == 1 ? true : false; 6256 } 6257 6258 static int 6259 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode) 6260 { 6261 #define FEC_CAPA_NUM 2 6262 struct hns3_adapter *hns = dev->data->dev_private; 6263 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns); 6264 struct hns3_pf *pf = &hns->pf; 6265 struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM]; 6266 uint32_t cur_capa; 6267 uint32_t num = FEC_CAPA_NUM; 6268 int ret; 6269 6270 ret = hns3_fec_get_capability(dev, fec_capa, num); 6271 if (ret < 0) 6272 return ret; 6273 6274 /* HNS3 PMD only support one bit set mode, e.g. 0x1, 0x4 */ 6275 if (!is_fec_mode_one_bit_set(mode)) { 6276 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD, " 6277 "FEC mode should be only one bit set", mode); 6278 return -EINVAL; 6279 } 6280 6281 /* 6282 * Check whether the configured mode is within the FEC capability. 6283 * If not, the configured mode will not be supported. 6284 */ 6285 cur_capa = get_current_speed_fec_cap(hw, fec_capa); 6286 if (!(cur_capa & mode)) { 6287 hns3_err(hw, "unsupported FEC mode = 0x%x", mode); 6288 return -EINVAL; 6289 } 6290 6291 rte_spinlock_lock(&hw->lock); 6292 ret = hns3_set_fec_hw(hw, mode); 6293 if (ret) { 6294 rte_spinlock_unlock(&hw->lock); 6295 return ret; 6296 } 6297 6298 pf->fec_mode = mode; 6299 rte_spinlock_unlock(&hw->lock); 6300 6301 return 0; 6302 } 6303 6304 static int 6305 hns3_restore_fec(struct hns3_hw *hw) 6306 { 6307 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 6308 struct hns3_pf *pf = &hns->pf; 6309 uint32_t mode = pf->fec_mode; 6310 int ret; 6311 6312 ret = hns3_set_fec_hw(hw, mode); 6313 if (ret) 6314 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d", 6315 mode, ret); 6316 6317 return ret; 6318 } 6319 6320 static int 6321 hns3_query_dev_fec_info(struct hns3_hw *hw) 6322 { 6323 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 6324 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns); 6325 int ret; 6326 6327 ret = hns3_fec_get_internal(hw, &pf->fec_mode); 6328 if (ret) 6329 hns3_err(hw, "query device FEC info failed, ret = %d", ret); 6330 6331 return ret; 6332 } 6333 6334 static bool 6335 hns3_optical_module_existed(struct hns3_hw *hw) 6336 { 6337 struct hns3_cmd_desc desc; 6338 bool existed; 6339 int ret; 6340 6341 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true); 6342 ret = hns3_cmd_send(hw, &desc, 1); 6343 if (ret) { 6344 hns3_err(hw, 6345 "fail to get optical module exist state, ret = %d.\n", 6346 ret); 6347 return false; 6348 } 6349 existed = !!desc.data[0]; 6350 6351 return existed; 6352 } 6353 6354 static int 6355 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset, 6356 uint32_t len, uint8_t *data) 6357 { 6358 #define HNS3_SFP_INFO_CMD_NUM 6 6359 #define HNS3_SFP_INFO_MAX_LEN \ 6360 (HNS3_SFP_INFO_BD0_LEN + \ 6361 (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN) 6362 struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM]; 6363 struct hns3_sfp_info_bd0_cmd *sfp_info_bd0; 6364 uint16_t read_len; 6365 uint16_t copy_len; 6366 int ret; 6367 int i; 6368 6369 for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) { 6370 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM, 6371 true); 6372 if (i < HNS3_SFP_INFO_CMD_NUM - 1) 6373 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 6374 } 6375 6376 sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data; 6377 sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset); 6378 read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN); 6379 sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len); 6380 6381 ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM); 6382 if (ret) { 6383 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n", 6384 ret); 6385 return ret; 6386 } 6387 6388 /* The data format in BD0 is different with the others. */ 6389 copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN); 6390 memcpy(data, sfp_info_bd0->data, copy_len); 6391 read_len = copy_len; 6392 6393 for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) { 6394 if (read_len >= len) 6395 break; 6396 6397 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN); 6398 memcpy(data + read_len, desc[i].data, copy_len); 6399 read_len += copy_len; 6400 } 6401 6402 return (int)read_len; 6403 } 6404 6405 static int 6406 hns3_get_module_eeprom(struct rte_eth_dev *dev, 6407 struct rte_dev_eeprom_info *info) 6408 { 6409 struct hns3_adapter *hns = dev->data->dev_private; 6410 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns); 6411 uint32_t offset = info->offset; 6412 uint32_t len = info->length; 6413 uint8_t *data = info->data; 6414 uint32_t read_len = 0; 6415 6416 if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER) 6417 return -ENOTSUP; 6418 6419 if (!hns3_optical_module_existed(hw)) { 6420 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n"); 6421 return -EIO; 6422 } 6423 6424 while (read_len < len) { 6425 int ret; 6426 ret = hns3_get_module_eeprom_data(hw, offset + read_len, 6427 len - read_len, 6428 data + read_len); 6429 if (ret < 0) 6430 return -EIO; 6431 read_len += ret; 6432 } 6433 6434 return 0; 6435 } 6436 6437 static int 6438 hns3_get_module_info(struct rte_eth_dev *dev, 6439 struct rte_eth_dev_module_info *modinfo) 6440 { 6441 #define HNS3_SFF8024_ID_SFP 0x03 6442 #define HNS3_SFF8024_ID_QSFP_8438 0x0c 6443 #define HNS3_SFF8024_ID_QSFP_8436_8636 0x0d 6444 #define HNS3_SFF8024_ID_QSFP28_8636 0x11 6445 #define HNS3_SFF_8636_V1_3 0x03 6446 struct hns3_adapter *hns = dev->data->dev_private; 6447 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns); 6448 struct rte_dev_eeprom_info info; 6449 struct hns3_sfp_type sfp_type; 6450 int ret; 6451 6452 memset(&sfp_type, 0, sizeof(sfp_type)); 6453 memset(&info, 0, sizeof(info)); 6454 info.data = (uint8_t *)&sfp_type; 6455 info.length = sizeof(sfp_type); 6456 ret = hns3_get_module_eeprom(dev, &info); 6457 if (ret) 6458 return ret; 6459 6460 switch (sfp_type.type) { 6461 case HNS3_SFF8024_ID_SFP: 6462 modinfo->type = RTE_ETH_MODULE_SFF_8472; 6463 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 6464 break; 6465 case HNS3_SFF8024_ID_QSFP_8438: 6466 modinfo->type = RTE_ETH_MODULE_SFF_8436; 6467 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN; 6468 break; 6469 case HNS3_SFF8024_ID_QSFP_8436_8636: 6470 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) { 6471 modinfo->type = RTE_ETH_MODULE_SFF_8436; 6472 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN; 6473 } else { 6474 modinfo->type = RTE_ETH_MODULE_SFF_8636; 6475 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN; 6476 } 6477 break; 6478 case HNS3_SFF8024_ID_QSFP28_8636: 6479 modinfo->type = RTE_ETH_MODULE_SFF_8636; 6480 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN; 6481 break; 6482 default: 6483 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n", 6484 sfp_type.type, sfp_type.ext_type); 6485 return -EINVAL; 6486 } 6487 6488 return 0; 6489 } 6490 6491 static const struct eth_dev_ops hns3_eth_dev_ops = { 6492 .dev_configure = hns3_dev_configure, 6493 .dev_start = hns3_dev_start, 6494 .dev_stop = hns3_dev_stop, 6495 .dev_close = hns3_dev_close, 6496 .promiscuous_enable = hns3_dev_promiscuous_enable, 6497 .promiscuous_disable = hns3_dev_promiscuous_disable, 6498 .allmulticast_enable = hns3_dev_allmulticast_enable, 6499 .allmulticast_disable = hns3_dev_allmulticast_disable, 6500 .mtu_set = hns3_dev_mtu_set, 6501 .stats_get = hns3_stats_get, 6502 .stats_reset = hns3_stats_reset, 6503 .xstats_get = hns3_dev_xstats_get, 6504 .xstats_get_names = hns3_dev_xstats_get_names, 6505 .xstats_reset = hns3_dev_xstats_reset, 6506 .xstats_get_by_id = hns3_dev_xstats_get_by_id, 6507 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id, 6508 .dev_infos_get = hns3_dev_infos_get, 6509 .fw_version_get = hns3_fw_version_get, 6510 .rx_queue_setup = hns3_rx_queue_setup, 6511 .tx_queue_setup = hns3_tx_queue_setup, 6512 .rx_queue_release = hns3_dev_rx_queue_release, 6513 .tx_queue_release = hns3_dev_tx_queue_release, 6514 .rx_queue_start = hns3_dev_rx_queue_start, 6515 .rx_queue_stop = hns3_dev_rx_queue_stop, 6516 .tx_queue_start = hns3_dev_tx_queue_start, 6517 .tx_queue_stop = hns3_dev_tx_queue_stop, 6518 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable, 6519 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable, 6520 .rxq_info_get = hns3_rxq_info_get, 6521 .txq_info_get = hns3_txq_info_get, 6522 .rx_burst_mode_get = hns3_rx_burst_mode_get, 6523 .tx_burst_mode_get = hns3_tx_burst_mode_get, 6524 .flow_ctrl_get = hns3_flow_ctrl_get, 6525 .flow_ctrl_set = hns3_flow_ctrl_set, 6526 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set, 6527 .mac_addr_add = hns3_add_mac_addr, 6528 .mac_addr_remove = hns3_remove_mac_addr, 6529 .mac_addr_set = hns3_set_default_mac_addr, 6530 .set_mc_addr_list = hns3_set_mc_mac_addr_list, 6531 .link_update = hns3_dev_link_update, 6532 .dev_set_link_up = hns3_dev_set_link_up, 6533 .dev_set_link_down = hns3_dev_set_link_down, 6534 .rss_hash_update = hns3_dev_rss_hash_update, 6535 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get, 6536 .reta_update = hns3_dev_rss_reta_update, 6537 .reta_query = hns3_dev_rss_reta_query, 6538 .flow_ops_get = hns3_dev_flow_ops_get, 6539 .vlan_filter_set = hns3_vlan_filter_set, 6540 .vlan_tpid_set = hns3_vlan_tpid_set, 6541 .vlan_offload_set = hns3_vlan_offload_set, 6542 .vlan_pvid_set = hns3_vlan_pvid_set, 6543 .get_reg = hns3_get_regs, 6544 .get_module_info = hns3_get_module_info, 6545 .get_module_eeprom = hns3_get_module_eeprom, 6546 .get_dcb_info = hns3_get_dcb_info, 6547 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get, 6548 .fec_get_capability = hns3_fec_get_capability, 6549 .fec_get = hns3_fec_get, 6550 .fec_set = hns3_fec_set, 6551 .tm_ops_get = hns3_tm_ops_get, 6552 .tx_done_cleanup = hns3_tx_done_cleanup, 6553 .timesync_enable = hns3_timesync_enable, 6554 .timesync_disable = hns3_timesync_disable, 6555 .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp, 6556 .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp, 6557 .timesync_adjust_time = hns3_timesync_adjust_time, 6558 .timesync_read_time = hns3_timesync_read_time, 6559 .timesync_write_time = hns3_timesync_write_time, 6560 .eth_dev_priv_dump = hns3_eth_dev_priv_dump, 6561 }; 6562 6563 static const struct hns3_reset_ops hns3_reset_ops = { 6564 .reset_service = hns3_reset_service, 6565 .stop_service = hns3_stop_service, 6566 .prepare_reset = hns3_prepare_reset, 6567 .wait_hardware_ready = hns3_wait_hardware_ready, 6568 .reinit_dev = hns3_reinit_dev, 6569 .restore_conf = hns3_restore_conf, 6570 .start_service = hns3_start_service, 6571 }; 6572 6573 static void 6574 hns3_init_hw_ops(struct hns3_hw *hw) 6575 { 6576 hw->ops.add_mc_mac_addr = hns3_add_mc_mac_addr; 6577 hw->ops.del_mc_mac_addr = hns3_remove_mc_mac_addr; 6578 hw->ops.add_uc_mac_addr = hns3_add_uc_mac_addr; 6579 hw->ops.del_uc_mac_addr = hns3_remove_uc_mac_addr; 6580 hw->ops.bind_ring_with_vector = hns3_bind_ring_with_vector; 6581 } 6582 6583 static int 6584 hns3_dev_init(struct rte_eth_dev *eth_dev) 6585 { 6586 struct hns3_adapter *hns = eth_dev->data->dev_private; 6587 struct hns3_hw *hw = &hns->hw; 6588 int ret; 6589 6590 PMD_INIT_FUNC_TRACE(); 6591 6592 hns3_flow_init(eth_dev); 6593 6594 hns3_set_rxtx_function(eth_dev); 6595 eth_dev->dev_ops = &hns3_eth_dev_ops; 6596 eth_dev->rx_queue_count = hns3_rx_queue_count; 6597 ret = hns3_mp_init(eth_dev); 6598 if (ret) 6599 goto err_mp_init; 6600 6601 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 6602 hns3_tx_push_init(eth_dev); 6603 return 0; 6604 } 6605 6606 hw->adapter_state = HNS3_NIC_UNINITIALIZED; 6607 hns->is_vf = false; 6608 hw->data = eth_dev->data; 6609 hns3_parse_devargs(eth_dev); 6610 6611 /* 6612 * Set default max packet size according to the mtu 6613 * default vale in DPDK frame. 6614 */ 6615 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD; 6616 6617 ret = hns3_reset_init(hw); 6618 if (ret) 6619 goto err_init_reset; 6620 hw->reset.ops = &hns3_reset_ops; 6621 6622 hns3_init_hw_ops(hw); 6623 ret = hns3_init_pf(eth_dev); 6624 if (ret) { 6625 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret); 6626 goto err_init_pf; 6627 } 6628 6629 ret = hns3_init_mac_addrs(eth_dev); 6630 if (ret != 0) 6631 goto err_init_mac_addrs; 6632 6633 hw->adapter_state = HNS3_NIC_INITIALIZED; 6634 6635 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) == 6636 SCHEDULE_PENDING) { 6637 hns3_err(hw, "Reschedule reset service after dev_init"); 6638 hns3_schedule_reset(hns); 6639 } else { 6640 /* IMP will wait ready flag before reset */ 6641 hns3_notify_reset_ready(hw, false); 6642 } 6643 6644 hns3_info(hw, "hns3 dev initialization successful!"); 6645 return 0; 6646 6647 err_init_mac_addrs: 6648 hns3_uninit_pf(eth_dev); 6649 6650 err_init_pf: 6651 rte_free(hw->reset.wait_data); 6652 6653 err_init_reset: 6654 hns3_mp_uninit(eth_dev); 6655 6656 err_mp_init: 6657 eth_dev->dev_ops = NULL; 6658 eth_dev->rx_pkt_burst = NULL; 6659 eth_dev->rx_descriptor_status = NULL; 6660 eth_dev->tx_pkt_burst = NULL; 6661 eth_dev->tx_pkt_prepare = NULL; 6662 eth_dev->tx_descriptor_status = NULL; 6663 return ret; 6664 } 6665 6666 static int 6667 hns3_dev_uninit(struct rte_eth_dev *eth_dev) 6668 { 6669 struct hns3_adapter *hns = eth_dev->data->dev_private; 6670 struct hns3_hw *hw = &hns->hw; 6671 6672 PMD_INIT_FUNC_TRACE(); 6673 6674 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 6675 hns3_mp_uninit(eth_dev); 6676 return 0; 6677 } 6678 6679 if (hw->adapter_state < HNS3_NIC_CLOSING) 6680 hns3_dev_close(eth_dev); 6681 6682 hw->adapter_state = HNS3_NIC_REMOVED; 6683 return 0; 6684 } 6685 6686 static int 6687 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 6688 struct rte_pci_device *pci_dev) 6689 { 6690 return rte_eth_dev_pci_generic_probe(pci_dev, 6691 sizeof(struct hns3_adapter), 6692 hns3_dev_init); 6693 } 6694 6695 static int 6696 eth_hns3_pci_remove(struct rte_pci_device *pci_dev) 6697 { 6698 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit); 6699 } 6700 6701 static const struct rte_pci_id pci_id_hns3_map[] = { 6702 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) }, 6703 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) }, 6704 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) }, 6705 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) }, 6706 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) }, 6707 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) }, 6708 { .vendor_id = 0, }, /* sentinel */ 6709 }; 6710 6711 static struct rte_pci_driver rte_hns3_pmd = { 6712 .id_table = pci_id_hns3_map, 6713 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 6714 .probe = eth_hns3_pci_probe, 6715 .remove = eth_hns3_pci_remove, 6716 }; 6717 6718 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd); 6719 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map); 6720 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci"); 6721 RTE_PMD_REGISTER_PARAM_STRING(net_hns3, 6722 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common " 6723 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common " 6724 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> " 6725 HNS3_DEVARG_MBX_TIME_LIMIT_MS "=<uint16> "); 6726 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_init, init, NOTICE); 6727 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_driver, driver, NOTICE); 6728