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Searched refs:pixel_format (Results 1 – 25 of 50) sorted by relevance

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/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn201/
H A Ddcn201_dpp.c53 uint32_t pixel_format = 0; in dpp201_cnv_setup() local
71 pixel_format = 1; in dpp201_cnv_setup()
74 pixel_format = 3; in dpp201_cnv_setup()
79 pixel_format = 8; in dpp201_cnv_setup()
83 pixel_format = 10; in dpp201_cnv_setup()
88 pixel_format = 65; in dpp201_cnv_setup()
94 pixel_format = 64; in dpp201_cnv_setup()
100 pixel_format = 67; in dpp201_cnv_setup()
106 pixel_format = 66; in dpp201_cnv_setup()
111 pixel_format = 22; in dpp201_cnv_setup()
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn20/
H A Ddcn20_dpp.c104 uint32_t pixel_format = 0; in dpp2_cnv_setup() local
129 pixel_format = 1; in dpp2_cnv_setup()
132 pixel_format = 3; in dpp2_cnv_setup()
137 pixel_format = 8; in dpp2_cnv_setup()
141 pixel_format = 10; in dpp2_cnv_setup()
146 pixel_format = 65; in dpp2_cnv_setup()
152 pixel_format = 64; in dpp2_cnv_setup()
158 pixel_format = 67; in dpp2_cnv_setup()
164 pixel_format = 66; in dpp2_cnv_setup()
170 pixel_format = 26; /* ARGB16161616_UNORM */ in dpp2_cnv_setup()
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H A Ddcn20_dsc.c401 …dsc_reg_vals->pixel_format = dsc_dc_pixel_encoding_to_dsc_pixel_format(dsc_cfg->pixel_encoding, ds… in dsc_prepare_config()
425 …if (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || dsc_reg_vals->pixel_format == DSC_… in dsc_prepare_config()
430 dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0; in dsc_prepare_config()
431 dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422); in dsc_prepare_config()
432 dsc_reg_vals->pps.native_420 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420); in dsc_prepare_config()
433 dsc_reg_vals->pps.simple_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422); in dsc_prepare_config()
449 dsc_optc_cfg->is_pixel_format_444 = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB || in dsc_prepare_config()
450 dsc_reg_vals->pixel_format == DSC_PIXFMT_YCBCR444 || in dsc_prepare_config()
451 dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422; in dsc_prepare_config()
594 INPUT_PIXEL_FORMAT, reg_vals->pixel_format, in dsc_write_to_registers()
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/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn10/
H A Ddcn10_dpp.c282 uint32_t pixel_format; in dpp1_cnv_setup() local
295 pixel_format = 0; in dpp1_cnv_setup()
325 pixel_format = 1; in dpp1_cnv_setup()
328 pixel_format = 3; in dpp1_cnv_setup()
333 pixel_format = 8; in dpp1_cnv_setup()
337 pixel_format = 10; in dpp1_cnv_setup()
341 pixel_format = 65; in dpp1_cnv_setup()
347 pixel_format = 64; in dpp1_cnv_setup()
353 pixel_format = 67; in dpp1_cnv_setup()
359 pixel_format = 66; in dpp1_cnv_setup()
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H A Ddcn10_dpp_dscl.c105 static bool dpp1_dscl_is_video_format(enum pixel_format format) in dpp1_dscl_is_video_format()
114 static bool dpp1_dscl_is_420_format(enum pixel_format format) in dpp1_dscl_is_420_format()
H A Ddcn10_hw_sequencer_debug.c146 s->pixel_format, in dcn10_get_hubp_states()
165 s->pixel_format, in dcn10_get_hubp_states()
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn30/
H A Ddcn30_dpp.c179 uint32_t pixel_format = 0; in dpp3_cnv_setup() local
207 pixel_format = 1; in dpp3_cnv_setup()
210 pixel_format = 3; in dpp3_cnv_setup()
215 pixel_format = 8; in dpp3_cnv_setup()
219 pixel_format = 10; in dpp3_cnv_setup()
224 pixel_format = 65; in dpp3_cnv_setup()
230 pixel_format = 64; in dpp3_cnv_setup()
236 pixel_format = 67; in dpp3_cnv_setup()
242 pixel_format = 66; in dpp3_cnv_setup()
248 pixel_format = 26; /* ARGB16161616_UNORM */ in dpp3_cnv_setup()
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/openbsd-src/sys/dev/pci/drm/i915/display/
H A Di9xx_plane.c697 u32 pixel_format, u64 modifier, in hsw_primary_max_stride() argument
700 const struct drm_format_info *info = drm_format_info(pixel_format); in hsw_primary_max_stride()
709 u32 pixel_format, u64 modifier, in ilk_primary_max_stride() argument
712 const struct drm_format_info *info = drm_format_info(pixel_format); in ilk_primary_max_stride()
724 u32 pixel_format, u64 modifier, in i965_plane_max_stride() argument
727 const struct drm_format_info *info = drm_format_info(pixel_format); in i965_plane_max_stride()
739 u32 pixel_format, u64 modifier, in i9xx_plane_max_stride() argument
984 int fourcc, pixel_format; in i9xx_get_initial_plane_config() local
1020 pixel_format = val & DISP_FORMAT_MASK; in i9xx_get_initial_plane_config()
1021 fourcc = i9xx_format_to_fourcc(pixel_format); in i9xx_get_initial_plane_config()
[all...]
H A Di9xx_plane.h20 u32 pixel_format, u64 modifier,
H A Dvlv_dsi_pll.c121 int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in vlv_dsi_pclk()
182 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, in vlv_dsi_pll_compute()
343 int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in bxt_dsi_pclk()
487 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, in bxt_dsi_pll_compute()
H A Dintel_dsi.c34 int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in intel_dsi_bitrate()
H A Dintel_dsi.h80 enum mipi_dsi_pixel_format pixel_format; member
H A Dicl_dsi.c335 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in afe_clk()
728 switch (intel_dsi->pixel_format) { in gen11_dsi_configure_transcoder()
730 MISSING_CASE(intel_dsi->pixel_format); in gen11_dsi_configure_transcoder()
864 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in gen11_dsi_set_transcoder_timings()
889 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in gen11_dsi_set_transcoder_timings()
911 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0) in gen11_dsi_set_transcoder_timings()
1463 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in gen11_dsi_get_timings()
1645 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) in gen11_dsi_compute_config()
H A Dskl_universal_plane.c464 u32 pixel_format, u64 modifier, in skl_plane_max_stride() argument
468 const struct drm_format_info *info = drm_format_info(pixel_format); in skl_plane_max_stride()
674 static u32 skl_plane_ctl_format(u32 pixel_format) in skl_plane_ctl_format() argument
676 switch (pixel_format) { in skl_plane_ctl_format()
730 MISSING_CASE(pixel_format); in skl_plane_ctl_format()
2399 int fourcc, pixel_format; in skl_get_initial_plane_config() local
2429 pixel_format = val & PLANE_CTL_FORMAT_MASK_ICL; in skl_get_initial_plane_config()
2431 pixel_format = val & PLANE_CTL_FORMAT_MASK_SKL; in skl_get_initial_plane_config()
2442 fourcc = skl_format_to_fourcc(pixel_format, in skl_get_initial_plane_config()
H A Dintel_fb.c316 return lookup_format_info(md->formats, md->format_count, cmd->pixel_format); in intel_fb_get_format_info()
1755 u32 pixel_format, u64 modifier) in intel_fb_max_stride() argument
1765 return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier); in intel_fb_max_stride()
1974 mode_cmd->pixel_format, in intel_framebuffer_init()
1978 &mode_cmd->pixel_format, mode_cmd->modifier[0]); in intel_framebuffer_init()
1993 max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format, in intel_framebuffer_init()
H A Dvlv_dsi.c299 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) in intel_dsi_compute_config()
649 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888) in intel_dsi_port_enable()
1216 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in set_dsi_timings()
1308 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in intel_dsi_prepare()
1364 val |= pixel_format_to_reg(intel_dsi->pixel_format); in intel_dsi_prepare()
H A Dintel_sprite.c936 u32 pixel_format, u64 modifier, in g4x_sprite_max_stride() argument
939 const struct drm_format_info *info = drm_format_info(pixel_format); in g4x_sprite_max_stride()
951 u32 pixel_format, u64 modifier, in hsw_sprite_max_stride() argument
954 const struct drm_format_info *info = drm_format_info(pixel_format); in hsw_sprite_max_stride()
H A Dintel_plane_initial.c296 mode_cmd.pixel_format = fb->format->format; in plane_config_fini()
H A Dintel_cursor.c177 u32 pixel_format, u64 modifier, in i845_cursor_max_stride() argument
327 u32 pixel_format, u64 modifier, in i9xx_cursor_max_stride() argument
H A Dintel_dsi_vbt.c813 drm_dbg_kms(&i915->drm, "Pixel Format %d\n", intel_dsi->pixel_format); in intel_dsi_log_params()
848 intel_dsi->pixel_format = in intel_dsi_vbt_init()
/openbsd-src/sys/dev/pci/drm/i915/gvt/
H A Dfb_decoder.c43 struct pixel_format { struct
49 static const struct pixel_format bdw_pixel_formats[] = { argument
62 static const struct pixel_format skl_pixel_formats[] = {
395 static const struct pixel_format sprite_pixel_formats[SPRITE_FORMAT_NUM] = {
/openbsd-src/sys/dev/pci/drm/
H A Ddrm_framebuffer.c126 r.pixel_format = drm_driver_legacy_fb_format(dev, or->bpp, or->depth); in drm_mode_addfb()
127 if (r.pixel_format == DRM_FORMAT_INVALID) { in drm_mode_addfb()
179 if (!__drm_format_info(r->pixel_format)) { in framebuffer_check()
181 &r->pixel_format); in framebuffer_check()
244 if (r->pixel_format != DRM_FORMAT_NV12 || in framebuffer_check()
594 r->pixel_format = fb->format->format; in drm_mode_getfb2_ioctl()
/openbsd-src/sys/dev/pci/drm/amd/display/dc/inc/hw/
H A Dhw_shared.h186 enum pixel_format surface_pixel_format;
H A Dtransform.h178 enum pixel_format format;
/openbsd-src/sys/dev/pci/drm/include/uapi/drm/
H A Ddrm_mode.h714 __u32 pixel_format; member

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