xref: /openbsd-src/sys/dev/pci/drm/i915/display/intel_dsi.h (revision f005ef32267c16bdb134f0e9fa4477dbe07c263a)
1c349dbc7Sjsg /*
2c349dbc7Sjsg  * Copyright © 2013 Intel Corporation
3c349dbc7Sjsg  *
4c349dbc7Sjsg  * Permission is hereby granted, free of charge, to any person obtaining a
5c349dbc7Sjsg  * copy of this software and associated documentation files (the "Software"),
6c349dbc7Sjsg  * to deal in the Software without restriction, including without limitation
7c349dbc7Sjsg  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8c349dbc7Sjsg  * and/or sell copies of the Software, and to permit persons to whom the
9c349dbc7Sjsg  * Software is furnished to do so, subject to the following conditions:
10c349dbc7Sjsg  *
11c349dbc7Sjsg  * The above copyright notice and this permission notice (including the next
12c349dbc7Sjsg  * paragraph) shall be included in all copies or substantial portions of the
13c349dbc7Sjsg  * Software.
14c349dbc7Sjsg  *
15c349dbc7Sjsg  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16c349dbc7Sjsg  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17c349dbc7Sjsg  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18c349dbc7Sjsg  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19c349dbc7Sjsg  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20c349dbc7Sjsg  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21c349dbc7Sjsg  * DEALINGS IN THE SOFTWARE.
22c349dbc7Sjsg  */
23c349dbc7Sjsg 
24c349dbc7Sjsg #ifndef _INTEL_DSI_H
25c349dbc7Sjsg #define _INTEL_DSI_H
26c349dbc7Sjsg 
27c349dbc7Sjsg #include <drm/drm_crtc.h>
28c349dbc7Sjsg #include <drm/drm_mipi_dsi.h>
29c349dbc7Sjsg 
30c349dbc7Sjsg #include "intel_display_types.h"
31c349dbc7Sjsg 
32c349dbc7Sjsg #define INTEL_DSI_VIDEO_MODE	0
33c349dbc7Sjsg #define INTEL_DSI_COMMAND_MODE	1
34c349dbc7Sjsg 
35c349dbc7Sjsg /* Dual Link support */
36c349dbc7Sjsg #define DSI_DUAL_LINK_NONE		0
37c349dbc7Sjsg #define DSI_DUAL_LINK_FRONT_BACK	1
38c349dbc7Sjsg #define DSI_DUAL_LINK_PIXEL_ALT		2
39c349dbc7Sjsg 
40c349dbc7Sjsg struct intel_dsi_host;
41c349dbc7Sjsg 
42c349dbc7Sjsg struct intel_dsi {
43c349dbc7Sjsg 	struct intel_encoder base;
44c349dbc7Sjsg 
45c349dbc7Sjsg 	struct intel_dsi_host *dsi_hosts[I915_MAX_PORTS];
46c349dbc7Sjsg 	intel_wakeref_t io_wakeref[I915_MAX_PORTS];
47c349dbc7Sjsg 
48c349dbc7Sjsg 	/* GPIO Desc for panel and backlight control */
49c349dbc7Sjsg 	struct gpio_desc *gpio_panel;
50c349dbc7Sjsg 	struct gpio_desc *gpio_backlight;
51c349dbc7Sjsg 
52c349dbc7Sjsg 	struct intel_connector *attached_connector;
53c349dbc7Sjsg 
54c349dbc7Sjsg 	/* bit mask of ports (vlv dsi) or phys (icl dsi) being driven */
55c349dbc7Sjsg 	union {
56c349dbc7Sjsg 		u16 ports;	/* VLV DSI */
57c349dbc7Sjsg 		u16 phys;	/* ICL DSI */
58c349dbc7Sjsg 	};
59c349dbc7Sjsg 
60c349dbc7Sjsg 	/* if true, use HS mode, otherwise LP */
61c349dbc7Sjsg 	bool hs;
62c349dbc7Sjsg 
63c349dbc7Sjsg 	/* virtual channel */
64c349dbc7Sjsg 	int channel;
65c349dbc7Sjsg 
66c349dbc7Sjsg 	/* Video mode or command mode */
67c349dbc7Sjsg 	u16 operation_mode;
68c349dbc7Sjsg 
69c349dbc7Sjsg 	/* number of DSI lanes */
70c349dbc7Sjsg 	unsigned int lane_count;
71c349dbc7Sjsg 
72c349dbc7Sjsg 	/* i2c bus associated with the slave device */
73c349dbc7Sjsg 	int i2c_bus_num;
74c349dbc7Sjsg 
75c349dbc7Sjsg 	/*
76c349dbc7Sjsg 	 * video mode pixel format
77c349dbc7Sjsg 	 *
78c349dbc7Sjsg 	 * XXX: consolidate on .format in struct mipi_dsi_device.
79c349dbc7Sjsg 	 */
80c349dbc7Sjsg 	enum mipi_dsi_pixel_format pixel_format;
81c349dbc7Sjsg 
821bb76ff1Sjsg 	/* NON_BURST_SYNC_PULSE, NON_BURST_SYNC_EVENTS, or BURST_MODE */
831bb76ff1Sjsg 	int video_mode;
84c349dbc7Sjsg 
85c349dbc7Sjsg 	/* eot for MIPI_EOT_DISABLE register */
86c349dbc7Sjsg 	u8 eotp_pkt;
87c349dbc7Sjsg 	u8 clock_stop;
88c349dbc7Sjsg 
89c349dbc7Sjsg 	u8 escape_clk_div;
90c349dbc7Sjsg 	u8 dual_link;
91c349dbc7Sjsg 
92c349dbc7Sjsg 	/* RGB or BGR */
93c349dbc7Sjsg 	bool bgr_enabled;
94c349dbc7Sjsg 
95c349dbc7Sjsg 	u8 pixel_overlap;
96c349dbc7Sjsg 	u32 port_bits;
97c349dbc7Sjsg 	u32 bw_timer;
98c349dbc7Sjsg 	u32 dphy_reg;
99c349dbc7Sjsg 
100c349dbc7Sjsg 	/* data lanes dphy timing */
101c349dbc7Sjsg 	u32 dphy_data_lane_reg;
102c349dbc7Sjsg 	u32 video_frmt_cfg_bits;
103c349dbc7Sjsg 	u16 lp_byte_clk;
104c349dbc7Sjsg 
105c349dbc7Sjsg 	/* timeouts in byte clocks */
106c349dbc7Sjsg 	u16 hs_tx_timeout;
107c349dbc7Sjsg 	u16 lp_rx_timeout;
108c349dbc7Sjsg 	u16 turn_arnd_val;
109c349dbc7Sjsg 	u16 rst_timer_val;
110c349dbc7Sjsg 	u16 hs_to_lp_count;
111c349dbc7Sjsg 	u16 clk_lp_to_hs_count;
112c349dbc7Sjsg 	u16 clk_hs_to_lp_count;
113c349dbc7Sjsg 
114c349dbc7Sjsg 	u16 init_count;
115c349dbc7Sjsg 	u32 pclk;
116c349dbc7Sjsg 	u16 burst_mode_ratio;
117c349dbc7Sjsg 
118c349dbc7Sjsg 	/* all delays in ms */
119c349dbc7Sjsg 	u16 backlight_off_delay;
120c349dbc7Sjsg 	u16 backlight_on_delay;
121c349dbc7Sjsg 	u16 panel_on_delay;
122c349dbc7Sjsg 	u16 panel_off_delay;
123c349dbc7Sjsg 	u16 panel_pwr_cycle_delay;
1245ca02815Sjsg 	ktime_t panel_power_off_time;
125c349dbc7Sjsg };
126c349dbc7Sjsg 
127c349dbc7Sjsg struct intel_dsi_host {
128c349dbc7Sjsg 	struct mipi_dsi_host base;
129c349dbc7Sjsg 	struct intel_dsi *intel_dsi;
130c349dbc7Sjsg 	enum port port;
131c349dbc7Sjsg 
132c349dbc7Sjsg 	/* our little hack */
133c349dbc7Sjsg 	struct mipi_dsi_device *device;
134c349dbc7Sjsg };
135c349dbc7Sjsg 
to_intel_dsi_host(struct mipi_dsi_host * h)136c349dbc7Sjsg static inline struct intel_dsi_host *to_intel_dsi_host(struct mipi_dsi_host *h)
137c349dbc7Sjsg {
138c349dbc7Sjsg 	return container_of(h, struct intel_dsi_host, base);
139c349dbc7Sjsg }
140c349dbc7Sjsg 
141c349dbc7Sjsg #define for_each_dsi_port(__port, __ports_mask) \
142c349dbc7Sjsg 	for_each_port_masked(__port, __ports_mask)
143c349dbc7Sjsg #define for_each_dsi_phy(__phy, __phys_mask) \
144c349dbc7Sjsg 	for_each_phy_masked(__phy, __phys_mask)
145c349dbc7Sjsg 
enc_to_intel_dsi(struct intel_encoder * encoder)146c349dbc7Sjsg static inline struct intel_dsi *enc_to_intel_dsi(struct intel_encoder *encoder)
147c349dbc7Sjsg {
148c349dbc7Sjsg 	return container_of(&encoder->base, struct intel_dsi, base.base);
149c349dbc7Sjsg }
150c349dbc7Sjsg 
is_vid_mode(struct intel_dsi * intel_dsi)151c349dbc7Sjsg static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
152c349dbc7Sjsg {
153c349dbc7Sjsg 	return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
154c349dbc7Sjsg }
155c349dbc7Sjsg 
is_cmd_mode(struct intel_dsi * intel_dsi)156c349dbc7Sjsg static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
157c349dbc7Sjsg {
158c349dbc7Sjsg 	return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
159c349dbc7Sjsg }
160c349dbc7Sjsg 
intel_dsi_encoder_ports(struct intel_encoder * encoder)161c349dbc7Sjsg static inline u16 intel_dsi_encoder_ports(struct intel_encoder *encoder)
162c349dbc7Sjsg {
163c349dbc7Sjsg 	return enc_to_intel_dsi(encoder)->ports;
164c349dbc7Sjsg }
165c349dbc7Sjsg 
166c349dbc7Sjsg int intel_dsi_bitrate(const struct intel_dsi *intel_dsi);
167c349dbc7Sjsg int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi);
168c349dbc7Sjsg enum drm_panel_orientation
169c349dbc7Sjsg intel_dsi_get_panel_orientation(struct intel_connector *connector);
170c349dbc7Sjsg int intel_dsi_get_modes(struct drm_connector *connector);
171c349dbc7Sjsg enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector,
172c349dbc7Sjsg 					  struct drm_display_mode *mode);
173c349dbc7Sjsg struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
174c349dbc7Sjsg 					   const struct mipi_dsi_host_ops *funcs,
175c349dbc7Sjsg 					   enum port port);
176*f005ef32Sjsg void intel_dsi_wait_panel_power_cycle(struct intel_dsi *intel_dsi);
177*f005ef32Sjsg void intel_dsi_shutdown(struct intel_encoder *encoder);
178c349dbc7Sjsg 
179c349dbc7Sjsg #endif /* _INTEL_DSI_H */
180