xref: /openbsd-src/sys/dev/pci/drm/i915/display/intel_dsi.c (revision f005ef32267c16bdb134f0e9fa4477dbe07c263a)
1c349dbc7Sjsg // SPDX-License-Identifier: MIT
2c349dbc7Sjsg /*
3c349dbc7Sjsg  * Copyright © 2018 Intel Corporation
4c349dbc7Sjsg  */
5c349dbc7Sjsg 
6c349dbc7Sjsg #include <drm/drm_mipi_dsi.h>
71bb76ff1Sjsg 
81bb76ff1Sjsg #include "i915_drv.h"
9c349dbc7Sjsg #include "intel_dsi.h"
101bb76ff1Sjsg #include "intel_panel.h"
11c349dbc7Sjsg 
intel_dsi_wait_panel_power_cycle(struct intel_dsi * intel_dsi)12*f005ef32Sjsg void intel_dsi_wait_panel_power_cycle(struct intel_dsi *intel_dsi)
13*f005ef32Sjsg {
14*f005ef32Sjsg 	ktime_t panel_power_on_time;
15*f005ef32Sjsg 	s64 panel_power_off_duration;
16*f005ef32Sjsg 
17*f005ef32Sjsg 	panel_power_on_time = ktime_get_boottime();
18*f005ef32Sjsg 	panel_power_off_duration = ktime_ms_delta(panel_power_on_time,
19*f005ef32Sjsg 						  intel_dsi->panel_power_off_time);
20*f005ef32Sjsg 
21*f005ef32Sjsg 	if (panel_power_off_duration < (s64)intel_dsi->panel_pwr_cycle_delay)
22*f005ef32Sjsg 		drm_msleep(intel_dsi->panel_pwr_cycle_delay - panel_power_off_duration);
23*f005ef32Sjsg }
24*f005ef32Sjsg 
intel_dsi_shutdown(struct intel_encoder * encoder)25*f005ef32Sjsg void intel_dsi_shutdown(struct intel_encoder *encoder)
26*f005ef32Sjsg {
27*f005ef32Sjsg 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
28*f005ef32Sjsg 
29*f005ef32Sjsg 	intel_dsi_wait_panel_power_cycle(intel_dsi);
30*f005ef32Sjsg }
31*f005ef32Sjsg 
intel_dsi_bitrate(const struct intel_dsi * intel_dsi)32c349dbc7Sjsg int intel_dsi_bitrate(const struct intel_dsi *intel_dsi)
33c349dbc7Sjsg {
34c349dbc7Sjsg 	int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
35c349dbc7Sjsg 
36c349dbc7Sjsg 	if (WARN_ON(bpp < 0))
37c349dbc7Sjsg 		bpp = 16;
38c349dbc7Sjsg 
39c349dbc7Sjsg 	return intel_dsi->pclk * bpp / intel_dsi->lane_count;
40c349dbc7Sjsg }
41c349dbc7Sjsg 
intel_dsi_tlpx_ns(const struct intel_dsi * intel_dsi)42c349dbc7Sjsg int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi)
43c349dbc7Sjsg {
44c349dbc7Sjsg 	switch (intel_dsi->escape_clk_div) {
45c349dbc7Sjsg 	default:
46c349dbc7Sjsg 	case 0:
47c349dbc7Sjsg 		return 50;
48c349dbc7Sjsg 	case 1:
49c349dbc7Sjsg 		return 100;
50c349dbc7Sjsg 	case 2:
51c349dbc7Sjsg 		return 200;
52c349dbc7Sjsg 	}
53c349dbc7Sjsg }
54c349dbc7Sjsg 
intel_dsi_get_modes(struct drm_connector * connector)55c349dbc7Sjsg int intel_dsi_get_modes(struct drm_connector *connector)
56c349dbc7Sjsg {
571bb76ff1Sjsg 	return intel_panel_get_modes(to_intel_connector(connector));
58c349dbc7Sjsg }
59c349dbc7Sjsg 
intel_dsi_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)60c349dbc7Sjsg enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector,
61c349dbc7Sjsg 					  struct drm_display_mode *mode)
62c349dbc7Sjsg {
63c349dbc7Sjsg 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
64c349dbc7Sjsg 	struct intel_connector *intel_connector = to_intel_connector(connector);
651bb76ff1Sjsg 	const struct drm_display_mode *fixed_mode =
661bb76ff1Sjsg 		intel_panel_fixed_mode(intel_connector, mode);
67c349dbc7Sjsg 	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
681bb76ff1Sjsg 	enum drm_mode_status status;
69c349dbc7Sjsg 
70ad8b1aafSjsg 	drm_dbg_kms(&dev_priv->drm, "\n");
71c349dbc7Sjsg 
72c349dbc7Sjsg 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
73c349dbc7Sjsg 		return MODE_NO_DBLESCAN;
74c349dbc7Sjsg 
751bb76ff1Sjsg 	status = intel_panel_mode_valid(intel_connector, mode);
761bb76ff1Sjsg 	if (status != MODE_OK)
771bb76ff1Sjsg 		return status;
781bb76ff1Sjsg 
79c349dbc7Sjsg 	if (fixed_mode->clock > max_dotclk)
80c349dbc7Sjsg 		return MODE_CLOCK_HIGH;
81c349dbc7Sjsg 
825ca02815Sjsg 	return intel_mode_valid_max_plane_size(dev_priv, mode, false);
83c349dbc7Sjsg }
84c349dbc7Sjsg 
intel_dsi_host_init(struct intel_dsi * intel_dsi,const struct mipi_dsi_host_ops * funcs,enum port port)85c349dbc7Sjsg struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
86c349dbc7Sjsg 					   const struct mipi_dsi_host_ops *funcs,
87c349dbc7Sjsg 					   enum port port)
88c349dbc7Sjsg {
89c349dbc7Sjsg 	struct intel_dsi_host *host;
90c349dbc7Sjsg 	struct mipi_dsi_device *device;
91c349dbc7Sjsg 
92c349dbc7Sjsg 	host = kzalloc(sizeof(*host), GFP_KERNEL);
93c349dbc7Sjsg 	if (!host)
94c349dbc7Sjsg 		return NULL;
95c349dbc7Sjsg 
96c349dbc7Sjsg 	host->base.ops = funcs;
97c349dbc7Sjsg 	host->intel_dsi = intel_dsi;
98c349dbc7Sjsg 	host->port = port;
99c349dbc7Sjsg 
100c349dbc7Sjsg 	/*
101c349dbc7Sjsg 	 * We should call mipi_dsi_host_register(&host->base) here, but we don't
102c349dbc7Sjsg 	 * have a host->dev, and we don't have OF stuff either. So just use the
103c349dbc7Sjsg 	 * dsi framework as a library and hope for the best. Create the dsi
104c349dbc7Sjsg 	 * devices by ourselves here too. Need to be careful though, because we
105c349dbc7Sjsg 	 * don't initialize any of the driver model devices here.
106c349dbc7Sjsg 	 */
107c349dbc7Sjsg 	device = kzalloc(sizeof(*device), GFP_KERNEL);
108c349dbc7Sjsg 	if (!device) {
109c349dbc7Sjsg 		kfree(host);
110c349dbc7Sjsg 		return NULL;
111c349dbc7Sjsg 	}
112c349dbc7Sjsg 
113c349dbc7Sjsg 	device->host = &host->base;
114c349dbc7Sjsg 	host->device = device;
115c349dbc7Sjsg 
116c349dbc7Sjsg 	return host;
117c349dbc7Sjsg }
118c349dbc7Sjsg 
119c349dbc7Sjsg enum drm_panel_orientation
intel_dsi_get_panel_orientation(struct intel_connector * connector)120c349dbc7Sjsg intel_dsi_get_panel_orientation(struct intel_connector *connector)
121c349dbc7Sjsg {
122c349dbc7Sjsg 	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
123c349dbc7Sjsg 	enum drm_panel_orientation orientation;
124c349dbc7Sjsg 
1251bb76ff1Sjsg 	orientation = connector->panel.vbt.dsi.orientation;
126c349dbc7Sjsg 	if (orientation != DRM_MODE_PANEL_ORIENTATION_UNKNOWN)
127c349dbc7Sjsg 		return orientation;
128c349dbc7Sjsg 
1291bb76ff1Sjsg 	orientation = dev_priv->display.vbt.orientation;
130c349dbc7Sjsg 	if (orientation != DRM_MODE_PANEL_ORIENTATION_UNKNOWN)
131c349dbc7Sjsg 		return orientation;
132c349dbc7Sjsg 
133c349dbc7Sjsg 	return DRM_MODE_PANEL_ORIENTATION_NORMAL;
134c349dbc7Sjsg }
135