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Searched refs:setOpcode (Results 1 – 25 of 89) sorted by relevance

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/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp710 Result.setOpcode(Hexagon::SA1_inc); in deriveSubInst()
716 Result.setOpcode(Hexagon::SA1_dec); in deriveSubInst()
723 Result.setOpcode(Hexagon::SA1_addsp); in deriveSubInst()
729 Result.setOpcode(Hexagon::SA1_addi); in deriveSubInst()
735 Result.setOpcode(Hexagon::SA1_addrx); in deriveSubInst()
741 Result.setOpcode(Hexagon::SS2_allocframe); in deriveSubInst()
746 Result.setOpcode(Hexagon::SA1_zxtb); in deriveSubInst()
751 Result.setOpcode(Hexagon::SA1_and1); in deriveSubInst()
757 Result.setOpcode(Hexagon::SA1_cmpeqi); in deriveSubInst()
766 Result.setOpcode(Hexago in deriveSubInst()
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H A DHexagonMCCompound.cpp214 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
227 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
241 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
254 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
267 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
285 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
303 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
314 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
325 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonAsmPrinter.cpp247 T.setOpcode(Inst.getOpcode()); in ScaleVectorOffset()
276 Inst.setOpcode(Hexagon::A2_addi); in HexagonProcessInstruction()
290 Inst.setOpcode(Hexagon::A2_paddif); in HexagonProcessInstruction()
297 Inst.setOpcode(Hexagon::A2_paddit); in HexagonProcessInstruction()
304 Inst.setOpcode(Hexagon::A2_paddifnew); in HexagonProcessInstruction()
311 Inst.setOpcode(Hexagon::A2_padditnew); in HexagonProcessInstruction()
318 Inst.setOpcode(Hexagon::A2_andir); in HexagonProcessInstruction()
335 TmpInst.setOpcode(Hexagon::L2_loadrdgp); in HexagonProcessInstruction()
352 TmpInst.setOpcode(Hexagon::L2_loadrigp); in HexagonProcessInstruction()
365 MappedInst.setOpcode(Hexago in HexagonProcessInstruction()
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/llvm-project/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp256 Inst.setOpcode(XCore::STW_2rus); in Decode2OpInstructionFail()
259 Inst.setOpcode(XCore::LDW_2rus); in Decode2OpInstructionFail()
262 Inst.setOpcode(XCore::ADD_3r); in Decode2OpInstructionFail()
265 Inst.setOpcode(XCore::SUB_3r); in Decode2OpInstructionFail()
268 Inst.setOpcode(XCore::SHL_3r); in Decode2OpInstructionFail()
271 Inst.setOpcode(XCore::SHR_3r); in Decode2OpInstructionFail()
274 Inst.setOpcode(XCore::EQ_3r); in Decode2OpInstructionFail()
277 Inst.setOpcode(XCore::AND_3r); in Decode2OpInstructionFail()
280 Inst.setOpcode(XCore::OR_3r); in Decode2OpInstructionFail()
283 Inst.setOpcode(XCore::LDW_3r); in Decode2OpInstructionFail()
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/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp162 MCB.setOpcode(Hexagon::BUNDLE); in HexagonAsmParser()
542 NewInst.setOpcode(MCI.getOpcode()); in canonicalizeImmediates()
1290 TmpInst.setOpcode(opCode); in makeCombineInst()
1397 Inst.setOpcode(Hexagon::A2_addi); in processInstruction()
1431 Inst.setOpcode(Hexagon::C2_cmpgti); in processInstruction()
1445 TmpInst.setOpcode(Hexagon::C2_cmpeq); in processInstruction()
1455 Inst.setOpcode(Hexagon::C2_cmpgtui); in processInstruction()
1467 Inst.setOpcode(Hexagon::A2_combinew); in processInstruction()
1478 Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt) in processInstruction()
1490 Inst.setOpcode((Ins in processInstruction()
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/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVAsmPrinter.cpp168 FunctionEndInst.setOpcode(SPIRV::OpFunctionEnd); in emitBasicBlockStart()
183 LabelInst.setOpcode(SPIRV::OpLabel); in printOperand()
301 Inst.setOpcode(SPIRV::OpSourceExtension); in outputOpMemoryModel()
309 Inst.setOpcode(SPIRV::OpSource);
321 Inst.setOpcode(SPIRV::OpExtInstImport); in outputEntryPoints()
332 Inst.setOpcode(SPIRV::OpMemoryModel); in outputEntryPoints()
381 Inst.setOpcode(SPIRV::OpCapability); in encodeVecTypeHint()
389 Inst.setOpcode(SPIRV::OpExtension); in encodeVecTypeHint()
459 Inst.setOpcode(SPIRV::OpExecutionMode); in outputExecutionModeFromNumthreadsAttribute()
478 Inst.setOpcode(SPIR in outputExecutionMode()
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/llvm-project/llvm/lib/Target/AVR/Disassembler/
H A DAVRDisassembler.cpp280 Inst.setOpcode(AVR::RJMPk); in decodeFBRk()
283 Inst.setOpcode(AVR::RCALLk); in decodeFBRk()
316 Inst.setOpcode(It->second); in decodeCondBranch()
320 Inst.setOpcode(Insn & 0x400 ? AVR::BRBCsk : AVR::BRBSsk); in decodeCondBranch()
339 Inst.setOpcode(AVR::LDDRdPtrQ); in decodeLoadStore()
344 Inst.setOpcode(AVR::STDPtrQRr); in decodeLoadStore()
392 Inst.setOpcode(AVR::STPtrRr); in decodeLoadStore()
397 Inst.setOpcode(AVR::STPtrPiRr); in decodeLoadStore()
400 Inst.setOpcode(AVR::STPtrPdRr); in decodeLoadStore()
403 Inst.setOpcode(AV in decodeLoadStore()
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/llvm-project/bolt/lib/Target/AArch64/
H A DAArch64MCPlusBuilder.cpp39 Inst.setOpcode(AArch64::MRS); in getSystemFlag()
46 Inst.setOpcode(AArch64::MSR); in setSystemFlag()
55 Inst.setOpcode(NewOpcode); in createPushRegisters()
66 Inst.setOpcode(NewOpcode); in createPopRegisters()
75 Inst.setOpcode(AArch64::LDRXui); in loadReg()
78 Inst.setOpcode(AArch64::LDRXpost); in loadReg()
91 Inst.setOpcode(AArch64::STRXui); in storeReg()
94 Inst.setOpcode(AArch64::STRXpre); in storeReg()
108 Inst.setOpcode(AArch64::LDADDX); in atomicAdd()
118 Inst.setOpcode(AArch6 in createMovz()
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/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYAsmBackend.cpp301 Res.setOpcode(CSKY::LRW32); in relaxInstruction()
306 Res.setOpcode(CSKY::BR32); in relaxInstruction()
310 Res.setOpcode(CSKY::JSRI32); in relaxInstruction()
314 Res.setOpcode(CSKY::JMPI32); in relaxInstruction()
319 Res.setOpcode(Inst.getOpcode() == CSKY::JBT32 ? CSKY::JBT_E : CSKY::JBF_E); in relaxInstruction()
325 Res.setOpcode(CSKY::JBR32); in relaxInstruction()
338 Res.setOpcode(opcode); in relaxInstruction()
/llvm-project/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp834 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ? in ProcessInstruction()
846 TmpInst.setOpcode(PPC::DCBT); in ProcessInstruction()
856 TmpInst.setOpcode(PPC::DCBTST); in ProcessInstruction()
879 TmpInst.setOpcode(PPC::DCBF); in ProcessInstruction()
888 TmpInst.setOpcode(PPC::LA); in ProcessInstruction()
898 TmpInst.setOpcode(Opcode == PPC::PLA ? PPC::PADDI : PPC::PADDI8); in ProcessInstruction()
908 TmpInst.setOpcode(Opcode == PPC::PLApc ? PPC::PADDIpc : PPC::PADDI8pc); in ProcessInstruction()
917 TmpInst.setOpcode(PPC::ADDI); in ProcessInstruction()
926 TmpInst.setOpcode(PPC::PADDI); in ProcessInstruction()
935 TmpInst.setOpcode(PP in ProcessInstruction()
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/llvm-project/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp622 MI.setOpcode(Mips::BOVC); in DecodeAddiGroupBranch()
625 MI.setOpcode(Mips::BEQC); in DecodeAddiGroupBranch()
628 MI.setOpcode(Mips::BEQZALC); in DecodeAddiGroupBranch()
650 MI.setOpcode(Mips::BOVC_MMR6); in DecodePOP35GroupBranchMMR6()
657 MI.setOpcode(Mips::BEQC_MMR6); in DecodePOP35GroupBranchMMR6()
664 MI.setOpcode(Mips::BEQZALC_MMR6); in DecodePOP35GroupBranchMMR6()
695 MI.setOpcode(Mips::BNVC); in DecodeDaddiGroupBranch()
698 MI.setOpcode(Mips::BNEC); in DecodeDaddiGroupBranch()
701 MI.setOpcode(Mips::BNEZALC); in DecodeDaddiGroupBranch()
723 MI.setOpcode(Mip in DecodePOP37GroupBranchMMR6()
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/llvm-project/llvm/lib/Target/VE/
H A DVEAsmPrinter.cpp85 SICInst.setOpcode(VE::SIC); in emitSIC()
93 BSICInst.setOpcode(VE::BSICrii); in emitBSIC()
105 LEAInst.setOpcode(VE::LEAzii); in emitLEAzzi()
117 LEASLInst.setOpcode(VE::LEASLzii); in emitLEASLzzi()
129 LEAInst.setOpcode(VE::LEAzii); in emitLEAzii()
142 LEASLInst.setOpcode(VE::LEASLrri); in emitLEASLrri()
154 Inst.setOpcode(Opcode); in emitBinary()
/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2471 Inst.setOpcode(ARM::RFEDA); in DecodeMemMultipleWritebackInstruction()
2474 Inst.setOpcode(ARM::RFEDA_UPD); in DecodeMemMultipleWritebackInstruction()
2477 Inst.setOpcode(ARM::RFEDB); in DecodeMemMultipleWritebackInstruction()
2480 Inst.setOpcode(ARM::RFEDB_UPD); in DecodeMemMultipleWritebackInstruction()
2483 Inst.setOpcode(ARM::RFEIA); in DecodeMemMultipleWritebackInstruction()
2486 Inst.setOpcode(ARM::RFEIA_UPD); in DecodeMemMultipleWritebackInstruction()
2489 Inst.setOpcode(ARM::RFEIB); in DecodeMemMultipleWritebackInstruction()
2492 Inst.setOpcode(ARM::RFEIB_UPD); in DecodeMemMultipleWritebackInstruction()
2495 Inst.setOpcode(ARM::SRSDA); in DecodeMemMultipleWritebackInstruction()
2498 Inst.setOpcode(AR in DecodeMemMultipleWritebackInstruction()
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/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86EncodingOptimization.cpp96 MI.setOpcode(NewOpc); in optimizeInstFromVEX3ToVEX2()
197 MI.setOpcode(NewOpc); in optimizeShiftRotateWithImmediateOne()
284 MI.setOpcode(NewOpc); in optimizeVPCMPWithImmediateOneOrSix()
307 MI.setOpcode(NewOpc); in optimizeMOVSX()
328 MI.setOpcode(NewOpc); in optimizeINCDEC()
388 MI.setOpcode(NewOpc); in optimizeMOV()
446 MI.setOpcode(NewOpc); in optimizeToFixedRegisterForm()
494 MI.setOpcode(NewOpc); in optimizeToShortImmediateForm()
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AsmPrinter.cpp1779 MI.setOpcode(Opcode); in LowerMOVaddrPAC()
1835 MOVI.setOpcode(AArch64::MOVID); in LowerMOVaddrPAC()
1844 FMov.setOpcode(STI->hasFullFP16() ? AArch64::FMOVWHr : AArch64::FMOVWSr); in LowerMOVaddrPAC()
1851 FMov.setOpcode(AArch64::FMOVWSr); in LowerMOVaddrPAC()
1856 FMov.setOpcode(AArch64::FMOVXDr); in LowerMOVaddrPAC()
2121 AUTInst.setOpcode(AUTOpc); in emitInstruction()
2163 PACInst.setOpcode(PACOpc); in emitInstruction()
2218 BRInst.setOpcode(Opc); in emitInstruction()
2678 MovZ.setOpcode(AArch64::MOVZXi);
2685 MovK.setOpcode(AArch6
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/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp299 ITInst.setOpcode(ARM::t2IT); in flushPendingInstructions()
5883 case ARM::tBcc: Inst.setOpcode(ARM::tB); break; in cvtThumbBranches()
5884 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break; in cvtThumbBranches()
5890 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc); in cvtThumbBranches()
5894 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc); in cvtThumbBranches()
5905 Inst.setOpcode(ARM::t2B); in cvtMVEVMOVQtoDReg()
5912 Inst.setOpcode(ARM::t2Bcc); in cvtMVEVMOVQtoDReg()
8948 TmpInst.setOpcode(Opcode); in processInstruction()
8966 TmpInst.setOpcode(Opcode); in processInstruction()
8984 TmpInst.setOpcode(AR in processInstruction()
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/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp179 TmpInst.setOpcode(Opcode); in emitR()
188 TmpInst.setOpcode(Opcode); in emitRX()
208 TmpInst.setOpcode(Opcode); in emitII()
219 TmpInst.setOpcode(Opcode); in emitRRX()
237 TmpInst.setOpcode(Opcode); in emitRRRX()
257 TmpInst.setOpcode(Opcode); in emitRRIII()
1175 TmpInst.setOpcode(Mips::LUi); in emitDirectiveCpLoad()
1187 TmpInst.setOpcode(Mips::ADDiu); in emitDirectiveCpLoad()
1200 TmpInst.setOpcode(Mips::ADDu); in emitDirectiveCpLoad()
1287 Inst.setOpcode(Mip in emitDirectiveCpreturn()
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/llvm-project/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp181 MI.setOpcode(Hexagon::BUNDLE); in getInstruction()
213 MI.setOpcode(Hexagon::S6_allocframe_to_raw); in remapInstruction()
221 MI.setOpcode(L6_deallocframe_map_to_raw); in remapInstruction()
229 MI.setOpcode(L6_return_map_to_raw); in remapInstruction()
237 MI.setOpcode(L4_return_map_to_raw_t); in remapInstruction()
245 MI.setOpcode(L4_return_map_to_raw_f); in remapInstruction()
253 MI.setOpcode(L4_return_map_to_raw_tnew_pt); in remapInstruction()
261 MI.setOpcode(L4_return_map_to_raw_fnew_pt); in remapInstruction()
269 MI.setOpcode(L4_return_map_to_raw_tnew_pnt); in remapInstruction()
277 MI.setOpcode(L4_return_map_to_raw_fnew_pn in remapInstruction()
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/llvm-project/llvm/lib/Target/Mips/
H A DMipsAsmPrinter.cpp116 TmpInst0.setOpcode(Mips::JALR64); in emitPseudoIndirectBranch()
121 TmpInst0.setOpcode(Mips::JRC16_MMR6); in emitPseudoIndirectBranch()
123 TmpInst0.setOpcode(Mips::JALR); in emitPseudoIndirectBranch()
128 TmpInst0.setOpcode(Mips::JR_MM); in emitPseudoIndirectBranch()
131 TmpInst0.setOpcode(Mips::JR); in emitPseudoIndirectBranch()
826 I.setOpcode(Mips::JAL); in EmitJal()
835 I.setOpcode(Opcode); in EmitInstrReg()
854 I.setOpcode(Opcode); in EmitInstrRegReg()
864 I.setOpcode(Opcode); in EmitInstrRegRegReg()
H A DMipsMCInstLower.cpp225 OutMI.setOpcode(Mips::LUi); in lowerLongBranchLUi()
263 OutMI.setOpcode(Opcode); in lowerLongBranchADDiu()
328 OutMI.setOpcode(MI->getOpcode());
/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrInfo.cpp34 NopInst.setOpcode(ARM::HINT);
39 NopInst.setOpcode(ARM::MOVr); in getNop()
/llvm-project/bolt/lib/Target/RISCV/
H A DRISCVMCPlusBuilder.cpp157 Inst.setOpcode(Opcode); in reverseBranchCondition()
221 Inst.setOpcode(RISCV::JALR); in createReturn()
230 Inst.setOpcode(RISCV::JAL); in createUncondBranch()
243 Inst.setOpcode(Opcode); in createCall()
/llvm-project/llvm/lib/Target/M68k/
H A DM68kMCInstLower.cpp162 OutMI.setOpcode(Opcode); in Lower()
183 OutMI.setOpcode(Opcode); in Lower()
/llvm-project/llvm/lib/Target/Sparc/
H A DSparcAsmPrinter.cpp109 CallInst.setOpcode(SP::CALL); in EmitCall()
117 RDPCInst.setOpcode(SP::RDASR); in EmitRDPC()
128 SETHIInst.setOpcode(SP::SETHIi); in EmitSETHI()
139 Inst.setOpcode(Opcode); in EmitBinary()
/llvm-project/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp408 OutMI.setOpcode(MI->getOpcode()); in Lower()
448 OutMI.setOpcode(NewOpc); in Lower()
465 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget())); in Lower()
471 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget())); in Lower()
479 OutMI.setOpcode(getRetOpcode(Subtarget)); in Lower()
491 OutMI.setOpcode(convertTailJumpOpcode(OutMI.getOpcode())); in Lower()
496 OutMI.setOpcode(convertTailJumpOpcode(OutMI.getOpcode())); in Lower()
503 OutMI.setOpcode(convertTailJumpOpcode(OutMI.getOpcode())); in Lower()
838 CallInst.setOpcode(CallOpcode); in LowerSTATEPOINT()
873 MI.setOpcode(Opcod in LowerFAULTING_OP()
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