1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "ARMBaseInstrInfo.h" 10 #include "MCTargetDesc/ARMAddressingModes.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMMCTargetDesc.h" 13 #include "TargetInfo/ARMTargetInfo.h" 14 #include "Utils/ARMBaseInfo.h" 15 #include "llvm/MC/MCContext.h" 16 #include "llvm/MC/MCDecoderOps.h" 17 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCInstrInfo.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/MC/TargetRegistry.h" 23 #include "llvm/Support/Compiler.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/MathExtras.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include "llvm/TargetParser/SubtargetFeature.h" 28 #include <algorithm> 29 #include <cassert> 30 #include <cstdint> 31 #include <vector> 32 33 using namespace llvm; 34 35 #define DEBUG_TYPE "arm-disassembler" 36 37 using DecodeStatus = MCDisassembler::DecodeStatus; 38 39 namespace { 40 41 // Handles the condition code status of instructions in IT blocks 42 class ITStatus 43 { 44 public: 45 // Returns the condition code for instruction in IT block 46 unsigned getITCC() { 47 unsigned CC = ARMCC::AL; 48 if (instrInITBlock()) 49 CC = ITStates.back(); 50 return CC; 51 } 52 53 // Advances the IT block state to the next T or E 54 void advanceITState() { 55 ITStates.pop_back(); 56 } 57 58 // Returns true if the current instruction is in an IT block 59 bool instrInITBlock() { 60 return !ITStates.empty(); 61 } 62 63 // Returns true if current instruction is the last instruction in an IT block 64 bool instrLastInITBlock() { 65 return ITStates.size() == 1; 66 } 67 68 // Called when decoding an IT instruction. Sets the IT state for 69 // the following instructions that for the IT block. Firstcond 70 // corresponds to the field in the IT instruction encoding; Mask 71 // is in the MCOperand format in which 1 means 'else' and 0 'then'. 72 void setITState(char Firstcond, char Mask) { 73 // (3 - the number of trailing zeros) is the number of then / else. 74 unsigned NumTZ = llvm::countr_zero<uint8_t>(Mask); 75 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 76 assert(NumTZ <= 3 && "Invalid IT mask!"); 77 // push condition codes onto the stack the correct order for the pops 78 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 79 unsigned Else = (Mask >> Pos) & 1; 80 ITStates.push_back(CCBits ^ Else); 81 } 82 ITStates.push_back(CCBits); 83 } 84 85 private: 86 std::vector<unsigned char> ITStates; 87 }; 88 89 class VPTStatus 90 { 91 public: 92 unsigned getVPTPred() { 93 unsigned Pred = ARMVCC::None; 94 if (instrInVPTBlock()) 95 Pred = VPTStates.back(); 96 return Pred; 97 } 98 99 void advanceVPTState() { 100 VPTStates.pop_back(); 101 } 102 103 bool instrInVPTBlock() { 104 return !VPTStates.empty(); 105 } 106 107 bool instrLastInVPTBlock() { 108 return VPTStates.size() == 1; 109 } 110 111 void setVPTState(char Mask) { 112 // (3 - the number of trailing zeros) is the number of then / else. 113 unsigned NumTZ = llvm::countr_zero<uint8_t>(Mask); 114 assert(NumTZ <= 3 && "Invalid VPT mask!"); 115 // push predicates onto the stack the correct order for the pops 116 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 117 bool T = ((Mask >> Pos) & 1) == 0; 118 if (T) 119 VPTStates.push_back(ARMVCC::Then); 120 else 121 VPTStates.push_back(ARMVCC::Else); 122 } 123 VPTStates.push_back(ARMVCC::Then); 124 } 125 126 private: 127 SmallVector<unsigned char, 4> VPTStates; 128 }; 129 130 /// ARM disassembler for all ARM platforms. 131 class ARMDisassembler : public MCDisassembler { 132 public: 133 std::unique_ptr<const MCInstrInfo> MCII; 134 135 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 136 const MCInstrInfo *MCII) 137 : MCDisassembler(STI, Ctx), MCII(MCII) { 138 InstructionEndianness = STI.hasFeature(ARM::ModeBigEndianInstructions) 139 ? llvm::endianness::big 140 : llvm::endianness::little; 141 } 142 143 ~ARMDisassembler() override = default; 144 145 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 146 ArrayRef<uint8_t> Bytes, uint64_t Address, 147 raw_ostream &CStream) const override; 148 149 uint64_t suggestBytesToSkip(ArrayRef<uint8_t> Bytes, 150 uint64_t Address) const override; 151 152 private: 153 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size, 154 ArrayRef<uint8_t> Bytes, uint64_t Address, 155 raw_ostream &CStream) const; 156 157 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size, 158 ArrayRef<uint8_t> Bytes, uint64_t Address, 159 raw_ostream &CStream) const; 160 161 mutable ITStatus ITBlock; 162 mutable VPTStatus VPTBlock; 163 164 void AddThumb1SBit(MCInst &MI, bool InITBlock) const; 165 bool isVectorPredicable(const MCInst &MI) const; 166 DecodeStatus AddThumbPredicate(MCInst&) const; 167 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 168 169 llvm::endianness InstructionEndianness; 170 }; 171 172 } // end anonymous namespace 173 174 // Forward declare these because the autogenerated code will reference them. 175 // Definitions are further down. 176 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 177 uint64_t Address, 178 const MCDisassembler *Decoder); 179 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 180 uint64_t Address, 181 const MCDisassembler *Decoder); 182 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 183 uint64_t Address, 184 const MCDisassembler *Decoder); 185 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 186 uint64_t Address, 187 const MCDisassembler *Decoder); 188 static DecodeStatus 189 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, 190 uint64_t Address, 191 const MCDisassembler *Decoder); 192 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 193 uint64_t Address, 194 const MCDisassembler *Decoder); 195 static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo, 196 uint64_t Address, 197 const MCDisassembler *Decoder); 198 static DecodeStatus 199 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 200 const MCDisassembler *Decoder); 201 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, 202 uint64_t Address, 203 const MCDisassembler *Decoder); 204 static DecodeStatus 205 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 206 const MCDisassembler *Decoder); 207 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 208 uint64_t Address, 209 const MCDisassembler *Decoder); 210 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 211 uint64_t Address, 212 const MCDisassembler *Decoder); 213 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 214 uint64_t Address, 215 const MCDisassembler *Decoder); 216 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 217 uint64_t Address, 218 const MCDisassembler *Decoder); 219 static DecodeStatus 220 DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 221 const MCDisassembler *Decoder); 222 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 223 uint64_t Address, 224 const MCDisassembler *Decoder); 225 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 226 uint64_t Address, 227 const MCDisassembler *Decoder); 228 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 229 uint64_t Address, 230 const MCDisassembler *Decoder); 231 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 232 uint64_t Address, 233 const MCDisassembler *Decoder); 234 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 235 uint64_t Address, 236 const MCDisassembler *Decoder); 237 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 238 uint64_t Address, 239 const MCDisassembler *Decoder); 240 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 241 uint64_t Address, 242 const MCDisassembler *Decoder); 243 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 244 uint64_t Address, 245 const MCDisassembler *Decoder); 246 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 247 uint64_t Address, 248 const MCDisassembler *Decoder); 249 static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 250 uint64_t Address, 251 const MCDisassembler *Decoder); 252 static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 253 uint64_t Address, 254 const MCDisassembler *Decoder); 255 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 256 uint64_t Address, 257 const MCDisassembler *Decoder); 258 static DecodeStatus 259 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 260 const MCDisassembler *Decoder); 261 262 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 263 uint64_t Address, 264 const MCDisassembler *Decoder); 265 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 266 uint64_t Address, 267 const MCDisassembler *Decoder); 268 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 269 uint64_t Address, 270 const MCDisassembler *Decoder); 271 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 272 uint64_t Address, 273 const MCDisassembler *Decoder); 274 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 275 uint64_t Address, 276 const MCDisassembler *Decoder); 277 278 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 279 uint64_t Address, 280 const MCDisassembler *Decoder); 281 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 282 uint64_t Address, 283 const MCDisassembler *Decoder); 284 static DecodeStatus 285 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 286 const MCDisassembler *Decoder); 287 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 288 uint64_t Address, 289 const MCDisassembler *Decoder); 290 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 291 uint64_t Address, 292 const MCDisassembler *Decoder); 293 static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn, 294 uint64_t Address, 295 const MCDisassembler *Decoder); 296 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 297 uint64_t Address, 298 const MCDisassembler *Decoder); 299 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 300 uint64_t Address, 301 const MCDisassembler *Decoder); 302 303 static DecodeStatus 304 DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, 305 uint64_t Adddress, 306 const MCDisassembler *Decoder); 307 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 308 uint64_t Address, 309 const MCDisassembler *Decoder); 310 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 311 uint64_t Address, 312 const MCDisassembler *Decoder); 313 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 314 uint64_t Address, 315 const MCDisassembler *Decoder); 316 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 317 uint64_t Address, 318 const MCDisassembler *Decoder); 319 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 320 uint64_t Address, 321 const MCDisassembler *Decoder); 322 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 323 uint64_t Address, 324 const MCDisassembler *Decoder); 325 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 326 uint64_t Address, 327 const MCDisassembler *Decoder); 328 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 329 uint64_t Address, 330 const MCDisassembler *Decoder); 331 static DecodeStatus DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, 332 uint64_t Address, 333 const MCDisassembler *Decoder); 334 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 335 uint64_t Address, 336 const MCDisassembler *Decoder); 337 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 338 uint64_t Address, 339 const MCDisassembler *Decoder); 340 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 341 uint64_t Address, 342 const MCDisassembler *Decoder); 343 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 344 uint64_t Address, 345 const MCDisassembler *Decoder); 346 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 347 uint64_t Address, 348 const MCDisassembler *Decoder); 349 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 350 uint64_t Address, 351 const MCDisassembler *Decoder); 352 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 353 uint64_t Address, 354 const MCDisassembler *Decoder); 355 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 356 uint64_t Address, 357 const MCDisassembler *Decoder); 358 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 359 uint64_t Address, 360 const MCDisassembler *Decoder); 361 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 362 uint64_t Address, 363 const MCDisassembler *Decoder); 364 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 365 uint64_t Address, 366 const MCDisassembler *Decoder); 367 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 368 uint64_t Address, 369 const MCDisassembler *Decoder); 370 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 371 uint64_t Address, 372 const MCDisassembler *Decoder); 373 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 374 uint64_t Address, 375 const MCDisassembler *Decoder); 376 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 377 uint64_t Address, 378 const MCDisassembler *Decoder); 379 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 380 uint64_t Address, 381 const MCDisassembler *Decoder); 382 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 383 uint64_t Address, 384 const MCDisassembler *Decoder); 385 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Val, 386 uint64_t Address, 387 const MCDisassembler *Decoder); 388 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Val, 389 uint64_t Address, 390 const MCDisassembler *Decoder); 391 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 392 uint64_t Address, 393 const MCDisassembler *Decoder); 394 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 395 uint64_t Address, 396 const MCDisassembler *Decoder); 397 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 398 uint64_t Address, 399 const MCDisassembler *Decoder); 400 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 401 uint64_t Address, 402 const MCDisassembler *Decoder); 403 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 404 uint64_t Address, 405 const MCDisassembler *Decoder); 406 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 407 uint64_t Address, 408 const MCDisassembler *Decoder); 409 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 410 uint64_t Address, 411 const MCDisassembler *Decoder); 412 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 413 uint64_t Address, 414 const MCDisassembler *Decoder); 415 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 416 uint64_t Address, 417 const MCDisassembler *Decoder); 418 template <int shift> 419 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 420 uint64_t Address, 421 const MCDisassembler *Decoder); 422 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 423 uint64_t Address, 424 const MCDisassembler *Decoder); 425 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 426 uint64_t Address, 427 const MCDisassembler *Decoder); 428 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 429 uint64_t Address, 430 const MCDisassembler *Decoder); 431 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, uint64_t Address, 432 const MCDisassembler *Decoder); 433 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 434 uint64_t Address, 435 const MCDisassembler *Decoder); 436 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 437 uint64_t Address, 438 const MCDisassembler *Decoder); 439 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 440 uint64_t Address, 441 const MCDisassembler *Decoder); 442 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 443 uint64_t Address, 444 const MCDisassembler *Decoder); 445 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 446 uint64_t Address, 447 const MCDisassembler *Decoder); 448 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 449 uint64_t Address, 450 const MCDisassembler *Decoder); 451 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 452 uint64_t Address, 453 const MCDisassembler *Decoder); 454 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, 455 const MCDisassembler *Decoder); 456 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, 457 const MCDisassembler *Decoder); 458 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, 459 const MCDisassembler *Decoder); 460 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, 461 const MCDisassembler *Decoder); 462 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, 463 const MCDisassembler *Decoder); 464 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, 465 const MCDisassembler *Decoder); 466 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, 467 const MCDisassembler *Decoder); 468 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, 469 const MCDisassembler *Decoder); 470 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, 471 const MCDisassembler *Decoder); 472 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, 473 const MCDisassembler *Decoder); 474 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, 475 const MCDisassembler *Decoder); 476 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, 477 const MCDisassembler *Decoder); 478 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, 479 const MCDisassembler *Decoder); 480 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn, 481 uint64_t Address, 482 const MCDisassembler *Decoder); 483 static DecodeStatus 484 DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Val, uint64_t Address, 485 const MCDisassembler *Decoder); 486 487 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 488 uint64_t Address, 489 const MCDisassembler *Decoder); 490 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 491 uint64_t Address, 492 const MCDisassembler *Decoder); 493 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 494 uint64_t Address, 495 const MCDisassembler *Decoder); 496 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 497 uint64_t Address, 498 const MCDisassembler *Decoder); 499 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 500 uint64_t Address, 501 const MCDisassembler *Decoder); 502 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 503 uint64_t Address, 504 const MCDisassembler *Decoder); 505 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 506 uint64_t Address, 507 const MCDisassembler *Decoder); 508 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 509 uint64_t Address, 510 const MCDisassembler *Decoder); 511 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 512 uint64_t Address, 513 const MCDisassembler *Decoder); 514 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 515 uint64_t Address, 516 const MCDisassembler *Decoder); 517 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 518 uint64_t Address, 519 const MCDisassembler *Decoder); 520 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 521 uint64_t Address, 522 const MCDisassembler *Decoder); 523 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, 524 const MCDisassembler *Decoder); 525 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 526 uint64_t Address, 527 const MCDisassembler *Decoder); 528 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, 529 const MCDisassembler *Decoder); 530 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 531 const MCDisassembler *Decoder); 532 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 533 uint64_t Address, 534 const MCDisassembler *Decoder); 535 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 536 uint64_t Address, 537 const MCDisassembler *Decoder); 538 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val, 539 uint64_t Address, 540 const MCDisassembler *Decoder); 541 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, 542 const MCDisassembler *Decoder); 543 template <int shift> 544 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address, 545 const MCDisassembler *Decoder); 546 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 547 uint64_t Address, 548 const MCDisassembler *Decoder); 549 template <int shift> 550 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 551 uint64_t Address, 552 const MCDisassembler *Decoder); 553 template <int shift, int WriteBack> 554 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 555 uint64_t Address, 556 const MCDisassembler *Decoder); 557 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 558 uint64_t Address, 559 const MCDisassembler *Decoder); 560 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 561 uint64_t Address, 562 const MCDisassembler *Decoder); 563 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 564 uint64_t Address, 565 const MCDisassembler *Decoder); 566 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 567 uint64_t Address, 568 const MCDisassembler *Decoder); 569 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 570 uint64_t Address, 571 const MCDisassembler *Decoder); 572 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 573 uint64_t Address, 574 const MCDisassembler *Decoder); 575 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 576 uint64_t Address, 577 const MCDisassembler *Decoder); 578 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 579 uint64_t Address, 580 const MCDisassembler *Decoder); 581 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, 582 const MCDisassembler *Decoder); 583 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 584 uint64_t Address, 585 const MCDisassembler *Decoder); 586 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 587 uint64_t Address, 588 const MCDisassembler *Decoder); 589 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, uint64_t Address, 590 const MCDisassembler *Decoder); 591 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 592 uint64_t Address, 593 const MCDisassembler *Decoder); 594 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 595 uint64_t Address, 596 const MCDisassembler *Decoder); 597 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, uint64_t Address, 598 const MCDisassembler *Decoder); 599 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 600 uint64_t Address, 601 const MCDisassembler *Decoder); 602 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 603 uint64_t Address, 604 const MCDisassembler *Decoder); 605 606 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, 607 const MCDisassembler *Decoder); 608 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 609 uint64_t Address, 610 const MCDisassembler *Decoder); 611 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 612 uint64_t Address, 613 const MCDisassembler *Decoder); 614 615 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 616 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, 617 uint64_t Address, 618 const MCDisassembler *Decoder); 619 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, 620 uint64_t Address, 621 const MCDisassembler *Decoder); 622 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 623 uint64_t Address, 624 const MCDisassembler *Decoder); 625 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 626 const MCDisassembler *Decoder); 627 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 628 uint64_t Address, 629 const MCDisassembler *Decoder); 630 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 631 const MCDisassembler *Decoder); 632 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 633 uint64_t Address, 634 const MCDisassembler *Decoder); 635 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val, 636 uint64_t Address, 637 const MCDisassembler *Decoder); 638 static DecodeStatus DecodeVpredNOperand(MCInst &Inst, unsigned Val, 639 uint64_t Address, 640 const MCDisassembler *Decoder); 641 static DecodeStatus 642 DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 643 const MCDisassembler *Decoder); 644 static DecodeStatus 645 DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 646 const MCDisassembler *Decoder); 647 static DecodeStatus 648 DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 649 const MCDisassembler *Decoder); 650 static DecodeStatus 651 DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 652 const MCDisassembler *Decoder); 653 template <bool Writeback> 654 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, 655 uint64_t Address, 656 const MCDisassembler *Decoder); 657 template <int shift> 658 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 659 uint64_t Address, 660 const MCDisassembler *Decoder); 661 template <int shift> 662 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 663 uint64_t Address, 664 const MCDisassembler *Decoder); 665 template <int shift> 666 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 667 uint64_t Address, 668 const MCDisassembler *Decoder); 669 template <unsigned MinLog, unsigned MaxLog> 670 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 671 uint64_t Address, 672 const MCDisassembler *Decoder); 673 template <unsigned start> 674 static DecodeStatus 675 DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address, 676 const MCDisassembler *Decoder); 677 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 678 uint64_t Address, 679 const MCDisassembler *Decoder); 680 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 681 uint64_t Address, 682 const MCDisassembler *Decoder); 683 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, 684 uint64_t Address, 685 const MCDisassembler *Decoder); 686 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val, 687 uint64_t Address, 688 const MCDisassembler *Decoder); 689 template <bool scalar, OperandDecoder predicate_decoder> 690 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, 691 const MCDisassembler *Decoder); 692 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, 693 const MCDisassembler *Decoder); 694 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, 695 uint64_t Address, 696 const MCDisassembler *Decoder); 697 static DecodeStatus 698 DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address, 699 const MCDisassembler *Decoder); 700 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 701 uint64_t Address, 702 const MCDisassembler *Decoder); 703 static DecodeStatus DecodeLazyLoadStoreMul(MCInst &Inst, unsigned Insn, 704 uint64_t Address, 705 const MCDisassembler *Decoder); 706 707 #include "ARMGenDisassemblerTables.inc" 708 709 static MCDisassembler *createARMDisassembler(const Target &T, 710 const MCSubtargetInfo &STI, 711 MCContext &Ctx) { 712 return new ARMDisassembler(STI, Ctx, T.createMCInstrInfo()); 713 } 714 715 // Post-decoding checks 716 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 717 uint64_t Address, raw_ostream &CS, 718 uint32_t Insn, 719 DecodeStatus Result) { 720 switch (MI.getOpcode()) { 721 case ARM::HVC: { 722 // HVC is undefined if condition = 0xf otherwise upredictable 723 // if condition != 0xe 724 uint32_t Cond = (Insn >> 28) & 0xF; 725 if (Cond == 0xF) 726 return MCDisassembler::Fail; 727 if (Cond != 0xE) 728 return MCDisassembler::SoftFail; 729 return Result; 730 } 731 case ARM::t2ADDri: 732 case ARM::t2ADDri12: 733 case ARM::t2ADDrr: 734 case ARM::t2ADDrs: 735 case ARM::t2SUBri: 736 case ARM::t2SUBri12: 737 case ARM::t2SUBrr: 738 case ARM::t2SUBrs: 739 if (MI.getOperand(0).getReg() == ARM::SP && 740 MI.getOperand(1).getReg() != ARM::SP) 741 return MCDisassembler::SoftFail; 742 return Result; 743 default: return Result; 744 } 745 } 746 747 uint64_t ARMDisassembler::suggestBytesToSkip(ArrayRef<uint8_t> Bytes, 748 uint64_t Address) const { 749 // In Arm state, instructions are always 4 bytes wide, so there's no 750 // point in skipping any smaller number of bytes if an instruction 751 // can't be decoded. 752 if (!STI.hasFeature(ARM::ModeThumb)) 753 return 4; 754 755 // In a Thumb instruction stream, a halfword is a standalone 2-byte 756 // instruction if and only if its value is less than 0xE800. 757 // Otherwise, it's the first halfword of a 4-byte instruction. 758 // 759 // So, if we can see the upcoming halfword, we can judge on that 760 // basis, and maybe skip a whole 4-byte instruction that we don't 761 // know how to decode, without accidentally trying to interpret its 762 // second half as something else. 763 // 764 // If we don't have the instruction data available, we just have to 765 // recommend skipping the minimum sensible distance, which is 2 766 // bytes. 767 if (Bytes.size() < 2) 768 return 2; 769 770 uint16_t Insn16 = llvm::support::endian::read<uint16_t>( 771 Bytes.data(), InstructionEndianness); 772 return Insn16 < 0xE800 ? 2 : 4; 773 } 774 775 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 776 ArrayRef<uint8_t> Bytes, 777 uint64_t Address, 778 raw_ostream &CS) const { 779 if (STI.hasFeature(ARM::ModeThumb)) 780 return getThumbInstruction(MI, Size, Bytes, Address, CS); 781 return getARMInstruction(MI, Size, Bytes, Address, CS); 782 } 783 784 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size, 785 ArrayRef<uint8_t> Bytes, 786 uint64_t Address, 787 raw_ostream &CS) const { 788 CommentStream = &CS; 789 790 assert(!STI.hasFeature(ARM::ModeThumb) && 791 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 792 "mode!"); 793 794 // We want to read exactly 4 bytes of data. 795 if (Bytes.size() < 4) { 796 Size = 0; 797 return MCDisassembler::Fail; 798 } 799 800 // Encoded as a 32-bit word in the stream. 801 uint32_t Insn = llvm::support::endian::read<uint32_t>(Bytes.data(), 802 InstructionEndianness); 803 804 // Calling the auto-generated decoder function. 805 DecodeStatus Result = 806 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 807 if (Result != MCDisassembler::Fail) { 808 Size = 4; 809 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 810 } 811 812 struct DecodeTable { 813 const uint8_t *P; 814 bool DecodePred; 815 }; 816 817 const DecodeTable Tables[] = { 818 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 819 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 820 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 821 {DecoderTablev8Crypto32, false}, 822 }; 823 824 for (auto Table : Tables) { 825 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 826 if (Result != MCDisassembler::Fail) { 827 Size = 4; 828 // Add a fake predicate operand, because we share these instruction 829 // definitions with Thumb2 where these instructions are predicable. 830 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 831 return MCDisassembler::Fail; 832 return Result; 833 } 834 } 835 836 Result = 837 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 838 if (Result != MCDisassembler::Fail) { 839 Size = 4; 840 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 841 } 842 843 Size = 4; 844 return MCDisassembler::Fail; 845 } 846 847 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 848 /// immediate Value in the MCInst. The immediate Value has had any PC 849 /// adjustment made by the caller. If the instruction is a branch instruction 850 /// then isBranch is true, else false. If the getOpInfo() function was set as 851 /// part of the setupForSymbolicDisassembly() call then that function is called 852 /// to get any symbolic information at the Address for this instruction. If 853 /// that returns non-zero then the symbolic information it returns is used to 854 /// create an MCExpr and that is added as an operand to the MCInst. If 855 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 856 /// Value is done and if a symbol is found an MCExpr is created with that, else 857 /// an MCExpr with Value is created. This function returns true if it adds an 858 /// operand to the MCInst and false otherwise. 859 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 860 bool isBranch, uint64_t InstSize, 861 MCInst &MI, 862 const MCDisassembler *Decoder) { 863 // FIXME: Does it make sense for value to be negative? 864 return Decoder->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, 865 isBranch, /*Offset=*/0, /*OpSize=*/0, 866 InstSize); 867 } 868 869 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 870 /// referenced by a load instruction with the base register that is the Pc. 871 /// These can often be values in a literal pool near the Address of the 872 /// instruction. The Address of the instruction and its immediate Value are 873 /// used as a possible literal pool entry. The SymbolLookUp call back will 874 /// return the name of a symbol referenced by the literal pool's entry if 875 /// the referenced address is that of a symbol. Or it will return a pointer to 876 /// a literal 'C' string if the referenced address of the literal pool's entry 877 /// is an address into a section with 'C' string literals. 878 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 879 const MCDisassembler *Decoder) { 880 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 881 Dis->tryAddingPcLoadReferenceComment(Value, Address); 882 } 883 884 // Thumb1 instructions don't have explicit S bits. Rather, they 885 // implicitly set CPSR. Since it's not represented in the encoding, the 886 // auto-generated decoder won't inject the CPSR operand. We need to fix 887 // that as a post-pass. 888 void ARMDisassembler::AddThumb1SBit(MCInst &MI, bool InITBlock) const { 889 const MCInstrDesc &MCID = MCII->get(MI.getOpcode()); 890 MCInst::iterator I = MI.begin(); 891 for (unsigned i = 0; i < MCID.NumOperands; ++i, ++I) { 892 if (I == MI.end()) break; 893 if (MCID.operands()[i].isOptionalDef() && 894 MCID.operands()[i].RegClass == ARM::CCRRegClassID) { 895 if (i > 0 && MCID.operands()[i - 1].isPredicate()) 896 continue; 897 MI.insert(I, 898 MCOperand::createReg(InITBlock ? ARM::NoRegister : ARM::CPSR)); 899 return; 900 } 901 } 902 903 MI.insert(I, MCOperand::createReg(InITBlock ? ARM::NoRegister : ARM::CPSR)); 904 } 905 906 bool ARMDisassembler::isVectorPredicable(const MCInst &MI) const { 907 const MCInstrDesc &MCID = MCII->get(MI.getOpcode()); 908 for (unsigned i = 0; i < MCID.NumOperands; ++i) { 909 if (ARM::isVpred(MCID.operands()[i].OperandType)) 910 return true; 911 } 912 return false; 913 } 914 915 // Most Thumb instructions don't have explicit predicates in the 916 // encoding, but rather get their predicates from IT context. We need 917 // to fix up the predicate operands using this context information as a 918 // post-pass. 919 MCDisassembler::DecodeStatus 920 ARMDisassembler::AddThumbPredicate(MCInst &MI) const { 921 MCDisassembler::DecodeStatus S = Success; 922 923 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 924 925 // A few instructions actually have predicates encoded in them. Don't 926 // try to overwrite it if we're seeing one of those. 927 switch (MI.getOpcode()) { 928 case ARM::tBcc: 929 case ARM::t2Bcc: 930 case ARM::tCBZ: 931 case ARM::tCBNZ: 932 case ARM::tCPS: 933 case ARM::t2CPS3p: 934 case ARM::t2CPS2p: 935 case ARM::t2CPS1p: 936 case ARM::t2CSEL: 937 case ARM::t2CSINC: 938 case ARM::t2CSINV: 939 case ARM::t2CSNEG: 940 case ARM::tMOVSr: 941 case ARM::tSETEND: 942 // Some instructions (mostly conditional branches) are not 943 // allowed in IT blocks. 944 if (ITBlock.instrInITBlock()) 945 S = SoftFail; 946 else 947 return Success; 948 break; 949 case ARM::t2HINT: 950 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 951 S = SoftFail; 952 break; 953 case ARM::tB: 954 case ARM::t2B: 955 case ARM::t2TBB: 956 case ARM::t2TBH: 957 // Some instructions (mostly unconditional branches) can 958 // only appears at the end of, or outside of, an IT. 959 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 960 S = SoftFail; 961 break; 962 default: 963 break; 964 } 965 966 // Warn on non-VPT predicable instruction in a VPT block and a VPT 967 // predicable instruction in an IT block 968 if ((!isVectorPredicable(MI) && VPTBlock.instrInVPTBlock()) || 969 (isVectorPredicable(MI) && ITBlock.instrInITBlock())) 970 S = SoftFail; 971 972 // If we're in an IT/VPT block, base the predicate on that. Otherwise, 973 // assume a predicate of AL. 974 unsigned CC = ARMCC::AL; 975 unsigned VCC = ARMVCC::None; 976 if (ITBlock.instrInITBlock()) { 977 CC = ITBlock.getITCC(); 978 ITBlock.advanceITState(); 979 } else if (VPTBlock.instrInVPTBlock()) { 980 VCC = VPTBlock.getVPTPred(); 981 VPTBlock.advanceVPTState(); 982 } 983 984 const MCInstrDesc &MCID = MCII->get(MI.getOpcode()); 985 986 MCInst::iterator CCI = MI.begin(); 987 for (unsigned i = 0; i < MCID.NumOperands; ++i, ++CCI) { 988 if (MCID.operands()[i].isPredicate() || CCI == MI.end()) 989 break; 990 } 991 992 if (MCID.isPredicable()) { 993 CCI = MI.insert(CCI, MCOperand::createImm(CC)); 994 ++CCI; 995 if (CC == ARMCC::AL) 996 MI.insert(CCI, MCOperand::createReg(ARM::NoRegister)); 997 else 998 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); 999 } else if (CC != ARMCC::AL) { 1000 Check(S, SoftFail); 1001 } 1002 1003 MCInst::iterator VCCI = MI.begin(); 1004 unsigned VCCPos; 1005 for (VCCPos = 0; VCCPos < MCID.NumOperands; ++VCCPos, ++VCCI) { 1006 if (ARM::isVpred(MCID.operands()[VCCPos].OperandType) || VCCI == MI.end()) 1007 break; 1008 } 1009 1010 if (isVectorPredicable(MI)) { 1011 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC)); 1012 ++VCCI; 1013 if (VCC == ARMVCC::None) 1014 VCCI = MI.insert(VCCI, MCOperand::createReg(0)); 1015 else 1016 VCCI = MI.insert(VCCI, MCOperand::createReg(ARM::P0)); 1017 ++VCCI; 1018 VCCI = MI.insert(VCCI, MCOperand::createReg(0)); 1019 ++VCCI; 1020 if (MCID.operands()[VCCPos].OperandType == ARM::OPERAND_VPRED_R) { 1021 int TiedOp = MCID.getOperandConstraint(VCCPos + 3, MCOI::TIED_TO); 1022 assert(TiedOp >= 0 && 1023 "Inactive register in vpred_r is not tied to an output!"); 1024 // Copy the operand to ensure it's not invalidated when MI grows. 1025 MI.insert(VCCI, MCOperand(MI.getOperand(TiedOp))); 1026 } 1027 } else if (VCC != ARMVCC::None) { 1028 Check(S, SoftFail); 1029 } 1030 1031 return S; 1032 } 1033 1034 // Thumb VFP instructions are a special case. Because we share their 1035 // encodings between ARM and Thumb modes, and they are predicable in ARM 1036 // mode, the auto-generated decoder will give them an (incorrect) 1037 // predicate operand. We need to rewrite these operands based on the IT 1038 // context as a post-pass. 1039 void ARMDisassembler::UpdateThumbVFPPredicate( 1040 DecodeStatus &S, MCInst &MI) const { 1041 unsigned CC; 1042 CC = ITBlock.getITCC(); 1043 if (CC == 0xF) 1044 CC = ARMCC::AL; 1045 if (ITBlock.instrInITBlock()) 1046 ITBlock.advanceITState(); 1047 else if (VPTBlock.instrInVPTBlock()) { 1048 CC = VPTBlock.getVPTPred(); 1049 VPTBlock.advanceVPTState(); 1050 } 1051 1052 const MCInstrDesc &MCID = MCII->get(MI.getOpcode()); 1053 ArrayRef<MCOperandInfo> OpInfo = MCID.operands(); 1054 MCInst::iterator I = MI.begin(); 1055 unsigned short NumOps = MCID.NumOperands; 1056 for (unsigned i = 0; i < NumOps; ++i, ++I) { 1057 if (OpInfo[i].isPredicate() ) { 1058 if (CC != ARMCC::AL && !MCID.isPredicable()) 1059 Check(S, SoftFail); 1060 I->setImm(CC); 1061 ++I; 1062 if (CC == ARMCC::AL) 1063 I->setReg(ARM::NoRegister); 1064 else 1065 I->setReg(ARM::CPSR); 1066 return; 1067 } 1068 } 1069 } 1070 1071 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size, 1072 ArrayRef<uint8_t> Bytes, 1073 uint64_t Address, 1074 raw_ostream &CS) const { 1075 CommentStream = &CS; 1076 1077 assert(STI.hasFeature(ARM::ModeThumb) && 1078 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 1079 1080 // We want to read exactly 2 bytes of data. 1081 if (Bytes.size() < 2) { 1082 Size = 0; 1083 return MCDisassembler::Fail; 1084 } 1085 1086 uint16_t Insn16 = llvm::support::endian::read<uint16_t>( 1087 Bytes.data(), InstructionEndianness); 1088 DecodeStatus Result = 1089 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 1090 if (Result != MCDisassembler::Fail) { 1091 Size = 2; 1092 Check(Result, AddThumbPredicate(MI)); 1093 return Result; 1094 } 1095 1096 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 1097 STI); 1098 if (Result) { 1099 Size = 2; 1100 bool InITBlock = ITBlock.instrInITBlock(); 1101 Check(Result, AddThumbPredicate(MI)); 1102 AddThumb1SBit(MI, InITBlock); 1103 return Result; 1104 } 1105 1106 Result = 1107 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 1108 if (Result != MCDisassembler::Fail) { 1109 Size = 2; 1110 1111 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 1112 // the Thumb predicate. 1113 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 1114 Result = MCDisassembler::SoftFail; 1115 1116 Check(Result, AddThumbPredicate(MI)); 1117 1118 // If we find an IT instruction, we need to parse its condition 1119 // code and mask operands so that we can apply them correctly 1120 // to the subsequent instructions. 1121 if (MI.getOpcode() == ARM::t2IT) { 1122 unsigned Firstcond = MI.getOperand(0).getImm(); 1123 unsigned Mask = MI.getOperand(1).getImm(); 1124 ITBlock.setITState(Firstcond, Mask); 1125 1126 // An IT instruction that would give a 'NV' predicate is unpredictable. 1127 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 1128 CS << "unpredictable IT predicate sequence"; 1129 } 1130 1131 return Result; 1132 } 1133 1134 // We want to read exactly 4 bytes of data. 1135 if (Bytes.size() < 4) { 1136 Size = 0; 1137 return MCDisassembler::Fail; 1138 } 1139 1140 uint32_t Insn32 = 1141 (uint32_t(Insn16) << 16) | llvm::support::endian::read<uint16_t>( 1142 Bytes.data() + 2, InstructionEndianness); 1143 1144 Result = 1145 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI); 1146 if (Result != MCDisassembler::Fail) { 1147 Size = 4; 1148 1149 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add 1150 // the VPT predicate. 1151 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) 1152 Result = MCDisassembler::SoftFail; 1153 1154 Check(Result, AddThumbPredicate(MI)); 1155 1156 if (isVPTOpcode(MI.getOpcode())) { 1157 unsigned Mask = MI.getOperand(0).getImm(); 1158 VPTBlock.setVPTState(Mask); 1159 } 1160 1161 return Result; 1162 } 1163 1164 Result = 1165 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 1166 if (Result != MCDisassembler::Fail) { 1167 Size = 4; 1168 bool InITBlock = ITBlock.instrInITBlock(); 1169 Check(Result, AddThumbPredicate(MI)); 1170 AddThumb1SBit(MI, InITBlock); 1171 return Result; 1172 } 1173 1174 Result = 1175 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 1176 if (Result != MCDisassembler::Fail) { 1177 Size = 4; 1178 Check(Result, AddThumbPredicate(MI)); 1179 return checkDecodedInstruction(MI, Size, Address, CS, Insn32, Result); 1180 } 1181 1182 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1183 Result = 1184 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 1185 if (Result != MCDisassembler::Fail) { 1186 Size = 4; 1187 UpdateThumbVFPPredicate(Result, MI); 1188 return Result; 1189 } 1190 } 1191 1192 Result = 1193 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 1194 if (Result != MCDisassembler::Fail) { 1195 Size = 4; 1196 return Result; 1197 } 1198 1199 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1200 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 1201 STI); 1202 if (Result != MCDisassembler::Fail) { 1203 Size = 4; 1204 Check(Result, AddThumbPredicate(MI)); 1205 return Result; 1206 } 1207 } 1208 1209 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 1210 uint32_t NEONLdStInsn = Insn32; 1211 NEONLdStInsn &= 0xF0FFFFFF; 1212 NEONLdStInsn |= 0x04000000; 1213 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 1214 Address, this, STI); 1215 if (Result != MCDisassembler::Fail) { 1216 Size = 4; 1217 Check(Result, AddThumbPredicate(MI)); 1218 return Result; 1219 } 1220 } 1221 1222 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 1223 uint32_t NEONDataInsn = Insn32; 1224 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 1225 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1226 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 1227 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 1228 Address, this, STI); 1229 if (Result != MCDisassembler::Fail) { 1230 Size = 4; 1231 Check(Result, AddThumbPredicate(MI)); 1232 return Result; 1233 } 1234 1235 uint32_t NEONCryptoInsn = Insn32; 1236 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 1237 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1238 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 1239 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 1240 Address, this, STI); 1241 if (Result != MCDisassembler::Fail) { 1242 Size = 4; 1243 return Result; 1244 } 1245 1246 uint32_t NEONv8Insn = Insn32; 1247 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 1248 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 1249 this, STI); 1250 if (Result != MCDisassembler::Fail) { 1251 Size = 4; 1252 return Result; 1253 } 1254 } 1255 1256 uint32_t Coproc = fieldFromInstruction(Insn32, 8, 4); 1257 const uint8_t *DecoderTable = ARM::isCDECoproc(Coproc, STI) 1258 ? DecoderTableThumb2CDE32 1259 : DecoderTableThumb2CoProc32; 1260 Result = 1261 decodeInstruction(DecoderTable, MI, Insn32, Address, this, STI); 1262 if (Result != MCDisassembler::Fail) { 1263 Size = 4; 1264 Check(Result, AddThumbPredicate(MI)); 1265 return Result; 1266 } 1267 1268 Size = 0; 1269 return MCDisassembler::Fail; 1270 } 1271 1272 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMDisassembler() { 1273 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 1274 createARMDisassembler); 1275 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 1276 createARMDisassembler); 1277 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 1278 createARMDisassembler); 1279 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 1280 createARMDisassembler); 1281 } 1282 1283 static const uint16_t GPRDecoderTable[] = { 1284 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1285 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1286 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1287 ARM::R12, ARM::SP, ARM::LR, ARM::PC 1288 }; 1289 1290 static const uint16_t CLRMGPRDecoderTable[] = { 1291 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1292 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1293 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1294 ARM::R12, 0, ARM::LR, ARM::APSR 1295 }; 1296 1297 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1298 uint64_t Address, 1299 const MCDisassembler *Decoder) { 1300 if (RegNo > 15) 1301 return MCDisassembler::Fail; 1302 1303 unsigned Register = GPRDecoderTable[RegNo]; 1304 Inst.addOperand(MCOperand::createReg(Register)); 1305 return MCDisassembler::Success; 1306 } 1307 1308 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1309 uint64_t Address, 1310 const MCDisassembler *Decoder) { 1311 if (RegNo > 15) 1312 return MCDisassembler::Fail; 1313 1314 unsigned Register = CLRMGPRDecoderTable[RegNo]; 1315 if (Register == 0) 1316 return MCDisassembler::Fail; 1317 1318 Inst.addOperand(MCOperand::createReg(Register)); 1319 return MCDisassembler::Success; 1320 } 1321 1322 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 1323 uint64_t Address, 1324 const MCDisassembler *Decoder) { 1325 DecodeStatus S = MCDisassembler::Success; 1326 1327 if (RegNo == 15) 1328 S = MCDisassembler::SoftFail; 1329 1330 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1331 1332 return S; 1333 } 1334 1335 static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo, 1336 uint64_t Address, 1337 const MCDisassembler *Decoder) { 1338 DecodeStatus S = MCDisassembler::Success; 1339 1340 if (RegNo == 13) 1341 S = MCDisassembler::SoftFail; 1342 1343 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1344 1345 return S; 1346 } 1347 1348 static DecodeStatus 1349 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1350 const MCDisassembler *Decoder) { 1351 DecodeStatus S = MCDisassembler::Success; 1352 1353 if (RegNo == 15) 1354 { 1355 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 1356 return MCDisassembler::Success; 1357 } 1358 1359 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1360 return S; 1361 } 1362 1363 static DecodeStatus 1364 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1365 const MCDisassembler *Decoder) { 1366 DecodeStatus S = MCDisassembler::Success; 1367 1368 if (RegNo == 15) 1369 { 1370 Inst.addOperand(MCOperand::createReg(ARM::ZR)); 1371 return MCDisassembler::Success; 1372 } 1373 1374 if (RegNo == 13) 1375 Check(S, MCDisassembler::SoftFail); 1376 1377 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1378 return S; 1379 } 1380 1381 static DecodeStatus 1382 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1383 const MCDisassembler *Decoder) { 1384 DecodeStatus S = MCDisassembler::Success; 1385 if (RegNo == 13) 1386 return MCDisassembler::Fail; 1387 Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder)); 1388 return S; 1389 } 1390 1391 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1392 uint64_t Address, 1393 const MCDisassembler *Decoder) { 1394 if (RegNo > 7) 1395 return MCDisassembler::Fail; 1396 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 1397 } 1398 1399 static const uint16_t GPRPairDecoderTable[] = { 1400 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 1401 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 1402 }; 1403 1404 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 1405 uint64_t Address, 1406 const MCDisassembler *Decoder) { 1407 DecodeStatus S = MCDisassembler::Success; 1408 1409 // According to the Arm ARM RegNo = 14 is undefined, but we return fail 1410 // rather than SoftFail as there is no GPRPair table entry for index 7. 1411 if (RegNo > 13) 1412 return MCDisassembler::Fail; 1413 1414 if (RegNo & 1) 1415 S = MCDisassembler::SoftFail; 1416 1417 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1418 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1419 return S; 1420 } 1421 1422 static DecodeStatus 1423 DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1424 const MCDisassembler *Decoder) { 1425 if (RegNo > 13) 1426 return MCDisassembler::Fail; 1427 1428 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1429 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1430 1431 if ((RegNo & 1) || RegNo > 10) 1432 return MCDisassembler::SoftFail; 1433 return MCDisassembler::Success; 1434 } 1435 1436 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 1437 uint64_t Address, 1438 const MCDisassembler *Decoder) { 1439 if (RegNo != 13) 1440 return MCDisassembler::Fail; 1441 1442 unsigned Register = GPRDecoderTable[RegNo]; 1443 Inst.addOperand(MCOperand::createReg(Register)); 1444 return MCDisassembler::Success; 1445 } 1446 1447 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1448 uint64_t Address, 1449 const MCDisassembler *Decoder) { 1450 unsigned Register = 0; 1451 switch (RegNo) { 1452 case 0: 1453 Register = ARM::R0; 1454 break; 1455 case 1: 1456 Register = ARM::R1; 1457 break; 1458 case 2: 1459 Register = ARM::R2; 1460 break; 1461 case 3: 1462 Register = ARM::R3; 1463 break; 1464 case 9: 1465 Register = ARM::R9; 1466 break; 1467 case 12: 1468 Register = ARM::R12; 1469 break; 1470 default: 1471 return MCDisassembler::Fail; 1472 } 1473 1474 Inst.addOperand(MCOperand::createReg(Register)); 1475 return MCDisassembler::Success; 1476 } 1477 1478 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1479 uint64_t Address, 1480 const MCDisassembler *Decoder) { 1481 DecodeStatus S = MCDisassembler::Success; 1482 1483 const FeatureBitset &featureBits = 1484 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1485 1486 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 1487 S = MCDisassembler::SoftFail; 1488 1489 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1490 return S; 1491 } 1492 1493 static const uint16_t SPRDecoderTable[] = { 1494 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1495 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1496 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1497 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 1498 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 1499 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 1500 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1501 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1502 }; 1503 1504 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1505 uint64_t Address, 1506 const MCDisassembler *Decoder) { 1507 if (RegNo > 31) 1508 return MCDisassembler::Fail; 1509 1510 unsigned Register = SPRDecoderTable[RegNo]; 1511 Inst.addOperand(MCOperand::createReg(Register)); 1512 return MCDisassembler::Success; 1513 } 1514 1515 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1516 uint64_t Address, 1517 const MCDisassembler *Decoder) { 1518 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1519 } 1520 1521 static const uint16_t DPRDecoderTable[] = { 1522 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1523 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1524 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1525 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1526 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1527 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1528 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1529 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1530 }; 1531 1532 // Does this instruction/subtarget permit use of registers d16-d31? 1533 static bool PermitsD32(const MCInst &Inst, const MCDisassembler *Decoder) { 1534 if (Inst.getOpcode() == ARM::VSCCLRMD || Inst.getOpcode() == ARM::VSCCLRMS) 1535 return true; 1536 const FeatureBitset &featureBits = 1537 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1538 return featureBits[ARM::FeatureD32]; 1539 } 1540 1541 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1542 uint64_t Address, 1543 const MCDisassembler *Decoder) { 1544 if (RegNo > (PermitsD32(Inst, Decoder) ? 31u : 15u)) 1545 return MCDisassembler::Fail; 1546 1547 unsigned Register = DPRDecoderTable[RegNo]; 1548 Inst.addOperand(MCOperand::createReg(Register)); 1549 return MCDisassembler::Success; 1550 } 1551 1552 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1553 uint64_t Address, 1554 const MCDisassembler *Decoder) { 1555 if (RegNo > 7) 1556 return MCDisassembler::Fail; 1557 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1558 } 1559 1560 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1561 uint64_t Address, 1562 const MCDisassembler *Decoder) { 1563 if (RegNo > 15) 1564 return MCDisassembler::Fail; 1565 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1566 } 1567 1568 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1569 uint64_t Address, 1570 const MCDisassembler *Decoder) { 1571 if (RegNo > 15) 1572 return MCDisassembler::Fail; 1573 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1574 } 1575 1576 static const uint16_t QPRDecoderTable[] = { 1577 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1578 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1579 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1580 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1581 }; 1582 1583 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1584 uint64_t Address, 1585 const MCDisassembler *Decoder) { 1586 if (RegNo > 31 || (RegNo & 1) != 0) 1587 return MCDisassembler::Fail; 1588 RegNo >>= 1; 1589 1590 unsigned Register = QPRDecoderTable[RegNo]; 1591 Inst.addOperand(MCOperand::createReg(Register)); 1592 return MCDisassembler::Success; 1593 } 1594 1595 static const uint16_t DPairDecoderTable[] = { 1596 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1597 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1598 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1599 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1600 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1601 ARM::Q15 1602 }; 1603 1604 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1605 uint64_t Address, 1606 const MCDisassembler *Decoder) { 1607 if (RegNo > 30) 1608 return MCDisassembler::Fail; 1609 1610 unsigned Register = DPairDecoderTable[RegNo]; 1611 Inst.addOperand(MCOperand::createReg(Register)); 1612 return MCDisassembler::Success; 1613 } 1614 1615 static const uint16_t DPairSpacedDecoderTable[] = { 1616 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1617 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1618 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1619 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1620 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1621 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1622 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1623 ARM::D28_D30, ARM::D29_D31 1624 }; 1625 1626 static DecodeStatus 1627 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1628 const MCDisassembler *Decoder) { 1629 if (RegNo > 29) 1630 return MCDisassembler::Fail; 1631 1632 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1633 Inst.addOperand(MCOperand::createReg(Register)); 1634 return MCDisassembler::Success; 1635 } 1636 1637 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1638 uint64_t Address, 1639 const MCDisassembler *Decoder) { 1640 DecodeStatus S = MCDisassembler::Success; 1641 if (Val == 0xF) return MCDisassembler::Fail; 1642 // AL predicate is not allowed on Thumb1 branches. 1643 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1644 return MCDisassembler::Fail; 1645 const MCInstrInfo *MCII = 1646 static_cast<const ARMDisassembler *>(Decoder)->MCII.get(); 1647 if (Val != ARMCC::AL && !MCII->get(Inst.getOpcode()).isPredicable()) 1648 Check(S, MCDisassembler::SoftFail); 1649 Inst.addOperand(MCOperand::createImm(Val)); 1650 if (Val == ARMCC::AL) { 1651 Inst.addOperand(MCOperand::createReg(ARM::NoRegister)); 1652 } else 1653 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1654 return S; 1655 } 1656 1657 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1658 uint64_t Address, 1659 const MCDisassembler *Decoder) { 1660 if (Val) 1661 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1662 else 1663 Inst.addOperand(MCOperand::createReg(ARM::NoRegister)); 1664 return MCDisassembler::Success; 1665 } 1666 1667 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1668 uint64_t Address, 1669 const MCDisassembler *Decoder) { 1670 DecodeStatus S = MCDisassembler::Success; 1671 1672 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1673 unsigned type = fieldFromInstruction(Val, 5, 2); 1674 unsigned imm = fieldFromInstruction(Val, 7, 5); 1675 1676 // Register-immediate 1677 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1678 return MCDisassembler::Fail; 1679 1680 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1681 switch (type) { 1682 case 0: 1683 Shift = ARM_AM::lsl; 1684 break; 1685 case 1: 1686 Shift = ARM_AM::lsr; 1687 break; 1688 case 2: 1689 Shift = ARM_AM::asr; 1690 break; 1691 case 3: 1692 Shift = ARM_AM::ror; 1693 break; 1694 } 1695 1696 if (Shift == ARM_AM::ror && imm == 0) 1697 Shift = ARM_AM::rrx; 1698 1699 unsigned Op = Shift | (imm << 3); 1700 Inst.addOperand(MCOperand::createImm(Op)); 1701 1702 return S; 1703 } 1704 1705 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1706 uint64_t Address, 1707 const MCDisassembler *Decoder) { 1708 DecodeStatus S = MCDisassembler::Success; 1709 1710 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1711 unsigned type = fieldFromInstruction(Val, 5, 2); 1712 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1713 1714 // Register-register 1715 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1716 return MCDisassembler::Fail; 1717 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1718 return MCDisassembler::Fail; 1719 1720 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1721 switch (type) { 1722 case 0: 1723 Shift = ARM_AM::lsl; 1724 break; 1725 case 1: 1726 Shift = ARM_AM::lsr; 1727 break; 1728 case 2: 1729 Shift = ARM_AM::asr; 1730 break; 1731 case 3: 1732 Shift = ARM_AM::ror; 1733 break; 1734 } 1735 1736 Inst.addOperand(MCOperand::createImm(Shift)); 1737 1738 return S; 1739 } 1740 1741 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1742 uint64_t Address, 1743 const MCDisassembler *Decoder) { 1744 DecodeStatus S = MCDisassembler::Success; 1745 1746 bool NeedDisjointWriteback = false; 1747 MCRegister WritebackReg; 1748 bool CLRM = false; 1749 switch (Inst.getOpcode()) { 1750 default: 1751 break; 1752 case ARM::LDMIA_UPD: 1753 case ARM::LDMDB_UPD: 1754 case ARM::LDMIB_UPD: 1755 case ARM::LDMDA_UPD: 1756 case ARM::t2LDMIA_UPD: 1757 case ARM::t2LDMDB_UPD: 1758 case ARM::t2STMIA_UPD: 1759 case ARM::t2STMDB_UPD: 1760 NeedDisjointWriteback = true; 1761 WritebackReg = Inst.getOperand(0).getReg(); 1762 break; 1763 case ARM::t2CLRM: 1764 CLRM = true; 1765 break; 1766 } 1767 1768 // Empty register lists are not allowed. 1769 if (Val == 0) return MCDisassembler::Fail; 1770 for (unsigned i = 0; i < 16; ++i) { 1771 if (Val & (1 << i)) { 1772 if (CLRM) { 1773 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { 1774 return MCDisassembler::Fail; 1775 } 1776 } else { 1777 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1778 return MCDisassembler::Fail; 1779 // Writeback not allowed if Rn is in the target list. 1780 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1781 Check(S, MCDisassembler::SoftFail); 1782 } 1783 } 1784 } 1785 1786 return S; 1787 } 1788 1789 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1790 uint64_t Address, 1791 const MCDisassembler *Decoder) { 1792 DecodeStatus S = MCDisassembler::Success; 1793 1794 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1795 unsigned regs = fieldFromInstruction(Val, 0, 8); 1796 1797 // In case of unpredictable encoding, tweak the operands. 1798 if (regs == 0 || (Vd + regs) > 32) { 1799 regs = Vd + regs > 32 ? 32 - Vd : regs; 1800 regs = std::max( 1u, regs); 1801 S = MCDisassembler::SoftFail; 1802 } 1803 1804 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1805 return MCDisassembler::Fail; 1806 for (unsigned i = 0; i < (regs - 1); ++i) { 1807 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1808 return MCDisassembler::Fail; 1809 } 1810 1811 return S; 1812 } 1813 1814 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1815 uint64_t Address, 1816 const MCDisassembler *Decoder) { 1817 DecodeStatus S = MCDisassembler::Success; 1818 1819 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1820 unsigned regs = fieldFromInstruction(Val, 1, 7); 1821 1822 // In case of unpredictable encoding, tweak the operands. 1823 unsigned MaxReg = PermitsD32(Inst, Decoder) ? 32 : 16; 1824 if (regs == 0 || (Vd + regs) > MaxReg) { 1825 regs = Vd + regs > MaxReg ? MaxReg - Vd : regs; 1826 regs = std::max( 1u, regs); 1827 regs = std::min(MaxReg, regs); 1828 S = MCDisassembler::SoftFail; 1829 } 1830 1831 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1832 return MCDisassembler::Fail; 1833 for (unsigned i = 0; i < (regs - 1); ++i) { 1834 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1835 return MCDisassembler::Fail; 1836 } 1837 1838 return S; 1839 } 1840 1841 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1842 uint64_t Address, 1843 const MCDisassembler *Decoder) { 1844 // This operand encodes a mask of contiguous zeros between a specified MSB 1845 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1846 // the mask of all bits LSB-and-lower, and then xor them to create 1847 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1848 // create the final mask. 1849 unsigned msb = fieldFromInstruction(Val, 5, 5); 1850 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1851 1852 DecodeStatus S = MCDisassembler::Success; 1853 if (lsb > msb) { 1854 Check(S, MCDisassembler::SoftFail); 1855 // The check above will cause the warning for the "potentially undefined 1856 // instruction encoding" but we can't build a bad MCOperand value here 1857 // with a lsb > msb or else printing the MCInst will cause a crash. 1858 lsb = msb; 1859 } 1860 1861 uint32_t msb_mask = 0xFFFFFFFF; 1862 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1863 uint32_t lsb_mask = (1U << lsb) - 1; 1864 1865 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1866 return S; 1867 } 1868 1869 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1870 uint64_t Address, 1871 const MCDisassembler *Decoder) { 1872 DecodeStatus S = MCDisassembler::Success; 1873 1874 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1875 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1876 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1877 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1878 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1879 unsigned U = fieldFromInstruction(Insn, 23, 1); 1880 const FeatureBitset &featureBits = 1881 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1882 1883 switch (Inst.getOpcode()) { 1884 case ARM::LDC_OFFSET: 1885 case ARM::LDC_PRE: 1886 case ARM::LDC_POST: 1887 case ARM::LDC_OPTION: 1888 case ARM::LDCL_OFFSET: 1889 case ARM::LDCL_PRE: 1890 case ARM::LDCL_POST: 1891 case ARM::LDCL_OPTION: 1892 case ARM::STC_OFFSET: 1893 case ARM::STC_PRE: 1894 case ARM::STC_POST: 1895 case ARM::STC_OPTION: 1896 case ARM::STCL_OFFSET: 1897 case ARM::STCL_PRE: 1898 case ARM::STCL_POST: 1899 case ARM::STCL_OPTION: 1900 case ARM::t2LDC_OFFSET: 1901 case ARM::t2LDC_PRE: 1902 case ARM::t2LDC_POST: 1903 case ARM::t2LDC_OPTION: 1904 case ARM::t2LDCL_OFFSET: 1905 case ARM::t2LDCL_PRE: 1906 case ARM::t2LDCL_POST: 1907 case ARM::t2LDCL_OPTION: 1908 case ARM::t2STC_OFFSET: 1909 case ARM::t2STC_PRE: 1910 case ARM::t2STC_POST: 1911 case ARM::t2STC_OPTION: 1912 case ARM::t2STCL_OFFSET: 1913 case ARM::t2STCL_PRE: 1914 case ARM::t2STCL_POST: 1915 case ARM::t2STCL_OPTION: 1916 case ARM::t2LDC2_OFFSET: 1917 case ARM::t2LDC2L_OFFSET: 1918 case ARM::t2LDC2_PRE: 1919 case ARM::t2LDC2L_PRE: 1920 case ARM::t2STC2_OFFSET: 1921 case ARM::t2STC2L_OFFSET: 1922 case ARM::t2STC2_PRE: 1923 case ARM::t2STC2L_PRE: 1924 case ARM::LDC2_OFFSET: 1925 case ARM::LDC2L_OFFSET: 1926 case ARM::LDC2_PRE: 1927 case ARM::LDC2L_PRE: 1928 case ARM::STC2_OFFSET: 1929 case ARM::STC2L_OFFSET: 1930 case ARM::STC2_PRE: 1931 case ARM::STC2L_PRE: 1932 case ARM::t2LDC2_OPTION: 1933 case ARM::t2STC2_OPTION: 1934 case ARM::t2LDC2_POST: 1935 case ARM::t2LDC2L_POST: 1936 case ARM::t2STC2_POST: 1937 case ARM::t2STC2L_POST: 1938 case ARM::LDC2_POST: 1939 case ARM::LDC2L_POST: 1940 case ARM::STC2_POST: 1941 case ARM::STC2L_POST: 1942 if (coproc == 0xA || coproc == 0xB || 1943 (featureBits[ARM::HasV8_1MMainlineOps] && 1944 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB || 1945 coproc == 0xE || coproc == 0xF))) 1946 return MCDisassembler::Fail; 1947 break; 1948 default: 1949 break; 1950 } 1951 1952 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1953 return MCDisassembler::Fail; 1954 1955 Inst.addOperand(MCOperand::createImm(coproc)); 1956 Inst.addOperand(MCOperand::createImm(CRd)); 1957 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1958 return MCDisassembler::Fail; 1959 1960 switch (Inst.getOpcode()) { 1961 case ARM::t2LDC2_OFFSET: 1962 case ARM::t2LDC2L_OFFSET: 1963 case ARM::t2LDC2_PRE: 1964 case ARM::t2LDC2L_PRE: 1965 case ARM::t2STC2_OFFSET: 1966 case ARM::t2STC2L_OFFSET: 1967 case ARM::t2STC2_PRE: 1968 case ARM::t2STC2L_PRE: 1969 case ARM::LDC2_OFFSET: 1970 case ARM::LDC2L_OFFSET: 1971 case ARM::LDC2_PRE: 1972 case ARM::LDC2L_PRE: 1973 case ARM::STC2_OFFSET: 1974 case ARM::STC2L_OFFSET: 1975 case ARM::STC2_PRE: 1976 case ARM::STC2L_PRE: 1977 case ARM::t2LDC_OFFSET: 1978 case ARM::t2LDCL_OFFSET: 1979 case ARM::t2LDC_PRE: 1980 case ARM::t2LDCL_PRE: 1981 case ARM::t2STC_OFFSET: 1982 case ARM::t2STCL_OFFSET: 1983 case ARM::t2STC_PRE: 1984 case ARM::t2STCL_PRE: 1985 case ARM::LDC_OFFSET: 1986 case ARM::LDCL_OFFSET: 1987 case ARM::LDC_PRE: 1988 case ARM::LDCL_PRE: 1989 case ARM::STC_OFFSET: 1990 case ARM::STCL_OFFSET: 1991 case ARM::STC_PRE: 1992 case ARM::STCL_PRE: 1993 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1994 Inst.addOperand(MCOperand::createImm(imm)); 1995 break; 1996 case ARM::t2LDC2_POST: 1997 case ARM::t2LDC2L_POST: 1998 case ARM::t2STC2_POST: 1999 case ARM::t2STC2L_POST: 2000 case ARM::LDC2_POST: 2001 case ARM::LDC2L_POST: 2002 case ARM::STC2_POST: 2003 case ARM::STC2L_POST: 2004 case ARM::t2LDC_POST: 2005 case ARM::t2LDCL_POST: 2006 case ARM::t2STC_POST: 2007 case ARM::t2STCL_POST: 2008 case ARM::LDC_POST: 2009 case ARM::LDCL_POST: 2010 case ARM::STC_POST: 2011 case ARM::STCL_POST: 2012 imm |= U << 8; 2013 [[fallthrough]]; 2014 default: 2015 // The 'option' variant doesn't encode 'U' in the immediate since 2016 // the immediate is unsigned [0,255]. 2017 Inst.addOperand(MCOperand::createImm(imm)); 2018 break; 2019 } 2020 2021 switch (Inst.getOpcode()) { 2022 case ARM::LDC_OFFSET: 2023 case ARM::LDC_PRE: 2024 case ARM::LDC_POST: 2025 case ARM::LDC_OPTION: 2026 case ARM::LDCL_OFFSET: 2027 case ARM::LDCL_PRE: 2028 case ARM::LDCL_POST: 2029 case ARM::LDCL_OPTION: 2030 case ARM::STC_OFFSET: 2031 case ARM::STC_PRE: 2032 case ARM::STC_POST: 2033 case ARM::STC_OPTION: 2034 case ARM::STCL_OFFSET: 2035 case ARM::STCL_PRE: 2036 case ARM::STCL_POST: 2037 case ARM::STCL_OPTION: 2038 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2039 return MCDisassembler::Fail; 2040 break; 2041 default: 2042 break; 2043 } 2044 2045 return S; 2046 } 2047 2048 static DecodeStatus 2049 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 2050 const MCDisassembler *Decoder) { 2051 DecodeStatus S = MCDisassembler::Success; 2052 2053 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2054 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 2055 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2056 unsigned imm = fieldFromInstruction(Insn, 0, 12); 2057 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2058 unsigned reg = fieldFromInstruction(Insn, 25, 1); 2059 unsigned P = fieldFromInstruction(Insn, 24, 1); 2060 unsigned W = fieldFromInstruction(Insn, 21, 1); 2061 2062 // On stores, the writeback operand precedes Rt. 2063 switch (Inst.getOpcode()) { 2064 case ARM::STR_POST_IMM: 2065 case ARM::STR_POST_REG: 2066 case ARM::STRB_POST_IMM: 2067 case ARM::STRB_POST_REG: 2068 case ARM::STRT_POST_REG: 2069 case ARM::STRT_POST_IMM: 2070 case ARM::STRBT_POST_REG: 2071 case ARM::STRBT_POST_IMM: 2072 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2073 return MCDisassembler::Fail; 2074 break; 2075 default: 2076 break; 2077 } 2078 2079 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2080 return MCDisassembler::Fail; 2081 2082 // On loads, the writeback operand comes after Rt. 2083 switch (Inst.getOpcode()) { 2084 case ARM::LDR_POST_IMM: 2085 case ARM::LDR_POST_REG: 2086 case ARM::LDRB_POST_IMM: 2087 case ARM::LDRB_POST_REG: 2088 case ARM::LDRBT_POST_REG: 2089 case ARM::LDRBT_POST_IMM: 2090 case ARM::LDRT_POST_REG: 2091 case ARM::LDRT_POST_IMM: 2092 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2093 return MCDisassembler::Fail; 2094 break; 2095 default: 2096 break; 2097 } 2098 2099 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2100 return MCDisassembler::Fail; 2101 2102 ARM_AM::AddrOpc Op = ARM_AM::add; 2103 if (!fieldFromInstruction(Insn, 23, 1)) 2104 Op = ARM_AM::sub; 2105 2106 bool writeback = (P == 0) || (W == 1); 2107 unsigned idx_mode = 0; 2108 if (P && writeback) 2109 idx_mode = ARMII::IndexModePre; 2110 else if (!P && writeback) 2111 idx_mode = ARMII::IndexModePost; 2112 2113 if (writeback && (Rn == 15 || Rn == Rt)) 2114 S = MCDisassembler::SoftFail; // UNPREDICTABLE 2115 2116 if (reg) { 2117 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2118 return MCDisassembler::Fail; 2119 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 2120 switch( fieldFromInstruction(Insn, 5, 2)) { 2121 case 0: 2122 Opc = ARM_AM::lsl; 2123 break; 2124 case 1: 2125 Opc = ARM_AM::lsr; 2126 break; 2127 case 2: 2128 Opc = ARM_AM::asr; 2129 break; 2130 case 3: 2131 Opc = ARM_AM::ror; 2132 break; 2133 default: 2134 return MCDisassembler::Fail; 2135 } 2136 unsigned amt = fieldFromInstruction(Insn, 7, 5); 2137 if (Opc == ARM_AM::ror && amt == 0) 2138 Opc = ARM_AM::rrx; 2139 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 2140 2141 Inst.addOperand(MCOperand::createImm(imm)); 2142 } else { 2143 Inst.addOperand(MCOperand::createReg(0)); 2144 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 2145 Inst.addOperand(MCOperand::createImm(tmp)); 2146 } 2147 2148 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2149 return MCDisassembler::Fail; 2150 2151 return S; 2152 } 2153 2154 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 2155 uint64_t Address, 2156 const MCDisassembler *Decoder) { 2157 DecodeStatus S = MCDisassembler::Success; 2158 2159 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2160 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2161 unsigned type = fieldFromInstruction(Val, 5, 2); 2162 unsigned imm = fieldFromInstruction(Val, 7, 5); 2163 unsigned U = fieldFromInstruction(Val, 12, 1); 2164 2165 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 2166 switch (type) { 2167 case 0: 2168 ShOp = ARM_AM::lsl; 2169 break; 2170 case 1: 2171 ShOp = ARM_AM::lsr; 2172 break; 2173 case 2: 2174 ShOp = ARM_AM::asr; 2175 break; 2176 case 3: 2177 ShOp = ARM_AM::ror; 2178 break; 2179 } 2180 2181 if (ShOp == ARM_AM::ror && imm == 0) 2182 ShOp = ARM_AM::rrx; 2183 2184 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2185 return MCDisassembler::Fail; 2186 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2187 return MCDisassembler::Fail; 2188 unsigned shift; 2189 if (U) 2190 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 2191 else 2192 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 2193 Inst.addOperand(MCOperand::createImm(shift)); 2194 2195 return S; 2196 } 2197 2198 static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn, 2199 uint64_t Address, 2200 const MCDisassembler *Decoder) { 2201 if (Inst.getOpcode() != ARM::TSB && Inst.getOpcode() != ARM::t2TSB) 2202 return MCDisassembler::Fail; 2203 2204 // The "csync" operand is not encoded into the "tsb" instruction (as this is 2205 // the only available operand), but LLVM expects the instruction to have one 2206 // operand, so we need to add the csync when decoding. 2207 Inst.addOperand(MCOperand::createImm(ARM_TSB::CSYNC)); 2208 return MCDisassembler::Success; 2209 } 2210 2211 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 2212 uint64_t Address, 2213 const MCDisassembler *Decoder) { 2214 DecodeStatus S = MCDisassembler::Success; 2215 2216 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 2217 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2218 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2219 unsigned type = fieldFromInstruction(Insn, 22, 1); 2220 unsigned imm = fieldFromInstruction(Insn, 8, 4); 2221 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 2222 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2223 unsigned W = fieldFromInstruction(Insn, 21, 1); 2224 unsigned P = fieldFromInstruction(Insn, 24, 1); 2225 unsigned Rt2 = Rt + 1; 2226 2227 bool writeback = (W == 1) | (P == 0); 2228 2229 // For {LD,ST}RD, Rt must be even, else undefined. 2230 switch (Inst.getOpcode()) { 2231 case ARM::STRD: 2232 case ARM::STRD_PRE: 2233 case ARM::STRD_POST: 2234 case ARM::LDRD: 2235 case ARM::LDRD_PRE: 2236 case ARM::LDRD_POST: 2237 if (Rt & 0x1) S = MCDisassembler::SoftFail; 2238 break; 2239 default: 2240 break; 2241 } 2242 switch (Inst.getOpcode()) { 2243 case ARM::STRD: 2244 case ARM::STRD_PRE: 2245 case ARM::STRD_POST: 2246 if (P == 0 && W == 1) 2247 S = MCDisassembler::SoftFail; 2248 2249 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 2250 S = MCDisassembler::SoftFail; 2251 if (type && Rm == 15) 2252 S = MCDisassembler::SoftFail; 2253 if (Rt2 == 15) 2254 S = MCDisassembler::SoftFail; 2255 if (!type && fieldFromInstruction(Insn, 8, 4)) 2256 S = MCDisassembler::SoftFail; 2257 break; 2258 case ARM::STRH: 2259 case ARM::STRH_PRE: 2260 case ARM::STRH_POST: 2261 if (Rt == 15) 2262 S = MCDisassembler::SoftFail; 2263 if (writeback && (Rn == 15 || Rn == Rt)) 2264 S = MCDisassembler::SoftFail; 2265 if (!type && Rm == 15) 2266 S = MCDisassembler::SoftFail; 2267 break; 2268 case ARM::LDRD: 2269 case ARM::LDRD_PRE: 2270 case ARM::LDRD_POST: 2271 if (type && Rn == 15) { 2272 if (Rt2 == 15) 2273 S = MCDisassembler::SoftFail; 2274 break; 2275 } 2276 if (P == 0 && W == 1) 2277 S = MCDisassembler::SoftFail; 2278 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 2279 S = MCDisassembler::SoftFail; 2280 if (!type && writeback && Rn == 15) 2281 S = MCDisassembler::SoftFail; 2282 if (writeback && (Rn == Rt || Rn == Rt2)) 2283 S = MCDisassembler::SoftFail; 2284 break; 2285 case ARM::LDRH: 2286 case ARM::LDRH_PRE: 2287 case ARM::LDRH_POST: 2288 if (type && Rn == 15) { 2289 if (Rt == 15) 2290 S = MCDisassembler::SoftFail; 2291 break; 2292 } 2293 if (Rt == 15) 2294 S = MCDisassembler::SoftFail; 2295 if (!type && Rm == 15) 2296 S = MCDisassembler::SoftFail; 2297 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2298 S = MCDisassembler::SoftFail; 2299 break; 2300 case ARM::LDRSH: 2301 case ARM::LDRSH_PRE: 2302 case ARM::LDRSH_POST: 2303 case ARM::LDRSB: 2304 case ARM::LDRSB_PRE: 2305 case ARM::LDRSB_POST: 2306 if (type && Rn == 15) { 2307 if (Rt == 15) 2308 S = MCDisassembler::SoftFail; 2309 break; 2310 } 2311 if (type && (Rt == 15 || (writeback && Rn == Rt))) 2312 S = MCDisassembler::SoftFail; 2313 if (!type && (Rt == 15 || Rm == 15)) 2314 S = MCDisassembler::SoftFail; 2315 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2316 S = MCDisassembler::SoftFail; 2317 break; 2318 default: 2319 break; 2320 } 2321 2322 if (writeback) { // Writeback 2323 if (P) 2324 U |= ARMII::IndexModePre << 9; 2325 else 2326 U |= ARMII::IndexModePost << 9; 2327 2328 // On stores, the writeback operand precedes Rt. 2329 switch (Inst.getOpcode()) { 2330 case ARM::STRD: 2331 case ARM::STRD_PRE: 2332 case ARM::STRD_POST: 2333 case ARM::STRH: 2334 case ARM::STRH_PRE: 2335 case ARM::STRH_POST: 2336 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2337 return MCDisassembler::Fail; 2338 break; 2339 default: 2340 break; 2341 } 2342 } 2343 2344 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2345 return MCDisassembler::Fail; 2346 switch (Inst.getOpcode()) { 2347 case ARM::STRD: 2348 case ARM::STRD_PRE: 2349 case ARM::STRD_POST: 2350 case ARM::LDRD: 2351 case ARM::LDRD_PRE: 2352 case ARM::LDRD_POST: 2353 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2354 return MCDisassembler::Fail; 2355 break; 2356 default: 2357 break; 2358 } 2359 2360 if (writeback) { 2361 // On loads, the writeback operand comes after Rt. 2362 switch (Inst.getOpcode()) { 2363 case ARM::LDRD: 2364 case ARM::LDRD_PRE: 2365 case ARM::LDRD_POST: 2366 case ARM::LDRH: 2367 case ARM::LDRH_PRE: 2368 case ARM::LDRH_POST: 2369 case ARM::LDRSH: 2370 case ARM::LDRSH_PRE: 2371 case ARM::LDRSH_POST: 2372 case ARM::LDRSB: 2373 case ARM::LDRSB_PRE: 2374 case ARM::LDRSB_POST: 2375 case ARM::LDRHTr: 2376 case ARM::LDRSBTr: 2377 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2378 return MCDisassembler::Fail; 2379 break; 2380 default: 2381 break; 2382 } 2383 } 2384 2385 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2386 return MCDisassembler::Fail; 2387 2388 if (type) { 2389 Inst.addOperand(MCOperand::createReg(0)); 2390 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 2391 } else { 2392 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2393 return MCDisassembler::Fail; 2394 Inst.addOperand(MCOperand::createImm(U)); 2395 } 2396 2397 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2398 return MCDisassembler::Fail; 2399 2400 return S; 2401 } 2402 2403 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 2404 uint64_t Address, 2405 const MCDisassembler *Decoder) { 2406 DecodeStatus S = MCDisassembler::Success; 2407 2408 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2409 unsigned mode = fieldFromInstruction(Insn, 23, 2); 2410 2411 switch (mode) { 2412 case 0: 2413 mode = ARM_AM::da; 2414 break; 2415 case 1: 2416 mode = ARM_AM::ia; 2417 break; 2418 case 2: 2419 mode = ARM_AM::db; 2420 break; 2421 case 3: 2422 mode = ARM_AM::ib; 2423 break; 2424 } 2425 2426 Inst.addOperand(MCOperand::createImm(mode)); 2427 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2428 return MCDisassembler::Fail; 2429 2430 return S; 2431 } 2432 2433 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 2434 uint64_t Address, 2435 const MCDisassembler *Decoder) { 2436 DecodeStatus S = MCDisassembler::Success; 2437 2438 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2439 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2440 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2441 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2442 2443 if (pred == 0xF) 2444 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2445 2446 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2447 return MCDisassembler::Fail; 2448 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2449 return MCDisassembler::Fail; 2450 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2451 return MCDisassembler::Fail; 2452 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2453 return MCDisassembler::Fail; 2454 return S; 2455 } 2456 2457 static DecodeStatus 2458 DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, 2459 uint64_t Address, 2460 const MCDisassembler *Decoder) { 2461 DecodeStatus S = MCDisassembler::Success; 2462 2463 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2464 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2465 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 2466 2467 if (pred == 0xF) { 2468 // Ambiguous with RFE and SRS 2469 switch (Inst.getOpcode()) { 2470 case ARM::LDMDA: 2471 Inst.setOpcode(ARM::RFEDA); 2472 break; 2473 case ARM::LDMDA_UPD: 2474 Inst.setOpcode(ARM::RFEDA_UPD); 2475 break; 2476 case ARM::LDMDB: 2477 Inst.setOpcode(ARM::RFEDB); 2478 break; 2479 case ARM::LDMDB_UPD: 2480 Inst.setOpcode(ARM::RFEDB_UPD); 2481 break; 2482 case ARM::LDMIA: 2483 Inst.setOpcode(ARM::RFEIA); 2484 break; 2485 case ARM::LDMIA_UPD: 2486 Inst.setOpcode(ARM::RFEIA_UPD); 2487 break; 2488 case ARM::LDMIB: 2489 Inst.setOpcode(ARM::RFEIB); 2490 break; 2491 case ARM::LDMIB_UPD: 2492 Inst.setOpcode(ARM::RFEIB_UPD); 2493 break; 2494 case ARM::STMDA: 2495 Inst.setOpcode(ARM::SRSDA); 2496 break; 2497 case ARM::STMDA_UPD: 2498 Inst.setOpcode(ARM::SRSDA_UPD); 2499 break; 2500 case ARM::STMDB: 2501 Inst.setOpcode(ARM::SRSDB); 2502 break; 2503 case ARM::STMDB_UPD: 2504 Inst.setOpcode(ARM::SRSDB_UPD); 2505 break; 2506 case ARM::STMIA: 2507 Inst.setOpcode(ARM::SRSIA); 2508 break; 2509 case ARM::STMIA_UPD: 2510 Inst.setOpcode(ARM::SRSIA_UPD); 2511 break; 2512 case ARM::STMIB: 2513 Inst.setOpcode(ARM::SRSIB); 2514 break; 2515 case ARM::STMIB_UPD: 2516 Inst.setOpcode(ARM::SRSIB_UPD); 2517 break; 2518 default: 2519 return MCDisassembler::Fail; 2520 } 2521 2522 // For stores (which become SRS's, the only operand is the mode. 2523 if (fieldFromInstruction(Insn, 20, 1) == 0) { 2524 // Check SRS encoding constraints 2525 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 2526 fieldFromInstruction(Insn, 20, 1) == 0)) 2527 return MCDisassembler::Fail; 2528 2529 Inst.addOperand( 2530 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 2531 return S; 2532 } 2533 2534 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 2535 } 2536 2537 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2538 return MCDisassembler::Fail; 2539 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2540 return MCDisassembler::Fail; // Tied 2541 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2542 return MCDisassembler::Fail; 2543 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 2544 return MCDisassembler::Fail; 2545 2546 return S; 2547 } 2548 2549 // Check for UNPREDICTABLE predicated ESB instruction 2550 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 2551 uint64_t Address, 2552 const MCDisassembler *Decoder) { 2553 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2554 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 2555 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2556 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2557 2558 DecodeStatus S = MCDisassembler::Success; 2559 2560 Inst.addOperand(MCOperand::createImm(imm8)); 2561 2562 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2563 return MCDisassembler::Fail; 2564 2565 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 2566 // so all predicates should be allowed. 2567 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 2568 S = MCDisassembler::SoftFail; 2569 2570 return S; 2571 } 2572 2573 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 2574 uint64_t Address, 2575 const MCDisassembler *Decoder) { 2576 unsigned imod = fieldFromInstruction(Insn, 18, 2); 2577 unsigned M = fieldFromInstruction(Insn, 17, 1); 2578 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 2579 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2580 2581 DecodeStatus S = MCDisassembler::Success; 2582 2583 // This decoder is called from multiple location that do not check 2584 // the full encoding is valid before they do. 2585 if (fieldFromInstruction(Insn, 5, 1) != 0 || 2586 fieldFromInstruction(Insn, 16, 1) != 0 || 2587 fieldFromInstruction(Insn, 20, 8) != 0x10) 2588 return MCDisassembler::Fail; 2589 2590 // imod == '01' --> UNPREDICTABLE 2591 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2592 // return failure here. The '01' imod value is unprintable, so there's 2593 // nothing useful we could do even if we returned UNPREDICTABLE. 2594 2595 if (imod == 1) return MCDisassembler::Fail; 2596 2597 if (imod && M) { 2598 Inst.setOpcode(ARM::CPS3p); 2599 Inst.addOperand(MCOperand::createImm(imod)); 2600 Inst.addOperand(MCOperand::createImm(iflags)); 2601 Inst.addOperand(MCOperand::createImm(mode)); 2602 } else if (imod && !M) { 2603 Inst.setOpcode(ARM::CPS2p); 2604 Inst.addOperand(MCOperand::createImm(imod)); 2605 Inst.addOperand(MCOperand::createImm(iflags)); 2606 if (mode) S = MCDisassembler::SoftFail; 2607 } else if (!imod && M) { 2608 Inst.setOpcode(ARM::CPS1p); 2609 Inst.addOperand(MCOperand::createImm(mode)); 2610 if (iflags) S = MCDisassembler::SoftFail; 2611 } else { 2612 // imod == '00' && M == '0' --> UNPREDICTABLE 2613 Inst.setOpcode(ARM::CPS1p); 2614 Inst.addOperand(MCOperand::createImm(mode)); 2615 S = MCDisassembler::SoftFail; 2616 } 2617 2618 return S; 2619 } 2620 2621 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2622 uint64_t Address, 2623 const MCDisassembler *Decoder) { 2624 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2625 unsigned M = fieldFromInstruction(Insn, 8, 1); 2626 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2627 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2628 2629 DecodeStatus S = MCDisassembler::Success; 2630 2631 // imod == '01' --> UNPREDICTABLE 2632 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2633 // return failure here. The '01' imod value is unprintable, so there's 2634 // nothing useful we could do even if we returned UNPREDICTABLE. 2635 2636 if (imod == 1) return MCDisassembler::Fail; 2637 2638 if (imod && M) { 2639 Inst.setOpcode(ARM::t2CPS3p); 2640 Inst.addOperand(MCOperand::createImm(imod)); 2641 Inst.addOperand(MCOperand::createImm(iflags)); 2642 Inst.addOperand(MCOperand::createImm(mode)); 2643 } else if (imod && !M) { 2644 Inst.setOpcode(ARM::t2CPS2p); 2645 Inst.addOperand(MCOperand::createImm(imod)); 2646 Inst.addOperand(MCOperand::createImm(iflags)); 2647 if (mode) S = MCDisassembler::SoftFail; 2648 } else if (!imod && M) { 2649 Inst.setOpcode(ARM::t2CPS1p); 2650 Inst.addOperand(MCOperand::createImm(mode)); 2651 if (iflags) S = MCDisassembler::SoftFail; 2652 } else { 2653 // imod == '00' && M == '0' --> this is a HINT instruction 2654 int imm = fieldFromInstruction(Insn, 0, 8); 2655 // HINT are defined only for immediate in [0..4] 2656 if(imm > 4) return MCDisassembler::Fail; 2657 Inst.setOpcode(ARM::t2HINT); 2658 Inst.addOperand(MCOperand::createImm(imm)); 2659 } 2660 2661 return S; 2662 } 2663 2664 static DecodeStatus 2665 DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 2666 const MCDisassembler *Decoder) { 2667 unsigned imm = fieldFromInstruction(Insn, 0, 8); 2668 2669 unsigned Opcode = ARM::t2HINT; 2670 2671 if (imm == 0x0D) { 2672 Opcode = ARM::t2PACBTI; 2673 } else if (imm == 0x1D) { 2674 Opcode = ARM::t2PAC; 2675 } else if (imm == 0x2D) { 2676 Opcode = ARM::t2AUT; 2677 } else if (imm == 0x0F) { 2678 Opcode = ARM::t2BTI; 2679 } 2680 2681 Inst.setOpcode(Opcode); 2682 if (Opcode == ARM::t2HINT) { 2683 Inst.addOperand(MCOperand::createImm(imm)); 2684 } 2685 2686 return MCDisassembler::Success; 2687 } 2688 2689 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2690 uint64_t Address, 2691 const MCDisassembler *Decoder) { 2692 DecodeStatus S = MCDisassembler::Success; 2693 2694 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2695 unsigned imm = 0; 2696 2697 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2698 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2699 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2700 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2701 2702 if (Inst.getOpcode() == ARM::t2MOVTi16) 2703 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2704 return MCDisassembler::Fail; 2705 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2706 return MCDisassembler::Fail; 2707 2708 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2709 Inst.addOperand(MCOperand::createImm(imm)); 2710 2711 return S; 2712 } 2713 2714 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2715 uint64_t Address, 2716 const MCDisassembler *Decoder) { 2717 DecodeStatus S = MCDisassembler::Success; 2718 2719 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2720 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2721 unsigned imm = 0; 2722 2723 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2724 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2725 2726 if (Inst.getOpcode() == ARM::MOVTi16) 2727 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2728 return MCDisassembler::Fail; 2729 2730 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2731 return MCDisassembler::Fail; 2732 2733 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2734 Inst.addOperand(MCOperand::createImm(imm)); 2735 2736 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2737 return MCDisassembler::Fail; 2738 2739 return S; 2740 } 2741 2742 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2743 uint64_t Address, 2744 const MCDisassembler *Decoder) { 2745 DecodeStatus S = MCDisassembler::Success; 2746 2747 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2748 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2749 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2750 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2751 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2752 2753 if (pred == 0xF) 2754 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2755 2756 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2757 return MCDisassembler::Fail; 2758 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2759 return MCDisassembler::Fail; 2760 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2761 return MCDisassembler::Fail; 2762 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2763 return MCDisassembler::Fail; 2764 2765 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2766 return MCDisassembler::Fail; 2767 2768 return S; 2769 } 2770 2771 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2772 uint64_t Address, 2773 const MCDisassembler *Decoder) { 2774 DecodeStatus S = MCDisassembler::Success; 2775 2776 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2777 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2778 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2779 2780 if (Pred == 0xF) 2781 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2782 2783 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2784 return MCDisassembler::Fail; 2785 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2786 return MCDisassembler::Fail; 2787 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2788 return MCDisassembler::Fail; 2789 2790 return S; 2791 } 2792 2793 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2794 uint64_t Address, 2795 const MCDisassembler *Decoder) { 2796 DecodeStatus S = MCDisassembler::Success; 2797 2798 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2799 2800 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2801 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2802 2803 if (!FeatureBits[ARM::HasV8_1aOps] || 2804 !FeatureBits[ARM::HasV8Ops]) 2805 return MCDisassembler::Fail; 2806 2807 // Decoder can be called from DecodeTST, which does not check the full 2808 // encoding is valid. 2809 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2810 fieldFromInstruction(Insn, 4,4) != 0) 2811 return MCDisassembler::Fail; 2812 if (fieldFromInstruction(Insn, 10,10) != 0 || 2813 fieldFromInstruction(Insn, 0,4) != 0) 2814 S = MCDisassembler::SoftFail; 2815 2816 Inst.setOpcode(ARM::SETPAN); 2817 Inst.addOperand(MCOperand::createImm(Imm)); 2818 2819 return S; 2820 } 2821 2822 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2823 uint64_t Address, 2824 const MCDisassembler *Decoder) { 2825 DecodeStatus S = MCDisassembler::Success; 2826 2827 unsigned add = fieldFromInstruction(Val, 12, 1); 2828 unsigned imm = fieldFromInstruction(Val, 0, 12); 2829 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2830 2831 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2832 return MCDisassembler::Fail; 2833 2834 if (!add) imm *= -1; 2835 if (imm == 0 && !add) imm = INT32_MIN; 2836 Inst.addOperand(MCOperand::createImm(imm)); 2837 if (Rn == 15) 2838 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2839 2840 return S; 2841 } 2842 2843 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2844 uint64_t Address, 2845 const MCDisassembler *Decoder) { 2846 DecodeStatus S = MCDisassembler::Success; 2847 2848 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2849 // U == 1 to add imm, 0 to subtract it. 2850 unsigned U = fieldFromInstruction(Val, 8, 1); 2851 unsigned imm = fieldFromInstruction(Val, 0, 8); 2852 2853 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2854 return MCDisassembler::Fail; 2855 2856 if (U) 2857 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2858 else 2859 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2860 2861 return S; 2862 } 2863 2864 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2865 uint64_t Address, 2866 const MCDisassembler *Decoder) { 2867 DecodeStatus S = MCDisassembler::Success; 2868 2869 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2870 // U == 1 to add imm, 0 to subtract it. 2871 unsigned U = fieldFromInstruction(Val, 8, 1); 2872 unsigned imm = fieldFromInstruction(Val, 0, 8); 2873 2874 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2875 return MCDisassembler::Fail; 2876 2877 if (U) 2878 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2879 else 2880 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2881 2882 return S; 2883 } 2884 2885 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2886 uint64_t Address, 2887 const MCDisassembler *Decoder) { 2888 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2889 } 2890 2891 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2892 uint64_t Address, 2893 const MCDisassembler *Decoder) { 2894 DecodeStatus Status = MCDisassembler::Success; 2895 2896 // Note the J1 and J2 values are from the encoded instruction. So here 2897 // change them to I1 and I2 values via as documented: 2898 // I1 = NOT(J1 EOR S); 2899 // I2 = NOT(J2 EOR S); 2900 // and build the imm32 with one trailing zero as documented: 2901 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2902 unsigned S = fieldFromInstruction(Insn, 26, 1); 2903 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2904 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2905 unsigned I1 = !(J1 ^ S); 2906 unsigned I2 = !(J2 ^ S); 2907 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2908 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2909 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2910 int imm32 = SignExtend32<25>(tmp << 1); 2911 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2912 true, 4, Inst, Decoder)) 2913 Inst.addOperand(MCOperand::createImm(imm32)); 2914 2915 return Status; 2916 } 2917 2918 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2919 uint64_t Address, 2920 const MCDisassembler *Decoder) { 2921 DecodeStatus S = MCDisassembler::Success; 2922 2923 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2924 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2925 2926 if (pred == 0xF) { 2927 Inst.setOpcode(ARM::BLXi); 2928 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2929 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2930 true, 4, Inst, Decoder)) 2931 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2932 return S; 2933 } 2934 2935 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2936 true, 4, Inst, Decoder)) 2937 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2938 2939 // We already have BL_pred for BL w/ predicate, no need to add addition 2940 // predicate opreands for BL 2941 if (Inst.getOpcode() != ARM::BL) 2942 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2943 return MCDisassembler::Fail; 2944 2945 return S; 2946 } 2947 2948 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2949 uint64_t Address, 2950 const MCDisassembler *Decoder) { 2951 DecodeStatus S = MCDisassembler::Success; 2952 2953 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2954 unsigned align = fieldFromInstruction(Val, 4, 2); 2955 2956 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2957 return MCDisassembler::Fail; 2958 if (!align) 2959 Inst.addOperand(MCOperand::createImm(0)); 2960 else 2961 Inst.addOperand(MCOperand::createImm(4 << align)); 2962 2963 return S; 2964 } 2965 2966 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2967 uint64_t Address, 2968 const MCDisassembler *Decoder) { 2969 DecodeStatus S = MCDisassembler::Success; 2970 2971 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2972 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2973 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2974 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2975 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2976 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2977 2978 // First output register 2979 switch (Inst.getOpcode()) { 2980 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2981 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2982 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2983 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2984 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2985 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2986 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2987 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2988 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2989 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2990 return MCDisassembler::Fail; 2991 break; 2992 case ARM::VLD2b16: 2993 case ARM::VLD2b32: 2994 case ARM::VLD2b8: 2995 case ARM::VLD2b16wb_fixed: 2996 case ARM::VLD2b16wb_register: 2997 case ARM::VLD2b32wb_fixed: 2998 case ARM::VLD2b32wb_register: 2999 case ARM::VLD2b8wb_fixed: 3000 case ARM::VLD2b8wb_register: 3001 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3002 return MCDisassembler::Fail; 3003 break; 3004 default: 3005 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3006 return MCDisassembler::Fail; 3007 } 3008 3009 // Second output register 3010 switch (Inst.getOpcode()) { 3011 case ARM::VLD3d8: 3012 case ARM::VLD3d16: 3013 case ARM::VLD3d32: 3014 case ARM::VLD3d8_UPD: 3015 case ARM::VLD3d16_UPD: 3016 case ARM::VLD3d32_UPD: 3017 case ARM::VLD4d8: 3018 case ARM::VLD4d16: 3019 case ARM::VLD4d32: 3020 case ARM::VLD4d8_UPD: 3021 case ARM::VLD4d16_UPD: 3022 case ARM::VLD4d32_UPD: 3023 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3024 return MCDisassembler::Fail; 3025 break; 3026 case ARM::VLD3q8: 3027 case ARM::VLD3q16: 3028 case ARM::VLD3q32: 3029 case ARM::VLD3q8_UPD: 3030 case ARM::VLD3q16_UPD: 3031 case ARM::VLD3q32_UPD: 3032 case ARM::VLD4q8: 3033 case ARM::VLD4q16: 3034 case ARM::VLD4q32: 3035 case ARM::VLD4q8_UPD: 3036 case ARM::VLD4q16_UPD: 3037 case ARM::VLD4q32_UPD: 3038 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3039 return MCDisassembler::Fail; 3040 break; 3041 default: 3042 break; 3043 } 3044 3045 // Third output register 3046 switch(Inst.getOpcode()) { 3047 case ARM::VLD3d8: 3048 case ARM::VLD3d16: 3049 case ARM::VLD3d32: 3050 case ARM::VLD3d8_UPD: 3051 case ARM::VLD3d16_UPD: 3052 case ARM::VLD3d32_UPD: 3053 case ARM::VLD4d8: 3054 case ARM::VLD4d16: 3055 case ARM::VLD4d32: 3056 case ARM::VLD4d8_UPD: 3057 case ARM::VLD4d16_UPD: 3058 case ARM::VLD4d32_UPD: 3059 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3060 return MCDisassembler::Fail; 3061 break; 3062 case ARM::VLD3q8: 3063 case ARM::VLD3q16: 3064 case ARM::VLD3q32: 3065 case ARM::VLD3q8_UPD: 3066 case ARM::VLD3q16_UPD: 3067 case ARM::VLD3q32_UPD: 3068 case ARM::VLD4q8: 3069 case ARM::VLD4q16: 3070 case ARM::VLD4q32: 3071 case ARM::VLD4q8_UPD: 3072 case ARM::VLD4q16_UPD: 3073 case ARM::VLD4q32_UPD: 3074 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3075 return MCDisassembler::Fail; 3076 break; 3077 default: 3078 break; 3079 } 3080 3081 // Fourth output register 3082 switch (Inst.getOpcode()) { 3083 case ARM::VLD4d8: 3084 case ARM::VLD4d16: 3085 case ARM::VLD4d32: 3086 case ARM::VLD4d8_UPD: 3087 case ARM::VLD4d16_UPD: 3088 case ARM::VLD4d32_UPD: 3089 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3090 return MCDisassembler::Fail; 3091 break; 3092 case ARM::VLD4q8: 3093 case ARM::VLD4q16: 3094 case ARM::VLD4q32: 3095 case ARM::VLD4q8_UPD: 3096 case ARM::VLD4q16_UPD: 3097 case ARM::VLD4q32_UPD: 3098 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3099 return MCDisassembler::Fail; 3100 break; 3101 default: 3102 break; 3103 } 3104 3105 // Writeback operand 3106 switch (Inst.getOpcode()) { 3107 case ARM::VLD1d8wb_fixed: 3108 case ARM::VLD1d16wb_fixed: 3109 case ARM::VLD1d32wb_fixed: 3110 case ARM::VLD1d64wb_fixed: 3111 case ARM::VLD1d8wb_register: 3112 case ARM::VLD1d16wb_register: 3113 case ARM::VLD1d32wb_register: 3114 case ARM::VLD1d64wb_register: 3115 case ARM::VLD1q8wb_fixed: 3116 case ARM::VLD1q16wb_fixed: 3117 case ARM::VLD1q32wb_fixed: 3118 case ARM::VLD1q64wb_fixed: 3119 case ARM::VLD1q8wb_register: 3120 case ARM::VLD1q16wb_register: 3121 case ARM::VLD1q32wb_register: 3122 case ARM::VLD1q64wb_register: 3123 case ARM::VLD1d8Twb_fixed: 3124 case ARM::VLD1d8Twb_register: 3125 case ARM::VLD1d16Twb_fixed: 3126 case ARM::VLD1d16Twb_register: 3127 case ARM::VLD1d32Twb_fixed: 3128 case ARM::VLD1d32Twb_register: 3129 case ARM::VLD1d64Twb_fixed: 3130 case ARM::VLD1d64Twb_register: 3131 case ARM::VLD1d8Qwb_fixed: 3132 case ARM::VLD1d8Qwb_register: 3133 case ARM::VLD1d16Qwb_fixed: 3134 case ARM::VLD1d16Qwb_register: 3135 case ARM::VLD1d32Qwb_fixed: 3136 case ARM::VLD1d32Qwb_register: 3137 case ARM::VLD1d64Qwb_fixed: 3138 case ARM::VLD1d64Qwb_register: 3139 case ARM::VLD2d8wb_fixed: 3140 case ARM::VLD2d16wb_fixed: 3141 case ARM::VLD2d32wb_fixed: 3142 case ARM::VLD2q8wb_fixed: 3143 case ARM::VLD2q16wb_fixed: 3144 case ARM::VLD2q32wb_fixed: 3145 case ARM::VLD2d8wb_register: 3146 case ARM::VLD2d16wb_register: 3147 case ARM::VLD2d32wb_register: 3148 case ARM::VLD2q8wb_register: 3149 case ARM::VLD2q16wb_register: 3150 case ARM::VLD2q32wb_register: 3151 case ARM::VLD2b8wb_fixed: 3152 case ARM::VLD2b16wb_fixed: 3153 case ARM::VLD2b32wb_fixed: 3154 case ARM::VLD2b8wb_register: 3155 case ARM::VLD2b16wb_register: 3156 case ARM::VLD2b32wb_register: 3157 Inst.addOperand(MCOperand::createImm(0)); 3158 break; 3159 case ARM::VLD3d8_UPD: 3160 case ARM::VLD3d16_UPD: 3161 case ARM::VLD3d32_UPD: 3162 case ARM::VLD3q8_UPD: 3163 case ARM::VLD3q16_UPD: 3164 case ARM::VLD3q32_UPD: 3165 case ARM::VLD4d8_UPD: 3166 case ARM::VLD4d16_UPD: 3167 case ARM::VLD4d32_UPD: 3168 case ARM::VLD4q8_UPD: 3169 case ARM::VLD4q16_UPD: 3170 case ARM::VLD4q32_UPD: 3171 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3172 return MCDisassembler::Fail; 3173 break; 3174 default: 3175 break; 3176 } 3177 3178 // AddrMode6 Base (register+alignment) 3179 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3180 return MCDisassembler::Fail; 3181 3182 // AddrMode6 Offset (register) 3183 switch (Inst.getOpcode()) { 3184 default: 3185 // The below have been updated to have explicit am6offset split 3186 // between fixed and register offset. For those instructions not 3187 // yet updated, we need to add an additional reg0 operand for the 3188 // fixed variant. 3189 // 3190 // The fixed offset encodes as Rm == 0xd, so we check for that. 3191 if (Rm == 0xd) { 3192 Inst.addOperand(MCOperand::createReg(0)); 3193 break; 3194 } 3195 // Fall through to handle the register offset variant. 3196 [[fallthrough]]; 3197 case ARM::VLD1d8wb_fixed: 3198 case ARM::VLD1d16wb_fixed: 3199 case ARM::VLD1d32wb_fixed: 3200 case ARM::VLD1d64wb_fixed: 3201 case ARM::VLD1d8Twb_fixed: 3202 case ARM::VLD1d16Twb_fixed: 3203 case ARM::VLD1d32Twb_fixed: 3204 case ARM::VLD1d64Twb_fixed: 3205 case ARM::VLD1d8Qwb_fixed: 3206 case ARM::VLD1d16Qwb_fixed: 3207 case ARM::VLD1d32Qwb_fixed: 3208 case ARM::VLD1d64Qwb_fixed: 3209 case ARM::VLD1d8wb_register: 3210 case ARM::VLD1d16wb_register: 3211 case ARM::VLD1d32wb_register: 3212 case ARM::VLD1d64wb_register: 3213 case ARM::VLD1q8wb_fixed: 3214 case ARM::VLD1q16wb_fixed: 3215 case ARM::VLD1q32wb_fixed: 3216 case ARM::VLD1q64wb_fixed: 3217 case ARM::VLD1q8wb_register: 3218 case ARM::VLD1q16wb_register: 3219 case ARM::VLD1q32wb_register: 3220 case ARM::VLD1q64wb_register: 3221 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3222 // variant encodes Rm == 0xf. Anything else is a register offset post- 3223 // increment and we need to add the register operand to the instruction. 3224 if (Rm != 0xD && Rm != 0xF && 3225 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3226 return MCDisassembler::Fail; 3227 break; 3228 case ARM::VLD2d8wb_fixed: 3229 case ARM::VLD2d16wb_fixed: 3230 case ARM::VLD2d32wb_fixed: 3231 case ARM::VLD2b8wb_fixed: 3232 case ARM::VLD2b16wb_fixed: 3233 case ARM::VLD2b32wb_fixed: 3234 case ARM::VLD2q8wb_fixed: 3235 case ARM::VLD2q16wb_fixed: 3236 case ARM::VLD2q32wb_fixed: 3237 break; 3238 } 3239 3240 return S; 3241 } 3242 3243 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 3244 uint64_t Address, 3245 const MCDisassembler *Decoder) { 3246 unsigned type = fieldFromInstruction(Insn, 8, 4); 3247 unsigned align = fieldFromInstruction(Insn, 4, 2); 3248 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 3249 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 3250 if (type == 10 && align == 3) return MCDisassembler::Fail; 3251 3252 unsigned load = fieldFromInstruction(Insn, 21, 1); 3253 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3254 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3255 } 3256 3257 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 3258 uint64_t Address, 3259 const MCDisassembler *Decoder) { 3260 unsigned size = fieldFromInstruction(Insn, 6, 2); 3261 if (size == 3) return MCDisassembler::Fail; 3262 3263 unsigned type = fieldFromInstruction(Insn, 8, 4); 3264 unsigned align = fieldFromInstruction(Insn, 4, 2); 3265 if (type == 8 && align == 3) return MCDisassembler::Fail; 3266 if (type == 9 && align == 3) return MCDisassembler::Fail; 3267 3268 unsigned load = fieldFromInstruction(Insn, 21, 1); 3269 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3270 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3271 } 3272 3273 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 3274 uint64_t Address, 3275 const MCDisassembler *Decoder) { 3276 unsigned size = fieldFromInstruction(Insn, 6, 2); 3277 if (size == 3) return MCDisassembler::Fail; 3278 3279 unsigned align = fieldFromInstruction(Insn, 4, 2); 3280 if (align & 2) return MCDisassembler::Fail; 3281 3282 unsigned load = fieldFromInstruction(Insn, 21, 1); 3283 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3284 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3285 } 3286 3287 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 3288 uint64_t Address, 3289 const MCDisassembler *Decoder) { 3290 unsigned size = fieldFromInstruction(Insn, 6, 2); 3291 if (size == 3) return MCDisassembler::Fail; 3292 3293 unsigned load = fieldFromInstruction(Insn, 21, 1); 3294 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3295 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3296 } 3297 3298 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 3299 uint64_t Address, 3300 const MCDisassembler *Decoder) { 3301 DecodeStatus S = MCDisassembler::Success; 3302 3303 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3304 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3305 unsigned wb = fieldFromInstruction(Insn, 16, 4); 3306 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3307 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 3308 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3309 3310 // Writeback Operand 3311 switch (Inst.getOpcode()) { 3312 case ARM::VST1d8wb_fixed: 3313 case ARM::VST1d16wb_fixed: 3314 case ARM::VST1d32wb_fixed: 3315 case ARM::VST1d64wb_fixed: 3316 case ARM::VST1d8wb_register: 3317 case ARM::VST1d16wb_register: 3318 case ARM::VST1d32wb_register: 3319 case ARM::VST1d64wb_register: 3320 case ARM::VST1q8wb_fixed: 3321 case ARM::VST1q16wb_fixed: 3322 case ARM::VST1q32wb_fixed: 3323 case ARM::VST1q64wb_fixed: 3324 case ARM::VST1q8wb_register: 3325 case ARM::VST1q16wb_register: 3326 case ARM::VST1q32wb_register: 3327 case ARM::VST1q64wb_register: 3328 case ARM::VST1d8Twb_fixed: 3329 case ARM::VST1d16Twb_fixed: 3330 case ARM::VST1d32Twb_fixed: 3331 case ARM::VST1d64Twb_fixed: 3332 case ARM::VST1d8Twb_register: 3333 case ARM::VST1d16Twb_register: 3334 case ARM::VST1d32Twb_register: 3335 case ARM::VST1d64Twb_register: 3336 case ARM::VST1d8Qwb_fixed: 3337 case ARM::VST1d16Qwb_fixed: 3338 case ARM::VST1d32Qwb_fixed: 3339 case ARM::VST1d64Qwb_fixed: 3340 case ARM::VST1d8Qwb_register: 3341 case ARM::VST1d16Qwb_register: 3342 case ARM::VST1d32Qwb_register: 3343 case ARM::VST1d64Qwb_register: 3344 case ARM::VST2d8wb_fixed: 3345 case ARM::VST2d16wb_fixed: 3346 case ARM::VST2d32wb_fixed: 3347 case ARM::VST2d8wb_register: 3348 case ARM::VST2d16wb_register: 3349 case ARM::VST2d32wb_register: 3350 case ARM::VST2q8wb_fixed: 3351 case ARM::VST2q16wb_fixed: 3352 case ARM::VST2q32wb_fixed: 3353 case ARM::VST2q8wb_register: 3354 case ARM::VST2q16wb_register: 3355 case ARM::VST2q32wb_register: 3356 case ARM::VST2b8wb_fixed: 3357 case ARM::VST2b16wb_fixed: 3358 case ARM::VST2b32wb_fixed: 3359 case ARM::VST2b8wb_register: 3360 case ARM::VST2b16wb_register: 3361 case ARM::VST2b32wb_register: 3362 if (Rm == 0xF) 3363 return MCDisassembler::Fail; 3364 Inst.addOperand(MCOperand::createImm(0)); 3365 break; 3366 case ARM::VST3d8_UPD: 3367 case ARM::VST3d16_UPD: 3368 case ARM::VST3d32_UPD: 3369 case ARM::VST3q8_UPD: 3370 case ARM::VST3q16_UPD: 3371 case ARM::VST3q32_UPD: 3372 case ARM::VST4d8_UPD: 3373 case ARM::VST4d16_UPD: 3374 case ARM::VST4d32_UPD: 3375 case ARM::VST4q8_UPD: 3376 case ARM::VST4q16_UPD: 3377 case ARM::VST4q32_UPD: 3378 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3379 return MCDisassembler::Fail; 3380 break; 3381 default: 3382 break; 3383 } 3384 3385 // AddrMode6 Base (register+alignment) 3386 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3387 return MCDisassembler::Fail; 3388 3389 // AddrMode6 Offset (register) 3390 switch (Inst.getOpcode()) { 3391 default: 3392 if (Rm == 0xD) 3393 Inst.addOperand(MCOperand::createReg(0)); 3394 else if (Rm != 0xF) { 3395 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3396 return MCDisassembler::Fail; 3397 } 3398 break; 3399 case ARM::VST1d8wb_fixed: 3400 case ARM::VST1d16wb_fixed: 3401 case ARM::VST1d32wb_fixed: 3402 case ARM::VST1d64wb_fixed: 3403 case ARM::VST1q8wb_fixed: 3404 case ARM::VST1q16wb_fixed: 3405 case ARM::VST1q32wb_fixed: 3406 case ARM::VST1q64wb_fixed: 3407 case ARM::VST1d8Twb_fixed: 3408 case ARM::VST1d16Twb_fixed: 3409 case ARM::VST1d32Twb_fixed: 3410 case ARM::VST1d64Twb_fixed: 3411 case ARM::VST1d8Qwb_fixed: 3412 case ARM::VST1d16Qwb_fixed: 3413 case ARM::VST1d32Qwb_fixed: 3414 case ARM::VST1d64Qwb_fixed: 3415 case ARM::VST2d8wb_fixed: 3416 case ARM::VST2d16wb_fixed: 3417 case ARM::VST2d32wb_fixed: 3418 case ARM::VST2q8wb_fixed: 3419 case ARM::VST2q16wb_fixed: 3420 case ARM::VST2q32wb_fixed: 3421 case ARM::VST2b8wb_fixed: 3422 case ARM::VST2b16wb_fixed: 3423 case ARM::VST2b32wb_fixed: 3424 break; 3425 } 3426 3427 // First input register 3428 switch (Inst.getOpcode()) { 3429 case ARM::VST1q16: 3430 case ARM::VST1q32: 3431 case ARM::VST1q64: 3432 case ARM::VST1q8: 3433 case ARM::VST1q16wb_fixed: 3434 case ARM::VST1q16wb_register: 3435 case ARM::VST1q32wb_fixed: 3436 case ARM::VST1q32wb_register: 3437 case ARM::VST1q64wb_fixed: 3438 case ARM::VST1q64wb_register: 3439 case ARM::VST1q8wb_fixed: 3440 case ARM::VST1q8wb_register: 3441 case ARM::VST2d16: 3442 case ARM::VST2d32: 3443 case ARM::VST2d8: 3444 case ARM::VST2d16wb_fixed: 3445 case ARM::VST2d16wb_register: 3446 case ARM::VST2d32wb_fixed: 3447 case ARM::VST2d32wb_register: 3448 case ARM::VST2d8wb_fixed: 3449 case ARM::VST2d8wb_register: 3450 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3451 return MCDisassembler::Fail; 3452 break; 3453 case ARM::VST2b16: 3454 case ARM::VST2b32: 3455 case ARM::VST2b8: 3456 case ARM::VST2b16wb_fixed: 3457 case ARM::VST2b16wb_register: 3458 case ARM::VST2b32wb_fixed: 3459 case ARM::VST2b32wb_register: 3460 case ARM::VST2b8wb_fixed: 3461 case ARM::VST2b8wb_register: 3462 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3463 return MCDisassembler::Fail; 3464 break; 3465 default: 3466 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3467 return MCDisassembler::Fail; 3468 } 3469 3470 // Second input register 3471 switch (Inst.getOpcode()) { 3472 case ARM::VST3d8: 3473 case ARM::VST3d16: 3474 case ARM::VST3d32: 3475 case ARM::VST3d8_UPD: 3476 case ARM::VST3d16_UPD: 3477 case ARM::VST3d32_UPD: 3478 case ARM::VST4d8: 3479 case ARM::VST4d16: 3480 case ARM::VST4d32: 3481 case ARM::VST4d8_UPD: 3482 case ARM::VST4d16_UPD: 3483 case ARM::VST4d32_UPD: 3484 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3485 return MCDisassembler::Fail; 3486 break; 3487 case ARM::VST3q8: 3488 case ARM::VST3q16: 3489 case ARM::VST3q32: 3490 case ARM::VST3q8_UPD: 3491 case ARM::VST3q16_UPD: 3492 case ARM::VST3q32_UPD: 3493 case ARM::VST4q8: 3494 case ARM::VST4q16: 3495 case ARM::VST4q32: 3496 case ARM::VST4q8_UPD: 3497 case ARM::VST4q16_UPD: 3498 case ARM::VST4q32_UPD: 3499 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3500 return MCDisassembler::Fail; 3501 break; 3502 default: 3503 break; 3504 } 3505 3506 // Third input register 3507 switch (Inst.getOpcode()) { 3508 case ARM::VST3d8: 3509 case ARM::VST3d16: 3510 case ARM::VST3d32: 3511 case ARM::VST3d8_UPD: 3512 case ARM::VST3d16_UPD: 3513 case ARM::VST3d32_UPD: 3514 case ARM::VST4d8: 3515 case ARM::VST4d16: 3516 case ARM::VST4d32: 3517 case ARM::VST4d8_UPD: 3518 case ARM::VST4d16_UPD: 3519 case ARM::VST4d32_UPD: 3520 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3521 return MCDisassembler::Fail; 3522 break; 3523 case ARM::VST3q8: 3524 case ARM::VST3q16: 3525 case ARM::VST3q32: 3526 case ARM::VST3q8_UPD: 3527 case ARM::VST3q16_UPD: 3528 case ARM::VST3q32_UPD: 3529 case ARM::VST4q8: 3530 case ARM::VST4q16: 3531 case ARM::VST4q32: 3532 case ARM::VST4q8_UPD: 3533 case ARM::VST4q16_UPD: 3534 case ARM::VST4q32_UPD: 3535 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3536 return MCDisassembler::Fail; 3537 break; 3538 default: 3539 break; 3540 } 3541 3542 // Fourth input register 3543 switch (Inst.getOpcode()) { 3544 case ARM::VST4d8: 3545 case ARM::VST4d16: 3546 case ARM::VST4d32: 3547 case ARM::VST4d8_UPD: 3548 case ARM::VST4d16_UPD: 3549 case ARM::VST4d32_UPD: 3550 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3551 return MCDisassembler::Fail; 3552 break; 3553 case ARM::VST4q8: 3554 case ARM::VST4q16: 3555 case ARM::VST4q32: 3556 case ARM::VST4q8_UPD: 3557 case ARM::VST4q16_UPD: 3558 case ARM::VST4q32_UPD: 3559 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3560 return MCDisassembler::Fail; 3561 break; 3562 default: 3563 break; 3564 } 3565 3566 return S; 3567 } 3568 3569 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 3570 uint64_t Address, 3571 const MCDisassembler *Decoder) { 3572 DecodeStatus S = MCDisassembler::Success; 3573 3574 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3575 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3576 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3577 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3578 unsigned align = fieldFromInstruction(Insn, 4, 1); 3579 unsigned size = fieldFromInstruction(Insn, 6, 2); 3580 3581 if (size == 0 && align == 1) 3582 return MCDisassembler::Fail; 3583 align *= (1 << size); 3584 3585 switch (Inst.getOpcode()) { 3586 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 3587 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 3588 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 3589 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 3590 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3591 return MCDisassembler::Fail; 3592 break; 3593 default: 3594 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3595 return MCDisassembler::Fail; 3596 break; 3597 } 3598 if (Rm != 0xF) { 3599 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3600 return MCDisassembler::Fail; 3601 } 3602 3603 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3604 return MCDisassembler::Fail; 3605 Inst.addOperand(MCOperand::createImm(align)); 3606 3607 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3608 // variant encodes Rm == 0xf. Anything else is a register offset post- 3609 // increment and we need to add the register operand to the instruction. 3610 if (Rm != 0xD && Rm != 0xF && 3611 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3612 return MCDisassembler::Fail; 3613 3614 return S; 3615 } 3616 3617 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 3618 uint64_t Address, 3619 const MCDisassembler *Decoder) { 3620 DecodeStatus S = MCDisassembler::Success; 3621 3622 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3623 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3624 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3625 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3626 unsigned align = fieldFromInstruction(Insn, 4, 1); 3627 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 3628 align *= 2*size; 3629 3630 switch (Inst.getOpcode()) { 3631 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 3632 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 3633 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 3634 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 3635 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3636 return MCDisassembler::Fail; 3637 break; 3638 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3639 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3640 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3641 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3642 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3643 return MCDisassembler::Fail; 3644 break; 3645 default: 3646 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3647 return MCDisassembler::Fail; 3648 break; 3649 } 3650 3651 if (Rm != 0xF) 3652 Inst.addOperand(MCOperand::createImm(0)); 3653 3654 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3655 return MCDisassembler::Fail; 3656 Inst.addOperand(MCOperand::createImm(align)); 3657 3658 if (Rm != 0xD && Rm != 0xF) { 3659 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3660 return MCDisassembler::Fail; 3661 } 3662 3663 return S; 3664 } 3665 3666 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3667 uint64_t Address, 3668 const MCDisassembler *Decoder) { 3669 DecodeStatus S = MCDisassembler::Success; 3670 3671 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3672 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3673 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3674 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3675 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3676 3677 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3678 return MCDisassembler::Fail; 3679 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3680 return MCDisassembler::Fail; 3681 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3682 return MCDisassembler::Fail; 3683 if (Rm != 0xF) { 3684 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3685 return MCDisassembler::Fail; 3686 } 3687 3688 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3689 return MCDisassembler::Fail; 3690 Inst.addOperand(MCOperand::createImm(0)); 3691 3692 if (Rm == 0xD) 3693 Inst.addOperand(MCOperand::createReg(0)); 3694 else if (Rm != 0xF) { 3695 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3696 return MCDisassembler::Fail; 3697 } 3698 3699 return S; 3700 } 3701 3702 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3703 uint64_t Address, 3704 const MCDisassembler *Decoder) { 3705 DecodeStatus S = MCDisassembler::Success; 3706 3707 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3708 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3709 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3710 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3711 unsigned size = fieldFromInstruction(Insn, 6, 2); 3712 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3713 unsigned align = fieldFromInstruction(Insn, 4, 1); 3714 3715 if (size == 0x3) { 3716 if (align == 0) 3717 return MCDisassembler::Fail; 3718 align = 16; 3719 } else { 3720 if (size == 2) { 3721 align *= 8; 3722 } else { 3723 size = 1 << size; 3724 align *= 4*size; 3725 } 3726 } 3727 3728 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3729 return MCDisassembler::Fail; 3730 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3731 return MCDisassembler::Fail; 3732 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3733 return MCDisassembler::Fail; 3734 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3735 return MCDisassembler::Fail; 3736 if (Rm != 0xF) { 3737 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3738 return MCDisassembler::Fail; 3739 } 3740 3741 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3742 return MCDisassembler::Fail; 3743 Inst.addOperand(MCOperand::createImm(align)); 3744 3745 if (Rm == 0xD) 3746 Inst.addOperand(MCOperand::createReg(0)); 3747 else if (Rm != 0xF) { 3748 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3749 return MCDisassembler::Fail; 3750 } 3751 3752 return S; 3753 } 3754 3755 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn, 3756 uint64_t Address, 3757 const MCDisassembler *Decoder) { 3758 DecodeStatus S = MCDisassembler::Success; 3759 3760 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3761 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3762 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3763 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3764 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3765 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3766 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3767 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3768 3769 if (Q) { 3770 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3771 return MCDisassembler::Fail; 3772 } else { 3773 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3774 return MCDisassembler::Fail; 3775 } 3776 3777 Inst.addOperand(MCOperand::createImm(imm)); 3778 3779 switch (Inst.getOpcode()) { 3780 case ARM::VORRiv4i16: 3781 case ARM::VORRiv2i32: 3782 case ARM::VBICiv4i16: 3783 case ARM::VBICiv2i32: 3784 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3785 return MCDisassembler::Fail; 3786 break; 3787 case ARM::VORRiv8i16: 3788 case ARM::VORRiv4i32: 3789 case ARM::VBICiv8i16: 3790 case ARM::VBICiv4i32: 3791 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3792 return MCDisassembler::Fail; 3793 break; 3794 default: 3795 break; 3796 } 3797 3798 return S; 3799 } 3800 3801 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, 3802 uint64_t Address, 3803 const MCDisassembler *Decoder) { 3804 DecodeStatus S = MCDisassembler::Success; 3805 3806 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 3807 fieldFromInstruction(Insn, 13, 3)); 3808 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 3809 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3810 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3811 imm |= fieldFromInstruction(Insn, 28, 1) << 7; 3812 imm |= cmode << 8; 3813 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3814 3815 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32) 3816 return MCDisassembler::Fail; 3817 3818 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3819 return MCDisassembler::Fail; 3820 3821 Inst.addOperand(MCOperand::createImm(imm)); 3822 3823 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 3824 Inst.addOperand(MCOperand::createReg(0)); 3825 Inst.addOperand(MCOperand::createImm(0)); 3826 3827 return S; 3828 } 3829 3830 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 3831 uint64_t Address, 3832 const MCDisassembler *Decoder) { 3833 DecodeStatus S = MCDisassembler::Success; 3834 3835 unsigned Qd = fieldFromInstruction(Insn, 13, 3); 3836 Qd |= fieldFromInstruction(Insn, 22, 1) << 3; 3837 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3838 return MCDisassembler::Fail; 3839 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3840 3841 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 3842 Qn |= fieldFromInstruction(Insn, 7, 1) << 3; 3843 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 3844 return MCDisassembler::Fail; 3845 unsigned Qm = fieldFromInstruction(Insn, 1, 3); 3846 Qm |= fieldFromInstruction(Insn, 5, 1) << 3; 3847 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 3848 return MCDisassembler::Fail; 3849 if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR 3850 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3851 Inst.addOperand(MCOperand::createImm(Qd)); 3852 3853 return S; 3854 } 3855 3856 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3857 uint64_t Address, 3858 const MCDisassembler *Decoder) { 3859 DecodeStatus S = MCDisassembler::Success; 3860 3861 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3862 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3863 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3864 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3865 unsigned size = fieldFromInstruction(Insn, 18, 2); 3866 3867 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3868 return MCDisassembler::Fail; 3869 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3870 return MCDisassembler::Fail; 3871 Inst.addOperand(MCOperand::createImm(8 << size)); 3872 3873 return S; 3874 } 3875 3876 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3877 uint64_t Address, 3878 const MCDisassembler *Decoder) { 3879 Inst.addOperand(MCOperand::createImm(8 - Val)); 3880 return MCDisassembler::Success; 3881 } 3882 3883 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3884 uint64_t Address, 3885 const MCDisassembler *Decoder) { 3886 Inst.addOperand(MCOperand::createImm(16 - Val)); 3887 return MCDisassembler::Success; 3888 } 3889 3890 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3891 uint64_t Address, 3892 const MCDisassembler *Decoder) { 3893 Inst.addOperand(MCOperand::createImm(32 - Val)); 3894 return MCDisassembler::Success; 3895 } 3896 3897 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3898 uint64_t Address, 3899 const MCDisassembler *Decoder) { 3900 Inst.addOperand(MCOperand::createImm(64 - Val)); 3901 return MCDisassembler::Success; 3902 } 3903 3904 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3905 uint64_t Address, 3906 const MCDisassembler *Decoder) { 3907 DecodeStatus S = MCDisassembler::Success; 3908 3909 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3910 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3911 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3912 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3913 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3914 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3915 unsigned op = fieldFromInstruction(Insn, 6, 1); 3916 3917 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3918 return MCDisassembler::Fail; 3919 if (op) { 3920 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3921 return MCDisassembler::Fail; // Writeback 3922 } 3923 3924 switch (Inst.getOpcode()) { 3925 case ARM::VTBL2: 3926 case ARM::VTBX2: 3927 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3928 return MCDisassembler::Fail; 3929 break; 3930 default: 3931 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3932 return MCDisassembler::Fail; 3933 } 3934 3935 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3936 return MCDisassembler::Fail; 3937 3938 return S; 3939 } 3940 3941 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3942 uint64_t Address, 3943 const MCDisassembler *Decoder) { 3944 DecodeStatus S = MCDisassembler::Success; 3945 3946 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3947 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3948 3949 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3950 return MCDisassembler::Fail; 3951 3952 switch(Inst.getOpcode()) { 3953 default: 3954 return MCDisassembler::Fail; 3955 case ARM::tADR: 3956 break; // tADR does not explicitly represent the PC as an operand. 3957 case ARM::tADDrSPi: 3958 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3959 break; 3960 } 3961 3962 Inst.addOperand(MCOperand::createImm(imm)); 3963 return S; 3964 } 3965 3966 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3967 uint64_t Address, 3968 const MCDisassembler *Decoder) { 3969 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3970 true, 2, Inst, Decoder)) 3971 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3972 return MCDisassembler::Success; 3973 } 3974 3975 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3976 uint64_t Address, 3977 const MCDisassembler *Decoder) { 3978 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3979 true, 4, Inst, Decoder)) 3980 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3981 return MCDisassembler::Success; 3982 } 3983 3984 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3985 uint64_t Address, 3986 const MCDisassembler *Decoder) { 3987 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3988 true, 2, Inst, Decoder)) 3989 Inst.addOperand(MCOperand::createImm(Val << 1)); 3990 return MCDisassembler::Success; 3991 } 3992 3993 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3994 uint64_t Address, 3995 const MCDisassembler *Decoder) { 3996 DecodeStatus S = MCDisassembler::Success; 3997 3998 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3999 unsigned Rm = fieldFromInstruction(Val, 3, 3); 4000 4001 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 4002 return MCDisassembler::Fail; 4003 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 4004 return MCDisassembler::Fail; 4005 4006 return S; 4007 } 4008 4009 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 4010 uint64_t Address, 4011 const MCDisassembler *Decoder) { 4012 DecodeStatus S = MCDisassembler::Success; 4013 4014 unsigned Rn = fieldFromInstruction(Val, 0, 3); 4015 unsigned imm = fieldFromInstruction(Val, 3, 5); 4016 4017 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 4018 return MCDisassembler::Fail; 4019 Inst.addOperand(MCOperand::createImm(imm)); 4020 4021 return S; 4022 } 4023 4024 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 4025 uint64_t Address, 4026 const MCDisassembler *Decoder) { 4027 unsigned imm = Val << 2; 4028 4029 Inst.addOperand(MCOperand::createImm(imm)); 4030 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 4031 4032 return MCDisassembler::Success; 4033 } 4034 4035 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 4036 uint64_t Address, 4037 const MCDisassembler *Decoder) { 4038 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4039 Inst.addOperand(MCOperand::createImm(Val)); 4040 4041 return MCDisassembler::Success; 4042 } 4043 4044 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 4045 uint64_t Address, 4046 const MCDisassembler *Decoder) { 4047 DecodeStatus S = MCDisassembler::Success; 4048 4049 unsigned Rn = fieldFromInstruction(Val, 6, 4); 4050 unsigned Rm = fieldFromInstruction(Val, 2, 4); 4051 unsigned imm = fieldFromInstruction(Val, 0, 2); 4052 4053 // Thumb stores cannot use PC as dest register. 4054 switch (Inst.getOpcode()) { 4055 case ARM::t2STRHs: 4056 case ARM::t2STRBs: 4057 case ARM::t2STRs: 4058 if (Rn == 15) 4059 return MCDisassembler::Fail; 4060 break; 4061 default: 4062 break; 4063 } 4064 4065 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4066 return MCDisassembler::Fail; 4067 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4068 return MCDisassembler::Fail; 4069 Inst.addOperand(MCOperand::createImm(imm)); 4070 4071 return S; 4072 } 4073 4074 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 4075 uint64_t Address, 4076 const MCDisassembler *Decoder) { 4077 DecodeStatus S = MCDisassembler::Success; 4078 4079 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4080 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4081 4082 const FeatureBitset &featureBits = 4083 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4084 4085 bool hasMP = featureBits[ARM::FeatureMP]; 4086 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4087 4088 if (Rn == 15) { 4089 switch (Inst.getOpcode()) { 4090 case ARM::t2LDRBs: 4091 Inst.setOpcode(ARM::t2LDRBpci); 4092 break; 4093 case ARM::t2LDRHs: 4094 Inst.setOpcode(ARM::t2LDRHpci); 4095 break; 4096 case ARM::t2LDRSHs: 4097 Inst.setOpcode(ARM::t2LDRSHpci); 4098 break; 4099 case ARM::t2LDRSBs: 4100 Inst.setOpcode(ARM::t2LDRSBpci); 4101 break; 4102 case ARM::t2LDRs: 4103 Inst.setOpcode(ARM::t2LDRpci); 4104 break; 4105 case ARM::t2PLDs: 4106 Inst.setOpcode(ARM::t2PLDpci); 4107 break; 4108 case ARM::t2PLIs: 4109 Inst.setOpcode(ARM::t2PLIpci); 4110 break; 4111 default: 4112 return MCDisassembler::Fail; 4113 } 4114 4115 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4116 } 4117 4118 if (Rt == 15) { 4119 switch (Inst.getOpcode()) { 4120 case ARM::t2LDRSHs: 4121 return MCDisassembler::Fail; 4122 case ARM::t2LDRHs: 4123 Inst.setOpcode(ARM::t2PLDWs); 4124 break; 4125 case ARM::t2LDRSBs: 4126 Inst.setOpcode(ARM::t2PLIs); 4127 break; 4128 default: 4129 break; 4130 } 4131 } 4132 4133 switch (Inst.getOpcode()) { 4134 case ARM::t2PLDs: 4135 break; 4136 case ARM::t2PLIs: 4137 if (!hasV7Ops) 4138 return MCDisassembler::Fail; 4139 break; 4140 case ARM::t2PLDWs: 4141 if (!hasV7Ops || !hasMP) 4142 return MCDisassembler::Fail; 4143 break; 4144 default: 4145 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4146 return MCDisassembler::Fail; 4147 } 4148 4149 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 4150 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 4151 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 4152 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 4153 return MCDisassembler::Fail; 4154 4155 return S; 4156 } 4157 4158 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 4159 uint64_t Address, 4160 const MCDisassembler *Decoder) { 4161 DecodeStatus S = MCDisassembler::Success; 4162 4163 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4164 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4165 unsigned U = fieldFromInstruction(Insn, 9, 1); 4166 unsigned imm = fieldFromInstruction(Insn, 0, 8); 4167 imm |= (U << 8); 4168 imm |= (Rn << 9); 4169 unsigned add = fieldFromInstruction(Insn, 9, 1); 4170 4171 const FeatureBitset &featureBits = 4172 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4173 4174 bool hasMP = featureBits[ARM::FeatureMP]; 4175 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4176 4177 if (Rn == 15) { 4178 switch (Inst.getOpcode()) { 4179 case ARM::t2LDRi8: 4180 Inst.setOpcode(ARM::t2LDRpci); 4181 break; 4182 case ARM::t2LDRBi8: 4183 Inst.setOpcode(ARM::t2LDRBpci); 4184 break; 4185 case ARM::t2LDRSBi8: 4186 Inst.setOpcode(ARM::t2LDRSBpci); 4187 break; 4188 case ARM::t2LDRHi8: 4189 Inst.setOpcode(ARM::t2LDRHpci); 4190 break; 4191 case ARM::t2LDRSHi8: 4192 Inst.setOpcode(ARM::t2LDRSHpci); 4193 break; 4194 case ARM::t2PLDi8: 4195 Inst.setOpcode(ARM::t2PLDpci); 4196 break; 4197 case ARM::t2PLIi8: 4198 Inst.setOpcode(ARM::t2PLIpci); 4199 break; 4200 default: 4201 return MCDisassembler::Fail; 4202 } 4203 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4204 } 4205 4206 if (Rt == 15) { 4207 switch (Inst.getOpcode()) { 4208 case ARM::t2LDRSHi8: 4209 return MCDisassembler::Fail; 4210 case ARM::t2LDRHi8: 4211 if (!add) 4212 Inst.setOpcode(ARM::t2PLDWi8); 4213 break; 4214 case ARM::t2LDRSBi8: 4215 Inst.setOpcode(ARM::t2PLIi8); 4216 break; 4217 default: 4218 break; 4219 } 4220 } 4221 4222 switch (Inst.getOpcode()) { 4223 case ARM::t2PLDi8: 4224 break; 4225 case ARM::t2PLIi8: 4226 if (!hasV7Ops) 4227 return MCDisassembler::Fail; 4228 break; 4229 case ARM::t2PLDWi8: 4230 if (!hasV7Ops || !hasMP) 4231 return MCDisassembler::Fail; 4232 break; 4233 default: 4234 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4235 return MCDisassembler::Fail; 4236 } 4237 4238 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 4239 return MCDisassembler::Fail; 4240 return S; 4241 } 4242 4243 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 4244 uint64_t Address, 4245 const MCDisassembler *Decoder) { 4246 DecodeStatus S = MCDisassembler::Success; 4247 4248 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4249 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4250 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4251 imm |= (Rn << 13); 4252 4253 const FeatureBitset &featureBits = 4254 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4255 4256 bool hasMP = featureBits[ARM::FeatureMP]; 4257 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4258 4259 if (Rn == 15) { 4260 switch (Inst.getOpcode()) { 4261 case ARM::t2LDRi12: 4262 Inst.setOpcode(ARM::t2LDRpci); 4263 break; 4264 case ARM::t2LDRHi12: 4265 Inst.setOpcode(ARM::t2LDRHpci); 4266 break; 4267 case ARM::t2LDRSHi12: 4268 Inst.setOpcode(ARM::t2LDRSHpci); 4269 break; 4270 case ARM::t2LDRBi12: 4271 Inst.setOpcode(ARM::t2LDRBpci); 4272 break; 4273 case ARM::t2LDRSBi12: 4274 Inst.setOpcode(ARM::t2LDRSBpci); 4275 break; 4276 case ARM::t2PLDi12: 4277 Inst.setOpcode(ARM::t2PLDpci); 4278 break; 4279 case ARM::t2PLIi12: 4280 Inst.setOpcode(ARM::t2PLIpci); 4281 break; 4282 default: 4283 return MCDisassembler::Fail; 4284 } 4285 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4286 } 4287 4288 if (Rt == 15) { 4289 switch (Inst.getOpcode()) { 4290 case ARM::t2LDRSHi12: 4291 return MCDisassembler::Fail; 4292 case ARM::t2LDRHi12: 4293 Inst.setOpcode(ARM::t2PLDWi12); 4294 break; 4295 case ARM::t2LDRSBi12: 4296 Inst.setOpcode(ARM::t2PLIi12); 4297 break; 4298 default: 4299 break; 4300 } 4301 } 4302 4303 switch (Inst.getOpcode()) { 4304 case ARM::t2PLDi12: 4305 break; 4306 case ARM::t2PLIi12: 4307 if (!hasV7Ops) 4308 return MCDisassembler::Fail; 4309 break; 4310 case ARM::t2PLDWi12: 4311 if (!hasV7Ops || !hasMP) 4312 return MCDisassembler::Fail; 4313 break; 4314 default: 4315 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4316 return MCDisassembler::Fail; 4317 } 4318 4319 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 4320 return MCDisassembler::Fail; 4321 return S; 4322 } 4323 4324 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, 4325 const MCDisassembler *Decoder) { 4326 DecodeStatus S = MCDisassembler::Success; 4327 4328 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4329 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4330 unsigned imm = fieldFromInstruction(Insn, 0, 8); 4331 imm |= (Rn << 9); 4332 4333 if (Rn == 15) { 4334 switch (Inst.getOpcode()) { 4335 case ARM::t2LDRT: 4336 Inst.setOpcode(ARM::t2LDRpci); 4337 break; 4338 case ARM::t2LDRBT: 4339 Inst.setOpcode(ARM::t2LDRBpci); 4340 break; 4341 case ARM::t2LDRHT: 4342 Inst.setOpcode(ARM::t2LDRHpci); 4343 break; 4344 case ARM::t2LDRSBT: 4345 Inst.setOpcode(ARM::t2LDRSBpci); 4346 break; 4347 case ARM::t2LDRSHT: 4348 Inst.setOpcode(ARM::t2LDRSHpci); 4349 break; 4350 default: 4351 return MCDisassembler::Fail; 4352 } 4353 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4354 } 4355 4356 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4357 return MCDisassembler::Fail; 4358 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 4359 return MCDisassembler::Fail; 4360 return S; 4361 } 4362 4363 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 4364 uint64_t Address, 4365 const MCDisassembler *Decoder) { 4366 DecodeStatus S = MCDisassembler::Success; 4367 4368 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4369 unsigned U = fieldFromInstruction(Insn, 23, 1); 4370 int imm = fieldFromInstruction(Insn, 0, 12); 4371 4372 const FeatureBitset &featureBits = 4373 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4374 4375 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4376 4377 if (Rt == 15) { 4378 switch (Inst.getOpcode()) { 4379 case ARM::t2LDRBpci: 4380 case ARM::t2LDRHpci: 4381 Inst.setOpcode(ARM::t2PLDpci); 4382 break; 4383 case ARM::t2LDRSBpci: 4384 Inst.setOpcode(ARM::t2PLIpci); 4385 break; 4386 case ARM::t2LDRSHpci: 4387 return MCDisassembler::Fail; 4388 default: 4389 break; 4390 } 4391 } 4392 4393 switch(Inst.getOpcode()) { 4394 case ARM::t2PLDpci: 4395 break; 4396 case ARM::t2PLIpci: 4397 if (!hasV7Ops) 4398 return MCDisassembler::Fail; 4399 break; 4400 default: 4401 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4402 return MCDisassembler::Fail; 4403 } 4404 4405 if (!U) { 4406 // Special case for #-0. 4407 if (imm == 0) 4408 imm = INT32_MIN; 4409 else 4410 imm = -imm; 4411 } 4412 Inst.addOperand(MCOperand::createImm(imm)); 4413 4414 return S; 4415 } 4416 4417 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, 4418 const MCDisassembler *Decoder) { 4419 if (Val == 0) 4420 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4421 else { 4422 int imm = Val & 0xFF; 4423 4424 if (!(Val & 0x100)) imm *= -1; 4425 Inst.addOperand(MCOperand::createImm(imm * 4)); 4426 } 4427 4428 return MCDisassembler::Success; 4429 } 4430 4431 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 4432 const MCDisassembler *Decoder) { 4433 if (Val == 0) 4434 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4435 else { 4436 int imm = Val & 0x7F; 4437 4438 if (!(Val & 0x80)) 4439 imm *= -1; 4440 Inst.addOperand(MCOperand::createImm(imm * 4)); 4441 } 4442 4443 return MCDisassembler::Success; 4444 } 4445 4446 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 4447 uint64_t Address, 4448 const MCDisassembler *Decoder) { 4449 DecodeStatus S = MCDisassembler::Success; 4450 4451 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4452 unsigned imm = fieldFromInstruction(Val, 0, 9); 4453 4454 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4455 return MCDisassembler::Fail; 4456 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 4457 return MCDisassembler::Fail; 4458 4459 return S; 4460 } 4461 4462 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 4463 uint64_t Address, 4464 const MCDisassembler *Decoder) { 4465 DecodeStatus S = MCDisassembler::Success; 4466 4467 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4468 unsigned imm = fieldFromInstruction(Val, 0, 8); 4469 4470 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4471 return MCDisassembler::Fail; 4472 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) 4473 return MCDisassembler::Fail; 4474 4475 return S; 4476 } 4477 4478 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val, 4479 uint64_t Address, 4480 const MCDisassembler *Decoder) { 4481 DecodeStatus S = MCDisassembler::Success; 4482 4483 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4484 unsigned imm = fieldFromInstruction(Val, 0, 8); 4485 4486 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4487 return MCDisassembler::Fail; 4488 4489 Inst.addOperand(MCOperand::createImm(imm)); 4490 4491 return S; 4492 } 4493 4494 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, 4495 const MCDisassembler *Decoder) { 4496 int imm = Val & 0xFF; 4497 if (Val == 0) 4498 imm = INT32_MIN; 4499 else if (!(Val & 0x100)) 4500 imm *= -1; 4501 Inst.addOperand(MCOperand::createImm(imm)); 4502 4503 return MCDisassembler::Success; 4504 } 4505 4506 template <int shift> 4507 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address, 4508 const MCDisassembler *Decoder) { 4509 int imm = Val & 0x7F; 4510 if (Val == 0) 4511 imm = INT32_MIN; 4512 else if (!(Val & 0x80)) 4513 imm *= -1; 4514 if (imm != INT32_MIN) 4515 imm *= (1U << shift); 4516 Inst.addOperand(MCOperand::createImm(imm)); 4517 4518 return MCDisassembler::Success; 4519 } 4520 4521 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 4522 uint64_t Address, 4523 const MCDisassembler *Decoder) { 4524 DecodeStatus S = MCDisassembler::Success; 4525 4526 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4527 unsigned imm = fieldFromInstruction(Val, 0, 9); 4528 4529 // Thumb stores cannot use PC as dest register. 4530 switch (Inst.getOpcode()) { 4531 case ARM::t2STRT: 4532 case ARM::t2STRBT: 4533 case ARM::t2STRHT: 4534 case ARM::t2STRi8: 4535 case ARM::t2STRHi8: 4536 case ARM::t2STRBi8: 4537 if (Rn == 15) 4538 return MCDisassembler::Fail; 4539 break; 4540 default: 4541 break; 4542 } 4543 4544 // Some instructions always use an additive offset. 4545 switch (Inst.getOpcode()) { 4546 case ARM::t2LDRT: 4547 case ARM::t2LDRBT: 4548 case ARM::t2LDRHT: 4549 case ARM::t2LDRSBT: 4550 case ARM::t2LDRSHT: 4551 case ARM::t2STRT: 4552 case ARM::t2STRBT: 4553 case ARM::t2STRHT: 4554 imm |= 0x100; 4555 break; 4556 default: 4557 break; 4558 } 4559 4560 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4561 return MCDisassembler::Fail; 4562 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 4563 return MCDisassembler::Fail; 4564 4565 return S; 4566 } 4567 4568 template <int shift> 4569 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 4570 uint64_t Address, 4571 const MCDisassembler *Decoder) { 4572 DecodeStatus S = MCDisassembler::Success; 4573 4574 unsigned Rn = fieldFromInstruction(Val, 8, 3); 4575 unsigned imm = fieldFromInstruction(Val, 0, 8); 4576 4577 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 4578 return MCDisassembler::Fail; 4579 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4580 return MCDisassembler::Fail; 4581 4582 return S; 4583 } 4584 4585 template <int shift, int WriteBack> 4586 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 4587 uint64_t Address, 4588 const MCDisassembler *Decoder) { 4589 DecodeStatus S = MCDisassembler::Success; 4590 4591 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4592 unsigned imm = fieldFromInstruction(Val, 0, 8); 4593 if (WriteBack) { 4594 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4595 return MCDisassembler::Fail; 4596 } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4597 return MCDisassembler::Fail; 4598 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4599 return MCDisassembler::Fail; 4600 4601 return S; 4602 } 4603 4604 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 4605 uint64_t Address, 4606 const MCDisassembler *Decoder) { 4607 DecodeStatus S = MCDisassembler::Success; 4608 4609 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4610 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4611 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4612 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 4613 addr |= Rn << 9; 4614 unsigned load = fieldFromInstruction(Insn, 20, 1); 4615 4616 if (Rn == 15) { 4617 switch (Inst.getOpcode()) { 4618 case ARM::t2LDR_PRE: 4619 case ARM::t2LDR_POST: 4620 Inst.setOpcode(ARM::t2LDRpci); 4621 break; 4622 case ARM::t2LDRB_PRE: 4623 case ARM::t2LDRB_POST: 4624 Inst.setOpcode(ARM::t2LDRBpci); 4625 break; 4626 case ARM::t2LDRH_PRE: 4627 case ARM::t2LDRH_POST: 4628 Inst.setOpcode(ARM::t2LDRHpci); 4629 break; 4630 case ARM::t2LDRSB_PRE: 4631 case ARM::t2LDRSB_POST: 4632 if (Rt == 15) 4633 Inst.setOpcode(ARM::t2PLIpci); 4634 else 4635 Inst.setOpcode(ARM::t2LDRSBpci); 4636 break; 4637 case ARM::t2LDRSH_PRE: 4638 case ARM::t2LDRSH_POST: 4639 Inst.setOpcode(ARM::t2LDRSHpci); 4640 break; 4641 default: 4642 return MCDisassembler::Fail; 4643 } 4644 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4645 } 4646 4647 if (!load) { 4648 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4649 return MCDisassembler::Fail; 4650 } 4651 4652 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4653 return MCDisassembler::Fail; 4654 4655 if (load) { 4656 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4657 return MCDisassembler::Fail; 4658 } 4659 4660 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 4661 return MCDisassembler::Fail; 4662 4663 return S; 4664 } 4665 4666 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 4667 uint64_t Address, 4668 const MCDisassembler *Decoder) { 4669 DecodeStatus S = MCDisassembler::Success; 4670 4671 unsigned Rn = fieldFromInstruction(Val, 13, 4); 4672 unsigned imm = fieldFromInstruction(Val, 0, 12); 4673 4674 // Thumb stores cannot use PC as dest register. 4675 switch (Inst.getOpcode()) { 4676 case ARM::t2STRi12: 4677 case ARM::t2STRBi12: 4678 case ARM::t2STRHi12: 4679 if (Rn == 15) 4680 return MCDisassembler::Fail; 4681 break; 4682 default: 4683 break; 4684 } 4685 4686 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4687 return MCDisassembler::Fail; 4688 Inst.addOperand(MCOperand::createImm(imm)); 4689 4690 return S; 4691 } 4692 4693 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 4694 uint64_t Address, 4695 const MCDisassembler *Decoder) { 4696 unsigned imm = fieldFromInstruction(Insn, 0, 7); 4697 4698 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4699 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4700 Inst.addOperand(MCOperand::createImm(imm)); 4701 4702 return MCDisassembler::Success; 4703 } 4704 4705 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 4706 uint64_t Address, 4707 const MCDisassembler *Decoder) { 4708 DecodeStatus S = MCDisassembler::Success; 4709 4710 if (Inst.getOpcode() == ARM::tADDrSP) { 4711 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 4712 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 4713 4714 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4715 return MCDisassembler::Fail; 4716 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4717 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4718 return MCDisassembler::Fail; 4719 } else if (Inst.getOpcode() == ARM::tADDspr) { 4720 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 4721 4722 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4723 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4724 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4725 return MCDisassembler::Fail; 4726 } 4727 4728 return S; 4729 } 4730 4731 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 4732 uint64_t Address, 4733 const MCDisassembler *Decoder) { 4734 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 4735 unsigned flags = fieldFromInstruction(Insn, 0, 3); 4736 4737 Inst.addOperand(MCOperand::createImm(imod)); 4738 Inst.addOperand(MCOperand::createImm(flags)); 4739 4740 return MCDisassembler::Success; 4741 } 4742 4743 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 4744 uint64_t Address, 4745 const MCDisassembler *Decoder) { 4746 DecodeStatus S = MCDisassembler::Success; 4747 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4748 unsigned add = fieldFromInstruction(Insn, 4, 1); 4749 4750 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 4751 return MCDisassembler::Fail; 4752 Inst.addOperand(MCOperand::createImm(add)); 4753 4754 return S; 4755 } 4756 4757 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 4758 uint64_t Address, 4759 const MCDisassembler *Decoder) { 4760 DecodeStatus S = MCDisassembler::Success; 4761 unsigned Rn = fieldFromInstruction(Insn, 3, 4); 4762 unsigned Qm = fieldFromInstruction(Insn, 0, 3); 4763 4764 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4765 return MCDisassembler::Fail; 4766 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4767 return MCDisassembler::Fail; 4768 4769 return S; 4770 } 4771 4772 template <int shift> 4773 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 4774 uint64_t Address, 4775 const MCDisassembler *Decoder) { 4776 DecodeStatus S = MCDisassembler::Success; 4777 unsigned Qm = fieldFromInstruction(Insn, 8, 3); 4778 int imm = fieldFromInstruction(Insn, 0, 7); 4779 4780 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4781 return MCDisassembler::Fail; 4782 4783 if(!fieldFromInstruction(Insn, 7, 1)) { 4784 if (imm == 0) 4785 imm = INT32_MIN; // indicate -0 4786 else 4787 imm *= -1; 4788 } 4789 if (imm != INT32_MIN) 4790 imm *= (1U << shift); 4791 Inst.addOperand(MCOperand::createImm(imm)); 4792 4793 return S; 4794 } 4795 4796 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 4797 uint64_t Address, 4798 const MCDisassembler *Decoder) { 4799 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 4800 // Note only one trailing zero not two. Also the J1 and J2 values are from 4801 // the encoded instruction. So here change to I1 and I2 values via: 4802 // I1 = NOT(J1 EOR S); 4803 // I2 = NOT(J2 EOR S); 4804 // and build the imm32 with two trailing zeros as documented: 4805 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 4806 unsigned S = (Val >> 23) & 1; 4807 unsigned J1 = (Val >> 22) & 1; 4808 unsigned J2 = (Val >> 21) & 1; 4809 unsigned I1 = !(J1 ^ S); 4810 unsigned I2 = !(J2 ^ S); 4811 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4812 int imm32 = SignExtend32<25>(tmp << 1); 4813 4814 if (!tryAddingSymbolicOperand(Address, 4815 (Address & ~2u) + imm32 + 4, 4816 true, 4, Inst, Decoder)) 4817 Inst.addOperand(MCOperand::createImm(imm32)); 4818 return MCDisassembler::Success; 4819 } 4820 4821 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 4822 uint64_t Address, 4823 const MCDisassembler *Decoder) { 4824 if (Val == 0xA || Val == 0xB) 4825 return MCDisassembler::Fail; 4826 4827 const FeatureBitset &featureBits = 4828 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4829 4830 if (!isValidCoprocessorNumber(Val, featureBits)) 4831 return MCDisassembler::Fail; 4832 4833 Inst.addOperand(MCOperand::createImm(Val)); 4834 return MCDisassembler::Success; 4835 } 4836 4837 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 4838 uint64_t Address, 4839 const MCDisassembler *Decoder) { 4840 const FeatureBitset &FeatureBits = 4841 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4842 DecodeStatus S = MCDisassembler::Success; 4843 4844 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4845 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4846 4847 if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail; 4848 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4849 return MCDisassembler::Fail; 4850 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4851 return MCDisassembler::Fail; 4852 return S; 4853 } 4854 4855 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4856 uint64_t Address, 4857 const MCDisassembler *Decoder) { 4858 DecodeStatus S = MCDisassembler::Success; 4859 4860 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4861 if (pred == 0xE || pred == 0xF) { 4862 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4863 switch (opc) { 4864 default: 4865 return MCDisassembler::Fail; 4866 case 0xf3bf8f4: 4867 Inst.setOpcode(ARM::t2DSB); 4868 break; 4869 case 0xf3bf8f5: 4870 Inst.setOpcode(ARM::t2DMB); 4871 break; 4872 case 0xf3bf8f6: 4873 Inst.setOpcode(ARM::t2ISB); 4874 break; 4875 } 4876 4877 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4878 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4879 } 4880 4881 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4882 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4883 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4884 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4885 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4886 4887 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4888 return MCDisassembler::Fail; 4889 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4890 return MCDisassembler::Fail; 4891 4892 return S; 4893 } 4894 4895 // Decode a shifted immediate operand. These basically consist 4896 // of an 8-bit value, and a 4-bit directive that specifies either 4897 // a splat operation or a rotation. 4898 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, 4899 const MCDisassembler *Decoder) { 4900 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4901 if (ctrl == 0) { 4902 unsigned byte = fieldFromInstruction(Val, 8, 2); 4903 unsigned imm = fieldFromInstruction(Val, 0, 8); 4904 switch (byte) { 4905 case 0: 4906 Inst.addOperand(MCOperand::createImm(imm)); 4907 break; 4908 case 1: 4909 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4910 break; 4911 case 2: 4912 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4913 break; 4914 case 3: 4915 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4916 (imm << 8) | imm)); 4917 break; 4918 } 4919 } else { 4920 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4921 unsigned rot = fieldFromInstruction(Val, 7, 5); 4922 unsigned imm = llvm::rotr<uint32_t>(unrot, rot); 4923 Inst.addOperand(MCOperand::createImm(imm)); 4924 } 4925 4926 return MCDisassembler::Success; 4927 } 4928 4929 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4930 uint64_t Address, 4931 const MCDisassembler *Decoder) { 4932 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4933 true, 2, Inst, Decoder)) 4934 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4935 return MCDisassembler::Success; 4936 } 4937 4938 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4939 uint64_t Address, 4940 const MCDisassembler *Decoder) { 4941 // Val is passed in as S:J1:J2:imm10:imm11 4942 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4943 // the encoded instruction. So here change to I1 and I2 values via: 4944 // I1 = NOT(J1 EOR S); 4945 // I2 = NOT(J2 EOR S); 4946 // and build the imm32 with one trailing zero as documented: 4947 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4948 unsigned S = (Val >> 23) & 1; 4949 unsigned J1 = (Val >> 22) & 1; 4950 unsigned J2 = (Val >> 21) & 1; 4951 unsigned I1 = !(J1 ^ S); 4952 unsigned I2 = !(J2 ^ S); 4953 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4954 int imm32 = SignExtend32<25>(tmp << 1); 4955 4956 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4957 true, 4, Inst, Decoder)) 4958 Inst.addOperand(MCOperand::createImm(imm32)); 4959 return MCDisassembler::Success; 4960 } 4961 4962 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4963 uint64_t Address, 4964 const MCDisassembler *Decoder) { 4965 if (Val & ~0xf) 4966 return MCDisassembler::Fail; 4967 4968 Inst.addOperand(MCOperand::createImm(Val)); 4969 return MCDisassembler::Success; 4970 } 4971 4972 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4973 uint64_t Address, 4974 const MCDisassembler *Decoder) { 4975 if (Val & ~0xf) 4976 return MCDisassembler::Fail; 4977 4978 Inst.addOperand(MCOperand::createImm(Val)); 4979 return MCDisassembler::Success; 4980 } 4981 4982 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address, 4983 const MCDisassembler *Decoder) { 4984 DecodeStatus S = MCDisassembler::Success; 4985 const FeatureBitset &FeatureBits = 4986 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4987 4988 if (FeatureBits[ARM::FeatureMClass]) { 4989 unsigned ValLow = Val & 0xff; 4990 4991 // Validate the SYSm value first. 4992 switch (ValLow) { 4993 case 0: // apsr 4994 case 1: // iapsr 4995 case 2: // eapsr 4996 case 3: // xpsr 4997 case 5: // ipsr 4998 case 6: // epsr 4999 case 7: // iepsr 5000 case 8: // msp 5001 case 9: // psp 5002 case 16: // primask 5003 case 20: // control 5004 break; 5005 case 17: // basepri 5006 case 18: // basepri_max 5007 case 19: // faultmask 5008 if (!(FeatureBits[ARM::HasV7Ops])) 5009 // Values basepri, basepri_max and faultmask are only valid for v7m. 5010 return MCDisassembler::Fail; 5011 break; 5012 case 0x8a: // msplim_ns 5013 case 0x8b: // psplim_ns 5014 case 0x91: // basepri_ns 5015 case 0x93: // faultmask_ns 5016 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 5017 return MCDisassembler::Fail; 5018 [[fallthrough]]; 5019 case 10: // msplim 5020 case 11: // psplim 5021 case 0x88: // msp_ns 5022 case 0x89: // psp_ns 5023 case 0x90: // primask_ns 5024 case 0x94: // control_ns 5025 case 0x98: // sp_ns 5026 if (!(FeatureBits[ARM::Feature8MSecExt])) 5027 return MCDisassembler::Fail; 5028 break; 5029 case 0x20: // pac_key_p_0 5030 case 0x21: // pac_key_p_1 5031 case 0x22: // pac_key_p_2 5032 case 0x23: // pac_key_p_3 5033 case 0x24: // pac_key_u_0 5034 case 0x25: // pac_key_u_1 5035 case 0x26: // pac_key_u_2 5036 case 0x27: // pac_key_u_3 5037 case 0xa0: // pac_key_p_0_ns 5038 case 0xa1: // pac_key_p_1_ns 5039 case 0xa2: // pac_key_p_2_ns 5040 case 0xa3: // pac_key_p_3_ns 5041 case 0xa4: // pac_key_u_0_ns 5042 case 0xa5: // pac_key_u_1_ns 5043 case 0xa6: // pac_key_u_2_ns 5044 case 0xa7: // pac_key_u_3_ns 5045 if (!(FeatureBits[ARM::FeaturePACBTI])) 5046 return MCDisassembler::Fail; 5047 break; 5048 default: 5049 // Architecturally defined as unpredictable 5050 S = MCDisassembler::SoftFail; 5051 break; 5052 } 5053 5054 if (Inst.getOpcode() == ARM::t2MSR_M) { 5055 unsigned Mask = fieldFromInstruction(Val, 10, 2); 5056 if (!(FeatureBits[ARM::HasV7Ops])) { 5057 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 5058 // unpredictable. 5059 if (Mask != 2) 5060 S = MCDisassembler::SoftFail; 5061 } 5062 else { 5063 // The ARMv7-M architecture stores an additional 2-bit mask value in 5064 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 5065 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 5066 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 5067 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 5068 // only if the processor includes the DSP extension. 5069 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 5070 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 5071 S = MCDisassembler::SoftFail; 5072 } 5073 } 5074 } else { 5075 // A/R class 5076 if (Val == 0) 5077 return MCDisassembler::Fail; 5078 } 5079 Inst.addOperand(MCOperand::createImm(Val)); 5080 return S; 5081 } 5082 5083 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 5084 uint64_t Address, 5085 const MCDisassembler *Decoder) { 5086 unsigned R = fieldFromInstruction(Val, 5, 1); 5087 unsigned SysM = fieldFromInstruction(Val, 0, 5); 5088 5089 // The table of encodings for these banked registers comes from B9.2.3 of the 5090 // ARM ARM. There are patterns, but nothing regular enough to make this logic 5091 // neater. So by fiat, these values are UNPREDICTABLE: 5092 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 5093 return MCDisassembler::Fail; 5094 5095 Inst.addOperand(MCOperand::createImm(Val)); 5096 return MCDisassembler::Success; 5097 } 5098 5099 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 5100 uint64_t Address, 5101 const MCDisassembler *Decoder) { 5102 DecodeStatus S = MCDisassembler::Success; 5103 5104 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5105 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5106 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5107 5108 if (Rn == 0xF) 5109 S = MCDisassembler::SoftFail; 5110 5111 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 5112 return MCDisassembler::Fail; 5113 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5114 return MCDisassembler::Fail; 5115 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5116 return MCDisassembler::Fail; 5117 5118 return S; 5119 } 5120 5121 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 5122 uint64_t Address, 5123 const MCDisassembler *Decoder) { 5124 DecodeStatus S = MCDisassembler::Success; 5125 5126 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5127 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 5128 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5129 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5130 5131 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 5132 return MCDisassembler::Fail; 5133 5134 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 5135 S = MCDisassembler::SoftFail; 5136 5137 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 5138 return MCDisassembler::Fail; 5139 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5140 return MCDisassembler::Fail; 5141 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5142 return MCDisassembler::Fail; 5143 5144 return S; 5145 } 5146 5147 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 5148 uint64_t Address, 5149 const MCDisassembler *Decoder) { 5150 DecodeStatus S = MCDisassembler::Success; 5151 5152 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5153 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5154 unsigned imm = fieldFromInstruction(Insn, 0, 12); 5155 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 5156 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 5157 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5158 5159 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 5160 5161 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 5162 return MCDisassembler::Fail; 5163 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5164 return MCDisassembler::Fail; 5165 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 5166 return MCDisassembler::Fail; 5167 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5168 return MCDisassembler::Fail; 5169 5170 return S; 5171 } 5172 5173 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 5174 uint64_t Address, 5175 const MCDisassembler *Decoder) { 5176 DecodeStatus S = MCDisassembler::Success; 5177 5178 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5179 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5180 unsigned imm = fieldFromInstruction(Insn, 0, 12); 5181 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 5182 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 5183 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5184 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5185 5186 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 5187 if (Rm == 0xF) S = MCDisassembler::SoftFail; 5188 5189 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 5190 return MCDisassembler::Fail; 5191 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5192 return MCDisassembler::Fail; 5193 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 5194 return MCDisassembler::Fail; 5195 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5196 return MCDisassembler::Fail; 5197 5198 return S; 5199 } 5200 5201 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 5202 uint64_t Address, 5203 const MCDisassembler *Decoder) { 5204 DecodeStatus S = MCDisassembler::Success; 5205 5206 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5207 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5208 unsigned imm = fieldFromInstruction(Insn, 0, 12); 5209 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 5210 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 5211 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5212 5213 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 5214 5215 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5216 return MCDisassembler::Fail; 5217 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 5218 return MCDisassembler::Fail; 5219 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 5220 return MCDisassembler::Fail; 5221 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5222 return MCDisassembler::Fail; 5223 5224 return S; 5225 } 5226 5227 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 5228 uint64_t Address, 5229 const MCDisassembler *Decoder) { 5230 DecodeStatus S = MCDisassembler::Success; 5231 5232 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5233 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5234 unsigned imm = fieldFromInstruction(Insn, 0, 12); 5235 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 5236 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 5237 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5238 5239 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 5240 5241 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5242 return MCDisassembler::Fail; 5243 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 5244 return MCDisassembler::Fail; 5245 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 5246 return MCDisassembler::Fail; 5247 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5248 return MCDisassembler::Fail; 5249 5250 return S; 5251 } 5252 5253 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5254 const MCDisassembler *Decoder) { 5255 DecodeStatus S = MCDisassembler::Success; 5256 5257 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5258 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5259 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5260 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5261 unsigned size = fieldFromInstruction(Insn, 10, 2); 5262 5263 unsigned align = 0; 5264 unsigned index = 0; 5265 switch (size) { 5266 default: 5267 return MCDisassembler::Fail; 5268 case 0: 5269 if (fieldFromInstruction(Insn, 4, 1)) 5270 return MCDisassembler::Fail; // UNDEFINED 5271 index = fieldFromInstruction(Insn, 5, 3); 5272 break; 5273 case 1: 5274 if (fieldFromInstruction(Insn, 5, 1)) 5275 return MCDisassembler::Fail; // UNDEFINED 5276 index = fieldFromInstruction(Insn, 6, 2); 5277 if (fieldFromInstruction(Insn, 4, 1)) 5278 align = 2; 5279 break; 5280 case 2: 5281 if (fieldFromInstruction(Insn, 6, 1)) 5282 return MCDisassembler::Fail; // UNDEFINED 5283 index = fieldFromInstruction(Insn, 7, 1); 5284 5285 switch (fieldFromInstruction(Insn, 4, 2)) { 5286 case 0 : 5287 align = 0; break; 5288 case 3: 5289 align = 4; break; 5290 default: 5291 return MCDisassembler::Fail; 5292 } 5293 break; 5294 } 5295 5296 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5297 return MCDisassembler::Fail; 5298 if (Rm != 0xF) { // Writeback 5299 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5300 return MCDisassembler::Fail; 5301 } 5302 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5303 return MCDisassembler::Fail; 5304 Inst.addOperand(MCOperand::createImm(align)); 5305 if (Rm != 0xF) { 5306 if (Rm != 0xD) { 5307 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5308 return MCDisassembler::Fail; 5309 } else 5310 Inst.addOperand(MCOperand::createReg(0)); 5311 } 5312 5313 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5314 return MCDisassembler::Fail; 5315 Inst.addOperand(MCOperand::createImm(index)); 5316 5317 return S; 5318 } 5319 5320 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5321 const MCDisassembler *Decoder) { 5322 DecodeStatus S = MCDisassembler::Success; 5323 5324 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5325 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5326 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5327 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5328 unsigned size = fieldFromInstruction(Insn, 10, 2); 5329 5330 unsigned align = 0; 5331 unsigned index = 0; 5332 switch (size) { 5333 default: 5334 return MCDisassembler::Fail; 5335 case 0: 5336 if (fieldFromInstruction(Insn, 4, 1)) 5337 return MCDisassembler::Fail; // UNDEFINED 5338 index = fieldFromInstruction(Insn, 5, 3); 5339 break; 5340 case 1: 5341 if (fieldFromInstruction(Insn, 5, 1)) 5342 return MCDisassembler::Fail; // UNDEFINED 5343 index = fieldFromInstruction(Insn, 6, 2); 5344 if (fieldFromInstruction(Insn, 4, 1)) 5345 align = 2; 5346 break; 5347 case 2: 5348 if (fieldFromInstruction(Insn, 6, 1)) 5349 return MCDisassembler::Fail; // UNDEFINED 5350 index = fieldFromInstruction(Insn, 7, 1); 5351 5352 switch (fieldFromInstruction(Insn, 4, 2)) { 5353 case 0: 5354 align = 0; break; 5355 case 3: 5356 align = 4; break; 5357 default: 5358 return MCDisassembler::Fail; 5359 } 5360 break; 5361 } 5362 5363 if (Rm != 0xF) { // Writeback 5364 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5365 return MCDisassembler::Fail; 5366 } 5367 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5368 return MCDisassembler::Fail; 5369 Inst.addOperand(MCOperand::createImm(align)); 5370 if (Rm != 0xF) { 5371 if (Rm != 0xD) { 5372 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5373 return MCDisassembler::Fail; 5374 } else 5375 Inst.addOperand(MCOperand::createReg(0)); 5376 } 5377 5378 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5379 return MCDisassembler::Fail; 5380 Inst.addOperand(MCOperand::createImm(index)); 5381 5382 return S; 5383 } 5384 5385 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5386 const MCDisassembler *Decoder) { 5387 DecodeStatus S = MCDisassembler::Success; 5388 5389 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5390 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5391 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5392 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5393 unsigned size = fieldFromInstruction(Insn, 10, 2); 5394 5395 unsigned align = 0; 5396 unsigned index = 0; 5397 unsigned inc = 1; 5398 switch (size) { 5399 default: 5400 return MCDisassembler::Fail; 5401 case 0: 5402 index = fieldFromInstruction(Insn, 5, 3); 5403 if (fieldFromInstruction(Insn, 4, 1)) 5404 align = 2; 5405 break; 5406 case 1: 5407 index = fieldFromInstruction(Insn, 6, 2); 5408 if (fieldFromInstruction(Insn, 4, 1)) 5409 align = 4; 5410 if (fieldFromInstruction(Insn, 5, 1)) 5411 inc = 2; 5412 break; 5413 case 2: 5414 if (fieldFromInstruction(Insn, 5, 1)) 5415 return MCDisassembler::Fail; // UNDEFINED 5416 index = fieldFromInstruction(Insn, 7, 1); 5417 if (fieldFromInstruction(Insn, 4, 1) != 0) 5418 align = 8; 5419 if (fieldFromInstruction(Insn, 6, 1)) 5420 inc = 2; 5421 break; 5422 } 5423 5424 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5425 return MCDisassembler::Fail; 5426 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5427 return MCDisassembler::Fail; 5428 if (Rm != 0xF) { // Writeback 5429 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5430 return MCDisassembler::Fail; 5431 } 5432 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5433 return MCDisassembler::Fail; 5434 Inst.addOperand(MCOperand::createImm(align)); 5435 if (Rm != 0xF) { 5436 if (Rm != 0xD) { 5437 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5438 return MCDisassembler::Fail; 5439 } else 5440 Inst.addOperand(MCOperand::createReg(0)); 5441 } 5442 5443 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5444 return MCDisassembler::Fail; 5445 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5446 return MCDisassembler::Fail; 5447 Inst.addOperand(MCOperand::createImm(index)); 5448 5449 return S; 5450 } 5451 5452 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5453 const MCDisassembler *Decoder) { 5454 DecodeStatus S = MCDisassembler::Success; 5455 5456 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5457 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5458 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5459 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5460 unsigned size = fieldFromInstruction(Insn, 10, 2); 5461 5462 unsigned align = 0; 5463 unsigned index = 0; 5464 unsigned inc = 1; 5465 switch (size) { 5466 default: 5467 return MCDisassembler::Fail; 5468 case 0: 5469 index = fieldFromInstruction(Insn, 5, 3); 5470 if (fieldFromInstruction(Insn, 4, 1)) 5471 align = 2; 5472 break; 5473 case 1: 5474 index = fieldFromInstruction(Insn, 6, 2); 5475 if (fieldFromInstruction(Insn, 4, 1)) 5476 align = 4; 5477 if (fieldFromInstruction(Insn, 5, 1)) 5478 inc = 2; 5479 break; 5480 case 2: 5481 if (fieldFromInstruction(Insn, 5, 1)) 5482 return MCDisassembler::Fail; // UNDEFINED 5483 index = fieldFromInstruction(Insn, 7, 1); 5484 if (fieldFromInstruction(Insn, 4, 1) != 0) 5485 align = 8; 5486 if (fieldFromInstruction(Insn, 6, 1)) 5487 inc = 2; 5488 break; 5489 } 5490 5491 if (Rm != 0xF) { // Writeback 5492 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5493 return MCDisassembler::Fail; 5494 } 5495 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5496 return MCDisassembler::Fail; 5497 Inst.addOperand(MCOperand::createImm(align)); 5498 if (Rm != 0xF) { 5499 if (Rm != 0xD) { 5500 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5501 return MCDisassembler::Fail; 5502 } else 5503 Inst.addOperand(MCOperand::createReg(0)); 5504 } 5505 5506 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5507 return MCDisassembler::Fail; 5508 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5509 return MCDisassembler::Fail; 5510 Inst.addOperand(MCOperand::createImm(index)); 5511 5512 return S; 5513 } 5514 5515 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5516 const MCDisassembler *Decoder) { 5517 DecodeStatus S = MCDisassembler::Success; 5518 5519 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5520 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5521 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5522 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5523 unsigned size = fieldFromInstruction(Insn, 10, 2); 5524 5525 unsigned align = 0; 5526 unsigned index = 0; 5527 unsigned inc = 1; 5528 switch (size) { 5529 default: 5530 return MCDisassembler::Fail; 5531 case 0: 5532 if (fieldFromInstruction(Insn, 4, 1)) 5533 return MCDisassembler::Fail; // UNDEFINED 5534 index = fieldFromInstruction(Insn, 5, 3); 5535 break; 5536 case 1: 5537 if (fieldFromInstruction(Insn, 4, 1)) 5538 return MCDisassembler::Fail; // UNDEFINED 5539 index = fieldFromInstruction(Insn, 6, 2); 5540 if (fieldFromInstruction(Insn, 5, 1)) 5541 inc = 2; 5542 break; 5543 case 2: 5544 if (fieldFromInstruction(Insn, 4, 2)) 5545 return MCDisassembler::Fail; // UNDEFINED 5546 index = fieldFromInstruction(Insn, 7, 1); 5547 if (fieldFromInstruction(Insn, 6, 1)) 5548 inc = 2; 5549 break; 5550 } 5551 5552 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5553 return MCDisassembler::Fail; 5554 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5555 return MCDisassembler::Fail; 5556 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5557 return MCDisassembler::Fail; 5558 5559 if (Rm != 0xF) { // Writeback 5560 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5561 return MCDisassembler::Fail; 5562 } 5563 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5564 return MCDisassembler::Fail; 5565 Inst.addOperand(MCOperand::createImm(align)); 5566 if (Rm != 0xF) { 5567 if (Rm != 0xD) { 5568 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5569 return MCDisassembler::Fail; 5570 } else 5571 Inst.addOperand(MCOperand::createReg(0)); 5572 } 5573 5574 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5575 return MCDisassembler::Fail; 5576 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5577 return MCDisassembler::Fail; 5578 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5579 return MCDisassembler::Fail; 5580 Inst.addOperand(MCOperand::createImm(index)); 5581 5582 return S; 5583 } 5584 5585 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5586 const MCDisassembler *Decoder) { 5587 DecodeStatus S = MCDisassembler::Success; 5588 5589 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5590 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5591 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5592 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5593 unsigned size = fieldFromInstruction(Insn, 10, 2); 5594 5595 unsigned align = 0; 5596 unsigned index = 0; 5597 unsigned inc = 1; 5598 switch (size) { 5599 default: 5600 return MCDisassembler::Fail; 5601 case 0: 5602 if (fieldFromInstruction(Insn, 4, 1)) 5603 return MCDisassembler::Fail; // UNDEFINED 5604 index = fieldFromInstruction(Insn, 5, 3); 5605 break; 5606 case 1: 5607 if (fieldFromInstruction(Insn, 4, 1)) 5608 return MCDisassembler::Fail; // UNDEFINED 5609 index = fieldFromInstruction(Insn, 6, 2); 5610 if (fieldFromInstruction(Insn, 5, 1)) 5611 inc = 2; 5612 break; 5613 case 2: 5614 if (fieldFromInstruction(Insn, 4, 2)) 5615 return MCDisassembler::Fail; // UNDEFINED 5616 index = fieldFromInstruction(Insn, 7, 1); 5617 if (fieldFromInstruction(Insn, 6, 1)) 5618 inc = 2; 5619 break; 5620 } 5621 5622 if (Rm != 0xF) { // Writeback 5623 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5624 return MCDisassembler::Fail; 5625 } 5626 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5627 return MCDisassembler::Fail; 5628 Inst.addOperand(MCOperand::createImm(align)); 5629 if (Rm != 0xF) { 5630 if (Rm != 0xD) { 5631 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5632 return MCDisassembler::Fail; 5633 } else 5634 Inst.addOperand(MCOperand::createReg(0)); 5635 } 5636 5637 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5638 return MCDisassembler::Fail; 5639 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5640 return MCDisassembler::Fail; 5641 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5642 return MCDisassembler::Fail; 5643 Inst.addOperand(MCOperand::createImm(index)); 5644 5645 return S; 5646 } 5647 5648 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5649 const MCDisassembler *Decoder) { 5650 DecodeStatus S = MCDisassembler::Success; 5651 5652 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5653 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5654 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5655 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5656 unsigned size = fieldFromInstruction(Insn, 10, 2); 5657 5658 unsigned align = 0; 5659 unsigned index = 0; 5660 unsigned inc = 1; 5661 switch (size) { 5662 default: 5663 return MCDisassembler::Fail; 5664 case 0: 5665 if (fieldFromInstruction(Insn, 4, 1)) 5666 align = 4; 5667 index = fieldFromInstruction(Insn, 5, 3); 5668 break; 5669 case 1: 5670 if (fieldFromInstruction(Insn, 4, 1)) 5671 align = 8; 5672 index = fieldFromInstruction(Insn, 6, 2); 5673 if (fieldFromInstruction(Insn, 5, 1)) 5674 inc = 2; 5675 break; 5676 case 2: 5677 switch (fieldFromInstruction(Insn, 4, 2)) { 5678 case 0: 5679 align = 0; break; 5680 case 3: 5681 return MCDisassembler::Fail; 5682 default: 5683 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5684 } 5685 5686 index = fieldFromInstruction(Insn, 7, 1); 5687 if (fieldFromInstruction(Insn, 6, 1)) 5688 inc = 2; 5689 break; 5690 } 5691 5692 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5693 return MCDisassembler::Fail; 5694 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5695 return MCDisassembler::Fail; 5696 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5697 return MCDisassembler::Fail; 5698 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5699 return MCDisassembler::Fail; 5700 5701 if (Rm != 0xF) { // Writeback 5702 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5703 return MCDisassembler::Fail; 5704 } 5705 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5706 return MCDisassembler::Fail; 5707 Inst.addOperand(MCOperand::createImm(align)); 5708 if (Rm != 0xF) { 5709 if (Rm != 0xD) { 5710 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5711 return MCDisassembler::Fail; 5712 } else 5713 Inst.addOperand(MCOperand::createReg(0)); 5714 } 5715 5716 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5717 return MCDisassembler::Fail; 5718 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5719 return MCDisassembler::Fail; 5720 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5721 return MCDisassembler::Fail; 5722 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5723 return MCDisassembler::Fail; 5724 Inst.addOperand(MCOperand::createImm(index)); 5725 5726 return S; 5727 } 5728 5729 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5730 const MCDisassembler *Decoder) { 5731 DecodeStatus S = MCDisassembler::Success; 5732 5733 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5734 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5735 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5736 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5737 unsigned size = fieldFromInstruction(Insn, 10, 2); 5738 5739 unsigned align = 0; 5740 unsigned index = 0; 5741 unsigned inc = 1; 5742 switch (size) { 5743 default: 5744 return MCDisassembler::Fail; 5745 case 0: 5746 if (fieldFromInstruction(Insn, 4, 1)) 5747 align = 4; 5748 index = fieldFromInstruction(Insn, 5, 3); 5749 break; 5750 case 1: 5751 if (fieldFromInstruction(Insn, 4, 1)) 5752 align = 8; 5753 index = fieldFromInstruction(Insn, 6, 2); 5754 if (fieldFromInstruction(Insn, 5, 1)) 5755 inc = 2; 5756 break; 5757 case 2: 5758 switch (fieldFromInstruction(Insn, 4, 2)) { 5759 case 0: 5760 align = 0; break; 5761 case 3: 5762 return MCDisassembler::Fail; 5763 default: 5764 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5765 } 5766 5767 index = fieldFromInstruction(Insn, 7, 1); 5768 if (fieldFromInstruction(Insn, 6, 1)) 5769 inc = 2; 5770 break; 5771 } 5772 5773 if (Rm != 0xF) { // Writeback 5774 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5775 return MCDisassembler::Fail; 5776 } 5777 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5778 return MCDisassembler::Fail; 5779 Inst.addOperand(MCOperand::createImm(align)); 5780 if (Rm != 0xF) { 5781 if (Rm != 0xD) { 5782 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5783 return MCDisassembler::Fail; 5784 } else 5785 Inst.addOperand(MCOperand::createReg(0)); 5786 } 5787 5788 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5789 return MCDisassembler::Fail; 5790 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5791 return MCDisassembler::Fail; 5792 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5793 return MCDisassembler::Fail; 5794 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5795 return MCDisassembler::Fail; 5796 Inst.addOperand(MCOperand::createImm(index)); 5797 5798 return S; 5799 } 5800 5801 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, 5802 const MCDisassembler *Decoder) { 5803 DecodeStatus S = MCDisassembler::Success; 5804 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5805 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5806 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5807 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5808 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5809 5810 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5811 S = MCDisassembler::SoftFail; 5812 5813 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5814 return MCDisassembler::Fail; 5815 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5816 return MCDisassembler::Fail; 5817 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5818 return MCDisassembler::Fail; 5819 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5820 return MCDisassembler::Fail; 5821 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5822 return MCDisassembler::Fail; 5823 5824 return S; 5825 } 5826 5827 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, 5828 const MCDisassembler *Decoder) { 5829 DecodeStatus S = MCDisassembler::Success; 5830 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5831 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5832 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5833 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5834 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5835 5836 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5837 S = MCDisassembler::SoftFail; 5838 5839 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5840 return MCDisassembler::Fail; 5841 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5842 return MCDisassembler::Fail; 5843 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5844 return MCDisassembler::Fail; 5845 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5846 return MCDisassembler::Fail; 5847 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5848 return MCDisassembler::Fail; 5849 5850 return S; 5851 } 5852 5853 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address, 5854 const MCDisassembler *Decoder) { 5855 DecodeStatus S = MCDisassembler::Success; 5856 unsigned pred = fieldFromInstruction(Insn, 4, 4); 5857 unsigned mask = fieldFromInstruction(Insn, 0, 4); 5858 5859 if (pred == 0xF) { 5860 pred = 0xE; 5861 S = MCDisassembler::SoftFail; 5862 } 5863 5864 if (mask == 0x0) 5865 return MCDisassembler::Fail; 5866 5867 // IT masks are encoded as a sequence of replacement low-order bits 5868 // for the condition code. So if the low bit of the starting 5869 // condition code is 1, then we have to flip all the bits above the 5870 // terminating bit (which is the lowest 1 bit). 5871 if (pred & 1) { 5872 unsigned LowBit = mask & -mask; 5873 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); 5874 mask ^= BitsAboveLowBit; 5875 } 5876 5877 Inst.addOperand(MCOperand::createImm(pred)); 5878 Inst.addOperand(MCOperand::createImm(mask)); 5879 return S; 5880 } 5881 5882 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5883 uint64_t Address, 5884 const MCDisassembler *Decoder) { 5885 DecodeStatus S = MCDisassembler::Success; 5886 5887 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5888 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5889 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5890 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5891 unsigned W = fieldFromInstruction(Insn, 21, 1); 5892 unsigned U = fieldFromInstruction(Insn, 23, 1); 5893 unsigned P = fieldFromInstruction(Insn, 24, 1); 5894 bool writeback = (W == 1) | (P == 0); 5895 5896 addr |= (U << 8) | (Rn << 9); 5897 5898 if (writeback && (Rn == Rt || Rn == Rt2)) 5899 Check(S, MCDisassembler::SoftFail); 5900 if (Rt == Rt2) 5901 Check(S, MCDisassembler::SoftFail); 5902 5903 // Rt 5904 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5905 return MCDisassembler::Fail; 5906 // Rt2 5907 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5908 return MCDisassembler::Fail; 5909 // Writeback operand 5910 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5911 return MCDisassembler::Fail; 5912 // addr 5913 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5914 return MCDisassembler::Fail; 5915 5916 return S; 5917 } 5918 5919 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5920 uint64_t Address, 5921 const MCDisassembler *Decoder) { 5922 DecodeStatus S = MCDisassembler::Success; 5923 5924 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5925 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5926 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5927 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5928 unsigned W = fieldFromInstruction(Insn, 21, 1); 5929 unsigned U = fieldFromInstruction(Insn, 23, 1); 5930 unsigned P = fieldFromInstruction(Insn, 24, 1); 5931 bool writeback = (W == 1) | (P == 0); 5932 5933 addr |= (U << 8) | (Rn << 9); 5934 5935 if (writeback && (Rn == Rt || Rn == Rt2)) 5936 Check(S, MCDisassembler::SoftFail); 5937 5938 // Writeback operand 5939 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5940 return MCDisassembler::Fail; 5941 // Rt 5942 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5943 return MCDisassembler::Fail; 5944 // Rt2 5945 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5946 return MCDisassembler::Fail; 5947 // addr 5948 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5949 return MCDisassembler::Fail; 5950 5951 return S; 5952 } 5953 5954 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address, 5955 const MCDisassembler *Decoder) { 5956 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5957 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5958 if (sign1 != sign2) return MCDisassembler::Fail; 5959 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 5960 assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst"); 5961 DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder); 5962 5963 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5964 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5965 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5966 // If sign, then it is decreasing the address. 5967 if (sign1) { 5968 // Following ARMv7 Architecture Manual, when the offset 5969 // is zero, it is decoded as a subw, not as a adr.w 5970 if (!Val) { 5971 Inst.setOpcode(ARM::t2SUBri12); 5972 Inst.addOperand(MCOperand::createReg(ARM::PC)); 5973 } else 5974 Val = -Val; 5975 } 5976 Inst.addOperand(MCOperand::createImm(Val)); 5977 return S; 5978 } 5979 5980 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5981 uint64_t Address, 5982 const MCDisassembler *Decoder) { 5983 DecodeStatus S = MCDisassembler::Success; 5984 5985 // Shift of "asr #32" is not allowed in Thumb2 mode. 5986 if (Val == 0x20) S = MCDisassembler::Fail; 5987 Inst.addOperand(MCOperand::createImm(Val)); 5988 return S; 5989 } 5990 5991 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, 5992 const MCDisassembler *Decoder) { 5993 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5994 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5995 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5996 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5997 5998 if (pred == 0xF) 5999 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 6000 6001 DecodeStatus S = MCDisassembler::Success; 6002 6003 if (Rt == Rn || Rn == Rt2) 6004 S = MCDisassembler::SoftFail; 6005 6006 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 6007 return MCDisassembler::Fail; 6008 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 6009 return MCDisassembler::Fail; 6010 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6011 return MCDisassembler::Fail; 6012 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 6013 return MCDisassembler::Fail; 6014 6015 return S; 6016 } 6017 6018 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, 6019 const MCDisassembler *Decoder) { 6020 const FeatureBitset &featureBits = 6021 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6022 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 6023 6024 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 6025 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 6026 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 6027 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 6028 unsigned imm = fieldFromInstruction(Insn, 16, 6); 6029 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 6030 unsigned op = fieldFromInstruction(Insn, 5, 1); 6031 6032 DecodeStatus S = MCDisassembler::Success; 6033 6034 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 6035 if (!(imm & 0x38)) { 6036 if (cmode == 0xF) { 6037 if (op == 1) return MCDisassembler::Fail; 6038 Inst.setOpcode(ARM::VMOVv2f32); 6039 } 6040 if (hasFullFP16) { 6041 if (cmode == 0xE) { 6042 if (op == 1) { 6043 Inst.setOpcode(ARM::VMOVv1i64); 6044 } else { 6045 Inst.setOpcode(ARM::VMOVv8i8); 6046 } 6047 } 6048 if (cmode == 0xD) { 6049 if (op == 1) { 6050 Inst.setOpcode(ARM::VMVNv2i32); 6051 } else { 6052 Inst.setOpcode(ARM::VMOVv2i32); 6053 } 6054 } 6055 if (cmode == 0xC) { 6056 if (op == 1) { 6057 Inst.setOpcode(ARM::VMVNv2i32); 6058 } else { 6059 Inst.setOpcode(ARM::VMOVv2i32); 6060 } 6061 } 6062 } 6063 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 6064 } 6065 6066 if (!(imm & 0x20)) return MCDisassembler::Fail; 6067 6068 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 6069 return MCDisassembler::Fail; 6070 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 6071 return MCDisassembler::Fail; 6072 Inst.addOperand(MCOperand::createImm(64 - imm)); 6073 6074 return S; 6075 } 6076 6077 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, 6078 const MCDisassembler *Decoder) { 6079 const FeatureBitset &featureBits = 6080 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6081 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 6082 6083 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 6084 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 6085 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 6086 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 6087 unsigned imm = fieldFromInstruction(Insn, 16, 6); 6088 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 6089 unsigned op = fieldFromInstruction(Insn, 5, 1); 6090 6091 DecodeStatus S = MCDisassembler::Success; 6092 6093 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 6094 if (!(imm & 0x38)) { 6095 if (cmode == 0xF) { 6096 if (op == 1) return MCDisassembler::Fail; 6097 Inst.setOpcode(ARM::VMOVv4f32); 6098 } 6099 if (hasFullFP16) { 6100 if (cmode == 0xE) { 6101 if (op == 1) { 6102 Inst.setOpcode(ARM::VMOVv2i64); 6103 } else { 6104 Inst.setOpcode(ARM::VMOVv16i8); 6105 } 6106 } 6107 if (cmode == 0xD) { 6108 if (op == 1) { 6109 Inst.setOpcode(ARM::VMVNv4i32); 6110 } else { 6111 Inst.setOpcode(ARM::VMOVv4i32); 6112 } 6113 } 6114 if (cmode == 0xC) { 6115 if (op == 1) { 6116 Inst.setOpcode(ARM::VMVNv4i32); 6117 } else { 6118 Inst.setOpcode(ARM::VMOVv4i32); 6119 } 6120 } 6121 } 6122 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 6123 } 6124 6125 if (!(imm & 0x20)) return MCDisassembler::Fail; 6126 6127 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 6128 return MCDisassembler::Fail; 6129 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 6130 return MCDisassembler::Fail; 6131 Inst.addOperand(MCOperand::createImm(64 - imm)); 6132 6133 return S; 6134 } 6135 6136 static DecodeStatus 6137 DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Insn, 6138 uint64_t Address, 6139 const MCDisassembler *Decoder) { 6140 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 6141 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 6142 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 6143 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 6144 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 6145 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 6146 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 6147 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 6148 6149 DecodeStatus S = MCDisassembler::Success; 6150 6151 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 6152 6153 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 6154 return MCDisassembler::Fail; 6155 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 6156 return MCDisassembler::Fail; 6157 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 6158 return MCDisassembler::Fail; 6159 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 6160 return MCDisassembler::Fail; 6161 // The lane index does not have any bits in the encoding, because it can only 6162 // be 0. 6163 Inst.addOperand(MCOperand::createImm(0)); 6164 Inst.addOperand(MCOperand::createImm(rotate)); 6165 6166 return S; 6167 } 6168 6169 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, 6170 const MCDisassembler *Decoder) { 6171 DecodeStatus S = MCDisassembler::Success; 6172 6173 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6174 unsigned Rt = fieldFromInstruction(Val, 12, 4); 6175 unsigned Rm = fieldFromInstruction(Val, 0, 4); 6176 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 6177 unsigned Cond = fieldFromInstruction(Val, 28, 4); 6178 6179 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 6180 S = MCDisassembler::SoftFail; 6181 6182 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 6183 return MCDisassembler::Fail; 6184 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6185 return MCDisassembler::Fail; 6186 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 6187 return MCDisassembler::Fail; 6188 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 6189 return MCDisassembler::Fail; 6190 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 6191 return MCDisassembler::Fail; 6192 6193 return S; 6194 } 6195 6196 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 6197 uint64_t Address, 6198 const MCDisassembler *Decoder) { 6199 DecodeStatus S = MCDisassembler::Success; 6200 6201 unsigned CRm = fieldFromInstruction(Val, 0, 4); 6202 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 6203 unsigned cop = fieldFromInstruction(Val, 8, 4); 6204 unsigned Rt = fieldFromInstruction(Val, 12, 4); 6205 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 6206 6207 if ((cop & ~0x1) == 0xa) 6208 return MCDisassembler::Fail; 6209 6210 if (Rt == Rt2) 6211 S = MCDisassembler::SoftFail; 6212 6213 // We have to check if the instruction is MRRC2 6214 // or MCRR2 when constructing the operands for 6215 // Inst. Reason is because MRRC2 stores to two 6216 // registers so it's tablegen desc has two 6217 // outputs whereas MCRR doesn't store to any 6218 // registers so all of it's operands are listed 6219 // as inputs, therefore the operand order for 6220 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 6221 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 6222 6223 if (Inst.getOpcode() == ARM::MRRC2) { 6224 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 6225 return MCDisassembler::Fail; 6226 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 6227 return MCDisassembler::Fail; 6228 } 6229 Inst.addOperand(MCOperand::createImm(cop)); 6230 Inst.addOperand(MCOperand::createImm(opc1)); 6231 if (Inst.getOpcode() == ARM::MCRR2) { 6232 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 6233 return MCDisassembler::Fail; 6234 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 6235 return MCDisassembler::Fail; 6236 } 6237 Inst.addOperand(MCOperand::createImm(CRm)); 6238 6239 return S; 6240 } 6241 6242 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 6243 uint64_t Address, 6244 const MCDisassembler *Decoder) { 6245 const FeatureBitset &featureBits = 6246 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6247 DecodeStatus S = MCDisassembler::Success; 6248 6249 // Add explicit operand for the destination sysreg, for cases where 6250 // we have to model it for code generation purposes. 6251 switch (Inst.getOpcode()) { 6252 case ARM::VMSR_FPSCR_NZCVQC: 6253 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 6254 break; 6255 case ARM::VMSR_P0: 6256 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6257 break; 6258 } 6259 6260 if (Inst.getOpcode() != ARM::FMSTAT) { 6261 unsigned Rt = fieldFromInstruction(Val, 12, 4); 6262 6263 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 6264 if (Rt == 13 || Rt == 15) 6265 S = MCDisassembler::SoftFail; 6266 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 6267 } else 6268 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 6269 } 6270 6271 // Add explicit operand for the source sysreg, similarly to above. 6272 switch (Inst.getOpcode()) { 6273 case ARM::VMRS_FPSCR_NZCVQC: 6274 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 6275 break; 6276 case ARM::VMRS_P0: 6277 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6278 break; 6279 } 6280 6281 if (featureBits[ARM::ModeThumb]) { 6282 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6283 Inst.addOperand(MCOperand::createReg(0)); 6284 } else { 6285 unsigned pred = fieldFromInstruction(Val, 28, 4); 6286 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 6287 return MCDisassembler::Fail; 6288 } 6289 6290 return S; 6291 } 6292 6293 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 6294 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, 6295 uint64_t Address, 6296 const MCDisassembler *Decoder) { 6297 DecodeStatus S = MCDisassembler::Success; 6298 if (Val == 0 && !zeroPermitted) 6299 S = MCDisassembler::Fail; 6300 6301 uint64_t DecVal; 6302 if (isSigned) 6303 DecVal = SignExtend32<size + 1>(Val << 1); 6304 else 6305 DecVal = (Val << 1); 6306 6307 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst, 6308 Decoder)) 6309 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal)); 6310 return S; 6311 } 6312 6313 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, 6314 uint64_t Address, 6315 const MCDisassembler *Decoder) { 6316 6317 uint64_t LocImm = Inst.getOperand(0).getImm(); 6318 Val = LocImm + (2 << Val); 6319 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst, 6320 Decoder)) 6321 Inst.addOperand(MCOperand::createImm(Val)); 6322 return MCDisassembler::Success; 6323 } 6324 6325 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 6326 uint64_t Address, 6327 const MCDisassembler *Decoder) { 6328 if (Val >= ARMCC::AL) // also exclude the non-condition NV 6329 return MCDisassembler::Fail; 6330 Inst.addOperand(MCOperand::createImm(Val)); 6331 return MCDisassembler::Success; 6332 } 6333 6334 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 6335 const MCDisassembler *Decoder) { 6336 DecodeStatus S = MCDisassembler::Success; 6337 6338 if (Inst.getOpcode() == ARM::MVE_LCTP) 6339 return S; 6340 6341 unsigned Imm = fieldFromInstruction(Insn, 11, 1) | 6342 fieldFromInstruction(Insn, 1, 10) << 1; 6343 switch (Inst.getOpcode()) { 6344 case ARM::t2LEUpdate: 6345 case ARM::MVE_LETP: 6346 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6347 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6348 [[fallthrough]]; 6349 case ARM::t2LE: 6350 if (!Check(S, DecodeBFLabelOperand<false, true, true, 11>( 6351 Inst, Imm, Address, Decoder))) 6352 return MCDisassembler::Fail; 6353 break; 6354 case ARM::t2WLS: 6355 case ARM::MVE_WLSTP_8: 6356 case ARM::MVE_WLSTP_16: 6357 case ARM::MVE_WLSTP_32: 6358 case ARM::MVE_WLSTP_64: 6359 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6360 if (!Check(S, 6361 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), 6362 Address, Decoder)) || 6363 !Check(S, DecodeBFLabelOperand<false, false, true, 11>( 6364 Inst, Imm, Address, Decoder))) 6365 return MCDisassembler::Fail; 6366 break; 6367 case ARM::t2DLS: 6368 case ARM::MVE_DLSTP_8: 6369 case ARM::MVE_DLSTP_16: 6370 case ARM::MVE_DLSTP_32: 6371 case ARM::MVE_DLSTP_64: 6372 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6373 if (Rn == 0xF) { 6374 // Enforce all the rest of the instruction bits in LCTP, which 6375 // won't have been reliably checked based on LCTP's own tablegen 6376 // record, because we came to this decode by a roundabout route. 6377 uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE; 6378 if ((Insn & ~SBZMask) != CanonicalLCTP) 6379 return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail 6380 if (Insn != CanonicalLCTP) 6381 Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail 6382 6383 Inst.setOpcode(ARM::MVE_LCTP); 6384 } else { 6385 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6386 if (!Check(S, DecoderGPRRegisterClass(Inst, 6387 fieldFromInstruction(Insn, 16, 4), 6388 Address, Decoder))) 6389 return MCDisassembler::Fail; 6390 } 6391 break; 6392 } 6393 return S; 6394 } 6395 6396 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 6397 uint64_t Address, 6398 const MCDisassembler *Decoder) { 6399 DecodeStatus S = MCDisassembler::Success; 6400 6401 if (Val == 0) 6402 Val = 32; 6403 6404 Inst.addOperand(MCOperand::createImm(Val)); 6405 6406 return S; 6407 } 6408 6409 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 6410 uint64_t Address, 6411 const MCDisassembler *Decoder) { 6412 if ((RegNo) + 1 > 11) 6413 return MCDisassembler::Fail; 6414 6415 unsigned Register = GPRDecoderTable[(RegNo) + 1]; 6416 Inst.addOperand(MCOperand::createReg(Register)); 6417 return MCDisassembler::Success; 6418 } 6419 6420 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 6421 uint64_t Address, 6422 const MCDisassembler *Decoder) { 6423 if ((RegNo) > 14) 6424 return MCDisassembler::Fail; 6425 6426 unsigned Register = GPRDecoderTable[(RegNo)]; 6427 Inst.addOperand(MCOperand::createReg(Register)); 6428 return MCDisassembler::Success; 6429 } 6430 6431 static DecodeStatus 6432 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, 6433 uint64_t Address, 6434 const MCDisassembler *Decoder) { 6435 if (RegNo == 15) { 6436 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 6437 return MCDisassembler::Success; 6438 } 6439 6440 unsigned Register = GPRDecoderTable[RegNo]; 6441 Inst.addOperand(MCOperand::createReg(Register)); 6442 6443 if (RegNo == 13) 6444 return MCDisassembler::SoftFail; 6445 6446 return MCDisassembler::Success; 6447 } 6448 6449 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 6450 const MCDisassembler *Decoder) { 6451 DecodeStatus S = MCDisassembler::Success; 6452 6453 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6454 Inst.addOperand(MCOperand::createReg(0)); 6455 unsigned regs = fieldFromInstruction(Insn, 0, 8); 6456 if (regs == 0) { 6457 // Register list contains only VPR 6458 } else if (Inst.getOpcode() == ARM::VSCCLRMD) { 6459 unsigned reglist = regs | (fieldFromInstruction(Insn, 12, 4) << 8) | 6460 (fieldFromInstruction(Insn, 22, 1) << 12); 6461 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { 6462 return MCDisassembler::Fail; 6463 } 6464 } else { 6465 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 1) | 6466 fieldFromInstruction(Insn, 22, 1); 6467 // Registers past s31 are permitted and treated as being half of a d 6468 // register, though both halves of each d register must be present. 6469 unsigned max_reg = Vd + regs; 6470 if (max_reg > 64 || (max_reg > 32 && (max_reg & 1))) 6471 S = MCDisassembler::SoftFail; 6472 unsigned max_sreg = std::min(32u, max_reg); 6473 unsigned max_dreg = std::min(32u, max_reg / 2); 6474 for (unsigned i = Vd; i < max_sreg; ++i) 6475 if (!Check(S, DecodeSPRRegisterClass(Inst, i, Address, Decoder))) 6476 return MCDisassembler::Fail; 6477 for (unsigned i = 16; i < max_dreg; ++i) 6478 if (!Check(S, DecodeDPRRegisterClass(Inst, i, Address, Decoder))) 6479 return MCDisassembler::Fail; 6480 } 6481 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6482 6483 return S; 6484 } 6485 6486 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6487 uint64_t Address, 6488 const MCDisassembler *Decoder) { 6489 if (RegNo > 7) 6490 return MCDisassembler::Fail; 6491 6492 unsigned Register = QPRDecoderTable[RegNo]; 6493 Inst.addOperand(MCOperand::createReg(Register)); 6494 return MCDisassembler::Success; 6495 } 6496 6497 static const uint16_t QQPRDecoderTable[] = { 6498 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, 6499 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 6500 }; 6501 6502 static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6503 uint64_t Address, 6504 const MCDisassembler *Decoder) { 6505 if (RegNo > 6) 6506 return MCDisassembler::Fail; 6507 6508 unsigned Register = QQPRDecoderTable[RegNo]; 6509 Inst.addOperand(MCOperand::createReg(Register)); 6510 return MCDisassembler::Success; 6511 } 6512 6513 static const uint16_t QQQQPRDecoderTable[] = { 6514 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, 6515 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 6516 }; 6517 6518 static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6519 uint64_t Address, 6520 const MCDisassembler *Decoder) { 6521 if (RegNo > 4) 6522 return MCDisassembler::Fail; 6523 6524 unsigned Register = QQQQPRDecoderTable[RegNo]; 6525 Inst.addOperand(MCOperand::createReg(Register)); 6526 return MCDisassembler::Success; 6527 } 6528 6529 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 6530 uint64_t Address, 6531 const MCDisassembler *Decoder) { 6532 DecodeStatus S = MCDisassembler::Success; 6533 6534 // Parse VPT mask and encode it in the MCInst as an immediate with the same 6535 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and 6536 // 't' as 0 and finish with a 1. 6537 unsigned Imm = 0; 6538 // We always start with a 't'. 6539 unsigned CurBit = 0; 6540 for (int i = 3; i >= 0; --i) { 6541 // If the bit we are looking at is not the same as last one, invert the 6542 // CurBit, if it is the same leave it as is. 6543 CurBit ^= (Val >> i) & 1U; 6544 6545 // Encode the CurBit at the right place in the immediate. 6546 Imm |= (CurBit << i); 6547 6548 // If we are done, finish the encoding with a 1. 6549 if ((Val & ~(~0U << i)) == 0) { 6550 Imm |= 1U << i; 6551 break; 6552 } 6553 } 6554 6555 Inst.addOperand(MCOperand::createImm(Imm)); 6556 6557 return S; 6558 } 6559 6560 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo, 6561 uint64_t Address, 6562 const MCDisassembler *Decoder) { 6563 // The vpred_r operand type includes an MQPR register field derived 6564 // from the encoding. But we don't actually want to add an operand 6565 // to the MCInst at this stage, because AddThumbPredicate will do it 6566 // later, and will infer the register number from the TIED_TO 6567 // constraint. So this is a deliberately empty decoder method that 6568 // will inhibit the auto-generated disassembly code from adding an 6569 // operand at all. 6570 return MCDisassembler::Success; 6571 } 6572 6573 [[maybe_unused]] static DecodeStatus 6574 DecodeVpredNOperand(MCInst &Inst, unsigned RegNo, uint64_t Address, 6575 const MCDisassembler *Decoder) { 6576 // Similar to above, we want to ensure that no operands are added for the 6577 // vpred operands. (This is marked "maybe_unused" for the moment; because 6578 // DecoderEmitter currently (wrongly) omits operands with no instruction bits, 6579 // the decoder doesn't actually call it yet. That will be addressed in a 6580 // future change.) 6581 return MCDisassembler::Success; 6582 } 6583 6584 static DecodeStatus 6585 DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6586 const MCDisassembler *Decoder) { 6587 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE)); 6588 return MCDisassembler::Success; 6589 } 6590 6591 static DecodeStatus 6592 DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6593 const MCDisassembler *Decoder) { 6594 unsigned Code; 6595 switch (Val & 0x3) { 6596 case 0: 6597 Code = ARMCC::GE; 6598 break; 6599 case 1: 6600 Code = ARMCC::LT; 6601 break; 6602 case 2: 6603 Code = ARMCC::GT; 6604 break; 6605 case 3: 6606 Code = ARMCC::LE; 6607 break; 6608 } 6609 Inst.addOperand(MCOperand::createImm(Code)); 6610 return MCDisassembler::Success; 6611 } 6612 6613 static DecodeStatus 6614 DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6615 const MCDisassembler *Decoder) { 6616 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI)); 6617 return MCDisassembler::Success; 6618 } 6619 6620 static DecodeStatus 6621 DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6622 const MCDisassembler *Decoder) { 6623 unsigned Code; 6624 switch (Val) { 6625 default: 6626 return MCDisassembler::Fail; 6627 case 0: 6628 Code = ARMCC::EQ; 6629 break; 6630 case 1: 6631 Code = ARMCC::NE; 6632 break; 6633 case 4: 6634 Code = ARMCC::GE; 6635 break; 6636 case 5: 6637 Code = ARMCC::LT; 6638 break; 6639 case 6: 6640 Code = ARMCC::GT; 6641 break; 6642 case 7: 6643 Code = ARMCC::LE; 6644 break; 6645 } 6646 6647 Inst.addOperand(MCOperand::createImm(Code)); 6648 return MCDisassembler::Success; 6649 } 6650 6651 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val, 6652 uint64_t Address, 6653 const MCDisassembler *Decoder) { 6654 DecodeStatus S = MCDisassembler::Success; 6655 6656 unsigned DecodedVal = 64 - Val; 6657 6658 switch (Inst.getOpcode()) { 6659 case ARM::MVE_VCVTf16s16_fix: 6660 case ARM::MVE_VCVTs16f16_fix: 6661 case ARM::MVE_VCVTf16u16_fix: 6662 case ARM::MVE_VCVTu16f16_fix: 6663 if (DecodedVal > 16) 6664 return MCDisassembler::Fail; 6665 break; 6666 case ARM::MVE_VCVTf32s32_fix: 6667 case ARM::MVE_VCVTs32f32_fix: 6668 case ARM::MVE_VCVTf32u32_fix: 6669 case ARM::MVE_VCVTu32f32_fix: 6670 if (DecodedVal > 32) 6671 return MCDisassembler::Fail; 6672 break; 6673 } 6674 6675 Inst.addOperand(MCOperand::createImm(64 - Val)); 6676 6677 return S; 6678 } 6679 6680 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) { 6681 switch (Opcode) { 6682 case ARM::VSTR_P0_off: 6683 case ARM::VSTR_P0_pre: 6684 case ARM::VSTR_P0_post: 6685 case ARM::VLDR_P0_off: 6686 case ARM::VLDR_P0_pre: 6687 case ARM::VLDR_P0_post: 6688 return ARM::P0; 6689 case ARM::VSTR_FPSCR_NZCVQC_off: 6690 case ARM::VSTR_FPSCR_NZCVQC_pre: 6691 case ARM::VSTR_FPSCR_NZCVQC_post: 6692 case ARM::VLDR_FPSCR_NZCVQC_off: 6693 case ARM::VLDR_FPSCR_NZCVQC_pre: 6694 case ARM::VLDR_FPSCR_NZCVQC_post: 6695 return ARM::FPSCR; 6696 default: 6697 return 0; 6698 } 6699 } 6700 6701 template <bool Writeback> 6702 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, 6703 uint64_t Address, 6704 const MCDisassembler *Decoder) { 6705 switch (Inst.getOpcode()) { 6706 case ARM::VSTR_FPSCR_pre: 6707 case ARM::VSTR_FPSCR_NZCVQC_pre: 6708 case ARM::VLDR_FPSCR_pre: 6709 case ARM::VLDR_FPSCR_NZCVQC_pre: 6710 case ARM::VSTR_FPSCR_off: 6711 case ARM::VSTR_FPSCR_NZCVQC_off: 6712 case ARM::VLDR_FPSCR_off: 6713 case ARM::VLDR_FPSCR_NZCVQC_off: 6714 case ARM::VSTR_FPSCR_post: 6715 case ARM::VSTR_FPSCR_NZCVQC_post: 6716 case ARM::VLDR_FPSCR_post: 6717 case ARM::VLDR_FPSCR_NZCVQC_post: 6718 const FeatureBitset &featureBits = 6719 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6720 6721 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2]) 6722 return MCDisassembler::Fail; 6723 } 6724 6725 DecodeStatus S = MCDisassembler::Success; 6726 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode())) 6727 Inst.addOperand(MCOperand::createReg(Sysreg)); 6728 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6729 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6730 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6731 6732 if (Writeback) { 6733 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6734 return MCDisassembler::Fail; 6735 } 6736 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) 6737 return MCDisassembler::Fail; 6738 6739 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6740 Inst.addOperand(MCOperand::createReg(0)); 6741 6742 return S; 6743 } 6744 6745 static inline DecodeStatus 6746 DecodeMVE_MEM_pre(MCInst &Inst, unsigned Val, uint64_t Address, 6747 const MCDisassembler *Decoder, unsigned Rn, 6748 OperandDecoder RnDecoder, OperandDecoder AddrDecoder) { 6749 DecodeStatus S = MCDisassembler::Success; 6750 6751 unsigned Qd = fieldFromInstruction(Val, 13, 3); 6752 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6753 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6754 6755 if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder))) 6756 return MCDisassembler::Fail; 6757 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6758 return MCDisassembler::Fail; 6759 if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder))) 6760 return MCDisassembler::Fail; 6761 6762 return S; 6763 } 6764 6765 template <int shift> 6766 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 6767 uint64_t Address, 6768 const MCDisassembler *Decoder) { 6769 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6770 fieldFromInstruction(Val, 16, 3), 6771 DecodetGPRRegisterClass, 6772 DecodeTAddrModeImm7<shift>); 6773 } 6774 6775 template <int shift> 6776 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 6777 uint64_t Address, 6778 const MCDisassembler *Decoder) { 6779 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6780 fieldFromInstruction(Val, 16, 4), 6781 DecoderGPRRegisterClass, 6782 DecodeT2AddrModeImm7<shift,1>); 6783 } 6784 6785 template <int shift> 6786 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 6787 uint64_t Address, 6788 const MCDisassembler *Decoder) { 6789 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6790 fieldFromInstruction(Val, 17, 3), 6791 DecodeMQPRRegisterClass, 6792 DecodeMveAddrModeQ<shift>); 6793 } 6794 6795 template <unsigned MinLog, unsigned MaxLog> 6796 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 6797 uint64_t Address, 6798 const MCDisassembler *Decoder) { 6799 DecodeStatus S = MCDisassembler::Success; 6800 6801 if (Val < MinLog || Val > MaxLog) 6802 return MCDisassembler::Fail; 6803 6804 Inst.addOperand(MCOperand::createImm(1LL << Val)); 6805 return S; 6806 } 6807 6808 template <unsigned start> 6809 static DecodeStatus 6810 DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6811 const MCDisassembler *Decoder) { 6812 DecodeStatus S = MCDisassembler::Success; 6813 6814 Inst.addOperand(MCOperand::createImm(start + Val)); 6815 6816 return S; 6817 } 6818 6819 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 6820 uint64_t Address, 6821 const MCDisassembler *Decoder) { 6822 DecodeStatus S = MCDisassembler::Success; 6823 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6824 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6825 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6826 fieldFromInstruction(Insn, 13, 3)); 6827 unsigned index = fieldFromInstruction(Insn, 4, 1); 6828 6829 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6830 return MCDisassembler::Fail; 6831 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6832 return MCDisassembler::Fail; 6833 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6834 return MCDisassembler::Fail; 6835 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6836 return MCDisassembler::Fail; 6837 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6838 return MCDisassembler::Fail; 6839 6840 return S; 6841 } 6842 6843 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 6844 uint64_t Address, 6845 const MCDisassembler *Decoder) { 6846 DecodeStatus S = MCDisassembler::Success; 6847 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6848 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6849 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6850 fieldFromInstruction(Insn, 13, 3)); 6851 unsigned index = fieldFromInstruction(Insn, 4, 1); 6852 6853 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6854 return MCDisassembler::Fail; 6855 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6856 return MCDisassembler::Fail; 6857 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6858 return MCDisassembler::Fail; 6859 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6860 return MCDisassembler::Fail; 6861 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6862 return MCDisassembler::Fail; 6863 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6864 return MCDisassembler::Fail; 6865 6866 return S; 6867 } 6868 6869 static DecodeStatus 6870 DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address, 6871 const MCDisassembler *Decoder) { 6872 DecodeStatus S = MCDisassembler::Success; 6873 6874 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1; 6875 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1; 6876 unsigned Rm = fieldFromInstruction(Insn, 12, 4); 6877 6878 if (RdaHi == 14) { 6879 // This value of RdaHi (really indicating pc, because RdaHi has to 6880 // be an odd-numbered register, so the low bit will be set by the 6881 // decode function below) indicates that we must decode as SQRSHR 6882 // or UQRSHL, which both have a single Rda register field with all 6883 // four bits. 6884 unsigned Rda = fieldFromInstruction(Insn, 16, 4); 6885 6886 switch (Inst.getOpcode()) { 6887 case ARM::MVE_ASRLr: 6888 case ARM::MVE_SQRSHRL: 6889 Inst.setOpcode(ARM::MVE_SQRSHR); 6890 break; 6891 case ARM::MVE_LSLLr: 6892 case ARM::MVE_UQRSHLL: 6893 Inst.setOpcode(ARM::MVE_UQRSHL); 6894 break; 6895 default: 6896 llvm_unreachable("Unexpected starting opcode!"); 6897 } 6898 6899 // Rda as output parameter 6900 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6901 return MCDisassembler::Fail; 6902 6903 // Rda again as input parameter 6904 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6905 return MCDisassembler::Fail; 6906 6907 // Rm, the amount to shift by 6908 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6909 return MCDisassembler::Fail; 6910 6911 if (fieldFromInstruction (Insn, 6, 3) != 4) 6912 return MCDisassembler::SoftFail; 6913 6914 if (Rda == Rm) 6915 return MCDisassembler::SoftFail; 6916 6917 return S; 6918 } 6919 6920 // Otherwise, we decode as whichever opcode our caller has already 6921 // put into Inst. Those all look the same: 6922 6923 // RdaLo,RdaHi as output parameters 6924 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6925 return MCDisassembler::Fail; 6926 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6927 return MCDisassembler::Fail; 6928 6929 // RdaLo,RdaHi again as input parameters 6930 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6931 return MCDisassembler::Fail; 6932 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6933 return MCDisassembler::Fail; 6934 6935 // Rm, the amount to shift by 6936 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6937 return MCDisassembler::Fail; 6938 6939 if (Inst.getOpcode() == ARM::MVE_SQRSHRL || 6940 Inst.getOpcode() == ARM::MVE_UQRSHLL) { 6941 unsigned Saturate = fieldFromInstruction(Insn, 7, 1); 6942 // Saturate, the bit position for saturation 6943 Inst.addOperand(MCOperand::createImm(Saturate)); 6944 } 6945 6946 return S; 6947 } 6948 6949 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, 6950 uint64_t Address, 6951 const MCDisassembler *Decoder) { 6952 DecodeStatus S = MCDisassembler::Success; 6953 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6954 fieldFromInstruction(Insn, 13, 3)); 6955 unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) | 6956 fieldFromInstruction(Insn, 1, 3)); 6957 unsigned imm6 = fieldFromInstruction(Insn, 16, 6); 6958 6959 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6960 return MCDisassembler::Fail; 6961 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6962 return MCDisassembler::Fail; 6963 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder))) 6964 return MCDisassembler::Fail; 6965 6966 return S; 6967 } 6968 6969 template <bool scalar, OperandDecoder predicate_decoder> 6970 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, 6971 const MCDisassembler *Decoder) { 6972 DecodeStatus S = MCDisassembler::Success; 6973 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6974 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 6975 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 6976 return MCDisassembler::Fail; 6977 6978 unsigned fc; 6979 6980 if (scalar) { 6981 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6982 fieldFromInstruction(Insn, 7, 1) | 6983 fieldFromInstruction(Insn, 5, 1) << 1; 6984 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 6985 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder))) 6986 return MCDisassembler::Fail; 6987 } else { 6988 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6989 fieldFromInstruction(Insn, 7, 1) | 6990 fieldFromInstruction(Insn, 0, 1) << 1; 6991 unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 | 6992 fieldFromInstruction(Insn, 1, 3); 6993 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6994 return MCDisassembler::Fail; 6995 } 6996 6997 if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder))) 6998 return MCDisassembler::Fail; 6999 7000 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 7001 Inst.addOperand(MCOperand::createReg(0)); 7002 Inst.addOperand(MCOperand::createImm(0)); 7003 7004 return S; 7005 } 7006 7007 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, 7008 const MCDisassembler *Decoder) { 7009 DecodeStatus S = MCDisassembler::Success; 7010 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 7011 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 7012 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 7013 return MCDisassembler::Fail; 7014 return S; 7015 } 7016 7017 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, 7018 uint64_t Address, 7019 const MCDisassembler *Decoder) { 7020 DecodeStatus S = MCDisassembler::Success; 7021 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 7022 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 7023 return S; 7024 } 7025 7026 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 7027 uint64_t Address, 7028 const MCDisassembler *Decoder) { 7029 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 7030 const unsigned Rn = fieldFromInstruction(Insn, 16, 4); 7031 const unsigned Imm12 = fieldFromInstruction(Insn, 26, 1) << 11 | 7032 fieldFromInstruction(Insn, 12, 3) << 8 | 7033 fieldFromInstruction(Insn, 0, 8); 7034 const unsigned TypeT3 = fieldFromInstruction(Insn, 25, 1); 7035 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 7036 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 7037 unsigned S = fieldFromInstruction(Insn, 20, 1); 7038 if (sign1 != sign2) 7039 return MCDisassembler::Fail; 7040 7041 // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm) 7042 DecodeStatus DS = MCDisassembler::Success; 7043 if ((!Check(DS, 7044 DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst 7045 (!Check(DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder)))) 7046 return MCDisassembler::Fail; 7047 if (TypeT3) { 7048 Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12); 7049 Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm12 7050 } else { 7051 Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm); 7052 if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12 7053 return MCDisassembler::Fail; 7054 if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out 7055 return MCDisassembler::Fail; 7056 } 7057 7058 return DS; 7059 } 7060 7061 static DecodeStatus DecodeLazyLoadStoreMul(MCInst &Inst, unsigned Insn, 7062 uint64_t Address, 7063 const MCDisassembler *Decoder) { 7064 DecodeStatus S = MCDisassembler::Success; 7065 7066 const unsigned Rn = fieldFromInstruction(Insn, 16, 4); 7067 // Adding Rn, holding memory location to save/load to/from, the only argument 7068 // that is being encoded. 7069 // '$Rn' in the assembly. 7070 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 7071 return MCDisassembler::Fail; 7072 // An optional predicate, '$p' in the assembly. 7073 DecodePredicateOperand(Inst, ARMCC::AL, Address, Decoder); 7074 // An immediate that represents a floating point registers list. '$regs' in 7075 // the assembly. 7076 Inst.addOperand(MCOperand::createImm(0)); // Arbitrary value, has no effect. 7077 7078 return S; 7079 } 7080