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Revision tags: llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5 |
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d4f2b71c |
| 19-Nov-2024 |
Simon Pilgrim <llvm-dev@redking.me.uk> |
[X86] Fix position of immediate argument in AVX512 VPCMP comparisons (#116646)
The 'i' arg was being put between the 'm' and 'b' args instead of afterwards like other avx512 instructions (VCMPPS/D,
[X86] Fix position of immediate argument in AVX512 VPCMP comparisons (#116646)
The 'i' arg was being put between the 'm' and 'b' args instead of afterwards like other avx512 instructions (VCMPPS/D, VPERMILPS/D etc.).
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Revision tags: llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1 |
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b47af5d1 |
| 22-Sep-2024 |
Craig Topper <craig.topper@sifive.com> |
[MC] Replace some comparisons of MCRegister and literal 0. NFC
We can convert the MCRegister to bool instead. I think this should
allows us to remove MCRegister::operator==(int). All other compariso
[MC] Replace some comparisons of MCRegister and literal 0. NFC
We can convert the MCRegister to bool instead. I think this should
allows us to remove MCRegister::operator==(int). All other comparisons
in tree are unsigned.
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Revision tags: llvmorg-19.1.0 |
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a20a9738 |
| 14-Sep-2024 |
Craig Topper <craig.topper@sifive.com> |
[X86] Use MCRegister in more places. NFC (#108682)
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Revision tags: llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init |
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a9183b88 |
| 09-Jul-2024 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86][MC] Fix encoding bug for CCMP introduced in #85175
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Revision tags: llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2 |
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| #
92d7aca4 |
| 09-Mar-2024 |
Simon Pilgrim <llvm-dev@redking.me.uk> |
[X86] Add missing immediate qualifier to the (V)CMPSS/D instructions (#84496)
Matches (V)CMPPS/D and makes it easier to algorithmically recreate the instruction name in various analysis scripts I'm
[X86] Add missing immediate qualifier to the (V)CMPSS/D instructions (#84496)
Matches (V)CMPPS/D and makes it easier to algorithmically recreate the instruction name in various analysis scripts I'm working on
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Revision tags: llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2 |
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| #
5910e34a |
| 30-Jan-2024 |
XinWang10 <108658776+XinWang10@users.noreply.github.com> |
[X86][MC] Support encoding optimization & assembler relaxation about immediate operands for APX instructions (#78545)
Encoding optimization:
```
mi/mi32 -> mi8
ri/ri32 -> ri8
```
if the immedi
[X86][MC] Support encoding optimization & assembler relaxation about immediate operands for APX instructions (#78545)
Encoding optimization:
```
mi/mi32 -> mi8
ri/ri32 -> ri8
```
if the immediate operand is 8-bit wide.
Assembler relaxation:
```
mi8 -> mi/mi32
ri8 -> ri/ri32
```
If the immediate operand is a symbol expression and it's value is
unknown.
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Revision tags: llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5 |
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| #
3f1e9468 |
| 20-May-2023 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86][MC][bolt] Share code between encoding optimization and assembler relaxation, NFCI
PUSH[16|32|64]i[8|32] are not arithmetic instructions, so I renamed the
functions.
Reviewed By: Amir
Differe
[X86][MC][bolt] Share code between encoding optimization and assembler relaxation, NFCI
PUSH[16|32|64]i[8|32] are not arithmetic instructions, so I renamed the
functions.
Reviewed By: Amir
Differential Revision: https://reviews.llvm.org/D151028
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| #
f6038096 |
| 20-May-2023 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86] Move encoding optimization for PUSH32i, PUSH64i to MC lowering, NFCI
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| #
0d9b36ce |
| 20-May-2023 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86] Remove patterns for IMUL with immediate 8 and optimize during MC lowering, NFCI
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| #
c81a121f |
| 19-May-2023 |
Shengchen Kan <shengchen.kan@intel.com> |
Revert "Revert "[X86] Remove patterns for ADC/SBB with immediate 8 and optimize during MC lowering, NFCI""
This reverts commit cb16b33a03aff70b2499c3452f2f817f3f92d20d.
In fact, the test https://bu
Revert "Revert "[X86] Remove patterns for ADC/SBB with immediate 8 and optimize during MC lowering, NFCI""
This reverts commit cb16b33a03aff70b2499c3452f2f817f3f92d20d.
In fact, the test https://bugs.chromium.org/p/chromium/issues/detail?id=1446973#c2
already passed after 5586bc539acb26cb94e461438de01a5080513401
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| #
cb16b33a |
| 19-May-2023 |
Hans Wennborg <hans@chromium.org> |
Revert "[X86] Remove patterns for ADC/SBB with immediate 8 and optimize during MC lowering, NFCI"
This caused compiler assertions, see comment on
https://reviews.llvm.org/D150107.
This also reverts
Revert "[X86] Remove patterns for ADC/SBB with immediate 8 and optimize during MC lowering, NFCI"
This caused compiler assertions, see comment on
https://reviews.llvm.org/D150107.
This also reverts the dependent follow-up change:
> [X86] Remove patterns for ADD/AND/OR/SUB/XOR/CMP with immediate 8 and optimize during MC lowering, NFCI
>
> This is follow-up of D150107.
>
> In addition, the function `X86::optimizeToFixedRegisterOrShortImmediateForm` can be
> shared with project bolt and eliminates the code in X86InstrRelaxTables.cpp.
>
> Differential Revision: https://reviews.llvm.org/D150949
This reverts commit 2ef8ae134828876ab3ebda4a81bb2df7b095d030 and
5586bc539acb26cb94e461438de01a5080513401.
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| #
5586bc53 |
| 19-May-2023 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86] Remove patterns for ADD/AND/OR/SUB/XOR/CMP with immediate 8 and optimize during MC lowering, NFCI
This is follow-up of D150107.
In addition, the function `X86::optimizeToFixedRegisterOrShortI
[X86] Remove patterns for ADD/AND/OR/SUB/XOR/CMP with immediate 8 and optimize during MC lowering, NFCI
This is follow-up of D150107.
In addition, the function `X86::optimizeToFixedRegisterOrShortImmediateForm` can be
shared with project bolt and eliminates the code in X86InstrRelaxTables.cpp.
Differential Revision: https://reviews.llvm.org/D150949
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| #
2ef8ae13 |
| 19-May-2023 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86] Remove patterns for ADC/SBB with immediate 8 and optimize during MC lowering, NFCI
This is follow-up of D150107.
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| #
b87bb4e0 |
| 18-May-2023 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86][MC] Move the code about fixed register encoding optimization to X86EncodingOptimization.cpp, NFCI
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| #
025c1587 |
| 18-May-2023 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86][MC] Move encoding optimization for VCMP to X86::optimizeInstFromVEX3ToVEX2, NFCI
This is a follow-up for c13ed1cc7578
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| #
87671db0 |
| 18-May-2023 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86][MC] Simplify code for X86::optimizeInstFromVEX3ToVEX2
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| #
15100a2d |
| 18-May-2023 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86][MC] Move the code about MOV encoding optimization to X86EncodingOptimization.cpp, NFCI
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| #
4a92d69a |
| 18-May-2023 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86][MC] Move the code about INC/DEC encoding optimization to X86EncodingOptimization.cpp, NFCI
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| #
d9610b4a |
| 17-May-2023 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86][MC] Move the code about MOVSX encoding optimization to X86EncodingOptimization.cpp, NFCI
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| #
2fb7506f |
| 17-May-2023 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86][MC] Move the code about VPCMP encoding optimization to X86EncodingOptimization.cpp, NFCI
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Revision tags: llvmorg-16.0.4 |
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| #
db39d479 |
| 07-May-2023 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86][AsmParser] Reapply "Refactor code and optimize more instructions from VEX3 to VEX2"
This was reverted in d4994d0e7922 b/c a bolt test failed after the
encoding changed.
Relanded the patch wit
[X86][AsmParser] Reapply "Refactor code and optimize more instructions from VEX3 to VEX2"
This was reverted in d4994d0e7922 b/c a bolt test failed after the
encoding changed.
Relanded the patch with the updated test.
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| #
c13ed1cc |
| 07-May-2023 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86][AsmParser] Refactor code and optimize more instructions from VEX3 to VEX2
1. Share code `optimizeInstFromVEX3ToVEX2` with MCInstLower
2. Move the code of optimization for shift/rotate to a sep
[X86][AsmParser] Refactor code and optimize more instructions from VEX3 to VEX2
1. Share code `optimizeInstFromVEX3ToVEX2` with MCInstLower
2. Move the code of optimization for shift/rotate to a separate file
3. Since the function is shared, a side effect is that more encoding
optimizations are done on the Asmparser side. Considering we already
use reverse-encoding for optimization in AsmParser before this patch,
I believe the change is positive and expected.
This is a reland of D150068 with the fix D150440.
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| #
8d657c46 |
| 07-May-2023 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86][AsmParser] Refactor code in AsmParser
1. Share code `optimizeInstFromVEX3ToVEX2` with MCInstLower
2. Move the code of optimization for shift/rotate to a separate file
Reviewed By: craig.toppe
[X86][AsmParser] Refactor code in AsmParser
1. Share code `optimizeInstFromVEX3ToVEX2` with MCInstLower
2. Move the code of optimization for shift/rotate to a separate file
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D150068
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