| /llvm-project/llvm/lib/Support/ |
| H A D | FloatingPointMode.cpp | 17 NewMask |= fcPosInf; in fneg()
30 if (Mask & fcPosInf) in fneg()
43 if (Mask & fcPosInf) in inverse_fabs()
74 {fcPosInf, "pinf"},
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| H A D | APFloat.cpp | 5458 return isNegative() ? fcNegInf : fcPosInf;
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| /llvm-project/llvm/include/llvm/ADT/ |
| H A D | FloatingPointMode.h | 251 fcPosInf = 0x0200, enumerator
254 fcInf = fcPosInf | fcNegInf,
261 fcPositive = fcPosFinite | fcPosInf,
267 LLVM_DECLARE_ENUM_AS_BITMASK(FPClassTest, /* LargestValue */ fcPosInf);
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| /llvm-project/llvm/include/llvm/Analysis/ |
| H A D | ValueTracking.h | 299 return isKnownNever(fcPosInf); in isKnownNeverNegInfinity()
353 fcPosSubnormal | fcPosNormal | fcPosInf;
407 KnownFPClasses |= fcPosInf; in fabs()
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| /llvm-project/llvm/lib/CodeGen/ |
| H A D | CodeGenCommonISel.cpp | 186 case fcPosInf: in invertFPClassTestIfSimpler()
205 case fcPosInf | fcNan: in invertFPClassTestIfSimpler()
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| /llvm-project/llvm/lib/Analysis/ |
| H A D | ValueTracking.cpp | 4618 return exactClass(Src, fcPosSubnormal | fcPosNormal | fcPosInf); in fcmpImpliesClass()
4620 return exactClass(Src, fcPosSubnormal | fcPosNormal | fcPosInf | fcNan); in fcmpImpliesClass()
4651 // fcmp oeq x, +inf -> is_fpclass x, fcPosInf in computeKnownFPClassFromCond()
4656 // fcmp une x, +inf -> is_fpclass x, ~fcPosInf in computeKnownFPClassFromCond()
4665 Mask = fcPosInf; in computeKnownFPClassFromCond()
4679 // fcmp ueq x, +inf -> is_fpclass x, fcPosInf|fcNan in computeKnownFPClassFromContext()
4688 Mask = ~fcPosInf & ~fcNan; in computeKnownFPClassFromContext()
4727 // fcmp oge x, +inf -> fcPosInf
4729 // fcmp ult x, +inf -> ~fcPosInf
4730 Mask = fcPosInf;
[all...] |
| H A D | ConstantFolding.cpp | 3128 ((Mask & fcPosInf) && Op1V.isPosInfinity()); in ConstantFoldScalarCall3()
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| /llvm-project/llvm/unittests/Analysis/ |
| H A D | ValueTrackingTest.cpp | 1311 expectKnownFPClass(fcPosInf, false); in TEST_F()
1383 expectKnownFPClass(~fcPosInf, std::nullopt); in TEST_F()
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| /llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCalls.cpp | 919 case fcPosSubnormal | fcPosNormal | fcPosInf: in foldIntrinsicIsFPClass()
935 case fcPosNormal | fcPosInf: in foldIntrinsicIsFPClass()
1003 if ((OrderedMask == fcPosInf || OrderedMask == fcNegInf) && in foldIntrinsicIsFPClass()
1005 // is.fpclass(x, fcPosInf) -> fcmp oeq x, +inf in foldIntrinsicIsFPClass()
1007 // is.fpclass(x, fcPosInf|fcNan) -> fcmp ueq x, +inf in foldIntrinsicIsFPClass()
1018 if ((OrderedInvertedMask == fcPosInf || OrderedInvertedMask == fcNegInf) && in foldIntrinsicIsFPClass()
1020 // is.fpclass(x, ~fcPosInf) -> fcmp one x, +inf in foldIntrinsicIsFPClass()
1022 // is.fpclass(x, ~fcPosInf|fcNan) -> fcmp une x, +inf in foldIntrinsicIsFPClass()
1058 // is.fpclass(x, fcPosSubnormal | fcPosNormal | fcPosInf) -> fcmp ogt x, 0.0 in getKnownSignOrZero()
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| H A D | InstCombineSimplifyDemanded.cpp | 1953 case fcPosInf: in getFPClassConstant()
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| /llvm-project/llvm/test/Transforms/InstCombine/ |
| H A D | is_fpclass.ll | 492 %val = call i1 @llvm.is.fpclass.f32(float %x, i32 512) ; fcPosInf
501 %val = call i1 @llvm.is.fpclass.f32(float %x, i32 515) ; fcPosInf|fcNan
510 %val = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 512) ; fcPosInf
576 %val = call i1 @llvm.is.fpclass.f32(float %x, i32 512) strictfp ; fcPosInf
603 %val = call i1 @llvm.is.fpclass.f32(float %x, i32 515) strictfp ; fcPosInf|fcNan
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 5309 auto IsZeroOrInf = B.buildIsFPClass(LLT::scalar(1), SqrtX, fcZero | fcPosInf); in legalizeFSQRTF64()
5391 auto IsZeroOrInf = B.buildIsFPClass(LLT::scalar(1), SqrtX, fcZero | fcPosInf); in legalizeRsqClampIntrinsic()
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| H A D | SIISelLowering.cpp | 11383 DAG.getTargetConstant(fcZero | fcPosInf, DL, MVT::i32)); in performMemSDNodeCombine()
11463 DAG.getTargetConstant(fcZero | fcPosInf, DL, MVT::i32)); in getPermuteMask()
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| /llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchInstrInfo.td | 169 if (Check & fcPosInf)
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| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 5265 : (IsFabs ? fcInf : fcPosInf); in SimplifySetCC()
8814 if ((OrderedFPTestMask == fcPosInf || OrderedFPTestMask == fcNegInf) && in expandCTPOP()
9001 if (PartialCheck == fcPosInf) in CTTZTableLookup()
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| /llvm-project/llvm/lib/AsmParser/ |
| H A D | LLParser.cpp | 2589 return fcPosInf;
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| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 9185 if (PartialCheck == fcPosInf)
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| /llvm-project/llvm/unittests/ADT/ |
| H A D | APFloatTest.cpp | 2550 EXPECT_EQ(fcPosInf, PosInf.classify()); in TEST()
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| /llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 6479 if (Check & fcPosInf) in getTargetNodeName()
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| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 11590 if (Mask & fcPosInf) in LowerVectorStore()
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| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 6098 if (Check & fcPosInf) in hasMergeOp()
|