| /llvm-project/llvm/lib/MCA/Stages/ |
| H A D | DispatchStage.cpp | 48 for (const WriteState &RegDef : IR.getInstruction()->getDefs()) in checkPRF() local
49 RegDefs.emplace_back(RegDef.getRegisterID()); in checkPRF()
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| /llvm-project/llvm/include/llvm/IR/ |
| H A D | InlineAsm.h | 227 RegDef = 2, // Output register, "=r". enumerator
328 bool isRegDefKind() const { return getKind() == Kind::RegDef; } in isRegDefKind()
340 case Kind::RegDef: in getKindName()
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| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Utils.cpp | 98 MachineInstr *RegDef = MRI.getVRegDef(Reg); in constrainOperandRegClass() local
99 Observer->changedInstr(*RegDef); in constrainOperandRegClass()
1806 MachineInstr *RegDef = MRI.getVRegDef(Reg); in canCreateUndefOrPoison()
1809 if (auto *GMI = dyn_cast<GenericMachineInstr>(RegDef)) in canCreateUndefOrPoison()
1814 switch (RegDef->getOpcode()) { in canCreateUndefOrPoison()
1822 !shiftAmountKnownInRange(RegDef->getOperand(2).getReg(), MRI); in canCreateUndefOrPoison()
1855 !shiftAmountKnownInRange(RegDef->getOperand(2).getReg(), MRI); in isGuaranteedNotToBeUndefOrPoison()
1857 GInsertVectorElement *Insert = cast<GInsertVectorElement>(RegDef); in isGuaranteedNotToBeUndefOrPoison()
1869 GExtractVectorElement *Extract = cast<GExtractVectorElement>(RegDef); in isGuaranteedNotToBeUndefOrPoison()
1881 GShuffleVector *Shuffle = cast<GShuffleVector>(RegDef); in canCreateUndefOrPoison()
1781 MachineInstr *RegDef = MRI.getVRegDef(Reg); canCreateUndefOrPoison() local
1844 MachineInstr *RegDef = MRI.getVRegDef(Reg); isGuaranteedNotToBeUndefOrPoison() local
[all...] |
| H A D | CallLowering.cpp | 1171 MachineInstr *RegDef = getDefIgnoringCopies(OutInfo.Regs[0], MRI); in parametersInCSRMatch()
1172 if (!RegDef || RegDef->getOpcode() != TargetOpcode::COPY) { in parametersInCSRMatch()
1180 Register CopyRHS = RegDef->getOperand(1).getReg(); in parametersInCSRMatch()
1164 MachineInstr *RegDef = getDefIgnoringCopies(OutInfo.Regs[0], MRI); parametersInCSRMatch() local
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| H A D | InlineAsmLowering.cpp | 356 : InlineAsm::Kind::RegDef, in lowerInlineAsm()
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| /llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCChecker.cpp | 591 const MCRegister RegDef = I.getOperand(0).getReg(); in checkRegisterCurDefs() local
594 for (MCRegAliasIterator Alias(RegDef, &RI, true); Alias.isValid(); in checkRegisterCurDefs()
599 reportWarning("Register `" + Twine(RI.getName(RegDef)) + in checkRegisterCurDefs()
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| /llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineCopyPropagation.cpp | 877 Register RegDef = CopyOperands->Destination->getReg(); in ForwardCopyPropagateBlock()
879 if (!TRI->regsOverlap(RegDef, RegSrc)) { in ForwardCopyPropagateBlock()
880 assert(RegDef.isPhysical() && RegSrc.isPhysical() && in ForwardCopyPropagateBlock()
883 MCRegister Def = RegDef.asMCReg(); in ForwardCopyPropagateBlock()
784 Register RegDef = CopyOperands->Destination->getReg(); ForwardCopyPropagateBlock() local
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| /llvm-project/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIRParser.cpp | 376 const MachineOperand *RegDef = MRI.getOneDef(Reg); in computeFunctionProperties()
377 if (RegDef && RegDef->getSubReg() != 0) in computeFunctionProperties()
369 const MachineOperand *RegDef = MRI.getOneDef(Reg); isSSA() local
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| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGRRList.cpp | 565 SUnit *RegDef = LiveRegDefs[Pred.getReg()]; (void)RegDef; in ReleasePredecessors() local
566 assert((!RegDef || RegDef == SU || RegDef == Pred.getSUnit()) && in ReleasePredecessors()
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| H A D | FastISel.cpp | 161 Register RegDef; in findLocalRegDef() local
166 if (RegDef) in findLocalRegDef()
168 RegDef = MO.getReg(); in findLocalRegDef()
174 return RegDef; in findLocalRegDef()
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| H A D | InstrEmitter.cpp | 1360 case InlineAsm::Kind::RegDef: in EmitSpecialNode()
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| H A D | SelectionDAGBuilder.cpp | 10167 : InlineAsm::Kind::RegDef, in visitInlineAsm()
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FloatingPoint.cpp | 1642 case InlineAsm::Kind::RegDef: in handleSpecialFP()
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 688 case InlineAsm::Kind::RegDef: in LowerINLINEASM()
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| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 3971 case InlineAsm::Kind::RegDef: in LowerINLINEASM()
|