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Searched refs:AllocationOrder (Results 1 – 20 of 20) sorted by relevance

/llvm-project/llvm/unittests/CodeGen/
H A DAllocationOrderTest.cpp15 std::vector<MCPhysReg> loadOrder(const AllocationOrder &O, unsigned Limit = 0) { in loadOrder()
30 AllocationOrder O(std::move(Hints), Order, false); in TEST()
37 AllocationOrder O(std::move(Hints), Order, false); in TEST()
44 AllocationOrder O(std::move(Hints), Order, true); in TEST()
51 AllocationOrder O(std::move(Hints), Order, false); in TEST()
60 AllocationOrder O(std::move(Hints), Order, false); in TEST()
70 AllocationOrder O(std::move(Hints), Order, true); in TEST()
77 AllocationOrder O(std::move(Hints), Order, false); in TEST()
84 AllocationOrder O(std::move(Hints), Order, false); in TEST()
93 AllocationOrder O(std::move(Hints), Order, false); in TEST()
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/llvm-project/llvm/lib/CodeGen/
H A DRegAllocGreedy.h43 class AllocationOrder;
257 /// Candidate info for each PhysReg in AllocationOrder.
332 const AllocationOrder &Order);
343 MCRegister tryAssign(const LiveInterval &, AllocationOrder &,
345 MCRegister tryEvict(const LiveInterval &, AllocationOrder &,
348 MCRegister tryRegionSplit(const LiveInterval &, AllocationOrder &,
352 AllocationOrder &Order,
358 AllocationOrder &Order,
367 AllocationOrder &Order);
371 AllocationOrder
42 class AllocationOrder; global() variable
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H A DAllocationOrder.h30 class LLVM_LIBRARY_VISIBILITY AllocationOrder {
45 const AllocationOrder &AO;
49 Iterator(const AllocationOrder &AO, int Pos) : AO(AO), Pos(Pos) {} in Iterator()
84 static AllocationOrder create(unsigned VirtReg, const VirtRegMap &VRM,
90 AllocationOrder(SmallVector<MCPhysReg, 16> &&Hints, ArrayRef<MCPhysReg> Order, in AllocationOrder() function
H A DAllocationOrder.cpp1 //===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
12 // hints and target hooks. The AllocationOrder class encapsulates all of that.
16 #include "AllocationOrder.h"
29 AllocationOrder AllocationOrder::create(unsigned VirtReg, const VirtRegMap &VRM, in create()
50 return AllocationOrder(std::move(Hints), Order, HardHints); in create()
H A DRegAllocEvictionAdvisor.h21 class AllocationOrder; variable
108 const LiveInterval &VirtReg, const AllocationOrder &Order,
129 const AllocationOrder &Order,
211 const AllocationOrder &, uint8_t,
H A DRegisterScavenging.cpp129 const LiveRegUnits &LiveOut, ArrayRef<MCPhysReg> AllocationOrder, in findSurvivorBackwards()
151 for (MCPhysReg Reg : AllocationOrder) { in findSurvivorBackwards()
176 for (MCPhysReg Reg : AllocationOrder) { in findSurvivorBackwards()
304 ArrayRef<MCPhysReg> AllocationOrder = RC.getRawAllocationOrder(MF); in scavengeRegisterBackwards()
306 *MRI, std::prev(MBBI), To, LiveUnits, AllocationOrder, RestoreAfter); in scavengeRegisterBackwards()
130 findSurvivorBackwards(const MachineRegisterInfo & MRI,MachineBasicBlock::iterator From,MachineBasicBlock::iterator To,const LiveRegUnits & LiveOut,ArrayRef<MCPhysReg> AllocationOrder,bool RestoreAfter) findSurvivorBackwards() argument
305 ArrayRef<MCPhysReg> AllocationOrder = RC.getRawAllocationOrder(MF); scavengeRegisterBackwards() local
H A DRegAllocGreedy.cpp15 #include "AllocationOrder.h"
401 AllocationOrder &Order, in tryAssign()
467 AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix)) { in canReassign()
535 const AllocationOrder &Order, in getOrderLimit()
581 AllocationOrder &Order, in tryEvict()
872 const AllocationOrder &Order) { in calcGlobalSplitCost()
1064 AllocationOrder &Order, in tryRegionSplit()
1098 AllocationOrder &Order, in calculateRegionSplitCostAroundReg()
1175 AllocationOrder &Order, in calculateRegionSplitCost()
1237 AllocationOrder in trySplitAroundHintReg()
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H A DRegAllocFast.cpp941 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtReg()
942 for (MCPhysReg PhysReg : AllocationOrder) { in allocVirtReg()
991 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtRegUndef()
992 if (AllocationOrder.empty()) { in allocVirtRegUndef()
1001 PhysReg = AllocationOrder.front(); in allocVirtRegUndef()
1186 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in setPhysReg()
1187 if (AllocationOrder.empty()) { in setPhysReg()
1214 return AllocationOrder.front(); in setPhysReg()
938 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); allocVirtReg() local
993 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); allocVirtRegUndef() local
1072 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); defineVirtReg() local
1163 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); useVirtReg() local
H A DMLRegAllocEvictAdvisor.cpp13 #include "AllocationOrder.h"
155 // interferring live range at that position, in the order in AllocationOrder.
315 const AllocationOrder &Order,
331 const LiveInterval &VirtReg, const AllocationOrder &Order,
464 const LiveInterval &VirtReg, const AllocationOrder &Order, in DevelopmentModeEvictionAdvisorAnalysis()
613 const LiveInterval &, const AllocationOrder &, unsigned, uint8_t, in loadInterferenceFeatures()
699 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidate()
720 // Track the index->register mapping because AllocationOrder doesn't do that in tryFindEvictionCandidate()
733 // of AllocationOrder one at a time. If it's not legally available, we mask in tryFindEvictionCandidate()
736 // features at - in AllocationOrder orde in tryFindEvictionCandidate()
589 tryFindEvictionCandidatePosition(const LiveInterval &,const AllocationOrder &,unsigned,uint8_t,const SmallVirtRegSet &) const tryFindEvictionCandidatePosition() argument
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H A DRegAllocEvictionAdvisor.cpp14 #include "AllocationOrder.h"
277 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidate()
H A DRegAllocBasic.cpp14 #include "AllocationOrder.h"
267 AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix); in selectOrSplit()
H A DCMakeLists.txt27 AllocationOrder.cpp
/llvm-project/llvm/test/CodeGen/PowerPC/
H A Daix-csr-alloc.mir19 # CHECK-DAG: AllocationOrder(GPRC) = [ $r3 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $r12 $r0 $r31 $r30 $r2…
20 # CHECK-DAG: AllocationOrder(F4RC) = [ $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 …
21 # CHECK-DAG: AllocationOrder(GPRC_and_GPRC_NOR0) = [ $r3 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $r12 $r3…
H A Daix64-csr-alloc.mir19 # CHECK-DAG: AllocationOrder(VFRC) = [ $vf2 $vf3 $vf4 $vf5 $vf0 $vf1 $vf6 $vf7 $vf8 $vf9 $vf10 $vf11 $vf12 $vf13 $vf14 $vf15 $vf16 $vf17 $vf18 $vf19 $vf31 $vf30 $vf29 $vf28 $vf27 $vf26 $vf25 $vf24 $vf23 $vf22 $vf21 $vf20 ]
20 # CHECK-DAG: AllocationOrder(G8RC_and_G8RC_NOX0) = [ $x3 $x4 $x5 $x6 $x7 $x8 $x9 $x10 $x11 $x12 $x2 $x31 $x30 $x29 $x28 $x27 $x26 $x25 $x24 $x23 $x22 $x21 $x20 $x19 $x18 $x17 $x16 $x15 $x14 ]
21 # CHECK-DAG: AllocationOrder(F8RC) = [ $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23 $f22 $f21 $f20 $f19 $f18 $f17 $f16 $f15 $f14 ]
H A Dcompute-regpressure.ll4 ; DEBUG-COUNT-1: AllocationOrder(VRSAVERC) = [ ]
/llvm-project/llvm/test/CodeGen/ARM/
H A Dfavor-low-reg-for-Osize.ll9 ; DEBUG: AllocationOrder(GPR) = [ $r0 $r1 $r2 $r3 $r4 $r5 $r6 $r7 $r12 $lr $r8 $r9 $r10 $r1…
20 ; DEBUG: AllocationOrder(GPR) = [ $r0 $r1 $r2 $r3 $r12 $lr $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 ]
/llvm-project/llvm/utils/gn/secondary/llvm/lib/CodeGen/
H A DBUILD.gn26 "AllocationOrder.cpp",
/llvm-project/utils/bazel/llvm-project-overlay/llvm/unittests/
H A DBUILD.bazel160 features = ["-layering_check"], # #include "../lib/CodeGen/AllocationOrder.h"
/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td499 // Make AllocationOrder as similar as G8RC's to avoid potential spilling.
/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterInfo.td89 // or AllocationOrder