[CodeGen] Use MCRegister instead of MCPhysReg in RegisterMaskPair. NFC (#123688)

Update some other places to avoid implicit conversions this introduces,
but I probably missed some.

[RegAllocFast] Don't convert MCRegUnit to MCRegister. NFC (#123705)

Fix-forward 'RegAllocFast: Avoid using temporary DiagnosticInfo #120184' (#120268)

There was a buildbot breakage

(https://lab.llvm.org/buildbot/#/builders/24/builds/3329/steps/11/logs/stdio):

Fix-forward 'RegAllocFast: Avoid using temporary DiagnosticInfo #120184' (#120268)

There was a buildbot breakage

(https://lab.llvm.org/buildbot/#/builders/24/builds/3329/steps/11/logs/stdio):


/home/b/sanitizer-aarch64-linux-bootstrap-asan/build/llvm-project/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll:9:10:
error: CHECK: expected string not found in input
; CHECK: error: <unknown>:0:0: no registers from class available to
allocate in function 'no_registers_from_class_available_to_allocate'

2: ==75198==ERROR: AddressSanitizer: stack-use-after-scope on address
0xfa23f9f1c270 at pc 0xb2660dda9340 bp 0xfffffe8ab340 sp 0xfffffe8ab338

caused by https://github.com/llvm/llvm-project/pull/120184, which made a
partial fix but also renabled the tests. This patch attempts to fix
forward by applying the same fix to the error message highlighted in the
buildbot.

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RegAllocFast: Avoid using temporary DiagnosticInfo (#120184)

This reverts commit 1297933f35b4948b4d281259627a72094c407a75.

RegAlloc: Fix failure on undef use when all registers are reserved (#119647)

Greedy and fast would hit different assertions on undef uses if all
registers in a class were reserved.

RegAlloc: Do not fatal error if there are no registers in the alloc order (#119640)

Try to use DiagnosticInfo if every register in the class is reserved
by forcing assignment to a reserved register.

RegAlloc: Do not fatal error if there are no registers in the alloc order (#119640)

Try to use DiagnosticInfo if every register in the class is reserved
by forcing assignment to a reserved register. Also reduces the number
of redundant errors emitted, particularly with fast.

This is still broken in the case of undef uses. There are additional
complications in greedy and fast, so leave it for a separate fix.

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RegAlloc: Use DiagnosticInfo to report register allocation failures (#119492)

Improve the non-fatal cases to use DiagnosticInfo, which will now
provide a location. The allocators attempt to report d

RegAlloc: Use DiagnosticInfo to report register allocation failures (#119492)

Improve the non-fatal cases to use DiagnosticInfo, which will now
provide a location. The allocators attempt to report different errors
if it happens to see inline assembly is involved (this detection is
quite unreliable) using srcloc instead of dbgloc. For now, leave this
behavior unchanged. I think reporting the full location and context
function would be more useful.

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Reapply "DiagnosticInfo: Clean up usage of DiagnosticInfoInlineAsm" (#119575) (#119634)

This reverts commit 40986feda8b1437ed475b144d5b9a208b008782a.

Reapply with fix to prevent temporary Twine fro

Reapply "DiagnosticInfo: Clean up usage of DiagnosticInfoInlineAsm" (#119575) (#119634)

This reverts commit 40986feda8b1437ed475b144d5b9a208b008782a.

Reapply with fix to prevent temporary Twine from going out of scope.

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Revert "DiagnosticInfo: Clean up usage of DiagnosticInfoInlineAsm" (#119575)

Reverts llvm/llvm-project#119485

Breaks builders, details in llvm/llvm-project#119485

DiagnosticInfo: Clean up usage of DiagnosticInfoInlineAsm (#119485)

Currently LLVMContext::emitError emits any error as an "inline asm"
error which does not make any sense. InlineAsm appears to be s

DiagnosticInfo: Clean up usage of DiagnosticInfoInlineAsm (#119485)

Currently LLVMContext::emitError emits any error as an "inline asm"
error which does not make any sense. InlineAsm appears to be special,
in that it uses a "LocCookie" from srcloc metadata, which looks like
a parallel mechanism to ordinary source line locations. This meant
that other types of failures had degraded source information reported
when available.

Introduce some new generic error types, and only use inline asm
in the appropriate contexts. The DiagnosticInfo types are still
a bit of a mess, and I'm not sure why DiagnosticInfoWithLocationBase
exists instead of just having an optional DiagnosticLocation in the
base class.

DK_Generic is for any error that derives from an IR level instruction,
and thus can pull debug locations directly from it. DK_GenericWithLoc
is functionally the generic codegen error, since it does not depend
on the IR and instead can construct a DiagnosticLocation from the
MI debug location.

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Revert "[CodeGen] Use MachineInstr::{all_uses,all_defs} (NFC)" (#106451)

Reverts llvm/llvm-project#106404

Breaks:
https://lab.llvm.org/buildbot/#/builders/169/builds/2590
https://lab.llvm.org/b

Revert "[CodeGen] Use MachineInstr::{all_uses,all_defs} (NFC)" (#106451)

Reverts llvm/llvm-project#106404

Breaks:
https://lab.llvm.org/buildbot/#/builders/169/builds/2590
https://lab.llvm.org/buildbot/#/builders/164/builds/2454

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[CodeGen] Use MachineInstr::{all_uses,all_defs} (NFC) (#106404)

[CodeGen] Use MachineInstr::all_defs (NFC) (#106017)

[NFC] Use references to avoid copying (#99863)

Modifying `auto` to `auto&` to avoid unnecessary copying

[CodeGen] change prototype of regalloc filter function (#93525)

[CodeGen] Change the prototype of regalloc filter function

Change the prototype of the filter function so that we can
filter not j

[CodeGen] change prototype of regalloc filter function (#93525)

[CodeGen] Change the prototype of regalloc filter function

Change the prototype of the filter function so that we can
filter not just by RegClass. We need to implement more
complicated filter based upon some other info associated
with each register.

Patch provided by: Gang Chen (gangc@amd.com)

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[CodeGen][NewPM] Extract MachineFunctionProperties modification part to an RAII class (#94854)

Modify MachineFunctionProperties in PassModel makes `PassT P;
P.run(...);` not work properly. This is

[CodeGen][NewPM] Extract MachineFunctionProperties modification part to an RAII class (#94854)

Modify MachineFunctionProperties in PassModel makes `PassT P;
P.run(...);` not work properly. This is a necessary compromise.

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[RegAllocFast] Replace UsedInInstr with vector (#96323)

A SparseSet adds an avoidable layer of indirection and possibly looping
control flow. Avoid this overhead by using a vector to store
UsedInI

[RegAllocFast] Replace UsedInInstr with vector (#96323)

A SparseSet adds an avoidable layer of indirection and possibly looping
control flow. Avoid this overhead by using a vector to store
UsedInInstrs and PhysRegUses.

To avoid clearing the vector after every instruction, use a
monotonically increasing counter. The two maps are now merged and the
lowest bit indicates whether the use is relevant for the livethrough
handling code only.

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[RegAlloc] Don't call always-true ShouldAllocClass (#96296)

Previously, there was at least one virtual function call for every
allocated register. The only users of this feature are AMDGPU and RISC

[RegAlloc] Don't call always-true ShouldAllocClass (#96296)

Previously, there was at least one virtual function call for every
allocated register. The only users of this feature are AMDGPU and RISC-V
(RVV), other targets don't use this. To easily identify these cases,
change the default functor to nullptr and don't call it for every
allocated register.

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[RegAllocFast] Handle single-vdef instrs faster (#96284)

On x86, many instructions have tied operands, so allocateInstruction
uses the more complex assignment strategy, which computes the assignmen

[RegAllocFast] Handle single-vdef instrs faster (#96284)

On x86, many instructions have tied operands, so allocateInstruction
uses the more complex assignment strategy, which computes the assignment
order of virtual defs first. This involves iterating over all register
classes (or register aliases for physical defs) to compute the possible
number of defs per register class.

However, this information is only used for sorting virtual defs and
therefore not required when there's only one virtual def -- which is a
very common case. As iterating over all register classes/aliases is not
cheap, do this only when there's more than one virtual def.

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[RegAllocFast] Use unsigned for operand indices

MachineInstr operand indices can be up 24 bits currently. Use unsigned
as consistent data type for operand indices instead of uint16_t.

[NewPM][CodeGen] Port `regallocfast` to new pass manager (#94426)

This pull request port `regallocfast` to new pass manager. It exposes
the parameter `filter` to handle different register classes f

[NewPM][CodeGen] Port `regallocfast` to new pass manager (#94426)

This pull request port `regallocfast` to new pass manager. It exposes
the parameter `filter` to handle different register classes for AMDGPU.
IIUC AMDGPU need to allocate different register classes separately so it
need implement its own `--<reg-class>-regalloc`. Now users can use e.g.
`-passe=regallocfast<filter=sgpr>` to allocate specific register class.
The command line option `--regalloc-npm` is still in work progress, plan
to reuse the syntax of passes, e.g. use
`--regalloc-npm=regallocfast<filter=sgpr>,greedy<filter=vgpr>` to
replace `--sgpr-regalloc` and `--vgpr-regalloc`.

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[CodeGen] Do not pass MF into MachineRegisterInfo methods. NFC. (#84770)

MachineRegisterInfo already knows the MF so there is no need to pass it
in as an argument.

[RegAllocFast] Lazily initialize InstrPosIndexes for each MBB (#76275)

Most basic block do not need to query dominates. Defer initialization of
InstrPosIndexes to first query for each MBB.

[RegAllocFast] Avoid duplicate hash lookup (NFC)

[RegAllocFast] Refactor dominates algorithm for large basic block (#72250)

The original brute force dominates algorithm is O(n) complexity so it is
very slow for very large machine basic block whic

[RegAllocFast] Refactor dominates algorithm for large basic block (#72250)

The original brute force dominates algorithm is O(n) complexity so it is
very slow for very large machine basic block which is very common with
O0. This patch added InstrPosIndexes to assign index for each
instruction and use it to determine dominance. The complexity is now
O(1).

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