[CodeGen] Remove some implict conversions of MCRegister to unsigned by using(). NFC

Many of these are indexing BitVectors or something where we can't
using MCRegister and need the register number.

Reapply "Spiller: Detach legacy pass and supply analyses instead (#119181)" (#122665)

Makes Inline Spiller amenable to the new PM.

This reapplies commit a531800344dc54e9c197a13b22e013f919f3f5e1 r

Reapply "Spiller: Detach legacy pass and supply analyses instead (#119181)" (#122665)

Makes Inline Spiller amenable to the new PM.

This reapplies commit a531800344dc54e9c197a13b22e013f919f3f5e1 reverted
because of two unused private members reported on sanitizer bots.

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Revert "Spiller: Detach legacy pass and supply analyses instead (#119… (#122426)

…181)"

This reverts commit a531800344dc54e9c197a13b22e013f919f3f5e1.

Spiller: Detach legacy pass and supply analyses instead (#119181)

Makes Inline Spiller amenable to the new PM.

[LLVM] Fix various cl::desc typos and whitespace issues (NFC) (#121955)

RegAllocGreedy: Fix use after free during last chance recoloring (#120697)

Last chance recoloring can delete the current fixed interval
during recursive assignment of interfering live intervals. Che

RegAllocGreedy: Fix use after free during last chance recoloring (#120697)

Last chance recoloring can delete the current fixed interval
during recursive assignment of interfering live intervals. Check
if the virtual register value was assigned before attempting the
unassignment, as is done in other scenarios. This relies on the fact
that we do not recycle virtual register numbers.

I have only seen this occur in error situations where the allocation
will fail, but I think this can theoretically happen in working
allocations.

This feels very brute force, but I've spent over a week debugging
this and this is what works without any lit regressions. The surprising
piece to me was that unspillable live ranges may be spilled, and
a number of tests rely on optimizations occurring on them. My other
attempts to fixed this mostly revolved around not identifying unspillable
live ranges as snippet copies. I've also discovered we're making some
unproductive live range splits with subranges. If we avoid such splits,
some of the unspillable copies disappear but mandating that be precise
to fix a use after free doesn't sound right.

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RegAllocGreedy: Add dummy priority advisor for writing MIR tests (#121207)

I regularly struggle reproducing failures in greedy due to changes
in priority when resuming the allocation from MIR vs. a

RegAllocGreedy: Add dummy priority advisor for writing MIR tests (#121207)

I regularly struggle reproducing failures in greedy due to changes
in priority when resuming the allocation from MIR vs. a complete
compilation starting at IR. That is, the fix in
e0919b189bf2df4f97f22ba40260ab5153988b14 did not really fix the
problem of the instruction distance mattering.

Add a way to bypass all of the priority heuristics for MIR tests,
by prioritizing only by virtual register number. Could also
give this a more specific name, like PrioritizeLowVirtRegNumber

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RegAllocGreedy: Fix comment typo

RegAlloc: Fix failure on undef use when all registers are reserved (#119647)

Greedy and fast would hit different assertions on undef uses if all
registers in a class were reserved.

[CodeGen][NewPM] Port LiveStacks analysis to NPM (#118778)

[CodeGen][NewPM] Port LiveDebugVariables to NPM (#115468)

The existing analysis was already a pimpl wrapper.

I have extracted legacy pass logic to a LDVImpl wrapper named
`LiveDebugVariables` wh

[CodeGen][NewPM] Port LiveDebugVariables to NPM (#115468)

The existing analysis was already a pimpl wrapper.

I have extracted legacy pass logic to a LDVImpl wrapper named
`LiveDebugVariables` which is the analysis::Result now. This controls
whether to activate the LDV (depending on `-live-debug-variables` and
DIsubprogram) itself.

The legacy and new analysis only construct the LiveDebugVariables.

VirtRegRewriter will test this.

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[CodeGen][NewPM] Port SpillPlacement analysis to NPM (#116618)

[CodeGen][NewPM] Port EdgeBundles analysis to NPM (#116616)

[CodeGen] Remove unused includes (NFC) (#115996)

Identified with misc-include-cleaner.

[NewPM][CodeGen] Port LiveRegMatrix to NPM (#109938)

[NewPM][CodeGen] Port VirtRegMap to NPM (#109936)

[CodeGen][RAGreedy] Inform LiveDebugVariables about snippets spilled by InlineSpiller. (#109962)

RAGreedy invokes InlineSpiller to spill a particular virtreg inline.
When the spiller does this, it

[CodeGen][RAGreedy] Inform LiveDebugVariables about snippets spilled by InlineSpiller. (#109962)

RAGreedy invokes InlineSpiller to spill a particular virtreg inline.
When the spiller does this, it also identifies small, adjacent liveranges called
snippets. These are also spilled or rematerialized in the process.

However, the spiller does not inform RA that it has spilled these regs.
This means that debug variable locations referencing these regs/ranges
are lost.

Mark any spilled regs which do not have a stack slot assigned to them as
allocated to the slot being spilled to to tell LDV that those regs are
located in that slot, even though the regs might no longer exist in the
program after regalloc is finished. Also, inform RA about all of the
regs which were replaced (spilled or rematted), not just the one that was
requested so that it can properly manage the ranges of the debug vars.

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llvm-reduce: Don't print verifier failed machine functions (#109673)

This produces far too much terminal output, particularly for the
instruction reduction. Since it doesn't consider the liveness o

llvm-reduce: Don't print verifier failed machine functions (#109673)

This produces far too much terminal output, particularly for the
instruction reduction. Since it doesn't consider the liveness of of
the instructions it's deleting, it produces quite a lot of verifier
errors.

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[CodeGen] change prototype of regalloc filter function (#93525)

[CodeGen] Change the prototype of regalloc filter function

Change the prototype of the filter function so that we can
filter not j

[CodeGen] change prototype of regalloc filter function (#93525)

[CodeGen] Change the prototype of regalloc filter function

Change the prototype of the filter function so that we can
filter not just by RegClass. We need to implement more
complicated filter based upon some other info associated
with each register.

Patch provided by: Gang Chen (gangc@amd.com)

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[CodeGen] Use range-based for loops (NFC) (#98706)

[CodeGen][NewPM] Port `machine-block-freq` to new pass manager (#98317)

- Add `MachineBlockFrequencyAnalysis`.
- Add `MachineBlockFrequencyPrinterPass`.
- Use `MachineBlockFrequencyInfoWrapperPass

[CodeGen][NewPM] Port `machine-block-freq` to new pass manager (#98317)

- Add `MachineBlockFrequencyAnalysis`.
- Add `MachineBlockFrequencyPrinterPass`.
- Use `MachineBlockFrequencyInfoWrapperPass` in legacy pass manager.
- `LazyMachineBlockFrequencyInfo::print` is empty, drop it due to new
pass manager migration.

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[CodeGen][NewPM] Port `LiveIntervals` to new pass manager (#98118)

- Add `LiveIntervalsAnalysis`.
- Add `LiveIntervalsPrinterPass`.
- Use `LiveIntervalsWrapperPass` in legacy pass manager.
- Use

[CodeGen][NewPM] Port `LiveIntervals` to new pass manager (#98118)

- Add `LiveIntervalsAnalysis`.
- Add `LiveIntervalsPrinterPass`.
- Use `LiveIntervalsWrapperPass` in legacy pass manager.
- Use `std::unique_ptr` instead of raw pointer for `LICalc`, so
destructor and default move constructor can handle it correctly.

This would be the last analysis required by `PHIElimination`.

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[CodeGen][NewPM] Port `SlotIndexes` to new pass manager (#97941)

- Add `SlotIndexesAnalysis`.
- Add `SlotIndexesPrinterPass`.
- Use `SlotIndexesWrapperPass` in legacy pass.

[CodeGen][NewPM] Port `machine-loops` to new pass manager (#97793)

- Add `MachineLoopAnalysis`.
- Add `MachineLoopPrinterPass`.
- Convert to `MachineLoopInfoWrapperPass` in legacy pass manager.

[RegAlloc] Don't call always-true ShouldAllocClass (#96296)

Previously, there was at least one virtual function call for every
allocated register. The only users of this feature are AMDGPU and RISC

[RegAlloc] Don't call always-true ShouldAllocClass (#96296)

Previously, there was at least one virtual function call for every
allocated register. The only users of this feature are AMDGPU and RISC-V
(RVV), other targets don't use this. To easily identify these cases,
change the default functor to nullptr and don't call it for every
allocated register.

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