[InstCombine] fold not-shift of signbit to icmp+zext, part 2

Follow-up to:
6c39a3aae1dc

That converted a pattern with ashr directly to icmp+zext, and
this updates the pattern that we used to conver

[InstCombine] fold not-shift of signbit to icmp+zext, part 2

Follow-up to:
6c39a3aae1dc

That converted a pattern with ashr directly to icmp+zext, and
this updates the pattern that we used to convert to.

This canonicalizes to icmp for better analysis in the minimum case
and shortens patterns where the source type is not the same as dest type:
https://alive2.llvm.org/ce/z/tpXJ64
https://alive2.llvm.org/ce/z/dQ405O

This requires an adjustment to an icmp transform to avoid infinite looping.

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Attributes: convert Optional to std::optional

[InstCombine] Update debug intrinsics when rewriting allocas

[Assignment Tracking][14/*] Account for assignment tracking in instcombine

The Assignment Tracking debug-info feature is outlined in this RFC:

https://discourse.llvm.org/t/
rfc-assignment-tracking-

[Assignment Tracking][14/*] Account for assignment tracking in instcombine

The Assignment Tracking debug-info feature is outlined in this RFC:

https://discourse.llvm.org/t/
rfc-assignment-tracking-a-better-way-of-specifying-variable-locations-in-ir

Most of the updates here are just to ensure DIAssignID attachments are
maintained and propagated correctly.

Reviewed By: jmorse

Differential Revision: https://reviews.llvm.org/D133307

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[InstCombine] reduce multi-use casts+masks

As noted in the code comment, we could generalize this:
https://alive2.llvm.org/ce/z/N5m-eZ

It saves an instruction even without a constant operand,
but t

[InstCombine] reduce multi-use casts+masks

As noted in the code comment, we could generalize this:
https://alive2.llvm.org/ce/z/N5m-eZ

It saves an instruction even without a constant operand,
but the 'and' is wider. We can do that as another step
if it doesn't harm anything.

I noticed that this missing pattern with a constant operand
inhibited other transforms in a recent bug report, so this
is enough to solve that case.

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[InstCombine] Remove buggy zext of icmp eq with pow2 fold (PR57899)

For the case where the constant is a power of two rather than zero,
the fold is incorrect, because it fails to check that the bit

[InstCombine] Remove buggy zext of icmp eq with pow2 fold (PR57899)

For the case where the constant is a power of two rather than zero,
the fold is incorrect, because it fails to check that the bit set
in the LHS matches the bit in the RHS.

Rather than fixing this, remove the power of two handling entirely,
as a different fold will already canonicalize such comparisons to
use a zero constant.

Fixes https://github.com/llvm/llvm-project/issues/57899.

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[InstCombine] delete redundant folds; NFC

InstSimplify does this via isKnownNonEqual(), so it's already
using knownbits on these patterns and trying other folds.

[InstCombine] recognize bitreverse disguised as shufflevector

This patch complete TODO left in D66965, and achieve
related pattern for bitreverse.

Reviewed By: RKSimon

Differential Revision: https

[InstCombine] recognize bitreverse disguised as shufflevector

This patch complete TODO left in D66965, and achieve
related pattern for bitreverse.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D132431

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[InstCombine] Add undef elements support for shrinkFPConstantVector

Reviewed By: RKSimon, spatel

Differential Revision: https://reviews.llvm.org/D132343

[ADT] Deprecate is_splat and replace all uses with all_equal

See the discussion thread for more details:
https://discourse.llvm.org/t/adt-is-splat-and-empty-ranges/64692

Reviewed By: dblaikie

Diff

[ADT] Deprecate is_splat and replace all uses with all_equal

See the discussion thread for more details:
https://discourse.llvm.org/t/adt-is-splat-and-empty-ranges/64692

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D132335

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[InstCombine] Make use of low zero bits to determine exact int->fp cast

According the comment https://reviews.llvm.org/D127854#inline-1226805,
We could also make use of these low zero bits, https://

[InstCombine] Make use of low zero bits to determine exact int->fp cast

According the comment https://reviews.llvm.org/D127854#inline-1226805,
We could also make use of these low zero bits, https://alive2.llvm.org/ce/z/GYxTRu

Reviewed By: spatel, nikic, xbolva00

Differential Revision: https://reviews.llvm.org/D128895

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[InstCombine] Use known bits to determine exact int->fp cast

Reviewed By: spatel, nikic

Differential Revision: https://reviews.llvm.org/D127854

[llvm] Don't use Optional::getValue (NFC)

[InstCombine] decomposeSimpleLinearExpr should bail out on negative operands.

InstCombine tries to rewrite

%prod = mul nsw i64 %X, Scale
%acc = add nsw i64 %prod, Offset
%0 = alloca i8, i

[InstCombine] decomposeSimpleLinearExpr should bail out on negative operands.

InstCombine tries to rewrite

%prod = mul nsw i64 %X, Scale
%acc = add nsw i64 %prod, Offset
%0 = alloca i8, i64 %acc, align 4
%1 = bitcast i8* %0 to i32*
Use ( %1 )

into

%prod = mul nsw i64 %X, Scale/4
%acc = add nsw i64 %prod, Offset/4
%0 = alloca i32, i64 %acc, align 4
Use (%0)

But it assumes Scale is unsigned, and performs an unsigned division.
So we should bail out if Scale cannot be interpreted as an unsigned safely.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D126546

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[InstCombine] bitcast (extractelement <1 x elt>, dest) -> bitcast(<1 x elt>, dest)

Only solve dest type is vector to avoid inverse transform in visitBitCast.

Reviewed By: spatel

Differential Revis

[InstCombine] bitcast (extractelement <1 x elt>, dest) -> bitcast(<1 x elt>, dest)

Only solve dest type is vector to avoid inverse transform in visitBitCast.

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D125951

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[InstCombine] bitcast(logic(bitcast(X), bitcast(Y))) -> bitcast'(logic(bitcast'(X), Y))

This patch break foldBitCastBitwiseLogic limite the destination
must have an integer element type, and elimina

[InstCombine] bitcast(logic(bitcast(X), bitcast(Y))) -> bitcast'(logic(bitcast'(X), Y))

This patch break foldBitCastBitwiseLogic limite the destination
must have an integer element type, and eliminate one bitcast by
doing the logic op in the type of the input that has an integer
element type.

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D126184

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[InstCombine] [NFC] Move transforms for truncated shifts into narrowBinOp

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D126056

[InstCombine] [NFC] Use a pattern matcher for ExtractElementInst

Reviewed By: RKSimon, rampitec

Differential Revision: https://reviews.llvm.org/D125857

[InstCombine] remove cast-of-signbit to shift transform

The transform was wrong in 3 ways:

1. It created an extra instruction when the source and dest types don't match.
2. It did not account for a

[InstCombine] remove cast-of-signbit to shift transform

The transform was wrong in 3 ways:

1. It created an extra instruction when the source and dest types don't match.
2. It did not account for an extra use of the icmp, so could create 2 extra insts.
3. It favored bit hacks over icmp (icmp generally has better analysis).

This fixes #54692 (modeled by the PhaseOrdering tests).

This is a minimal step to fix the bug, but we should likely invert
this and the sibling transform for the "is negative" pattern too.

The backend should be able to invert this back to a shift if that
leads to better codegen.

This is a reduced try of 3794cc0e9964 - that was reverted because
it could cause infinite loops by conflicting with the related
transforms in this block that create shifts.

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[KnownBits] Add operator==

Checking whether two KnownBits are the same is somewhat common,
mainly in test code.

I don't think there is a lot of room for confusion with "determine
what the KnownBits

[KnownBits] Add operator==

Checking whether two KnownBits are the same is somewhat common,
mainly in test code.

I don't think there is a lot of room for confusion with "determine
what the KnownBits for an icmp eq would be", as that has a
different result type (this is what the eq() method implements,
which returns Optional<bool>).

Differential Revision: https://reviews.llvm.org/D125692

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Revert "[InstCombine] invert canonicalization for cast of signbit test"

This reverts commit 3794cc0e996481e10307b67c8436aa44e0d65d22.
This change is suspected of causing bots to hang at stage 2
comp

Revert "[InstCombine] invert canonicalization for cast of signbit test"

This reverts commit 3794cc0e996481e10307b67c8436aa44e0d65d22.
This change is suspected of causing bots to hang at stage 2
compiles, so reverting to confirm and investigate.

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[InstCombine] invert canonicalization for cast of signbit test

The existing transform was wrong in 3 ways:
1. It created an extra instruction when the source and dest types don't match.
2. It did no

[InstCombine] invert canonicalization for cast of signbit test

The existing transform was wrong in 3 ways:
1. It created an extra instruction when the source and dest types don't match.
2. It did not account for an extra use of the icmp, so could create 2 extra insts.
3. It favored bit hacks over icmp (icmp generally has better analysis).

This fixes #54692 (modeled by the PhaseOrdering tests).

This is a minimal step to fix the bug, but we should likely invert
the sibling transform for the "is negative" pattern too.

The backend should be able to invert this back to a shift if that
leads to better codegen.

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[InstCombine] fix miscompile when casting int->FP->int

As shown in https://github.com/llvm/llvm-project/issues/55150 -
the existing fold may be wrong when converting to a signed value.
This is a qui

[InstCombine] fix miscompile when casting int->FP->int

As shown in https://github.com/llvm/llvm-project/issues/55150 -
the existing fold may be wrong when converting to a signed value.
This is a quick fix to avoid the miscompile.

I added tests/comments for all of the signed/unsigned combinations
at either side of the boundary width, and tried to confirm with Alive2:
https://alive2.llvm.org/ce/z/3p9DSu

There are already some TODO items in the test file that suggest
possible refinements, so the regression with ui->FP->si is probably ok.
It seems unlikely that we'd see these kind of edge cases with
non-byte-width integer types in real code. The potential miscompile
went undetected for several years.

This and 747c6a0c734e fixes #55150.

Differential Revision: https://reviews.llvm.org/D124692

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[InstCombine] add casts from splat-a-bit pattern if necessary

Splatting a bit of constant-index across a value:
sext (ashr (trunc iN X to iM), M-1) to iN --> ashr (shl X, N-M), N-1
If the dest type

[InstCombine] add casts from splat-a-bit pattern if necessary

Splatting a bit of constant-index across a value:
sext (ashr (trunc iN X to iM), M-1) to iN --> ashr (shl X, N-M), N-1
If the dest type is different, use a cast (adjust use check).

https://alive2.llvm.org/ce/z/acAan3

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D124590

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[InstCombine] use isKnownNonNegative to reduce code duplication; NFC

We may be able to make the ValueTracking wrapper smarter
in the future (for example, analyze a simple recurrence),
so this will a

[InstCombine] use isKnownNonNegative to reduce code duplication; NFC

We may be able to make the ValueTracking wrapper smarter
in the future (for example, analyze a simple recurrence),
so this will automatically benefit if that happens.

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