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Searched refs:phy_data (Results 1 – 15 of 15) sorted by relevance

/onnv-gate/usr/src/uts/common/io/igb/
H A Digb_phy.c810 u16 phy_data; in e1000_copper_link_setup_82577() local
828 ret_val = phy->ops.read_reg(hw, I82577_CFG_REG, &phy_data); in e1000_copper_link_setup_82577()
832 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; in e1000_copper_link_setup_82577()
835 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; in e1000_copper_link_setup_82577()
837 ret_val = phy->ops.write_reg(hw, I82577_CFG_REG, phy_data); in e1000_copper_link_setup_82577()
855 u16 phy_data; in e1000_copper_link_setup_m88() local
865 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); in e1000_copper_link_setup_m88()
869 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; in e1000_copper_link_setup_m88()
879 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; in e1000_copper_link_setup_m88()
883 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; in e1000_copper_link_setup_m88()
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/onnv-gate/usr/src/uts/common/io/e1000g/
H A De1000_phy.c743 u16 phy_data; in e1000_copper_link_setup_82577() local
753 ret_val = phy->ops.read_reg(hw, I82577_CFG_REG, &phy_data); in e1000_copper_link_setup_82577()
757 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; in e1000_copper_link_setup_82577()
760 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; in e1000_copper_link_setup_82577()
762 ret_val = phy->ops.write_reg(hw, I82577_CFG_REG, phy_data); in e1000_copper_link_setup_82577()
767 ret_val = phy->ops.read_reg(hw, I82577_CTRL_REG, &phy_data); in e1000_copper_link_setup_82577()
770 phy_data &= ~I82577_CTRL_DOWNSHIFT_MASK; in e1000_copper_link_setup_82577()
771 ret_val = phy->ops.write_reg(hw, I82577_CTRL_REG, phy_data); in e1000_copper_link_setup_82577()
789 u16 phy_data; in e1000_copper_link_setup_m88() local
799 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); in e1000_copper_link_setup_m88()
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H A De1000_80003es2lan.c715 u16 phy_data; in e1000_phy_force_speed_duplex_80003es2lan() local
727 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); in e1000_phy_force_speed_duplex_80003es2lan()
731 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO; in e1000_phy_force_speed_duplex_80003es2lan()
732 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); in e1000_phy_force_speed_duplex_80003es2lan()
736 DEBUGOUT1("GG82563 PSCR: %X\n", phy_data); in e1000_phy_force_speed_duplex_80003es2lan()
738 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data); in e1000_phy_force_speed_duplex_80003es2lan()
742 e1000_phy_force_speed_duplex_setup(hw, &phy_data); in e1000_phy_force_speed_duplex_80003es2lan()
745 phy_data |= MII_CR_RESET; in e1000_phy_force_speed_duplex_80003es2lan()
747 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data); in e1000_phy_force_speed_duplex_80003es2lan()
780 hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); in e1000_phy_force_speed_duplex_80003es2lan()
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H A De1000g_rx.c151 uint16_t phy_data; in e1000g_rx_setup() local
329 (void) e1000_read_phy_reg(hw, PHY_REG(770, 26), &phy_data); in e1000g_rx_setup()
330 phy_data &= 0xfff8; in e1000g_rx_setup()
331 phy_data |= (1 << 2); in e1000g_rx_setup()
332 (void) e1000_write_phy_reg(hw, PHY_REG(770, 26), phy_data); in e1000g_rx_setup()
335 (void) e1000_read_phy_reg(hw, 22, &phy_data); in e1000g_rx_setup()
336 phy_data &= 0x0fff; in e1000g_rx_setup()
337 phy_data |= (1 << 14); in e1000g_rx_setup()
340 (void) e1000_write_phy_reg(hw, 22, phy_data); in e1000g_rx_setup()
H A De1000_82541.c697 u16 phy_data, phy_saved_data, speed, duplex, i; in e1000_config_dsp_after_link_change_82541() local
729 &phy_data); in e1000_config_dsp_after_link_change_82541()
733 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; in e1000_config_dsp_after_link_change_82541()
737 phy_data); in e1000_config_dsp_after_link_change_82541()
751 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); in e1000_config_dsp_after_link_change_82541()
759 &phy_data); in e1000_config_dsp_after_link_change_82541()
763 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); in e1000_config_dsp_after_link_change_82541()
806 &phy_data); in e1000_config_dsp_after_link_change_82541()
810 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; in e1000_config_dsp_after_link_change_82541()
811 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; in e1000_config_dsp_after_link_change_82541()
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H A De1000_82540.c537 u16 phy_data; in e1000_set_vco_speed_82540() local
553 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); in e1000_set_vco_speed_82540()
557 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; in e1000_set_vco_speed_82540()
558 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); in e1000_set_vco_speed_82540()
568 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); in e1000_set_vco_speed_82540()
572 phy_data |= M88E1000_PHY_VCO_REG_BIT11; in e1000_set_vco_speed_82540()
573 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); in e1000_set_vco_speed_82540()
H A De1000_ich8lan.c3553 u16 phy_data; in e1000_clear_hw_cntrs_ich8lan() local
3576 (void) hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
3577 (void) hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
3578 (void) hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
3579 (void) hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
3580 (void) hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
3581 (void) hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
3582 (void) hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
3583 (void) hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
3584 (void) hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
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H A De1000_82543.c1430 u16 phy_data; in e1000_config_mac_to_phy_82543() local
1446 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); in e1000_config_mac_to_phy_82543()
1451 if (phy_data & M88E1000_PSSR_DPLX) in e1000_config_mac_to_phy_82543()
1460 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) in e1000_config_mac_to_phy_82543()
1462 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) in e1000_config_mac_to_phy_82543()
/onnv-gate/usr/src/grub/grub-0.97/netboot/
H A De1000.c110 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
111 static int e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
112 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
113 static int e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
1546 uint16_t phy_data; local
1601 &phy_data)))
1607 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX |
1613 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1617 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1620 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
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H A Ddavicom.c211 u16 phy_data; in phy_read() local
242 for (phy_data=0, i=0; i<16; i++) { in phy_read()
243 phy_data<<=1; in phy_read()
244 phy_data|=phy_read_1bit(io_dcr9); in phy_read()
247 return phy_data; in phy_read()
253 static void phy_write(int location, u16 phy_data) in phy_write() argument
288 phy_write_1bit(io_dcr9, phy_data&i ? PHY_DATA_1: PHY_DATA_0); in phy_write()
294 static void phy_write_1bit(u32 ee_addr, u32 phy_data) in phy_write_1bit() argument
297 outl(phy_data, ee_addr); /* MII Clock Low */ in phy_write_1bit()
299 outl(phy_data|MDCLKH, ee_addr); /* MII Clock High */ in phy_write_1bit()
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/onnv-gate/usr/src/uts/common/io/ixgbe/
H A Dixgbe_phy.c289 u32 device_type, u16 *phy_data) in ixgbe_read_phy_reg_generic() argument
372 *phy_data = (u16)(data); in ixgbe_read_phy_reg_generic()
390 u32 device_type, u16 phy_data) in ixgbe_write_phy_reg_generic() argument
411 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); in ixgbe_write_phy_reg_generic()
667 u16 phy_data = 0; in ixgbe_check_phy_link_tnx() local
685 &phy_data); in ixgbe_check_phy_link_tnx()
686 phy_link = phy_data & in ixgbe_check_phy_link_tnx()
688 phy_speed = phy_data & in ixgbe_check_phy_link_tnx()
845 u16 phy_data = 0; in ixgbe_reset_phy_nl() local
852 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); in ixgbe_reset_phy_nl()
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H A Dixgbe_phy.h104 u32 device_type, u16 *phy_data);
106 u32 device_type, u16 phy_data);
H A Dixgbe_api.c443 u16 *phy_data) in ixgbe_read_phy_reg() argument
449 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); in ixgbe_read_phy_reg()
461 u16 phy_data) in ixgbe_write_phy_reg() argument
467 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); in ixgbe_write_phy_reg()
H A Dixgbe_api.h57 u16 *phy_data);
59 u16 phy_data);
/onnv-gate/usr/src/uts/common/io/nxge/
H A Dnxge_mac.c2882 uint16_t phy_data = 0; in nxge_nlp2020_i2c_read() local
2892 phy_data = ((address + 1) << NLP2020_XCVR_I2C_ADDR_SH) | reg; in nxge_nlp2020_i2c_read()
2894 phy_dev, phy_reg, phy_data) != NXGE_OK) in nxge_nlp2020_i2c_read()
2906 &phy_data); in nxge_nlp2020_i2c_read()
2907 *data = (phy_data >> 8); in nxge_nlp2020_i2c_read()