1 /*
2 * This file is provided under a CDDLv1 license. When using or
3 * redistributing this file, you may do so under this license.
4 * In redistributing this file this license must be included
5 * and no other modification of this header file is permitted.
6 *
7 * CDDL LICENSE SUMMARY
8 *
9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved.
10 *
11 * The contents of this file are subject to the terms of Version
12 * 1.0 of the Common Development and Distribution License (the "License").
13 *
14 * You should have received a copy of the License with this software.
15 * You can obtain a copy of the License at
16 * http://www.opensolaris.org/os/licensing.
17 * See the License for the specific language governing permissions
18 * and limitations under the License.
19 */
20
21 /*
22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms of the CDDLv1.
24 */
25
26 /*
27 * IntelVersion: 1.68 v3-1-10-1_2009-9-18_Release14-6
28 */
29
30 /*
31 * 82543GC Gigabit Ethernet Controller (Fiber)
32 * 82543GC Gigabit Ethernet Controller (Copper)
33 * 82544EI Gigabit Ethernet Controller (Copper)
34 * 82544EI Gigabit Ethernet Controller (Fiber)
35 * 82544GC Gigabit Ethernet Controller (Copper)
36 * 82544GC Gigabit Ethernet Controller (LOM)
37 */
38
39 #include "e1000_api.h"
40
41 static s32 e1000_init_phy_params_82543(struct e1000_hw *hw);
42 static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw);
43 static s32 e1000_init_mac_params_82543(struct e1000_hw *hw);
44 static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset,
45 u16 *data);
46 static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset,
47 u16 data);
48 static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw);
49 static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw);
50 static s32 e1000_reset_hw_82543(struct e1000_hw *hw);
51 static s32 e1000_init_hw_82543(struct e1000_hw *hw);
52 static s32 e1000_setup_link_82543(struct e1000_hw *hw);
53 static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw);
54 static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw);
55 static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw);
56 static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw);
57 static s32 e1000_led_on_82543(struct e1000_hw *hw);
58 static s32 e1000_led_off_82543(struct e1000_hw *hw);
59 static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset,
60 u32 value);
61 static void e1000_mta_set_82543(struct e1000_hw *hw, u32 hash_value);
62 static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw);
63 static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw);
64 static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw);
65 static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
66 static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw);
67 static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
68 static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw);
69 static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
70 u16 count);
71 static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw);
72 static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state);
73
74 /*
75 * e1000_init_phy_params_82543 - Init PHY func ptrs.
76 * @hw: pointer to the HW structure
77 */
78 static s32
e1000_init_phy_params_82543(struct e1000_hw * hw)79 e1000_init_phy_params_82543(struct e1000_hw *hw)
80 {
81 struct e1000_phy_info *phy = &hw->phy;
82 s32 ret_val = E1000_SUCCESS;
83
84 DEBUGFUNC("e1000_init_phy_params_82543");
85
86 if (hw->phy.media_type != e1000_media_type_copper) {
87 phy->type = e1000_phy_none;
88 goto out;
89 } else {
90 phy->ops.power_up = e1000_power_up_phy_copper;
91 phy->ops.power_down = e1000_power_down_phy_copper;
92 }
93
94 phy->addr = 1;
95 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
96 phy->reset_delay_us = 10000;
97 phy->type = e1000_phy_m88;
98
99 /* Function Pointers */
100 phy->ops.check_polarity = e1000_check_polarity_m88;
101 phy->ops.commit = e1000_phy_sw_reset_generic;
102 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82543;
103 phy->ops.get_cable_length = e1000_get_cable_length_m88;
104 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
105 phy->ops.read_reg = (hw->mac.type == e1000_82543)
106 ? e1000_read_phy_reg_82543
107 : e1000_read_phy_reg_m88;
108 phy->ops.reset = (hw->mac.type == e1000_82543)
109 ? e1000_phy_hw_reset_82543
110 : e1000_phy_hw_reset_generic;
111 phy->ops.write_reg = (hw->mac.type == e1000_82543)
112 ? e1000_write_phy_reg_82543
113 : e1000_write_phy_reg_m88;
114 phy->ops.get_info = e1000_get_phy_info_m88;
115
116 /*
117 * The external PHY of the 82543 can be in a funky state.
118 * Resetting helps us read the PHY registers for acquiring
119 * the PHY ID.
120 */
121 if (!e1000_init_phy_disabled_82543(hw)) {
122 ret_val = phy->ops.reset(hw);
123 if (ret_val) {
124 DEBUGOUT("Resetting PHY during init failed.\n");
125 goto out;
126 }
127 msec_delay(20);
128 }
129
130 ret_val = e1000_get_phy_id(hw);
131 if (ret_val)
132 goto out;
133
134 /* Verify phy id */
135 switch (hw->mac.type) {
136 case e1000_82543:
137 if (phy->id != M88E1000_E_PHY_ID) {
138 ret_val = -E1000_ERR_PHY;
139 goto out;
140 }
141 break;
142 case e1000_82544:
143 if (phy->id != M88E1000_I_PHY_ID) {
144 ret_val = -E1000_ERR_PHY;
145 goto out;
146 }
147 break;
148 default:
149 ret_val = -E1000_ERR_PHY;
150 goto out;
151 }
152
153 out:
154 return (ret_val);
155 }
156
157 /*
158 * e1000_init_nvm_params_82543 - Init NVM func ptrs.
159 * @hw: pointer to the HW structure
160 */
161 static s32
e1000_init_nvm_params_82543(struct e1000_hw * hw)162 e1000_init_nvm_params_82543(struct e1000_hw *hw)
163 {
164 struct e1000_nvm_info *nvm = &hw->nvm;
165
166 DEBUGFUNC("e1000_init_nvm_params_82543");
167
168 nvm->type = e1000_nvm_eeprom_microwire;
169 nvm->word_size = 64;
170 nvm->delay_usec = 50;
171 nvm->address_bits = 6;
172 nvm->opcode_bits = 3;
173
174 /* Function Pointers */
175 nvm->ops.read = e1000_read_nvm_microwire;
176 nvm->ops.update = e1000_update_nvm_checksum_generic;
177 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
178 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
179 nvm->ops.write = e1000_write_nvm_microwire;
180
181 return (E1000_SUCCESS);
182 }
183
184 /*
185 * e1000_init_mac_params_82543 - Init MAC func ptrs.
186 * @hw: pointer to the HW structure
187 */
188 static s32
e1000_init_mac_params_82543(struct e1000_hw * hw)189 e1000_init_mac_params_82543(struct e1000_hw *hw)
190 {
191 struct e1000_mac_info *mac = &hw->mac;
192
193 DEBUGFUNC("e1000_init_mac_params_82543");
194
195 /* Set media type */
196 switch (hw->device_id) {
197 case E1000_DEV_ID_82543GC_FIBER:
198 case E1000_DEV_ID_82544EI_FIBER:
199 hw->phy.media_type = e1000_media_type_fiber;
200 break;
201 default:
202 hw->phy.media_type = e1000_media_type_copper;
203 break;
204 }
205
206 /* Set mta register count */
207 mac->mta_reg_count = 128;
208 /* Set rar entry count */
209 mac->rar_entry_count = E1000_RAR_ENTRIES;
210
211 /* Function pointers */
212
213 /* bus type/speed/width */
214 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
215 /* function id */
216 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
217 /* reset */
218 mac->ops.reset_hw = e1000_reset_hw_82543;
219 /* hw initialization */
220 mac->ops.init_hw = e1000_init_hw_82543;
221 /* link setup */
222 mac->ops.setup_link = e1000_setup_link_82543;
223 /* physical interface setup */
224 mac->ops.setup_physical_interface =
225 (hw->phy.media_type == e1000_media_type_copper)
226 ? e1000_setup_copper_link_82543
227 : e1000_setup_fiber_link_82543;
228 /* check for link */
229 mac->ops.check_for_link =
230 (hw->phy.media_type == e1000_media_type_copper)
231 ? e1000_check_for_copper_link_82543
232 : e1000_check_for_fiber_link_82543;
233 /* link info */
234 mac->ops.get_link_up_info =
235 (hw->phy.media_type == e1000_media_type_copper)
236 ? e1000_get_speed_and_duplex_copper_generic
237 : e1000_get_speed_and_duplex_fiber_serdes_generic;
238 /* multicast address update */
239 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
240 /* writing VFTA */
241 mac->ops.write_vfta = e1000_write_vfta_82543;
242 /* clearing VFTA */
243 mac->ops.clear_vfta = e1000_clear_vfta_generic;
244 /* setting MTA */
245 mac->ops.mta_set = e1000_mta_set_82543;
246 /* turn on/off LED */
247 mac->ops.led_on = e1000_led_on_82543;
248 mac->ops.led_off = e1000_led_off_82543;
249 /* clear hardware counters */
250 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82543;
251
252 /* Set tbi compatibility */
253 if ((hw->mac.type != e1000_82543) ||
254 (hw->phy.media_type == e1000_media_type_fiber))
255 e1000_set_tbi_compatibility_82543(hw, false);
256
257 return (E1000_SUCCESS);
258 }
259
260 /*
261 * e1000_init_function_pointers_82543 - Init func ptrs.
262 * @hw: pointer to the HW structure
263 *
264 * Called to initialize all function pointers and parameters.
265 */
266 void
e1000_init_function_pointers_82543(struct e1000_hw * hw)267 e1000_init_function_pointers_82543(struct e1000_hw *hw)
268 {
269 DEBUGFUNC("e1000_init_function_pointers_82543");
270
271 hw->mac.ops.init_params = e1000_init_mac_params_82543;
272 hw->nvm.ops.init_params = e1000_init_nvm_params_82543;
273 hw->phy.ops.init_params = e1000_init_phy_params_82543;
274 }
275
276 /*
277 * e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status
278 * @hw: pointer to the HW structure
279 *
280 * Returns the current status of 10-bit Interface (TBI) compatibility
281 * (enabled/disabled).
282 */
283 static bool
e1000_tbi_compatibility_enabled_82543(struct e1000_hw * hw)284 e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw)
285 {
286 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
287 bool state = false;
288
289 DEBUGFUNC("e1000_tbi_compatibility_enabled_82543");
290
291 if (hw->mac.type != e1000_82543) {
292 DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
293 goto out;
294 }
295
296 state = (dev_spec->tbi_compatibility & TBI_COMPAT_ENABLED)
297 ? true : false;
298
299 out:
300 return (state);
301 }
302
303 /*
304 * e1000_set_tbi_compatibility_82543 - Set TBI compatibility
305 * @hw: pointer to the HW structure
306 * @state: enable/disable TBI compatibility
307 *
308 * Enables or disabled 10-bit Interface (TBI) compatibility.
309 */
310 void
e1000_set_tbi_compatibility_82543(struct e1000_hw * hw,bool state)311 e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, bool state)
312 {
313 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
314
315 DEBUGFUNC("e1000_set_tbi_compatibility_82543");
316
317 if (hw->mac.type != e1000_82543) {
318 DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
319 return;
320 }
321
322 if (state)
323 dev_spec->tbi_compatibility |= TBI_COMPAT_ENABLED;
324 else
325 dev_spec->tbi_compatibility &= ~TBI_COMPAT_ENABLED;
326 }
327
328 /*
329 * e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status
330 * @hw: pointer to the HW structure
331 *
332 * Returns the current status of 10-bit Interface (TBI) store bad packet (SBP)
333 * (enabled/disabled).
334 */
335 bool
e1000_tbi_sbp_enabled_82543(struct e1000_hw * hw)336 e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw)
337 {
338 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
339 bool state = false;
340
341 DEBUGFUNC("e1000_tbi_sbp_enabled_82543");
342
343 if (hw->mac.type != e1000_82543) {
344 DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
345 goto out;
346 }
347
348 state = (dev_spec->tbi_compatibility & TBI_SBP_ENABLED)
349 ? true : false;
350
351 out:
352 return (state);
353 }
354
355 /*
356 * e1000_set_tbi_sbp_82543 - Set TBI SBP
357 * @hw: pointer to the HW structure
358 * @state: enable/disable TBI store bad packet
359 *
360 * Enables or disabled 10-bit Interface (TBI) store bad packet (SBP).
361 */
362 static void
e1000_set_tbi_sbp_82543(struct e1000_hw * hw,bool state)363 e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state)
364 {
365 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
366
367 DEBUGFUNC("e1000_set_tbi_sbp_82543");
368
369 if (state && e1000_tbi_compatibility_enabled_82543(hw))
370 dev_spec->tbi_compatibility |= TBI_SBP_ENABLED;
371 else
372 dev_spec->tbi_compatibility &= ~TBI_SBP_ENABLED;
373 }
374
375 /*
376 * e1000_init_phy_disabled_82543 - Returns init PHY status
377 * @hw: pointer to the HW structure
378 *
379 * Returns the current status of whether PHY initialization is disabled.
380 * True if PHY initialization is disabled else false.
381 */
382 static bool
e1000_init_phy_disabled_82543(struct e1000_hw * hw)383 e1000_init_phy_disabled_82543(struct e1000_hw *hw)
384 {
385 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
386 bool ret_val;
387
388 DEBUGFUNC("e1000_init_phy_disabled_82543");
389
390 if (hw->mac.type != e1000_82543) {
391 ret_val = false;
392 goto out;
393 }
394
395 ret_val = dev_spec->init_phy_disabled;
396
397 out:
398 return (ret_val);
399 }
400
401 /*
402 * e1000_tbi_adjust_stats_82543 - Adjust stats when TBI enabled
403 * @hw: pointer to the HW structure
404 * @stats: Struct containing statistic register values
405 * @frame_len: The length of the frame in question
406 * @mac_addr: The Ethernet destination address of the frame in question
407 * @max_frame_size: The maximum frame size
408 *
409 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
410 */
411 void
e1000_tbi_adjust_stats_82543(struct e1000_hw * hw,struct e1000_hw_stats * stats,u32 frame_len,u8 * mac_addr,u32 max_frame_size)412 e1000_tbi_adjust_stats_82543(struct e1000_hw *hw,
413 struct e1000_hw_stats *stats, u32 frame_len,
414 u8 *mac_addr, u32 max_frame_size)
415 {
416 if (!(e1000_tbi_sbp_enabled_82543(hw)))
417 return;
418
419 /* First adjust the frame length. */
420 frame_len--;
421 /*
422 * We need to adjust the statistics counters, since the hardware
423 * counters overcount this packet as a CRC error and undercount
424 * the packet as a good packet
425 */
426 /* This packet should not be counted as a CRC error. */
427 stats->crcerrs--;
428 /* This packet does count as a Good Packet Received. */
429 stats->gprc++;
430
431 /* Adjust the Good Octets received counters */
432 stats->gorc += frame_len;
433
434 /*
435 * Is this a broadcast or multicast? Check broadcast first, since
436 * the test for a multicast frame will test positive on a broadcast
437 * frame.
438 */
439 if ((mac_addr[0] == 0xff) && (mac_addr[1] == 0xff))
440 /* Broadcast packet */
441 stats->bprc++;
442 else if (*mac_addr & 0x01)
443 /* Multicast packet */
444 stats->mprc++;
445
446 /*
447 * In this case, the hardware has overcounted the number of
448 * oversize frames.
449 */
450 if ((frame_len == max_frame_size) && (stats->roc > 0))
451 stats->roc--;
452
453 /*
454 * Adjust the bin counters when the extra byte put the frame in the
455 * wrong bin. Remember that the frame_len was adjusted above.
456 */
457 if (frame_len == 64) {
458 stats->prc64++;
459 stats->prc127--;
460 } else if (frame_len == 127) {
461 stats->prc127++;
462 stats->prc255--;
463 } else if (frame_len == 255) {
464 stats->prc255++;
465 stats->prc511--;
466 } else if (frame_len == 511) {
467 stats->prc511++;
468 stats->prc1023--;
469 } else if (frame_len == 1023) {
470 stats->prc1023++;
471 stats->prc1522--;
472 } else if (frame_len == 1522) {
473 stats->prc1522++;
474 }
475 }
476
477 /*
478 * e1000_read_phy_reg_82543 - Read PHY register
479 * @hw: pointer to the HW structure
480 * @offset: register offset to be read
481 * @data: pointer to the read data
482 *
483 * Reads the PHY at offset and stores the information read to data.
484 */
485 static s32
e1000_read_phy_reg_82543(struct e1000_hw * hw,u32 offset,u16 * data)486 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 * data)
487 {
488 u32 mdic;
489 s32 ret_val = E1000_SUCCESS;
490
491 DEBUGFUNC("e1000_read_phy_reg_82543");
492
493 if (offset > MAX_PHY_REG_ADDRESS) {
494 DEBUGOUT1("PHY Address %d is out of range\n", offset);
495 ret_val = -E1000_ERR_PARAM;
496 goto out;
497 }
498
499 /*
500 * We must first send a preamble through the MDIO pin to signal the
501 * beginning of an MII instruction. This is done by sending 32
502 * consecutive "1" bits.
503 */
504 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
505
506 /*
507 * Now combine the next few fields that are required for a read
508 * operation. We use this method instead of calling the
509 * e1000_shift_out_mdi_bits routine five different times. The format
510 * of an MII read instruction consists of a shift out of 14 bits and
511 * is defined as follows:
512 * <Preamble><SOF><Op Code><Phy Addr><Offset>
513 * followed by a shift in of 18 bits. This first two bits shifted in
514 * are TurnAround bits used to avoid contention on the MDIO pin when a
515 * READ operation is performed. These two bits are thrown away
516 * followed by a shift in of 16 bits which contains the desired data.
517 */
518 mdic = (offset | (hw->phy.addr << 5) |
519 (PHY_OP_READ << 10) | (PHY_SOF << 12));
520
521 e1000_shift_out_mdi_bits_82543(hw, mdic, 14);
522
523 /*
524 * Now that we've shifted out the read command to the MII, we need to
525 * "shift in" the 16-bit value (18 total bits) of the requested PHY
526 * register address.
527 */
528 *data = e1000_shift_in_mdi_bits_82543(hw);
529
530 out:
531 return (ret_val);
532 }
533
534 /*
535 * e1000_write_phy_reg_82543 - Write PHY register
536 * @hw: pointer to the HW structure
537 * @offset: register offset to be written
538 * @data: pointer to the data to be written at offset
539 *
540 * Writes data to the PHY at offset.
541 */
542 static s32
e1000_write_phy_reg_82543(struct e1000_hw * hw,u32 offset,u16 data)543 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data)
544 {
545 u32 mdic;
546 s32 ret_val = E1000_SUCCESS;
547
548 DEBUGFUNC("e1000_write_phy_reg_82543");
549
550 if (offset > MAX_PHY_REG_ADDRESS) {
551 DEBUGOUT1("PHY Address %d is out of range\n", offset);
552 ret_val = -E1000_ERR_PARAM;
553 goto out;
554 }
555
556 /*
557 * We'll need to use the SW defined pins to shift the write command
558 * out to the PHY. We first send a preamble to the PHY to signal the
559 * beginning of the MII instruction. This is done by sending 32
560 * consecutive "1" bits.
561 */
562 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
563
564 /*
565 * Now combine the remaining required fields that will indicate a
566 * write operation. We use this method instead of calling the
567 * e1000_shift_out_mdi_bits routine for each field in the command. The
568 * format of a MII write instruction is as follows:
569 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
570 */
571 mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) |
572 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
573 mdic <<= 16;
574 mdic |= (u32) data;
575
576 e1000_shift_out_mdi_bits_82543(hw, mdic, 32);
577
578 out:
579 return (ret_val);
580 }
581
582 /*
583 * e1000_raise_mdi_clk_82543 - Raise Management Data Input clock
584 * @hw: pointer to the HW structure
585 * @ctrl: pointer to the control register
586 *
587 * Raise the management data input clock by setting the MDC bit in the control
588 * register.
589 */
590 static void
e1000_raise_mdi_clk_82543(struct e1000_hw * hw,u32 * ctrl)591 e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 * ctrl)
592 {
593 /*
594 * Raise the clock input to the Management Data Clock (by setting the
595 * MDC bit), and then delay a sufficient amount of time.
596 */
597 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC));
598 E1000_WRITE_FLUSH(hw);
599 usec_delay(10);
600 }
601
602 /*
603 * e1000_lower_mdi_clk_82543 - Lower Management Data Input clock
604 * @hw: pointer to the HW structure
605 * @ctrl: pointer to the control register
606 *
607 * Lower the management data input clock by clearing the MDC bit in the control
608 * register.
609 */
610 static void
e1000_lower_mdi_clk_82543(struct e1000_hw * hw,u32 * ctrl)611 e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 * ctrl)
612 {
613 /*
614 * Lower the clock input to the Management Data Clock (by clearing the
615 * MDC bit), and then delay a sufficient amount of time.
616 */
617 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC));
618 E1000_WRITE_FLUSH(hw);
619 usec_delay(10);
620 }
621
622 /*
623 * e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY
624 * @hw: pointer to the HW structure
625 * @data: data to send to the PHY
626 * @count: number of bits to shift out
627 *
628 * We need to shift 'count' bits out to the PHY. So, the value in the
629 * "data" parameter will be shifted out to the PHY one bit at a time.
630 * In order to do this, "data" must be broken down into bits.
631 */
632 static void
e1000_shift_out_mdi_bits_82543(struct e1000_hw * hw,u32 data,u16 count)633 e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
634 u16 count)
635 {
636 u32 ctrl, mask;
637
638 /*
639 * We need to shift "count" number of bits out to the PHY. So, the
640 * value in the "data" parameter will be shifted out to the PHY one
641 * bit at a time. In order to do this, "data" must be broken down
642 * into bits.
643 */
644 mask = 0x01;
645 mask <<= (count - 1);
646
647 ctrl = E1000_READ_REG(hw, E1000_CTRL);
648
649 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
650 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
651
652 while (mask) {
653 /*
654 * A "1" is shifted out to the PHY by setting the MDIO bit to
655 * "1" and then raising and lowering the Management Data Clock.
656 * A "0" is shifted out to the PHY by setting the MDIO bit to
657 * "0" and then raising and lowering the clock.
658 */
659 if (data & mask)
660 ctrl |= E1000_CTRL_MDIO;
661 else
662 ctrl &= ~E1000_CTRL_MDIO;
663
664 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
665 E1000_WRITE_FLUSH(hw);
666
667 usec_delay(10);
668
669 e1000_raise_mdi_clk_82543(hw, &ctrl);
670 e1000_lower_mdi_clk_82543(hw, &ctrl);
671
672 mask >>= 1;
673 }
674 }
675
676 /*
677 * e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY
678 * @hw: pointer to the HW structure
679 *
680 * In order to read a register from the PHY, we need to shift 18 bits
681 * in from the PHY. Bits are "shifted in" by raising the clock input to
682 * the PHY (setting the MDC bit), and then reading the value of the data out
683 * MDIO bit.
684 */
685 static u16
e1000_shift_in_mdi_bits_82543(struct e1000_hw * hw)686 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw)
687 {
688 u32 ctrl;
689 u16 data = 0;
690 u8 i;
691
692 /*
693 * In order to read a register from the PHY, we need to shift in a
694 * total of 18 bits from the PHY. The first two bit (turnaround)
695 * times are used to avoid contention on the MDIO pin when a read
696 * operation is performed. These two bits are ignored by us and
697 * thrown away. Bits are "shifted in" by raising the input to the
698 * Management Data Clock (setting the MDC bit) and then reading the
699 * value of the MDIO bit.
700 */
701 ctrl = E1000_READ_REG(hw, E1000_CTRL);
702
703 /*
704 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as
705 * input.
706 */
707 ctrl &= ~E1000_CTRL_MDIO_DIR;
708 ctrl &= ~E1000_CTRL_MDIO;
709
710 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
711 E1000_WRITE_FLUSH(hw);
712
713 /*
714 * Raise and lower the clock before reading in the data. This accounts
715 * for the turnaround bits. The first clock occurred when we clocked
716 * out the last bit of the Register Address.
717 */
718 e1000_raise_mdi_clk_82543(hw, &ctrl);
719 e1000_lower_mdi_clk_82543(hw, &ctrl);
720
721 for (data = 0, i = 0; i < 16; i++) {
722 data <<= 1;
723 e1000_raise_mdi_clk_82543(hw, &ctrl);
724 ctrl = E1000_READ_REG(hw, E1000_CTRL);
725 /* Check to see if we shifted in a "1". */
726 if (ctrl & E1000_CTRL_MDIO)
727 data |= 1;
728 e1000_lower_mdi_clk_82543(hw, &ctrl);
729 }
730
731 e1000_raise_mdi_clk_82543(hw, &ctrl);
732 e1000_lower_mdi_clk_82543(hw, &ctrl);
733
734 return (data);
735 }
736
737 /*
738 * e1000_phy_force_speed_duplex_82543 - Force speed/duplex for PHY
739 * @hw: pointer to the HW structure
740 *
741 * Calls the function to force speed and duplex for the m88 PHY, and
742 * if the PHY is not auto-negotiating and the speed is forced to 10Mbit,
743 * then call the function for polarity reversal workaround.
744 */
745 static s32
e1000_phy_force_speed_duplex_82543(struct e1000_hw * hw)746 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw)
747 {
748 s32 ret_val;
749
750 DEBUGFUNC("e1000_phy_force_speed_duplex_82543");
751
752 ret_val = e1000_phy_force_speed_duplex_m88(hw);
753 if (ret_val)
754 goto out;
755
756 if (!hw->mac.autoneg &&
757 (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED))
758 ret_val = e1000_polarity_reversal_workaround_82543(hw);
759
760 out:
761 return (ret_val);
762 }
763
764 /*
765 * e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal
766 * @hw: pointer to the HW structure
767 *
768 * When forcing link to 10 Full or 10 Half, the PHY can reverse the polarity
769 * inadvertently. To workaround the issue, we disable the transmitter on
770 * the PHY until we have established the link partner's link parameters.
771 */
772 static s32
e1000_polarity_reversal_workaround_82543(struct e1000_hw * hw)773 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw)
774 {
775 s32 ret_val = E1000_SUCCESS;
776 u16 mii_status_reg;
777 u16 i;
778 bool link;
779
780 if (!(hw->phy.ops.write_reg))
781 goto out;
782
783 /* Polarity reversal workaround for forced 10F/10H links. */
784
785 /* Disable the transmitter on the PHY */
786
787 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
788 if (ret_val)
789 goto out;
790 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
791 if (ret_val)
792 goto out;
793
794 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
795 if (ret_val)
796 goto out;
797
798 /*
799 * This loop will early-out if the NO link condition has been met.
800 * In other words, DO NOT use e1000_phy_has_link_generic() here.
801 */
802 for (i = PHY_FORCE_TIME; i > 0; i--) {
803 /*
804 * Read the MII Status Register and wait for Link Status bit
805 * to be clear.
806 */
807
808 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
809 if (ret_val)
810 goto out;
811
812 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
813 if (ret_val)
814 goto out;
815
816 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0)
817 break;
818 msec_delay_irq(100);
819 }
820
821 /* Recommended delay time after link has been lost */
822 msec_delay_irq(1000);
823
824 /* Now we will re-enable the transmitter on the PHY */
825
826 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
827 if (ret_val)
828 goto out;
829 msec_delay_irq(50);
830 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
831 if (ret_val)
832 goto out;
833 msec_delay_irq(50);
834 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
835 if (ret_val)
836 goto out;
837 msec_delay_irq(50);
838 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
839 if (ret_val)
840 goto out;
841
842 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
843 if (ret_val)
844 goto out;
845
846 /*
847 * Read the MII Status Register and wait for Link Status bit
848 * to be set.
849 */
850 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_TIME, 100000, &link);
851 if (ret_val)
852 goto out;
853
854 out:
855 return (ret_val);
856 }
857
858 /*
859 * e1000_phy_hw_reset_82543 - PHY hardware reset
860 * @hw: pointer to the HW structure
861 *
862 * Sets the PHY_RESET_DIR bit in the extended device control register
863 * to put the PHY into a reset and waits for completion. Once the reset
864 * has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out
865 * of reset.
866 */
867 static s32
e1000_phy_hw_reset_82543(struct e1000_hw * hw)868 e1000_phy_hw_reset_82543(struct e1000_hw *hw)
869 {
870 u32 ctrl_ext;
871 s32 ret_val;
872
873 DEBUGFUNC("e1000_phy_hw_reset_82543");
874
875 /*
876 * Read the Extended Device Control Register, assert the PHY_RESET_DIR
877 * bit to put the PHY into reset...
878 */
879 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
880 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
881 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
882 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
883 E1000_WRITE_FLUSH(hw);
884
885 msec_delay(10);
886
887 /* ...then take it out of reset. */
888 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
889 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
890 E1000_WRITE_FLUSH(hw);
891
892 usec_delay(150);
893
894 if (!(hw->phy.ops.get_cfg_done))
895 return (E1000_SUCCESS);
896
897 ret_val = hw->phy.ops.get_cfg_done(hw);
898
899 return (ret_val);
900 }
901
902 /*
903 * e1000_reset_hw_82543 - Reset hardware
904 * @hw: pointer to the HW structure
905 *
906 * This resets the hardware into a known state.
907 */
908 static s32
e1000_reset_hw_82543(struct e1000_hw * hw)909 e1000_reset_hw_82543(struct e1000_hw *hw)
910 {
911 u32 ctrl;
912 s32 ret_val = E1000_SUCCESS;
913
914 DEBUGFUNC("e1000_reset_hw_82543");
915
916 DEBUGOUT("Masking off all interrupts\n");
917 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
918
919 E1000_WRITE_REG(hw, E1000_RCTL, 0);
920 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
921 E1000_WRITE_FLUSH(hw);
922
923 e1000_set_tbi_sbp_82543(hw, false);
924
925 /*
926 * Delay to allow any outstanding PCI transactions to complete before
927 * resetting the device
928 */
929 msec_delay(10);
930
931 ctrl = E1000_READ_REG(hw, E1000_CTRL);
932
933 DEBUGOUT("Issuing a global reset to 82543/82544 MAC\n");
934 if (hw->mac.type == e1000_82543) {
935 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
936 } else {
937 /*
938 * The 82544 can't ACK the 64-bit write when issuing the
939 * reset, so use IO-mapping as a workaround.
940 */
941 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
942 }
943
944 /*
945 * After MAC reset, force reload of NVM to restore power-on
946 * settings to device.
947 */
948 hw->nvm.ops.reload(hw);
949 msec_delay(2);
950
951 /* Masking off and clearing any pending interrupts */
952 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
953 (void) E1000_READ_REG(hw, E1000_ICR);
954
955 return (ret_val);
956 }
957
958 /*
959 * e1000_init_hw_82543 - Initialize hardware
960 * @hw: pointer to the HW structure
961 *
962 * This inits the hardware readying it for operation.
963 */
964 static s32
e1000_init_hw_82543(struct e1000_hw * hw)965 e1000_init_hw_82543(struct e1000_hw *hw)
966 {
967 struct e1000_mac_info *mac = &hw->mac;
968 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
969 u32 ctrl;
970 s32 ret_val;
971 u16 i;
972
973 DEBUGFUNC("e1000_init_hw_82543");
974
975 /* Disabling VLAN filtering */
976 E1000_WRITE_REG(hw, E1000_VET, 0);
977 mac->ops.clear_vfta(hw);
978
979 /* Setup the receive address. */
980 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
981
982 /* Zero out the Multicast HASH table */
983 DEBUGOUT("Zeroing the MTA\n");
984 for (i = 0; i < mac->mta_reg_count; i++) {
985 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
986 E1000_WRITE_FLUSH(hw);
987 }
988
989 /*
990 * Set the PCI priority bit correctly in the CTRL register. This
991 * determines if the adapter gives priority to receives, or if it
992 * gives equal priority to transmits and receives.
993 */
994 if (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) {
995 ctrl = E1000_READ_REG(hw, E1000_CTRL);
996 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);
997 }
998
999 e1000_pcix_mmrbc_workaround_generic(hw);
1000
1001 /* Setup link and flow control */
1002 ret_val = mac->ops.setup_link(hw);
1003
1004 /*
1005 * Clear all of the statistics registers (clear on read). It is
1006 * important that we do this after we have tried to establish link
1007 * because the symbol error count will increment wildly if there
1008 * is no link.
1009 */
1010 e1000_clear_hw_cntrs_82543(hw);
1011
1012 return (ret_val);
1013 }
1014
1015 /*
1016 * e1000_setup_link_82543 - Setup flow control and link settings
1017 * @hw: pointer to the HW structure
1018 *
1019 * Read the EEPROM to determine the initial polarity value and write the
1020 * extended device control register with the information before calling
1021 * the generic setup link function, which does the following:
1022 * Determines which flow control settings to use, then configures flow
1023 * control. Calls the appropriate media-specific link configuration
1024 * function. Assuming the adapter has a valid link partner, a valid link
1025 * should be established. Assumes the hardware has previously been reset
1026 * and the transmitter and receiver are not enabled.
1027 */
1028 static s32
e1000_setup_link_82543(struct e1000_hw * hw)1029 e1000_setup_link_82543(struct e1000_hw *hw)
1030 {
1031 u32 ctrl_ext;
1032 s32 ret_val;
1033 u16 data;
1034
1035 DEBUGFUNC("e1000_setup_link_82543");
1036
1037 /*
1038 * Take the 4 bits from NVM word 0xF that determine the initial
1039 * polarity value for the SW controlled pins, and setup the
1040 * Extended Device Control reg with that info.
1041 * This is needed because one of the SW controlled pins is used for
1042 * signal detection. So this should be done before phy setup.
1043 */
1044 if (hw->mac.type == e1000_82543) {
1045 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1046 if (ret_val) {
1047 DEBUGOUT("NVM Read Error\n");
1048 ret_val = -E1000_ERR_NVM;
1049 goto out;
1050 }
1051 ctrl_ext = ((data & NVM_WORD0F_SWPDIO_EXT_MASK) <<
1052 NVM_SWDPIO_EXT_SHIFT);
1053 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1054 }
1055
1056 ret_val = e1000_setup_link_generic(hw);
1057
1058 out:
1059 return (ret_val);
1060 }
1061
1062 /*
1063 * e1000_setup_copper_link_82543 - Configure copper link settings
1064 * @hw: pointer to the HW structure
1065 *
1066 * Configures the link for auto-neg or forced speed and duplex. Then we check
1067 * for link, once link is established calls to configure collision distance
1068 * and flow control are called.
1069 */
1070 static s32
e1000_setup_copper_link_82543(struct e1000_hw * hw)1071 e1000_setup_copper_link_82543(struct e1000_hw *hw)
1072 {
1073 u32 ctrl;
1074 s32 ret_val;
1075 bool link;
1076
1077 DEBUGFUNC("e1000_setup_copper_link_82543");
1078
1079 ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU;
1080 /*
1081 * With 82543, we need to force speed and duplex on the MAC
1082 * equal to what the PHY speed and duplex configuration is.
1083 * In addition, we need to perform a hardware reset on the
1084 * PHY to take it out of reset.
1085 */
1086 if (hw->mac.type == e1000_82543) {
1087 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1088 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1089 ret_val = hw->phy.ops.reset(hw);
1090 if (ret_val)
1091 goto out;
1092 hw->phy.reset_disable = false;
1093 } else {
1094 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1095 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1096 }
1097
1098 /* Set MDI/MDI-X, Polarity Reversal, and downshift settings */
1099 ret_val = e1000_copper_link_setup_m88(hw);
1100 if (ret_val)
1101 goto out;
1102
1103 if (hw->mac.autoneg) {
1104 /*
1105 * Setup autoneg and flow control advertisement and perform
1106 * autonegotiation.
1107 */
1108 ret_val = e1000_copper_link_autoneg(hw);
1109 if (ret_val)
1110 goto out;
1111 } else {
1112 /*
1113 * PHY will be set to 10H, 10F, 100H or 100F
1114 * depending on user settings.
1115 */
1116 DEBUGOUT("Forcing Speed and Duplex\n");
1117 ret_val = e1000_phy_force_speed_duplex_82543(hw);
1118 if (ret_val) {
1119 DEBUGOUT("Error Forcing Speed and Duplex\n");
1120 goto out;
1121 }
1122 }
1123
1124 /*
1125 * Check link status. Wait up to 100 microseconds for link to become
1126 * valid.
1127 */
1128 ret_val = e1000_phy_has_link_generic(hw,
1129 COPPER_LINK_UP_LIMIT,
1130 10,
1131 &link);
1132 if (ret_val)
1133 goto out;
1134
1135
1136 if (link) {
1137 DEBUGOUT("Valid link established!!!\n");
1138 /* Config the MAC and PHY after link is up */
1139 if (hw->mac.type == e1000_82544) {
1140 e1000_config_collision_dist_generic(hw);
1141 } else {
1142 ret_val = e1000_config_mac_to_phy_82543(hw);
1143 if (ret_val)
1144 goto out;
1145 }
1146 ret_val = e1000_config_fc_after_link_up_generic(hw);
1147 } else {
1148 /* EMPTY */
1149 DEBUGOUT("Unable to establish link!!!\n");
1150 }
1151
1152 out:
1153 return (ret_val);
1154 }
1155
1156 /*
1157 * e1000_setup_fiber_link_82543 - Setup link for fiber
1158 * @hw: pointer to the HW structure
1159 *
1160 * Configures collision distance and flow control for fiber links. Upon
1161 * successful setup, poll for link.
1162 */
1163 static s32
e1000_setup_fiber_link_82543(struct e1000_hw * hw)1164 e1000_setup_fiber_link_82543(struct e1000_hw *hw)
1165 {
1166 u32 ctrl;
1167 s32 ret_val;
1168
1169 DEBUGFUNC("e1000_setup_fiber_link_82543");
1170
1171 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1172
1173 /* Take the link out of reset */
1174 ctrl &= ~E1000_CTRL_LRST;
1175
1176 e1000_config_collision_dist_generic(hw);
1177
1178 ret_val = e1000_commit_fc_settings_generic(hw);
1179 if (ret_val)
1180 goto out;
1181
1182 DEBUGOUT("Auto-negotiation enabled\n");
1183
1184 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1185 E1000_WRITE_FLUSH(hw);
1186 msec_delay(1);
1187
1188 /*
1189 * For these adapters, the SW definable pin 1 is cleared when the
1190 * optics detect a signal. If we have a signal, then poll for a
1191 * "Link-Up" indication.
1192 */
1193 if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1194 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1195 } else {
1196 /* EMPTY */
1197 DEBUGOUT("No signal detected\n");
1198 }
1199
1200 out:
1201 return (ret_val);
1202 }
1203
1204 /*
1205 * e1000_check_for_copper_link_82543 - Check for link (Copper)
1206 * @hw: pointer to the HW structure
1207 *
1208 * Checks the phy for link, if link exists, do the following:
1209 * - check for downshift
1210 * - do polarity workaround (if necessary)
1211 * - configure collision distance
1212 * - configure flow control after link up
1213 * - configure tbi compatibility
1214 */
1215 static s32
e1000_check_for_copper_link_82543(struct e1000_hw * hw)1216 e1000_check_for_copper_link_82543(struct e1000_hw *hw)
1217 {
1218 struct e1000_mac_info *mac = &hw->mac;
1219 u32 icr, rctl;
1220 s32 ret_val;
1221 u16 speed, duplex;
1222 bool link;
1223
1224 DEBUGFUNC("e1000_check_for_copper_link_82543");
1225
1226 if (!mac->get_link_status) {
1227 ret_val = E1000_SUCCESS;
1228 goto out;
1229 }
1230
1231 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1232 if (ret_val)
1233 goto out;
1234
1235 if (!link)
1236 goto out; /* No link detected */
1237
1238 mac->get_link_status = false;
1239
1240 (void) e1000_check_downshift_generic(hw);
1241
1242 /*
1243 * If we are forcing speed/duplex, then we can return since
1244 * we have already determined whether we have link or not.
1245 */
1246 if (!mac->autoneg) {
1247 /*
1248 * If speed and duplex are forced to 10H or 10F, then we will
1249 * implement the polarity reversal workaround. We disable
1250 * interrupts first, and upon returning, place the devices
1251 * interrupt state to its previous value except for the link
1252 * status change interrupt which will happened due to the
1253 * execution of this workaround.
1254 */
1255 if (mac->forced_speed_duplex & E1000_ALL_10_SPEED) {
1256 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
1257 ret_val = e1000_polarity_reversal_workaround_82543(hw);
1258 icr = E1000_READ_REG(hw, E1000_ICR);
1259 E1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC));
1260 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);
1261 }
1262
1263 ret_val = -E1000_ERR_CONFIG;
1264 goto out;
1265 }
1266
1267 /*
1268 * We have a M88E1000 PHY and Auto-Neg is enabled. If we
1269 * have Si on board that is 82544 or newer, Auto
1270 * Speed Detection takes care of MAC speed/duplex
1271 * configuration. So we only need to configure Collision
1272 * Distance in the MAC. Otherwise, we need to force
1273 * speed/duplex on the MAC to the current PHY speed/duplex
1274 * settings.
1275 */
1276 if (mac->type == e1000_82544)
1277 e1000_config_collision_dist_generic(hw);
1278 else {
1279 ret_val = e1000_config_mac_to_phy_82543(hw);
1280 if (ret_val) {
1281 DEBUGOUT("Error configuring MAC to PHY settings\n");
1282 goto out;
1283 }
1284 }
1285
1286 /*
1287 * Configure Flow Control now that Auto-Neg has completed.
1288 * First, we need to restore the desired flow control
1289 * settings because we may have had to re-autoneg with a
1290 * different link partner.
1291 */
1292 ret_val = e1000_config_fc_after_link_up_generic(hw);
1293 if (ret_val) {
1294 /* EMPTY */
1295 DEBUGOUT("Error configuring flow control\n");
1296 }
1297
1298 /*
1299 * At this point we know that we are on copper and we have
1300 * auto-negotiated link. These are conditions for checking the link
1301 * partner capability register. We use the link speed to determine if
1302 * TBI compatibility needs to be turned on or off. If the link is not
1303 * at gigabit speed, then TBI compatibility is not needed. If we are
1304 * at gigabit speed, we turn on TBI compatibility.
1305 */
1306 if (e1000_tbi_compatibility_enabled_82543(hw)) {
1307 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1308 if (ret_val) {
1309 DEBUGOUT("Error getting link speed and duplex\n");
1310 return (ret_val);
1311 }
1312 if (speed != SPEED_1000) {
1313 /*
1314 * If link speed is not set to gigabit speed,
1315 * we do not need to enable TBI compatibility.
1316 */
1317 if (e1000_tbi_sbp_enabled_82543(hw)) {
1318 /*
1319 * If we previously were in the mode,
1320 * turn it off.
1321 */
1322 e1000_set_tbi_sbp_82543(hw, false);
1323 rctl = E1000_READ_REG(hw, E1000_RCTL);
1324 rctl &= ~E1000_RCTL_SBP;
1325 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1326 }
1327 } else {
1328 /*
1329 * If TBI compatibility is was previously off,
1330 * turn it on. For compatibility with a TBI link
1331 * partner, we will store bad packets. Some
1332 * frames have an additional byte on the end and
1333 * will look like CRC errors to to the hardware.
1334 */
1335 if (!e1000_tbi_sbp_enabled_82543(hw)) {
1336 e1000_set_tbi_sbp_82543(hw, true);
1337 rctl = E1000_READ_REG(hw, E1000_RCTL);
1338 rctl |= E1000_RCTL_SBP;
1339 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1340 }
1341 }
1342 }
1343 out:
1344 return (ret_val);
1345 }
1346
1347 /*
1348 * e1000_check_for_fiber_link_82543 - Check for link (Fiber)
1349 * @hw: pointer to the HW structure
1350 *
1351 * Checks for link up on the hardware. If link is not up and we have
1352 * a signal, then we need to force link up.
1353 */
1354 static s32
e1000_check_for_fiber_link_82543(struct e1000_hw * hw)1355 e1000_check_for_fiber_link_82543(struct e1000_hw *hw)
1356 {
1357 struct e1000_mac_info *mac = &hw->mac;
1358 u32 rxcw, ctrl, status;
1359 s32 ret_val = E1000_SUCCESS;
1360
1361 DEBUGFUNC("e1000_check_for_fiber_link_82543");
1362
1363 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1364 status = E1000_READ_REG(hw, E1000_STATUS);
1365 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1366
1367 /*
1368 * If we don't have link (auto-negotiation failed or link partner
1369 * cannot auto-negotiate), the cable is plugged in (we have signal),
1370 * and our link partner is not trying to auto-negotiate with us (we
1371 * are receiving idles or data), we need to force link up. We also
1372 * need to give auto-negotiation time to complete, in case the cable
1373 * was just plugged in. The autoneg_failed flag does this.
1374 */
1375 /* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */
1376 if ((!(ctrl & E1000_CTRL_SWDPIN1)) &&
1377 (!(status & E1000_STATUS_LU)) &&
1378 (!(rxcw & E1000_RXCW_C))) {
1379 if (mac->autoneg_failed == 0) {
1380 mac->autoneg_failed = 1;
1381 ret_val = 0;
1382 goto out;
1383 }
1384 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
1385
1386 /* Disable auto-negotiation in the TXCW register */
1387 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1388
1389 /* Force link-up and also force full-duplex. */
1390 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1391 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1392 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1393
1394 /* Configure Flow Control after forcing link up. */
1395 ret_val = e1000_config_fc_after_link_up_generic(hw);
1396 if (ret_val) {
1397 DEBUGOUT("Error configuring flow control\n");
1398 goto out;
1399 }
1400 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
1401 /*
1402 * If we are forcing link and we are receiving /C/ ordered
1403 * sets, re-enable auto-negotiation in the TXCW register
1404 * and disable forced link in the Device Control register
1405 * in an attempt to auto-negotiate with our link partner.
1406 */
1407 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
1408 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1409 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
1410
1411 mac->serdes_has_link = true;
1412 }
1413
1414 out:
1415 return (ret_val);
1416 }
1417
1418 /*
1419 * e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings
1420 * @hw: pointer to the HW structure
1421 *
1422 * For the 82543 silicon, we need to set the MAC to match the settings
1423 * of the PHY, even if the PHY is auto-negotiating.
1424 */
1425 static s32
e1000_config_mac_to_phy_82543(struct e1000_hw * hw)1426 e1000_config_mac_to_phy_82543(struct e1000_hw *hw)
1427 {
1428 u32 ctrl;
1429 s32 ret_val = E1000_SUCCESS;
1430 u16 phy_data;
1431
1432 DEBUGFUNC("e1000_config_mac_to_phy_82543");
1433
1434 if (!(hw->phy.ops.read_reg))
1435 goto out;
1436
1437 /* Set the bits to force speed and duplex */
1438 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1439 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1440 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1441
1442 /*
1443 * Set up duplex in the Device Control and Transmit Control
1444 * registers depending on negotiated values.
1445 */
1446 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1447 if (ret_val)
1448 goto out;
1449
1450 ctrl &= ~E1000_CTRL_FD;
1451 if (phy_data & M88E1000_PSSR_DPLX)
1452 ctrl |= E1000_CTRL_FD;
1453
1454 e1000_config_collision_dist_generic(hw);
1455
1456 /*
1457 * Set up speed in the Device Control register depending on
1458 * negotiated values.
1459 */
1460 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1461 ctrl |= E1000_CTRL_SPD_1000;
1462 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1463 ctrl |= E1000_CTRL_SPD_100;
1464
1465 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1466
1467 out:
1468 return (ret_val);
1469 }
1470
1471 /*
1472 * e1000_write_vfta_82543 - Write value to VLAN filter table
1473 * @hw: pointer to the HW structure
1474 * @offset: the 32-bit offset in which to write the value to.
1475 * @value: the 32-bit value to write at location offset.
1476 *
1477 * This writes a 32-bit value to a 32-bit offset in the VLAN filter
1478 * table.
1479 */
1480 static void
e1000_write_vfta_82543(struct e1000_hw * hw,u32 offset,u32 value)1481 e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value)
1482 {
1483 u32 temp;
1484
1485 DEBUGFUNC("e1000_write_vfta_82543");
1486
1487 if ((hw->mac.type == e1000_82544) && (offset & 1)) {
1488 temp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1);
1489 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
1490 E1000_WRITE_FLUSH(hw);
1491 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp);
1492 E1000_WRITE_FLUSH(hw);
1493 } else {
1494 e1000_write_vfta_generic(hw, offset, value);
1495 }
1496 }
1497
1498 /*
1499 * e1000_mta_set_82543 - Set multicast filter table address
1500 * @hw: pointer to the HW structure
1501 * @hash_value: determines the MTA register and bit to set
1502 *
1503 * The multicast table address is a register array of 32-bit registers.
1504 * The hash_value is used to determine what register the bit is in, the
1505 * current value is read, the new bit is OR'd in and the new value is
1506 * written back into the register.
1507 */
1508 static void
e1000_mta_set_82543(struct e1000_hw * hw,u32 hash_value)1509 e1000_mta_set_82543(struct e1000_hw *hw, u32 hash_value)
1510 {
1511 u32 hash_bit, hash_reg, mta, temp;
1512
1513 DEBUGFUNC("e1000_mta_set_82543");
1514
1515 hash_reg = (hash_value >> 5);
1516
1517 /*
1518 * If we are on an 82544 and we are trying to write an odd offset
1519 * in the MTA, save off the previous entry before writing and
1520 * restore the old value after writing.
1521 */
1522 if ((hw->mac.type == e1000_82544) && (hash_reg & 1)) {
1523 hash_reg &= (hw->mac.mta_reg_count - 1);
1524 hash_bit = hash_value & 0x1F;
1525 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg);
1526 mta |= (1 << hash_bit);
1527 temp = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg - 1);
1528
1529 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta);
1530 E1000_WRITE_FLUSH(hw);
1531 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg - 1, temp);
1532 E1000_WRITE_FLUSH(hw);
1533 } else {
1534 e1000_mta_set_generic(hw, hash_value);
1535 }
1536 }
1537
1538 /*
1539 * e1000_led_on_82543 - Turn on SW controllable LED
1540 * @hw: pointer to the HW structure
1541 *
1542 * Turns the SW defined LED on.
1543 */
1544 static s32
e1000_led_on_82543(struct e1000_hw * hw)1545 e1000_led_on_82543(struct e1000_hw *hw)
1546 {
1547 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1548
1549 DEBUGFUNC("e1000_led_on_82543");
1550
1551 if (hw->mac.type == e1000_82544 &&
1552 hw->phy.media_type == e1000_media_type_copper) {
1553 /* Clear SW-definable Pin 0 to turn on the LED */
1554 ctrl &= ~E1000_CTRL_SWDPIN0;
1555 ctrl |= E1000_CTRL_SWDPIO0;
1556 } else {
1557 /* Fiber 82544 and all 82543 use this method */
1558 ctrl |= E1000_CTRL_SWDPIN0;
1559 ctrl |= E1000_CTRL_SWDPIO0;
1560 }
1561 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1562
1563 return (E1000_SUCCESS);
1564 }
1565
1566 /*
1567 * e1000_led_off_82543 - Turn off SW controllable LED
1568 * @hw: pointer to the HW structure
1569 *
1570 * Turns the SW defined LED off.
1571 */
1572 static s32
e1000_led_off_82543(struct e1000_hw * hw)1573 e1000_led_off_82543(struct e1000_hw *hw)
1574 {
1575 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1576
1577 DEBUGFUNC("e1000_led_off_82543");
1578
1579 if (hw->mac.type == e1000_82544 &&
1580 hw->phy.media_type == e1000_media_type_copper) {
1581 /* Set SW-definable Pin 0 to turn off the LED */
1582 ctrl |= E1000_CTRL_SWDPIN0;
1583 ctrl |= E1000_CTRL_SWDPIO0;
1584 } else {
1585 ctrl &= ~E1000_CTRL_SWDPIN0;
1586 ctrl |= E1000_CTRL_SWDPIO0;
1587 }
1588 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1589
1590 return (E1000_SUCCESS);
1591 }
1592
1593 /*
1594 * e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters
1595 * @hw: pointer to the HW structure
1596 *
1597 * Clears the hardware counters by reading the counter registers.
1598 */
1599 static void
e1000_clear_hw_cntrs_82543(struct e1000_hw * hw)1600 e1000_clear_hw_cntrs_82543(struct e1000_hw *hw)
1601 {
1602 DEBUGFUNC("e1000_clear_hw_cntrs_82543");
1603
1604 e1000_clear_hw_cntrs_base_generic(hw);
1605
1606 (void) E1000_READ_REG(hw, E1000_PRC64);
1607 (void) E1000_READ_REG(hw, E1000_PRC127);
1608 (void) E1000_READ_REG(hw, E1000_PRC255);
1609 (void) E1000_READ_REG(hw, E1000_PRC511);
1610 (void) E1000_READ_REG(hw, E1000_PRC1023);
1611 (void) E1000_READ_REG(hw, E1000_PRC1522);
1612 (void) E1000_READ_REG(hw, E1000_PTC64);
1613 (void) E1000_READ_REG(hw, E1000_PTC127);
1614 (void) E1000_READ_REG(hw, E1000_PTC255);
1615 (void) E1000_READ_REG(hw, E1000_PTC511);
1616 (void) E1000_READ_REG(hw, E1000_PTC1023);
1617 (void) E1000_READ_REG(hw, E1000_PTC1522);
1618
1619 (void) E1000_READ_REG(hw, E1000_ALGNERRC);
1620 (void) E1000_READ_REG(hw, E1000_RXERRC);
1621 (void) E1000_READ_REG(hw, E1000_TNCRS);
1622 (void) E1000_READ_REG(hw, E1000_CEXTERR);
1623 (void) E1000_READ_REG(hw, E1000_TSCTC);
1624 (void) E1000_READ_REG(hw, E1000_TSCTFC);
1625 }
1626