1 /*
2 * This file is provided under a CDDLv1 license. When using or
3 * redistributing this file, you may do so under this license.
4 * In redistributing this file this license must be included
5 * and no other modification of this header file is permitted.
6 *
7 * CDDL LICENSE SUMMARY
8 *
9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved.
10 *
11 * The contents of this file are subject to the terms of Version
12 * 1.0 of the Common Development and Distribution License (the "License").
13 *
14 * You should have received a copy of the License with this software.
15 * You can obtain a copy of the License at
16 * http://www.opensolaris.org/os/licensing.
17 * See the License for the specific language governing permissions
18 * and limitations under the License.
19 */
20
21 /*
22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms of the CDDLv1.
24 */
25
26 /*
27 * IntelVersion: 1.151 v3-1-10-1_2009-9-18_Release14-6
28 */
29 #include "e1000_api.h"
30
31 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
32 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
33 u16 *data, bool read);
34
35 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
36 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
37 u16 *data, bool read);
38
39 /* Cable length tables */
40 static const u16 e1000_m88_cable_length_table[] =
41 {0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED};
42
43 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
44 (sizeof (e1000_m88_cable_length_table) / \
45 sizeof (e1000_m88_cable_length_table[0]))
46
47 static const u16 e1000_igp_2_cable_length_table[] =
48 {0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
49 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
50 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
51 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
52 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
53 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
54 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
55 104, 109, 114, 118, 121, 124};
56
57 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
58 (sizeof (e1000_igp_2_cable_length_table) / \
59 sizeof (e1000_igp_2_cable_length_table[0]))
60
61 /*
62 * e1000_init_phy_ops_generic - Initialize PHY function pointers
63 * @hw: pointer to the HW structure
64 *
65 * Setups up the function pointers to no-op functions
66 */
67 void
e1000_init_phy_ops_generic(struct e1000_hw * hw)68 e1000_init_phy_ops_generic(struct e1000_hw *hw)
69 {
70 struct e1000_phy_info *phy = &hw->phy;
71 DEBUGFUNC("e1000_init_phy_ops_generic");
72
73 /* Initialize function pointers */
74 phy->ops.init_params = e1000_null_ops_generic;
75 phy->ops.acquire = e1000_null_ops_generic;
76 phy->ops.check_polarity = e1000_null_ops_generic;
77 phy->ops.check_reset_block = e1000_null_ops_generic;
78 phy->ops.commit = e1000_null_ops_generic;
79 phy->ops.force_speed_duplex = e1000_null_ops_generic;
80 phy->ops.get_cfg_done = e1000_null_ops_generic;
81 phy->ops.get_cable_length = e1000_null_ops_generic;
82 phy->ops.get_info = e1000_null_ops_generic;
83 phy->ops.read_reg = e1000_null_read_reg;
84 phy->ops.read_reg_locked = e1000_null_read_reg;
85 phy->ops.release = e1000_null_phy_generic;
86 phy->ops.reset = e1000_null_ops_generic;
87 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
88 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
89 phy->ops.write_reg = e1000_null_write_reg;
90 phy->ops.write_reg_locked = e1000_null_write_reg;
91 phy->ops.power_up = e1000_null_phy_generic;
92 phy->ops.power_down = e1000_null_phy_generic;
93 phy->ops.cfg_on_link_up = e1000_null_ops_generic;
94 }
95
96 /*
97 * e1000_null_read_reg - No-op function, return 0
98 * @hw: pointer to the HW structure
99 */
100 s32
e1000_null_read_reg(struct e1000_hw * hw,u32 offset,u16 * data)101 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data)
102 {
103 DEBUGFUNC("e1000_null_read_reg");
104 UNREFERENCED_3PARAMETER(hw, offset, data);
105 return (E1000_SUCCESS);
106 }
107
108 /*
109 * e1000_null_phy_generic - No-op function, return void
110 * @hw: pointer to the HW structure
111 */
112 void
e1000_null_phy_generic(struct e1000_hw * hw)113 e1000_null_phy_generic(struct e1000_hw *hw)
114 {
115 DEBUGFUNC("e1000_null_phy_generic");
116 UNREFERENCED_1PARAMETER(hw);
117 }
118
119 /*
120 * e1000_null_lplu_state - No-op function, return 0
121 * @hw: pointer to the HW structure
122 */
123 s32
e1000_null_lplu_state(struct e1000_hw * hw,bool active)124 e1000_null_lplu_state(struct e1000_hw *hw, bool active)
125 {
126 DEBUGFUNC("e1000_null_lplu_state");
127 UNREFERENCED_2PARAMETER(hw, active);
128 return (E1000_SUCCESS);
129 }
130
131 /*
132 * e1000_null_write_reg - No-op function, return 0
133 * @hw: pointer to the HW structure
134 */
135 s32
e1000_null_write_reg(struct e1000_hw * hw,u32 offset,u16 data)136 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data)
137 {
138 DEBUGFUNC("e1000_null_write_reg");
139 UNREFERENCED_3PARAMETER(hw, offset, data);
140 return (E1000_SUCCESS);
141 }
142
143 /*
144 * e1000_check_reset_block_generic - Check if PHY reset is blocked
145 * @hw: pointer to the HW structure
146 *
147 * Read the PHY management control register and check whether a PHY reset
148 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
149 * return E1000_BLK_PHY_RESET (12).
150 */
151 s32
e1000_check_reset_block_generic(struct e1000_hw * hw)152 e1000_check_reset_block_generic(struct e1000_hw *hw)
153 {
154 u32 manc;
155
156 DEBUGFUNC("e1000_check_reset_block");
157
158 manc = E1000_READ_REG(hw, E1000_MANC);
159
160 return ((manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
161 E1000_BLK_PHY_RESET : E1000_SUCCESS);
162 }
163
164 /*
165 * e1000_get_phy_id - Retrieve the PHY ID and revision
166 * @hw: pointer to the HW structure
167 *
168 * Reads the PHY registers and stores the PHY ID and possibly the PHY
169 * revision in the hardware structure.
170 */
171 s32
e1000_get_phy_id(struct e1000_hw * hw)172 e1000_get_phy_id(struct e1000_hw *hw)
173 {
174 struct e1000_phy_info *phy = &hw->phy;
175 s32 ret_val = E1000_SUCCESS;
176 u16 phy_id;
177 u16 retry_count = 0;
178
179 DEBUGFUNC("e1000_get_phy_id");
180
181 if (!(phy->ops.read_reg))
182 goto out;
183
184 while (retry_count < 2) {
185 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
186 if (ret_val)
187 goto out;
188
189 phy->id = (u32)(phy_id << 16);
190 usec_delay(20);
191 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
192 if (ret_val)
193 goto out;
194
195 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
196 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
197
198 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
199 goto out;
200
201 /*
202 * If the PHY ID is still unknown, we may have an 82577
203 * without link. We will try again after setting Slow MDIC
204 * mode. No harm in trying again in this case since the PHY
205 * ID is unknown at this point anyway.
206 */
207 ret_val = phy->ops.acquire(hw);
208 if (ret_val)
209 goto out;
210 ret_val = e1000_set_mdio_slow_mode_hv(hw, true);
211 if (ret_val)
212 goto out;
213 phy->ops.release(hw);
214
215 retry_count++;
216 }
217 out:
218 /* Revert to MDIO fast mode, if applicable */
219 if (retry_count) {
220 ret_val = phy->ops.acquire(hw);
221 if (ret_val)
222 return (ret_val);
223 ret_val = e1000_set_mdio_slow_mode_hv(hw, false);
224 phy->ops.release(hw);
225 }
226
227 return (ret_val);
228 }
229
230 /*
231 * e1000_phy_reset_dsp_generic - Reset PHY DSP
232 * @hw: pointer to the HW structure
233 *
234 * Reset the digital signal processor.
235 */
236 s32
e1000_phy_reset_dsp_generic(struct e1000_hw * hw)237 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
238 {
239 s32 ret_val = E1000_SUCCESS;
240
241 DEBUGFUNC("e1000_phy_reset_dsp_generic");
242
243 if (!(hw->phy.ops.write_reg))
244 goto out;
245
246 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
247 if (ret_val)
248 goto out;
249
250 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
251
252 out:
253 return (ret_val);
254 }
255
256 /*
257 * e1000_read_phy_reg_mdic - Read MDI control register
258 * @hw: pointer to the HW structure
259 * @offset: register offset to be read
260 * @data: pointer to the read data
261 *
262 * Reads the MDI control register in the PHY at offset and stores the
263 * information read to data.
264 */
265 s32
e1000_read_phy_reg_mdic(struct e1000_hw * hw,u32 offset,u16 * data)266 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
267 {
268 struct e1000_phy_info *phy = &hw->phy;
269 u32 i, mdic = 0;
270 s32 ret_val = E1000_SUCCESS;
271
272 DEBUGFUNC("e1000_read_phy_reg_mdic");
273
274 /*
275 * Set up Op-code, Phy Address, and register offset in the MDI Control
276 * register. The MAC will take care of interfacing with the PHY to
277 * retrieve the desired data.
278 */
279 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
280 (phy->addr << E1000_MDIC_PHY_SHIFT) |
281 (E1000_MDIC_OP_READ));
282
283 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
284
285 /*
286 * Poll the ready bit to see if the MDI read completed
287 * Increasing the time out as testing showed failures with
288 * the lower time out
289 */
290 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
291 usec_delay(50);
292 mdic = E1000_READ_REG(hw, E1000_MDIC);
293 if (mdic & E1000_MDIC_READY)
294 break;
295 }
296 if (!(mdic & E1000_MDIC_READY)) {
297 DEBUGOUT("MDI Read did not complete\n");
298 ret_val = -E1000_ERR_PHY;
299 goto out;
300 }
301 if (mdic & E1000_MDIC_ERROR) {
302 DEBUGOUT("MDI Error\n");
303 ret_val = -E1000_ERR_PHY;
304 goto out;
305 }
306 *data = (u16)mdic;
307
308 out:
309 return (ret_val);
310 }
311
312 /*
313 * e1000_write_phy_reg_mdic - Write MDI control register
314 * @hw: pointer to the HW structure
315 * @offset: register offset to write to
316 * @data: data to write to register at offset
317 *
318 * Writes data to MDI control register in the PHY at offset.
319 */
320 s32
e1000_write_phy_reg_mdic(struct e1000_hw * hw,u32 offset,u16 data)321 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
322 {
323 struct e1000_phy_info *phy = &hw->phy;
324 u32 i, mdic = 0;
325 s32 ret_val = E1000_SUCCESS;
326
327 DEBUGFUNC("e1000_write_phy_reg_mdic");
328
329 /*
330 * Set up Op-code, Phy Address, and register offset in the MDI Control
331 * register. The MAC will take care of interfacing with the PHY to
332 * retrieve the desired data.
333 */
334 mdic = (((u32)data) |
335 (offset << E1000_MDIC_REG_SHIFT) |
336 (phy->addr << E1000_MDIC_PHY_SHIFT) |
337 (E1000_MDIC_OP_WRITE));
338
339 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
340
341 /*
342 * Poll the ready bit to see if the MDI read completed
343 * Increasing the time out as testing showed failures with
344 * the lower time out
345 */
346 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
347 usec_delay(50);
348 mdic = E1000_READ_REG(hw, E1000_MDIC);
349 if (mdic & E1000_MDIC_READY)
350 break;
351 }
352 if (!(mdic & E1000_MDIC_READY)) {
353 DEBUGOUT("MDI Write did not complete\n");
354 ret_val = -E1000_ERR_PHY;
355 goto out;
356 }
357 if (mdic & E1000_MDIC_ERROR) {
358 DEBUGOUT("MDI Error\n");
359 ret_val = -E1000_ERR_PHY;
360 goto out;
361 }
362
363 out:
364 return (ret_val);
365 }
366
367 /*
368 * e1000_read_phy_reg_m88 - Read m88 PHY register
369 * @hw: pointer to the HW structure
370 * @offset: register offset to be read
371 * @data: pointer to the read data
372 *
373 * Acquires semaphore, if necessary, then reads the PHY register at offset
374 * and storing the retrieved information in data. Release any acquired
375 * semaphores before exiting.
376 */
377 s32
e1000_read_phy_reg_m88(struct e1000_hw * hw,u32 offset,u16 * data)378 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
379 {
380 s32 ret_val = E1000_SUCCESS;
381
382 DEBUGFUNC("e1000_read_phy_reg_m88");
383
384 if (!(hw->phy.ops.acquire))
385 goto out;
386
387 ret_val = hw->phy.ops.acquire(hw);
388 if (ret_val)
389 goto out;
390
391 ret_val = e1000_read_phy_reg_mdic(hw,
392 MAX_PHY_REG_ADDRESS & offset,
393 data);
394
395 hw->phy.ops.release(hw);
396
397 out:
398 return (ret_val);
399 }
400
401 /*
402 * e1000_write_phy_reg_m88 - Write m88 PHY register
403 * @hw: pointer to the HW structure
404 * @offset: register offset to write to
405 * @data: data to write at register offset
406 *
407 * Acquires semaphore, if necessary, then writes the data to PHY register
408 * at the offset. Release any acquired semaphores before exiting.
409 */
410 s32
e1000_write_phy_reg_m88(struct e1000_hw * hw,u32 offset,u16 data)411 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
412 {
413 s32 ret_val = E1000_SUCCESS;
414
415 DEBUGFUNC("e1000_write_phy_reg_m88");
416
417 if (!(hw->phy.ops.acquire))
418 goto out;
419
420 ret_val = hw->phy.ops.acquire(hw);
421 if (ret_val)
422 goto out;
423
424 ret_val = e1000_write_phy_reg_mdic(hw,
425 MAX_PHY_REG_ADDRESS & offset,
426 data);
427
428 hw->phy.ops.release(hw);
429
430 out:
431 return (ret_val);
432 }
433
434 /*
435 * e1000_read_phy_reg_igp - Read igp PHY register
436 * @hw: pointer to the HW structure
437 * @offset: register offset to be read
438 * @data: pointer to the read data
439 * @locked: semaphore has already been acquired or not
440 *
441 * Acquires semaphore, if necessary, then reads the PHY register at offset
442 * and stores the retrieved information in data. Release any acquired
443 * semaphores before exiting.
444 */
445 static s32
__e1000_read_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 * data,bool locked)446 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
447 bool locked)
448 {
449 s32 ret_val = E1000_SUCCESS;
450
451 DEBUGFUNC("__e1000_read_phy_reg_igp");
452
453 if (!locked) {
454 if (!(hw->phy.ops.acquire))
455 goto out;
456
457 ret_val = hw->phy.ops.acquire(hw);
458 if (ret_val)
459 goto out;
460 }
461
462 if (offset > MAX_PHY_MULTI_PAGE_REG) {
463 ret_val = e1000_write_phy_reg_mdic(hw,
464 IGP01E1000_PHY_PAGE_SELECT, (u16)offset);
465 if (ret_val)
466 goto release;
467 }
468
469 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
470 data);
471
472 release:
473 if (!locked)
474 hw->phy.ops.release(hw);
475 out:
476 return (ret_val);
477 }
478
479 /*
480 * e1000_read_phy_reg_igp - Read igp PHY register
481 * @hw: pointer to the HW structure
482 * @offset: register offset to be read
483 * @data: pointer to the read data
484 *
485 * Acquires semaphore then reads the PHY register at offset and stores the
486 * retrieved information in data.
487 * Release the acquired semaphore before exiting.
488 */
489 s32
e1000_read_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 * data)490 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
491 {
492 return (__e1000_read_phy_reg_igp(hw, offset, data, false));
493 }
494
495 /*
496 * e1000_read_phy_reg_igp_locked - Read igp PHY register
497 * @hw: pointer to the HW structure
498 * @offset: register offset to be read
499 * @data: pointer to the read data
500 *
501 * Reads the PHY register at offset and stores the retrieved information
502 * in data. Assumes semaphore already acquired.
503 */
504 s32
e1000_read_phy_reg_igp_locked(struct e1000_hw * hw,u32 offset,u16 * data)505 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
506 {
507 return (__e1000_read_phy_reg_igp(hw, offset, data, true));
508 }
509
510 /*
511 * e1000_write_phy_reg_igp - Write igp PHY register
512 * @hw: pointer to the HW structure
513 * @offset: register offset to write to
514 * @data: data to write at register offset
515 * @locked: semaphore has already been acquired or not
516 *
517 * Acquires semaphore, if necessary, then writes the data to PHY register
518 * at the offset. Release any acquired semaphores before exiting.
519 */
520 static s32
__e1000_write_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 data,bool locked)521 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
522 bool locked)
523 {
524 s32 ret_val = E1000_SUCCESS;
525
526 DEBUGFUNC("e1000_write_phy_reg_igp");
527
528 if (!locked) {
529 if (!(hw->phy.ops.acquire))
530 goto out;
531
532 ret_val = hw->phy.ops.acquire(hw);
533 if (ret_val)
534 goto out;
535 }
536
537 if (offset > MAX_PHY_MULTI_PAGE_REG) {
538 ret_val = e1000_write_phy_reg_mdic(hw,
539 IGP01E1000_PHY_PAGE_SELECT, (u16)offset);
540 if (ret_val)
541 goto release;
542 }
543
544 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
545 data);
546
547 release:
548 if (!locked)
549 hw->phy.ops.release(hw);
550
551 out:
552 return (ret_val);
553 }
554
555 /*
556 * e1000_write_phy_reg_igp - Write igp PHY register
557 * @hw: pointer to the HW structure
558 * @offset: register offset to write to
559 * @data: data to write at register offset
560 *
561 * Acquires semaphore then writes the data to PHY register
562 * at the offset. Release any acquired semaphores before exiting.
563 */
564 s32
e1000_write_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 data)565 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
566 {
567 return (__e1000_write_phy_reg_igp(hw, offset, data, false));
568 }
569
570 /*
571 * e1000_write_phy_reg_igp_locked - Write igp PHY register
572 * @hw: pointer to the HW structure
573 * @offset: register offset to write to
574 * @data: data to write at register offset
575 *
576 * Writes the data to PHY register at the offset.
577 * Assumes semaphore already acquired.
578 */
579 s32
e1000_write_phy_reg_igp_locked(struct e1000_hw * hw,u32 offset,u16 data)580 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
581 {
582 return (__e1000_write_phy_reg_igp(hw, offset, data, true));
583 }
584
585 /*
586 * __e1000_read_kmrn_reg - Read kumeran register
587 * @hw: pointer to the HW structure
588 * @offset: register offset to be read
589 * @data: pointer to the read data
590 * @locked: semaphore has already been acquired or not
591 *
592 * Acquires semaphore, if necessary. Then reads the PHY register at offset
593 * using the kumeran interface. The information retrieved is stored in data.
594 * Release any acquired semaphores before exiting.
595 */
596 static s32
__e1000_read_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 * data,bool locked)597 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, bool locked)
598 {
599 u32 kmrnctrlsta;
600 s32 ret_val = E1000_SUCCESS;
601
602 DEBUGFUNC("__e1000_read_kmrn_reg");
603
604 if (!locked) {
605 if (!(hw->phy.ops.acquire))
606 goto out;
607
608 ret_val = hw->phy.ops.acquire(hw);
609 if (ret_val)
610 goto out;
611 }
612
613 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
614 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
615 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
616
617 usec_delay(2);
618
619 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
620 *data = (u16)kmrnctrlsta;
621
622 if (!locked)
623 hw->phy.ops.release(hw);
624
625 out:
626 return (ret_val);
627 }
628
629 /*
630 * e1000_read_kmrn_reg_generic - Read kumeran register
631 * @hw: pointer to the HW structure
632 * @offset: register offset to be read
633 * @data: pointer to the read data
634 *
635 * Acquires semaphore then reads the PHY register at offset using the
636 * kumeran interface. The information retrieved is stored in data.
637 * Release the acquired semaphore before exiting.
638 */
639 s32
e1000_read_kmrn_reg_generic(struct e1000_hw * hw,u32 offset,u16 * data)640 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
641 {
642 return (__e1000_read_kmrn_reg(hw, offset, data, false));
643 }
644
645 /*
646 * e1000_read_kmrn_reg_locked - Read kumeran register
647 * @hw: pointer to the HW structure
648 * @offset: register offset to be read
649 * @data: pointer to the read data
650 *
651 * Reads the PHY register at offset using the kumeran interface. The
652 * information retrieved is stored in data.
653 * Assumes semaphore already acquired.
654 */
655 s32
e1000_read_kmrn_reg_locked(struct e1000_hw * hw,u32 offset,u16 * data)656 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
657 {
658 return (__e1000_read_kmrn_reg(hw, offset, data, true));
659 }
660
661 /*
662 * __e1000_write_kmrn_reg - Write kumeran register
663 * @hw: pointer to the HW structure
664 * @offset: register offset to write to
665 * @data: data to write at register offset
666 * @locked: semaphore has already been acquired or not
667 *
668 * Acquires semaphore, if necessary. Then write the data to PHY register
669 * at the offset using the kumeran interface. Release any acquired semaphores
670 * before exiting.
671 */
672 static s32
__e1000_write_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 data,bool locked)673 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, bool locked)
674 {
675 u32 kmrnctrlsta;
676 s32 ret_val = E1000_SUCCESS;
677
678 DEBUGFUNC("e1000_write_kmrn_reg_generic");
679
680 if (!locked) {
681 if (!(hw->phy.ops.acquire))
682 goto out;
683
684 ret_val = hw->phy.ops.acquire(hw);
685 if (ret_val)
686 goto out;
687 }
688
689 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
690 E1000_KMRNCTRLSTA_OFFSET) | data;
691 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
692
693 usec_delay(2);
694
695 if (!locked)
696 hw->phy.ops.release(hw);
697
698 out:
699 return (ret_val);
700 }
701
702 /*
703 * e1000_write_kmrn_reg_generic - Write kumeran register
704 * @hw: pointer to the HW structure
705 * @offset: register offset to write to
706 * @data: data to write at register offset
707 *
708 * Acquires semaphore then writes the data to the PHY register at the offset
709 * using the kumeran interface. Release the acquired semaphore before exiting.
710 */
711 s32
e1000_write_kmrn_reg_generic(struct e1000_hw * hw,u32 offset,u16 data)712 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
713 {
714 return (__e1000_write_kmrn_reg(hw, offset, data, false));
715 }
716
717 /*
718 * e1000_write_kmrn_reg_locked - Write kumeran register
719 * @hw: pointer to the HW structure
720 * @offset: register offset to write to
721 * @data: data to write at register offset
722 *
723 * Write the data to PHY register at the offset using the kumeran interface.
724 * Assumes semaphore already acquired.
725 */
726 s32
e1000_write_kmrn_reg_locked(struct e1000_hw * hw,u32 offset,u16 data)727 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
728 {
729 return (__e1000_write_kmrn_reg(hw, offset, data, true));
730 }
731
732 /*
733 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
734 * @hw: pointer to the HW structure
735 *
736 * Sets up Carrier-sense on Transmit and downshift values.
737 */
738 s32
e1000_copper_link_setup_82577(struct e1000_hw * hw)739 e1000_copper_link_setup_82577(struct e1000_hw *hw)
740 {
741 struct e1000_phy_info *phy = &hw->phy;
742 s32 ret_val;
743 u16 phy_data;
744
745 DEBUGFUNC("e1000_copper_link_setup_82577");
746
747 if (phy->reset_disable) {
748 ret_val = E1000_SUCCESS;
749 goto out;
750 }
751
752 /* Enable CRS on TX. This must be set for half-duplex operation. */
753 ret_val = phy->ops.read_reg(hw, I82577_CFG_REG, &phy_data);
754 if (ret_val)
755 goto out;
756
757 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
758
759 /* Enable downshift */
760 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
761
762 ret_val = phy->ops.write_reg(hw, I82577_CFG_REG, phy_data);
763 if (ret_val)
764 goto out;
765
766 /* Set number of link attempts before downshift */
767 ret_val = phy->ops.read_reg(hw, I82577_CTRL_REG, &phy_data);
768 if (ret_val)
769 goto out;
770 phy_data &= ~I82577_CTRL_DOWNSHIFT_MASK;
771 ret_val = phy->ops.write_reg(hw, I82577_CTRL_REG, phy_data);
772
773 out:
774 return (ret_val);
775 }
776
777 /*
778 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
779 * @hw: pointer to the HW structure
780 *
781 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
782 * and downshift values are set also.
783 */
784 s32
e1000_copper_link_setup_m88(struct e1000_hw * hw)785 e1000_copper_link_setup_m88(struct e1000_hw *hw)
786 {
787 struct e1000_phy_info *phy = &hw->phy;
788 s32 ret_val;
789 u16 phy_data;
790
791 DEBUGFUNC("e1000_copper_link_setup_m88");
792
793 if (phy->reset_disable) {
794 ret_val = E1000_SUCCESS;
795 goto out;
796 }
797
798 /* Enable CRS on TX. This must be set for half-duplex operation. */
799 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
800 if (ret_val)
801 goto out;
802
803 /* For BM PHY this bit is downshift enable */
804 if (phy->type != e1000_phy_bm)
805 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
806
807 /*
808 * Options:
809 * MDI/MDI-X = 0 (default)
810 * 0 - Auto for all speeds
811 * 1 - MDI mode
812 * 2 - MDI-X mode
813 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
814 */
815 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
816
817 switch (phy->mdix) {
818 case 1:
819 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
820 break;
821 case 2:
822 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
823 break;
824 case 3:
825 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
826 break;
827 case 0:
828 default:
829 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
830 break;
831 }
832
833 /*
834 * Options:
835 * disable_polarity_correction = 0 (default)
836 * Automatic Correction for Reversed Cable Polarity
837 * 0 - Disabled
838 * 1 - Enabled
839 */
840 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
841 if (phy->disable_polarity_correction == 1)
842 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
843
844 /* Enable downshift on BM (disabled by default) */
845 if (phy->type == e1000_phy_bm)
846 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
847
848 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
849 if (ret_val)
850 goto out;
851
852 if ((phy->type == e1000_phy_m88) &&
853 (phy->revision < E1000_REVISION_4) &&
854 (phy->id != BME1000_E_PHY_ID_R2)) {
855 /*
856 * Force TX_CLK in the Extended PHY Specific Control Register
857 * to 25MHz clock.
858 */
859 ret_val = phy->ops.read_reg(hw,
860 M88E1000_EXT_PHY_SPEC_CTRL,
861 &phy_data);
862 if (ret_val)
863 goto out;
864
865 phy_data |= M88E1000_EPSCR_TX_CLK_25;
866
867 if ((phy->revision == E1000_REVISION_2) &&
868 (phy->id == M88E1111_I_PHY_ID)) {
869 /* 82573L PHY - set the downshift counter to 5x. */
870 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
871 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
872 } else {
873 /* Configure Master and Slave downshift values */
874 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
875 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
876 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
877 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
878 }
879 ret_val = phy->ops.write_reg(hw,
880 M88E1000_EXT_PHY_SPEC_CTRL,
881 phy_data);
882 if (ret_val)
883 goto out;
884 }
885
886 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
887 /* Set PHY page 0, register 29 to 0x0003 */
888 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
889 if (ret_val)
890 goto out;
891
892 /* Set PHY page 0, register 30 to 0x0000 */
893 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
894 if (ret_val)
895 goto out;
896 }
897
898 /* Commit the changes. */
899 ret_val = phy->ops.commit(hw);
900 if (ret_val) {
901 DEBUGOUT("Error committing the PHY changes\n");
902 goto out;
903 }
904
905 if (phy->type == e1000_phy_82578) {
906 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
907 &phy_data);
908 if (ret_val)
909 goto out;
910
911 /* 82578 PHY - set the downshift count to 1x. */
912 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
913 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
914 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
915 phy_data);
916 if (ret_val)
917 goto out;
918 }
919
920 out:
921 return (ret_val);
922 }
923
924 /*
925 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
926 * @hw: pointer to the HW structure
927 *
928 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
929 * igp PHY's.
930 */
931 s32
e1000_copper_link_setup_igp(struct e1000_hw * hw)932 e1000_copper_link_setup_igp(struct e1000_hw *hw)
933 {
934 struct e1000_phy_info *phy = &hw->phy;
935 s32 ret_val;
936 u16 data;
937
938 DEBUGFUNC("e1000_copper_link_setup_igp");
939
940 if (phy->reset_disable) {
941 ret_val = E1000_SUCCESS;
942 goto out;
943 }
944
945 ret_val = hw->phy.ops.reset(hw);
946 if (ret_val) {
947 DEBUGOUT("Error resetting the PHY.\n");
948 goto out;
949 }
950
951 /*
952 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
953 * timeout issues when LFS is enabled.
954 */
955 msec_delay(100);
956
957 /*
958 * The NVM settings will configure LPLU in D3 for non-IGP1 PHYs.
959 */
960 if (phy->type == e1000_phy_igp) {
961 /* disable lplu d3 during driver init */
962 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);
963 if (ret_val) {
964 DEBUGOUT("Error Disabling LPLU D3\n");
965 goto out;
966 }
967 }
968
969 /* disable lplu d0 during driver init */
970 if (hw->phy.ops.set_d0_lplu_state) {
971 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
972 if (ret_val) {
973 DEBUGOUT("Error Disabling LPLU D0\n");
974 goto out;
975 }
976 }
977 /* Configure mdi-mdix settings */
978 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
979 if (ret_val)
980 goto out;
981
982 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
983
984 switch (phy->mdix) {
985 case 1:
986 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
987 break;
988 case 2:
989 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
990 break;
991 case 0:
992 default:
993 data |= IGP01E1000_PSCR_AUTO_MDIX;
994 break;
995 }
996 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
997 if (ret_val)
998 goto out;
999
1000 /* set auto-master slave resolution settings */
1001 if (hw->mac.autoneg) {
1002 /*
1003 * when autonegotiation advertisement is only 1000Mbps then we
1004 * should disable SmartSpeed and enable Auto MasterSlave
1005 * resolution as hardware default.
1006 */
1007 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1008 /* Disable SmartSpeed */
1009 ret_val = phy->ops.read_reg(hw,
1010 IGP01E1000_PHY_PORT_CONFIG,
1011 &data);
1012 if (ret_val)
1013 goto out;
1014
1015 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1016 ret_val = phy->ops.write_reg(hw,
1017 IGP01E1000_PHY_PORT_CONFIG,
1018 data);
1019 if (ret_val)
1020 goto out;
1021
1022 /* Set auto Master/Slave resolution process */
1023 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1024 if (ret_val)
1025 goto out;
1026
1027 data &= ~CR_1000T_MS_ENABLE;
1028 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1029 if (ret_val)
1030 goto out;
1031 }
1032
1033 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1034 if (ret_val)
1035 goto out;
1036
1037 /* load defaults for future use */
1038 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
1039 ((data & CR_1000T_MS_VALUE) ?
1040 e1000_ms_force_master :
1041 e1000_ms_force_slave) :
1042 e1000_ms_auto;
1043
1044 switch (phy->ms_type) {
1045 case e1000_ms_force_master:
1046 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1047 break;
1048 case e1000_ms_force_slave:
1049 data |= CR_1000T_MS_ENABLE;
1050 data &= ~(CR_1000T_MS_VALUE);
1051 break;
1052 case e1000_ms_auto:
1053 data &= ~CR_1000T_MS_ENABLE;
1054 default:
1055 break;
1056 }
1057 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1058 if (ret_val)
1059 goto out;
1060 }
1061
1062 out:
1063 return (ret_val);
1064 }
1065
1066 /*
1067 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1068 * @hw: pointer to the HW structure
1069 *
1070 * Performs initial bounds checking on autoneg advertisement parameter, then
1071 * configure to advertise the full capability. Setup the PHY to autoneg
1072 * and restart the negotiation process between the link partner. If
1073 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1074 */
1075 s32
e1000_copper_link_autoneg(struct e1000_hw * hw)1076 e1000_copper_link_autoneg(struct e1000_hw *hw)
1077 {
1078 struct e1000_phy_info *phy = &hw->phy;
1079 s32 ret_val;
1080 u16 phy_ctrl;
1081
1082 DEBUGFUNC("e1000_copper_link_autoneg");
1083
1084 /*
1085 * Perform some bounds checking on the autoneg advertisement
1086 * parameter.
1087 */
1088 phy->autoneg_advertised &= phy->autoneg_mask;
1089
1090 /*
1091 * If autoneg_advertised is zero, we assume it was not defaulted by
1092 * the calling code so we set to advertise full capability.
1093 */
1094 if (phy->autoneg_advertised == 0)
1095 phy->autoneg_advertised = phy->autoneg_mask;
1096
1097 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1098 ret_val = e1000_phy_setup_autoneg(hw);
1099 if (ret_val) {
1100 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1101 goto out;
1102 }
1103 DEBUGOUT("Restarting Auto-Neg\n");
1104
1105 /*
1106 * Restart auto-negotiation by setting the Auto Neg Enable bit and the
1107 * Auto Neg Restart bit in the PHY control register.
1108 */
1109 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1110 if (ret_val)
1111 goto out;
1112
1113 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1114 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1115 if (ret_val)
1116 goto out;
1117
1118 /*
1119 * Does the user want to wait for Auto-Neg to complete here, or check
1120 * at a later time (for example, callback routine).
1121 */
1122 if (phy->autoneg_wait_to_complete) {
1123 ret_val = hw->mac.ops.wait_autoneg(hw);
1124 if (ret_val) {
1125 DEBUGOUT("Error while waiting for "
1126 "autoneg to complete\n");
1127 goto out;
1128 }
1129 }
1130
1131 hw->mac.get_link_status = true;
1132
1133 out:
1134 return (ret_val);
1135 }
1136
1137 /*
1138 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1139 * @hw: pointer to the HW structure
1140 *
1141 * Reads the MII auto-neg advertisement register and/or the 1000T control
1142 * register and if the PHY is already setup for auto-negotiation, then
1143 * return successful. Otherwise, setup advertisement and flow control to
1144 * the appropriate values for the wanted auto-negotiation.
1145 */
1146 s32
e1000_phy_setup_autoneg(struct e1000_hw * hw)1147 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1148 {
1149 struct e1000_phy_info *phy = &hw->phy;
1150 s32 ret_val;
1151 u16 mii_autoneg_adv_reg;
1152 u16 mii_1000t_ctrl_reg = 0;
1153
1154 DEBUGFUNC("e1000_phy_setup_autoneg");
1155
1156 phy->autoneg_advertised &= phy->autoneg_mask;
1157
1158 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1159 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1160 if (ret_val)
1161 goto out;
1162
1163 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1164 /* Read the MII 1000Base-T Control Register (Address 9). */
1165 ret_val = phy->ops.read_reg(hw,
1166 PHY_1000T_CTRL,
1167 &mii_1000t_ctrl_reg);
1168 if (ret_val)
1169 goto out;
1170 }
1171
1172 /*
1173 * Need to parse both autoneg_advertised and fc and set up the
1174 * appropriate PHY registers. First we will parse for
1175 * autoneg_advertised software override. Since we can advertise a
1176 * plethora of combinations, we need to check each bit individually.
1177 */
1178
1179 /*
1180 * First we clear all the 10/100 mb speed bits in the Auto-Neg
1181 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1182 * the 1000Base-T Control Register (Address 9).
1183 */
1184 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1185 NWAY_AR_100TX_HD_CAPS |
1186 NWAY_AR_10T_FD_CAPS |
1187 NWAY_AR_10T_HD_CAPS);
1188 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1189
1190 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1191
1192 /* Do we want to advertise 10 Mb Half Duplex? */
1193 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1194 DEBUGOUT("Advertise 10mb Half duplex\n");
1195 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1196 }
1197
1198 /* Do we want to advertise 10 Mb Full Duplex? */
1199 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1200 DEBUGOUT("Advertise 10mb Full duplex\n");
1201 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1202 }
1203
1204 /* Do we want to advertise 100 Mb Half Duplex? */
1205 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1206 DEBUGOUT("Advertise 100mb Half duplex\n");
1207 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1208 }
1209
1210 /* Do we want to advertise 100 Mb Full Duplex? */
1211 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1212 DEBUGOUT("Advertise 100mb Full duplex\n");
1213 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1214 }
1215
1216 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1217 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) {
1218 /* EMPTY */
1219 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1220 }
1221
1222 /* Do we want to advertise 1000 Mb Full Duplex? */
1223 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1224 DEBUGOUT("Advertise 1000mb Full duplex\n");
1225 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1226 }
1227
1228 /*
1229 * Check for a software override of the flow control settings, and
1230 * setup the PHY advertisement registers accordingly. If
1231 * auto-negotiation is enabled, then software will have to set the
1232 * "PAUSE" bits to the correct value in the Auto-Negotiation
1233 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1234 * negotiation.
1235 *
1236 * The possible values of the "fc" parameter are:
1237 * 0: Flow control is completely disabled
1238 * 1: Rx flow control is enabled (we can receive pause frames
1239 * but not send pause frames).
1240 * 2: Tx flow control is enabled (we can send pause frames
1241 * but we do not support receiving pause frames).
1242 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1243 * other: No software override. The flow control configuration
1244 * in the EEPROM is used.
1245 */
1246 switch (hw->fc.current_mode) {
1247 case e1000_fc_none:
1248 /*
1249 * Flow control (Rx & Tx) is completely disabled by a software
1250 * over-ride.
1251 */
1252 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1253 break;
1254 case e1000_fc_rx_pause:
1255 /*
1256 * Rx Flow control is enabled, and Tx Flow control is
1257 * disabled, by a software over-ride.
1258 *
1259 * Since there really isn't a way to advertise that we are
1260 * capable of Rx Pause ONLY, we will advertise that we support
1261 * both symmetric and asymmetric Rx PAUSE. Later (in
1262 * e1000_config_fc_after_link_up) we will disable the hw's
1263 * ability to send PAUSE frames.
1264 */
1265 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1266 break;
1267 case e1000_fc_tx_pause:
1268 /*
1269 * Tx Flow control is enabled, and Rx Flow control is
1270 * disabled, by a software over-ride.
1271 */
1272 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1273 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1274 break;
1275 case e1000_fc_full:
1276 /*
1277 * Flow control (both Rx and Tx) is enabled by a software
1278 * over-ride.
1279 */
1280 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1281 break;
1282 default:
1283 DEBUGOUT("Flow control param set incorrectly\n");
1284 ret_val = -E1000_ERR_CONFIG;
1285 goto out;
1286 }
1287
1288 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1289 if (ret_val)
1290 goto out;
1291
1292 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1293
1294 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1295 ret_val = phy->ops.write_reg(hw,
1296 PHY_1000T_CTRL,
1297 mii_1000t_ctrl_reg);
1298 if (ret_val)
1299 goto out;
1300 }
1301
1302 out:
1303 return (ret_val);
1304 }
1305
1306 /*
1307 * e1000_setup_copper_link_generic - Configure copper link settings
1308 * @hw: pointer to the HW structure
1309 *
1310 * Calls the appropriate function to configure the link for auto-neg or forced
1311 * speed and duplex. Then we check for link, once link is established calls
1312 * to configure collision distance and flow control are called. If link is
1313 * not established, we return -E1000_ERR_PHY (-2).
1314 */
1315 s32
e1000_setup_copper_link_generic(struct e1000_hw * hw)1316 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1317 {
1318 s32 ret_val;
1319 bool link;
1320
1321 DEBUGFUNC("e1000_setup_copper_link_generic");
1322
1323 if (hw->mac.autoneg) {
1324 /*
1325 * Setup autoneg and flow control advertisement and perform
1326 * autonegotiation.
1327 */
1328 ret_val = e1000_copper_link_autoneg(hw);
1329 if (ret_val)
1330 goto out;
1331 } else {
1332 /*
1333 * PHY will be set to 10H, 10F, 100H or 100F depending on user
1334 * settings.
1335 */
1336 DEBUGOUT("Forcing Speed and Duplex\n");
1337 ret_val = hw->phy.ops.force_speed_duplex(hw);
1338 if (ret_val) {
1339 DEBUGOUT("Error Forcing Speed and Duplex\n");
1340 goto out;
1341 }
1342 }
1343
1344 /*
1345 * Check link status. Wait up to 100 microseconds for link to become
1346 * valid.
1347 */
1348 ret_val = e1000_phy_has_link_generic(hw,
1349 COPPER_LINK_UP_LIMIT,
1350 10,
1351 &link);
1352 if (ret_val)
1353 goto out;
1354
1355 if (link) {
1356 DEBUGOUT("Valid link established!!!\n");
1357 e1000_config_collision_dist_generic(hw);
1358 ret_val = e1000_config_fc_after_link_up_generic(hw);
1359 } else {
1360 /* EMPTY */
1361 DEBUGOUT("Unable to establish link!!!\n");
1362 }
1363
1364 out:
1365 return (ret_val);
1366 }
1367
1368 /*
1369 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1370 * @hw: pointer to the HW structure
1371 *
1372 * Calls the PHY setup function to force speed and duplex. Clears the
1373 * auto-crossover to force MDI manually. Waits for link and returns
1374 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1375 */
1376 s32
e1000_phy_force_speed_duplex_igp(struct e1000_hw * hw)1377 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1378 {
1379 struct e1000_phy_info *phy = &hw->phy;
1380 s32 ret_val;
1381 u16 phy_data;
1382 bool link;
1383
1384 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1385
1386 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1387 if (ret_val)
1388 goto out;
1389
1390 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1391
1392 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1393 if (ret_val)
1394 goto out;
1395
1396 /*
1397 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1398 * forced whenever speed and duplex are forced.
1399 */
1400 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1401 if (ret_val)
1402 goto out;
1403
1404 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1405 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1406
1407 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1408 if (ret_val)
1409 goto out;
1410
1411 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1412
1413 usec_delay(1);
1414
1415 if (phy->autoneg_wait_to_complete) {
1416 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1417
1418 ret_val = e1000_phy_has_link_generic(hw,
1419 PHY_FORCE_LIMIT,
1420 100000,
1421 &link);
1422 if (ret_val)
1423 goto out;
1424
1425 if (!link) {
1426 /* EMPTY */
1427 DEBUGOUT("Link taking longer than expected.\n");
1428 }
1429
1430 /* Try once more */
1431 ret_val = e1000_phy_has_link_generic(hw,
1432 PHY_FORCE_LIMIT,
1433 100000,
1434 &link);
1435 if (ret_val)
1436 goto out;
1437 }
1438
1439 out:
1440 return (ret_val);
1441 }
1442
1443 /*
1444 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1445 * @hw: pointer to the HW structure
1446 *
1447 * Calls the PHY setup function to force speed and duplex. Clears the
1448 * auto-crossover to force MDI manually. Resets the PHY to commit the
1449 * changes. If time expires while waiting for link up, we reset the DSP.
1450 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1451 * successful completion, else return corresponding error code.
1452 */
1453 s32
e1000_phy_force_speed_duplex_m88(struct e1000_hw * hw)1454 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1455 {
1456 struct e1000_phy_info *phy = &hw->phy;
1457 s32 ret_val;
1458 u16 phy_data;
1459 bool link;
1460
1461 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1462
1463 /*
1464 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1465 * forced whenever speed and duplex are forced.
1466 */
1467 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1468 if (ret_val)
1469 goto out;
1470
1471 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1472 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1473 if (ret_val)
1474 goto out;
1475
1476 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1477
1478 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1479 if (ret_val)
1480 goto out;
1481
1482 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1483
1484 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1485 if (ret_val)
1486 goto out;
1487
1488 /* Reset the phy to commit changes. */
1489 ret_val = hw->phy.ops.commit(hw);
1490 if (ret_val)
1491 goto out;
1492
1493 if (phy->autoneg_wait_to_complete) {
1494 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1495
1496 ret_val = e1000_phy_has_link_generic(hw,
1497 PHY_FORCE_LIMIT,
1498 100000,
1499 &link);
1500 if (ret_val)
1501 goto out;
1502
1503 if (!link) {
1504 /*
1505 * We didn't get link. Reset the DSP and cross our
1506 * fingers.
1507 */
1508 ret_val = phy->ops.write_reg(hw,
1509 M88E1000_PHY_PAGE_SELECT,
1510 0x001d);
1511 if (ret_val)
1512 goto out;
1513 ret_val = e1000_phy_reset_dsp_generic(hw);
1514 if (ret_val)
1515 goto out;
1516 }
1517 /* Try once more */
1518 ret_val = e1000_phy_has_link_generic(hw,
1519 PHY_FORCE_LIMIT,
1520 100000,
1521 &link);
1522 if (ret_val)
1523 goto out;
1524 }
1525 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1526 if (ret_val)
1527 goto out;
1528
1529 /*
1530 * Resetting the phy means we need to re-force TX_CLK in the Extended
1531 * PHY Specific Control Register to 25MHz clock from the reset value
1532 * of 2.5MHz.
1533 */
1534 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1535 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1536 if (ret_val)
1537 goto out;
1538
1539 /*
1540 * In addition, we must re-enable CRS on Tx for both half and full
1541 * duplex.
1542 */
1543 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1544 if (ret_val)
1545 goto out;
1546
1547 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1548 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1549
1550 out:
1551 return (ret_val);
1552 }
1553
1554 /*
1555 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1556 * @hw: pointer to the HW structure
1557 *
1558 * Forces the speed and duplex settings of the PHY.
1559 * This is a function pointer entry point only called by
1560 * PHY setup routines.
1561 */
1562 s32
e1000_phy_force_speed_duplex_ife(struct e1000_hw * hw)1563 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1564 {
1565 struct e1000_phy_info *phy = &hw->phy;
1566 s32 ret_val;
1567 u16 data;
1568 bool link;
1569
1570 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1571
1572 if (phy->type != e1000_phy_ife) {
1573 ret_val = e1000_phy_force_speed_duplex_igp(hw);
1574 goto out;
1575 }
1576
1577 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1578 if (ret_val)
1579 goto out;
1580
1581 e1000_phy_force_speed_duplex_setup(hw, &data);
1582
1583 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1584 if (ret_val)
1585 goto out;
1586
1587 /* Disable MDI-X support for 10/100 */
1588 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1589 if (ret_val)
1590 goto out;
1591
1592 data &= ~IFE_PMC_AUTO_MDIX;
1593 data &= ~IFE_PMC_FORCE_MDIX;
1594
1595 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1596 if (ret_val)
1597 goto out;
1598
1599 DEBUGOUT1("IFE PMC: %X\n", data);
1600
1601 usec_delay(1);
1602
1603 if (phy->autoneg_wait_to_complete) {
1604 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1605
1606 ret_val = e1000_phy_has_link_generic(hw,
1607 PHY_FORCE_LIMIT, 100000, &link);
1608 if (ret_val)
1609 goto out;
1610
1611 if (!link) {
1612 /* EMPTY */
1613 DEBUGOUT("Link taking longer than expected.\n");
1614 }
1615
1616 /* Try once more */
1617 ret_val = e1000_phy_has_link_generic(hw,
1618 PHY_FORCE_LIMIT, 100000, &link);
1619 if (ret_val)
1620 goto out;
1621 }
1622
1623 out:
1624 return (ret_val);
1625 }
1626
1627 /*
1628 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1629 * @hw: pointer to the HW structure
1630 * @phy_ctrl: pointer to current value of PHY_CONTROL
1631 *
1632 * Forces speed and duplex on the PHY by doing the following: disable flow
1633 * control, force speed/duplex on the MAC, disable auto speed detection,
1634 * disable auto-negotiation, configure duplex, configure speed, configure
1635 * the collision distance, write configuration to CTRL register. The
1636 * caller must write to the PHY_CONTROL register for these settings to
1637 * take affect.
1638 */
1639 void
e1000_phy_force_speed_duplex_setup(struct e1000_hw * hw,u16 * phy_ctrl)1640 e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1641 {
1642 struct e1000_mac_info *mac = &hw->mac;
1643 u32 ctrl;
1644
1645 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
1646
1647 /* Turn off flow control when forcing speed/duplex */
1648 hw->fc.current_mode = e1000_fc_none;
1649
1650 /* Force speed/duplex on the mac */
1651 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1652 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1653 ctrl &= ~E1000_CTRL_SPD_SEL;
1654
1655 /* Disable Auto Speed Detection */
1656 ctrl &= ~E1000_CTRL_ASDE;
1657
1658 /* Disable autoneg on the phy */
1659 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1660
1661 /* Forcing Full or Half Duplex? */
1662 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1663 ctrl &= ~E1000_CTRL_FD;
1664 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1665 DEBUGOUT("Half Duplex\n");
1666 } else {
1667 ctrl |= E1000_CTRL_FD;
1668 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1669 DEBUGOUT("Full Duplex\n");
1670 }
1671
1672 /* Forcing 10mb or 100mb? */
1673 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1674 ctrl |= E1000_CTRL_SPD_100;
1675 *phy_ctrl |= MII_CR_SPEED_100;
1676 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1677 DEBUGOUT("Forcing 100mb\n");
1678 } else {
1679 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1680 /* LINTED */
1681 *phy_ctrl |= MII_CR_SPEED_10;
1682 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1683 DEBUGOUT("Forcing 10mb\n");
1684 }
1685
1686 e1000_config_collision_dist_generic(hw);
1687
1688 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1689 }
1690
1691 /*
1692 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
1693 * @hw: pointer to the HW structure
1694 * @active: boolean used to enable/disable lplu
1695 *
1696 * Success returns 0, Failure returns 1
1697 *
1698 * The low power link up (lplu) state is set to the power management level D3
1699 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1700 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1701 * is used during Dx states where the power conservation is most important.
1702 * During driver activity, SmartSpeed should be enabled so performance is
1703 * maintained.
1704 */
1705 s32
e1000_set_d3_lplu_state_generic(struct e1000_hw * hw,bool active)1706 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
1707 {
1708 struct e1000_phy_info *phy = &hw->phy;
1709 s32 ret_val = E1000_SUCCESS;
1710 u16 data;
1711
1712 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
1713
1714 if (!(hw->phy.ops.read_reg))
1715 goto out;
1716
1717 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1718 if (ret_val)
1719 goto out;
1720
1721 if (!active) {
1722 data &= ~IGP02E1000_PM_D3_LPLU;
1723 ret_val = phy->ops.write_reg(hw,
1724 IGP02E1000_PHY_POWER_MGMT,
1725 data);
1726 if (ret_val)
1727 goto out;
1728 /*
1729 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1730 * during Dx states where the power conservation is most
1731 * important. During driver activity we should enable
1732 * SmartSpeed, so performance is maintained.
1733 */
1734 if (phy->smart_speed == e1000_smart_speed_on) {
1735 ret_val = phy->ops.read_reg(hw,
1736 IGP01E1000_PHY_PORT_CONFIG,
1737 &data);
1738 if (ret_val)
1739 goto out;
1740
1741 data |= IGP01E1000_PSCFR_SMART_SPEED;
1742 ret_val = phy->ops.write_reg(hw,
1743 IGP01E1000_PHY_PORT_CONFIG,
1744 data);
1745 if (ret_val)
1746 goto out;
1747 } else if (phy->smart_speed == e1000_smart_speed_off) {
1748 ret_val = phy->ops.read_reg(hw,
1749 IGP01E1000_PHY_PORT_CONFIG,
1750 &data);
1751 if (ret_val)
1752 goto out;
1753
1754 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1755 ret_val = phy->ops.write_reg(hw,
1756 IGP01E1000_PHY_PORT_CONFIG,
1757 data);
1758 if (ret_val)
1759 goto out;
1760 }
1761 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1762 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1763 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1764 data |= IGP02E1000_PM_D3_LPLU;
1765 ret_val = phy->ops.write_reg(hw,
1766 IGP02E1000_PHY_POWER_MGMT,
1767 data);
1768 if (ret_val)
1769 goto out;
1770
1771 /* When LPLU is enabled, we should disable SmartSpeed */
1772 ret_val = phy->ops.read_reg(hw,
1773 IGP01E1000_PHY_PORT_CONFIG,
1774 &data);
1775 if (ret_val)
1776 goto out;
1777
1778 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1779 ret_val = phy->ops.write_reg(hw,
1780 IGP01E1000_PHY_PORT_CONFIG,
1781 data);
1782 }
1783
1784 out:
1785 return (ret_val);
1786 }
1787
1788 /*
1789 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
1790 * @hw: pointer to the HW structure
1791 *
1792 * Success returns 0, Failure returns 1
1793 *
1794 * A downshift is detected by querying the PHY link health.
1795 */
1796 s32
e1000_check_downshift_generic(struct e1000_hw * hw)1797 e1000_check_downshift_generic(struct e1000_hw *hw)
1798 {
1799 struct e1000_phy_info *phy = &hw->phy;
1800 s32 ret_val;
1801 u16 phy_data, offset, mask;
1802
1803 DEBUGFUNC("e1000_check_downshift_generic");
1804
1805 switch (phy->type) {
1806 case e1000_phy_m88:
1807 case e1000_phy_gg82563:
1808 case e1000_phy_bm:
1809 case e1000_phy_82578:
1810 offset = M88E1000_PHY_SPEC_STATUS;
1811 mask = M88E1000_PSSR_DOWNSHIFT;
1812 break;
1813 case e1000_phy_igp_2:
1814 case e1000_phy_igp:
1815 case e1000_phy_igp_3:
1816 offset = IGP01E1000_PHY_LINK_HEALTH;
1817 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1818 break;
1819 default:
1820 /* speed downshift not supported */
1821 phy->speed_downgraded = false;
1822 ret_val = E1000_SUCCESS;
1823 goto out;
1824 }
1825
1826 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1827
1828 if (!ret_val)
1829 phy->speed_downgraded = (phy_data & mask) ? true : false;
1830
1831 out:
1832 return (ret_val);
1833 }
1834
1835 /*
1836 * e1000_check_polarity_m88 - Checks the polarity.
1837 * @hw: pointer to the HW structure
1838 *
1839 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1840 *
1841 * Polarity is determined based on the PHY specific status register.
1842 */
1843 s32
e1000_check_polarity_m88(struct e1000_hw * hw)1844 e1000_check_polarity_m88(struct e1000_hw *hw)
1845 {
1846 struct e1000_phy_info *phy = &hw->phy;
1847 s32 ret_val;
1848 u16 data;
1849
1850 DEBUGFUNC("e1000_check_polarity_m88");
1851
1852 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
1853
1854 if (!ret_val)
1855 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1856 ? e1000_rev_polarity_reversed
1857 : e1000_rev_polarity_normal;
1858
1859 return (ret_val);
1860 }
1861
1862 /*
1863 * e1000_check_polarity_igp - Checks the polarity.
1864 * @hw: pointer to the HW structure
1865 *
1866 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1867 *
1868 * Polarity is determined based on the PHY port status register, and the
1869 * current speed (since there is no polarity at 100Mbps).
1870 */
1871 s32
e1000_check_polarity_igp(struct e1000_hw * hw)1872 e1000_check_polarity_igp(struct e1000_hw *hw)
1873 {
1874 struct e1000_phy_info *phy = &hw->phy;
1875 s32 ret_val;
1876 u16 data, offset, mask;
1877
1878 DEBUGFUNC("e1000_check_polarity_igp");
1879
1880 /*
1881 * Polarity is determined based on the speed of our connection.
1882 */
1883 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1884 if (ret_val)
1885 goto out;
1886
1887 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1888 IGP01E1000_PSSR_SPEED_1000MBPS) {
1889 offset = IGP01E1000_PHY_PCS_INIT_REG;
1890 mask = IGP01E1000_PHY_POLARITY_MASK;
1891 } else {
1892 /*
1893 * This really only applies to 10Mbps since there is no
1894 * polarity for 100Mbps (always 0).
1895 */
1896 offset = IGP01E1000_PHY_PORT_STATUS;
1897 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1898 }
1899
1900 ret_val = phy->ops.read_reg(hw, offset, &data);
1901
1902 if (!ret_val)
1903 phy->cable_polarity = (data & mask)
1904 ? e1000_rev_polarity_reversed
1905 : e1000_rev_polarity_normal;
1906
1907 out:
1908 return (ret_val);
1909 }
1910
1911 /*
1912 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1913 * @hw: pointer to the HW structure
1914 *
1915 * Polarity is determined on the polarity reversal feature being enabled.
1916 */
1917 s32
e1000_check_polarity_ife(struct e1000_hw * hw)1918 e1000_check_polarity_ife(struct e1000_hw *hw)
1919 {
1920 struct e1000_phy_info *phy = &hw->phy;
1921 s32 ret_val;
1922 u16 phy_data, offset, mask;
1923
1924 DEBUGFUNC("e1000_check_polarity_ife");
1925
1926 /*
1927 * Polarity is determined based on the reversal feature being enabled.
1928 */
1929 if (phy->polarity_correction) {
1930 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1931 mask = IFE_PESC_POLARITY_REVERSED;
1932 } else {
1933 offset = IFE_PHY_SPECIAL_CONTROL;
1934 mask = IFE_PSC_FORCE_POLARITY;
1935 }
1936
1937 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1938
1939 if (!ret_val)
1940 phy->cable_polarity = (phy_data & mask)
1941 ? e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
1942
1943 return (ret_val);
1944 }
1945
1946 /*
1947 * e1000_wait_autoneg_generic - Wait for auto-neg completion
1948 * @hw: pointer to the HW structure
1949 *
1950 * Waits for auto-negotiation to complete or for the auto-negotiation time
1951 * limit to expire, which ever happens first.
1952 */
1953 s32
e1000_wait_autoneg_generic(struct e1000_hw * hw)1954 e1000_wait_autoneg_generic(struct e1000_hw *hw)
1955 {
1956 s32 ret_val = E1000_SUCCESS;
1957 u16 i, phy_status;
1958
1959 DEBUGFUNC("e1000_wait_autoneg_generic");
1960
1961 if (!(hw->phy.ops.read_reg))
1962 return (E1000_SUCCESS);
1963
1964 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1965 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1966 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1967 if (ret_val)
1968 break;
1969 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1970 if (ret_val)
1971 break;
1972 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1973 break;
1974 msec_delay(100);
1975 }
1976
1977 /*
1978 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation has
1979 * completed.
1980 */
1981 return (ret_val);
1982 }
1983
1984 /*
1985 * e1000_phy_has_link_generic - Polls PHY for link
1986 * @hw: pointer to the HW structure
1987 * @iterations: number of times to poll for link
1988 * @usec_interval: delay between polling attempts
1989 * @success: pointer to whether polling was successful or not
1990 *
1991 * Polls the PHY status register for link, 'iterations' number of times.
1992 */
1993 s32
e1000_phy_has_link_generic(struct e1000_hw * hw,u32 iterations,u32 usec_interval,bool * success)1994 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1995 u32 usec_interval, bool *success)
1996 {
1997 s32 ret_val = E1000_SUCCESS;
1998 u16 i, phy_status;
1999
2000 DEBUGFUNC("e1000_phy_has_link_generic");
2001
2002 if (!(hw->phy.ops.read_reg))
2003 return (E1000_SUCCESS);
2004
2005 for (i = 0; i < iterations; i++) {
2006 /*
2007 * Some PHYs require the PHY_STATUS register to be read twice
2008 * due to the link bit being sticky. No harm doing it across
2009 * the board.
2010 */
2011 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2012 if (ret_val) {
2013 /*
2014 * If the first read fails, another entity may have
2015 * ownership of the resources, wait and try again to
2016 * see if they have relinquished the resources yet.
2017 */
2018 usec_delay(usec_interval);
2019 }
2020 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2021 if (ret_val)
2022 break;
2023 if (phy_status & MII_SR_LINK_STATUS)
2024 break;
2025 if (usec_interval >= 1000)
2026 msec_delay_irq(usec_interval / 1000);
2027 else
2028 usec_delay(usec_interval);
2029 }
2030
2031 *success = (i < iterations) ? true : false;
2032
2033 return (ret_val);
2034 }
2035
2036 /*
2037 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2038 * @hw: pointer to the HW structure
2039 *
2040 * Reads the PHY specific status register to retrieve the cable length
2041 * information. The cable length is determined by averaging the minimum and
2042 * maximum values to get the "average" cable length. The m88 PHY has four
2043 * possible cable length values, which are:
2044 * Register Value Cable Length
2045 * 0 < 50 meters
2046 * 1 50 - 80 meters
2047 * 2 80 - 110 meters
2048 * 3 110 - 140 meters
2049 * 4 > 140 meters
2050 */
2051 s32
e1000_get_cable_length_m88(struct e1000_hw * hw)2052 e1000_get_cable_length_m88(struct e1000_hw *hw)
2053 {
2054 struct e1000_phy_info *phy = &hw->phy;
2055 s32 ret_val;
2056 u16 phy_data, index;
2057
2058 DEBUGFUNC("e1000_get_cable_length_m88");
2059
2060 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2061 if (ret_val)
2062 goto out;
2063
2064 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2065 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2066
2067 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
2068 ret_val = E1000_ERR_PHY;
2069 goto out;
2070 }
2071 phy->min_cable_length = e1000_m88_cable_length_table[index];
2072 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2073
2074 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2075
2076 out:
2077 return (ret_val);
2078 }
2079
2080 /*
2081 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2082 * @hw: pointer to the HW structure
2083 *
2084 * The automatic gain control (agc) normalizes the amplitude of the
2085 * received signal, adjusting for the attenuation produced by the
2086 * cable. By reading the AGC registers, which represent the
2087 * combination of coarse and fine gain value, the value can be put
2088 * into a lookup table to obtain the approximate cable length
2089 * for each channel.
2090 */
2091 s32
e1000_get_cable_length_igp_2(struct e1000_hw * hw)2092 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2093 {
2094 struct e1000_phy_info *phy = &hw->phy;
2095 s32 ret_val = E1000_SUCCESS;
2096 u16 phy_data, i, agc_value = 0;
2097 u16 cur_agc_index, max_agc_index = 0;
2098 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2099 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
2100 {IGP02E1000_PHY_AGC_A,
2101 IGP02E1000_PHY_AGC_B,
2102 IGP02E1000_PHY_AGC_C,
2103 IGP02E1000_PHY_AGC_D};
2104
2105 DEBUGFUNC("e1000_get_cable_length_igp_2");
2106
2107 /* Read the AGC registers for all channels */
2108 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2109 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2110 if (ret_val)
2111 goto out;
2112
2113 /*
2114 * Getting bits 15:9, which represent the combination of
2115 * coarse and fine gain values. The result is a number that
2116 * can be put into the lookup table to obtain the approximate
2117 * cable length.
2118 */
2119 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2120 IGP02E1000_AGC_LENGTH_MASK;
2121
2122 /* Array index bound check. */
2123 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2124 (cur_agc_index == 0)) {
2125 ret_val = -E1000_ERR_PHY;
2126 goto out;
2127 }
2128
2129 /* Remove min & max AGC values from calculation. */
2130 if (e1000_igp_2_cable_length_table[min_agc_index] >
2131 e1000_igp_2_cable_length_table[cur_agc_index])
2132 min_agc_index = cur_agc_index;
2133 if (e1000_igp_2_cable_length_table[max_agc_index] <
2134 e1000_igp_2_cable_length_table[cur_agc_index])
2135 max_agc_index = cur_agc_index;
2136
2137 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
2138 }
2139
2140 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2141 e1000_igp_2_cable_length_table[max_agc_index]);
2142 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2143
2144 /* Calculate cable length with the error range of +/- 10 meters. */
2145 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2146 (agc_value - IGP02E1000_AGC_RANGE) : 0;
2147 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2148
2149 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2150
2151 out:
2152 return (ret_val);
2153 }
2154
2155 /*
2156 * e1000_get_phy_info_m88 - Retrieve PHY information
2157 * @hw: pointer to the HW structure
2158 *
2159 * Valid for only copper links. Read the PHY status register (sticky read)
2160 * to verify that link is up. Read the PHY special control register to
2161 * determine the polarity and 10base-T extended distance. Read the PHY
2162 * special status register to determine MDI/MDIx and current speed. If
2163 * speed is 1000, then determine cable length, local and remote receiver.
2164 */
2165 s32
e1000_get_phy_info_m88(struct e1000_hw * hw)2166 e1000_get_phy_info_m88(struct e1000_hw *hw)
2167 {
2168 struct e1000_phy_info *phy = &hw->phy;
2169 s32 ret_val;
2170 u16 phy_data;
2171 bool link;
2172
2173 DEBUGFUNC("e1000_get_phy_info_m88");
2174
2175 if (hw->phy.media_type != e1000_media_type_copper) {
2176 DEBUGOUT("Phy info is only valid for copper media\n");
2177 ret_val = -E1000_ERR_CONFIG;
2178 goto out;
2179 }
2180
2181 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2182 if (ret_val)
2183 goto out;
2184
2185 if (!link) {
2186 DEBUGOUT("Phy info is only valid if link is up\n");
2187 ret_val = -E1000_ERR_CONFIG;
2188 goto out;
2189 }
2190
2191 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2192 if (ret_val)
2193 goto out;
2194
2195 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
2196 ? true
2197 : false;
2198
2199 ret_val = e1000_check_polarity_m88(hw);
2200 if (ret_val)
2201 goto out;
2202
2203 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2204 if (ret_val)
2205 goto out;
2206
2207 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false;
2208
2209 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2210 ret_val = hw->phy.ops.get_cable_length(hw);
2211 if (ret_val)
2212 goto out;
2213
2214 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2215 if (ret_val)
2216 goto out;
2217
2218 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2219 ? e1000_1000t_rx_status_ok
2220 : e1000_1000t_rx_status_not_ok;
2221
2222 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2223 ? e1000_1000t_rx_status_ok
2224 : e1000_1000t_rx_status_not_ok;
2225 } else {
2226 /* Set values to "undefined" */
2227 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2228 phy->local_rx = e1000_1000t_rx_status_undefined;
2229 phy->remote_rx = e1000_1000t_rx_status_undefined;
2230 }
2231
2232 out:
2233 return (ret_val);
2234 }
2235
2236 /*
2237 * e1000_get_phy_info_igp - Retrieve igp PHY information
2238 * @hw: pointer to the HW structure
2239 *
2240 * Read PHY status to determine if link is up. If link is up, then
2241 * set/determine 10base-T extended distance and polarity correction. Read
2242 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2243 * determine on the cable length, local and remote receiver.
2244 */
2245 s32
e1000_get_phy_info_igp(struct e1000_hw * hw)2246 e1000_get_phy_info_igp(struct e1000_hw *hw)
2247 {
2248 struct e1000_phy_info *phy = &hw->phy;
2249 s32 ret_val;
2250 u16 data;
2251 bool link;
2252
2253 DEBUGFUNC("e1000_get_phy_info_igp");
2254
2255 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2256 if (ret_val)
2257 goto out;
2258
2259 if (!link) {
2260 DEBUGOUT("Phy info is only valid if link is up\n");
2261 ret_val = -E1000_ERR_CONFIG;
2262 goto out;
2263 }
2264
2265 phy->polarity_correction = true;
2266
2267 ret_val = e1000_check_polarity_igp(hw);
2268 if (ret_val)
2269 goto out;
2270
2271 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2272 if (ret_val)
2273 goto out;
2274
2275 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false;
2276
2277 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2278 IGP01E1000_PSSR_SPEED_1000MBPS) {
2279 ret_val = hw->phy.ops.get_cable_length(hw);
2280 if (ret_val)
2281 goto out;
2282
2283 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2284 if (ret_val)
2285 goto out;
2286
2287 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2288 ? e1000_1000t_rx_status_ok
2289 : e1000_1000t_rx_status_not_ok;
2290
2291 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2292 ? e1000_1000t_rx_status_ok
2293 : e1000_1000t_rx_status_not_ok;
2294 } else {
2295 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2296 phy->local_rx = e1000_1000t_rx_status_undefined;
2297 phy->remote_rx = e1000_1000t_rx_status_undefined;
2298 }
2299
2300 out:
2301 return (ret_val);
2302 }
2303
2304 /*
2305 * e1000_phy_sw_reset_generic - PHY software reset
2306 * @hw: pointer to the HW structure
2307 *
2308 * Does a software reset of the PHY by reading the PHY control register and
2309 * setting/write the control register reset bit to the PHY.
2310 */
2311 s32
e1000_phy_sw_reset_generic(struct e1000_hw * hw)2312 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2313 {
2314 s32 ret_val = E1000_SUCCESS;
2315 u16 phy_ctrl;
2316
2317 DEBUGFUNC("e1000_phy_sw_reset_generic");
2318
2319 if (!(hw->phy.ops.read_reg))
2320 goto out;
2321
2322 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2323 if (ret_val)
2324 goto out;
2325
2326 phy_ctrl |= MII_CR_RESET;
2327 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2328 if (ret_val)
2329 goto out;
2330
2331 usec_delay(1);
2332
2333 out:
2334 return (ret_val);
2335 }
2336
2337 /*
2338 * e1000_phy_hw_reset_generic - PHY hardware reset
2339 * @hw: pointer to the HW structure
2340 *
2341 * Verify the reset block is not blocking us from resetting. Acquire
2342 * semaphore (if necessary) and read/set/write the device control reset
2343 * bit in the PHY. Wait the appropriate delay time for the device to
2344 * reset and release the semaphore (if necessary).
2345 */
2346 s32
e1000_phy_hw_reset_generic(struct e1000_hw * hw)2347 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2348 {
2349 struct e1000_phy_info *phy = &hw->phy;
2350 s32 ret_val = E1000_SUCCESS;
2351 u32 ctrl;
2352
2353 DEBUGFUNC("e1000_phy_hw_reset_generic");
2354
2355 ret_val = phy->ops.check_reset_block(hw);
2356 if (ret_val) {
2357 ret_val = E1000_SUCCESS;
2358 goto out;
2359 }
2360
2361 ret_val = phy->ops.acquire(hw);
2362 if (ret_val)
2363 goto out;
2364
2365 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2366 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2367 E1000_WRITE_FLUSH(hw);
2368
2369 usec_delay(phy->reset_delay_us);
2370
2371 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2372 E1000_WRITE_FLUSH(hw);
2373
2374 usec_delay(150);
2375
2376 phy->ops.release(hw);
2377
2378 ret_val = phy->ops.get_cfg_done(hw);
2379
2380 out:
2381 return (ret_val);
2382 }
2383
2384 /*
2385 * e1000_get_cfg_done_generic - Generic configuration done
2386 * @hw: pointer to the HW structure
2387 *
2388 * Generic function to wait 10 milli-seconds for configuration to complete
2389 * and return success.
2390 */
2391 s32
e1000_get_cfg_done_generic(struct e1000_hw * hw)2392 e1000_get_cfg_done_generic(struct e1000_hw *hw)
2393 {
2394 DEBUGFUNC("e1000_get_cfg_done_generic");
2395 UNREFERENCED_1PARAMETER(hw);
2396
2397 msec_delay_irq(10);
2398
2399 return (E1000_SUCCESS);
2400 }
2401
2402 /*
2403 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2404 * @hw: pointer to the HW structure
2405 *
2406 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2407 */
2408 s32
e1000_phy_init_script_igp3(struct e1000_hw * hw)2409 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2410 {
2411 DEBUGOUT("Running IGP 3 PHY init script\n");
2412
2413 /* PHY init IGP 3 */
2414 /* Enable rise/fall, 10-mode work in class-A */
2415 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2416 /* Remove all caps from Replica path filter */
2417 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2418 /* Bias trimming for ADC, AFE and Driver (Default) */
2419 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2420 /* Increase Hybrid poly bias */
2421 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2422 /* Add 4% to TX amplitude in Giga mode */
2423 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2424 /* Disable trimming (TTT) */
2425 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2426 /* Poly DC correction to 94.6% + 2% for all channels */
2427 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2428 /* ABS DC correction to 95.9% */
2429 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2430 /* BG temp curve trim */
2431 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2432 /* Increasing ADC OPAMP stage 1 currents to max */
2433 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2434 /* Force 1000 ( required for enabling PHY regs configuration) */
2435 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2436 /* Set upd_freq to 6 */
2437 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2438 /* Disable NPDFE */
2439 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2440 /* Disable adaptive fixed FFE (Default) */
2441 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2442 /* Enable FFE hysteresis */
2443 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2444 /* Fixed FFE for short cable lengths */
2445 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2446 /* Fixed FFE for medium cable lengths */
2447 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2448 /* Fixed FFE for long cable lengths */
2449 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2450 /* Enable Adaptive Clip Threshold */
2451 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2452 /* AHT reset limit to 1 */
2453 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2454 /* Set AHT master delay to 127 msec */
2455 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2456 /* Set scan bits for AHT */
2457 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2458 /* Set AHT Preset bits */
2459 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2460 /* Change integ_factor of channel A to 3 */
2461 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2462 /* Change prop_factor of channels BCD to 8 */
2463 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2464 /* Change cg_icount + enable integbp for channels BCD */
2465 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2466 /*
2467 * Change cg_icount + enable integbp + change prop_factor_master to 8
2468 * for channel A
2469 */
2470 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2471 /* Disable AHT in Slave mode on channel A */
2472 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2473 /*
2474 * Enable LPLU and disable AN to 1000 in non-D0a states, Enable
2475 * SPD+B2B
2476 */
2477 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2478 /* Enable restart AN on an1000_dis change */
2479 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2480 /* Enable wh_fifo read clock in 10/100 modes */
2481 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2482 /* Restart AN, Speed selection is 1000 */
2483 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2484
2485 return (E1000_SUCCESS);
2486 }
2487
2488 /*
2489 * e1000_get_phy_type_from_id - Get PHY type from id
2490 * @phy_id: phy_id read from the phy
2491 *
2492 * Returns the phy type from the id.
2493 */
2494 enum e1000_phy_type
e1000_get_phy_type_from_id(u32 phy_id)2495 e1000_get_phy_type_from_id(u32 phy_id)
2496 {
2497 enum e1000_phy_type phy_type = e1000_phy_unknown;
2498
2499 switch (phy_id) {
2500 case M88E1000_I_PHY_ID:
2501 case M88E1000_E_PHY_ID:
2502 case M88E1111_I_PHY_ID:
2503 case M88E1011_I_PHY_ID:
2504 phy_type = e1000_phy_m88;
2505 break;
2506 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2507 phy_type = e1000_phy_igp_2;
2508 break;
2509 case GG82563_E_PHY_ID:
2510 phy_type = e1000_phy_gg82563;
2511 break;
2512 case IGP03E1000_E_PHY_ID:
2513 phy_type = e1000_phy_igp_3;
2514 break;
2515 case IFE_E_PHY_ID:
2516 case IFE_PLUS_E_PHY_ID:
2517 case IFE_C_E_PHY_ID:
2518 phy_type = e1000_phy_ife;
2519 break;
2520 case BME1000_E_PHY_ID:
2521 case BME1000_E_PHY_ID_R2:
2522 phy_type = e1000_phy_bm;
2523 break;
2524 case I82578_E_PHY_ID:
2525 phy_type = e1000_phy_82578;
2526 break;
2527 case I82577_E_PHY_ID:
2528 phy_type = e1000_phy_82577;
2529 break;
2530 default:
2531 phy_type = e1000_phy_unknown;
2532 break;
2533 }
2534 return (phy_type);
2535 }
2536
2537 /*
2538 * e1000_determine_phy_address - Determines PHY address.
2539 * @hw: pointer to the HW structure
2540 *
2541 * This uses a trial and error method to loop through possible PHY
2542 * addresses. It tests each by reading the PHY ID registers and
2543 * checking for a match.
2544 */
2545 s32
e1000_determine_phy_address(struct e1000_hw * hw)2546 e1000_determine_phy_address(struct e1000_hw *hw)
2547 {
2548 s32 ret_val = -E1000_ERR_PHY_TYPE;
2549 u32 phy_addr = 0;
2550 u32 i;
2551 enum e1000_phy_type phy_type = e1000_phy_unknown;
2552
2553 hw->phy.id = phy_type;
2554
2555 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2556 hw->phy.addr = phy_addr;
2557 i = 0;
2558
2559 do {
2560 (void) e1000_get_phy_id(hw);
2561 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
2562
2563 /*
2564 * If phy_type is valid, break - we found our
2565 * PHY address
2566 */
2567 if (phy_type != e1000_phy_unknown) {
2568 ret_val = E1000_SUCCESS;
2569 goto out;
2570 }
2571 msec_delay(1);
2572 i++;
2573 } while (i < 10);
2574 }
2575
2576 out:
2577 return (ret_val);
2578 }
2579
2580 /*
2581 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2582 * @page: page to access
2583 *
2584 * Returns the phy address for the page requested.
2585 */
2586 static u32
e1000_get_phy_addr_for_bm_page(u32 page,u32 reg)2587 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2588 {
2589 u32 phy_addr = 2;
2590
2591 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2592 phy_addr = 1;
2593
2594 return (phy_addr);
2595 }
2596
2597 /*
2598 * e1000_write_phy_reg_bm - Write BM PHY register
2599 * @hw: pointer to the HW structure
2600 * @offset: register offset to write to
2601 * @data: data to write at register offset
2602 *
2603 * Acquires semaphore, if necessary, then writes the data to PHY register
2604 * at the offset. Release any acquired semaphores before exiting.
2605 */
2606 s32
e1000_write_phy_reg_bm(struct e1000_hw * hw,u32 offset,u16 data)2607 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2608 {
2609 s32 ret_val;
2610 u32 page_select = 0;
2611 u32 page = offset >> IGP_PAGE_SHIFT;
2612 u32 page_shift = 0;
2613
2614 DEBUGFUNC("e1000_write_phy_reg_bm");
2615
2616 ret_val = hw->phy.ops.acquire(hw);
2617 if (ret_val)
2618 goto out;
2619
2620 /* Page 800 works differently than the rest so it has its own func */
2621 if (page == BM_WUC_PAGE) {
2622 ret_val = e1000_access_phy_wakeup_reg_bm(hw,
2623 offset, &data, false);
2624 goto out;
2625 }
2626
2627 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2628
2629 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2630 /*
2631 * Page select is register 31 for phy address 1 and 22 for phy
2632 * address 2 and 3. Page select is shifted only for phy
2633 * address 1.
2634 */
2635 if (hw->phy.addr == 1) {
2636 page_shift = IGP_PAGE_SHIFT;
2637 page_select = IGP01E1000_PHY_PAGE_SELECT;
2638 } else {
2639 page_shift = 0;
2640 page_select = BM_PHY_PAGE_SELECT;
2641 }
2642
2643 /* Page is shifted left, PHY expects (page x 32) */
2644 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
2645 (page << page_shift));
2646 if (ret_val)
2647 goto out;
2648 }
2649
2650 ret_val = e1000_write_phy_reg_mdic(hw,
2651 MAX_PHY_REG_ADDRESS & offset,
2652 data);
2653
2654 out:
2655 hw->phy.ops.release(hw);
2656 return (ret_val);
2657 }
2658
2659 /*
2660 * e1000_read_phy_reg_bm - Read BM PHY register
2661 * @hw: pointer to the HW structure
2662 * @offset: register offset to be read
2663 * @data: pointer to the read data
2664 *
2665 * Acquires semaphore, if necessary, then reads the PHY register at offset
2666 * and storing the retrieved information in data. Release any acquired
2667 * semaphores before exiting.
2668 */
2669 s32
e1000_read_phy_reg_bm(struct e1000_hw * hw,u32 offset,u16 * data)2670 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2671 {
2672 s32 ret_val;
2673 u32 page_select = 0;
2674 u32 page = offset >> IGP_PAGE_SHIFT;
2675 u32 page_shift = 0;
2676
2677 DEBUGFUNC("e1000_read_phy_reg_bm");
2678
2679 ret_val = hw->phy.ops.acquire(hw);
2680 if (ret_val)
2681 goto out;
2682
2683 /* Page 800 works differently than the rest so it has its own func */
2684 if (page == BM_WUC_PAGE) {
2685 ret_val = e1000_access_phy_wakeup_reg_bm(hw,
2686 offset, data, true);
2687 goto out;
2688 }
2689
2690 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2691
2692 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2693 /*
2694 * Page select is register 31 for phy address 1 and 22 for phy
2695 * address 2 and 3. Page select is shifted only for phy
2696 * address 1.
2697 */
2698 if (hw->phy.addr == 1) {
2699 page_shift = IGP_PAGE_SHIFT;
2700 page_select = IGP01E1000_PHY_PAGE_SELECT;
2701 } else {
2702 page_shift = 0;
2703 page_select = BM_PHY_PAGE_SELECT;
2704 }
2705
2706 /* Page is shifted left, PHY expects (page x 32) */
2707 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
2708 (page << page_shift));
2709 if (ret_val)
2710 goto out;
2711 }
2712
2713 ret_val = e1000_read_phy_reg_mdic(hw,
2714 MAX_PHY_REG_ADDRESS & offset,
2715 data);
2716
2717 out:
2718 hw->phy.ops.release(hw);
2719 return (ret_val);
2720 }
2721
2722 /*
2723 * e1000_read_phy_reg_bm2 - Read BM PHY register
2724 * @hw: pointer to the HW structure
2725 * @offset: register offset to be read
2726 * @data: pointer to the read data
2727 *
2728 * Acquires semaphore, if necessary, then reads the PHY register at offset
2729 * and storing the retrieved information in data. Release any acquired
2730 * semaphores before exiting.
2731 */
2732 s32
e1000_read_phy_reg_bm2(struct e1000_hw * hw,u32 offset,u16 * data)2733 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2734 {
2735 s32 ret_val;
2736 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2737
2738 DEBUGFUNC("e1000_write_phy_reg_bm2");
2739
2740 ret_val = hw->phy.ops.acquire(hw);
2741 if (ret_val)
2742 goto out;
2743
2744 /* Page 800 works differently than the rest so it has its own func */
2745 if (page == BM_WUC_PAGE) {
2746 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2747 true);
2748 goto out;
2749 }
2750
2751 hw->phy.addr = 1;
2752
2753 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2754
2755 /* Page is shifted left, PHY expects (page x 32) */
2756 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2757 page);
2758
2759 if (ret_val)
2760 goto out;
2761 }
2762
2763 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2764 data);
2765
2766 out:
2767 hw->phy.ops.release(hw);
2768 return (ret_val);
2769 }
2770
2771 /*
2772 * e1000_write_phy_reg_bm2 - Write BM PHY register
2773 * @hw: pointer to the HW structure
2774 * @offset: register offset to write to
2775 * @data: data to write at register offset
2776 *
2777 * Acquires semaphore, if necessary, then writes the data to PHY register
2778 * at the offset. Release any acquired semaphores before exiting.
2779 */
2780 s32
e1000_write_phy_reg_bm2(struct e1000_hw * hw,u32 offset,u16 data)2781 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2782 {
2783 s32 ret_val;
2784 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2785
2786 DEBUGFUNC("e1000_write_phy_reg_bm2");
2787
2788 ret_val = hw->phy.ops.acquire(hw);
2789 if (ret_val)
2790 goto out;
2791
2792 /* Page 800 works differently than the rest so it has its own func */
2793 if (page == BM_WUC_PAGE) {
2794 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2795 false);
2796 goto out;
2797 }
2798
2799 hw->phy.addr = 1;
2800
2801 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2802 /* Page is shifted left, PHY expects (page x 32) */
2803 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2804 page);
2805
2806 if (ret_val)
2807 goto out;
2808 }
2809
2810 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2811 data);
2812
2813 out:
2814 hw->phy.ops.release(hw);
2815 return (ret_val);
2816 }
2817
2818 /*
2819 * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register
2820 * @hw: pointer to the HW structure
2821 * @offset: register offset to be read or written
2822 * @data: pointer to the data to read or write
2823 * @read: determines if operation is read or write
2824 *
2825 * Acquires semaphore, if necessary, then reads the PHY register at offset
2826 * and storing the retrieved information in data. Release any acquired
2827 * semaphores before exiting. Note that procedure to read the wakeup
2828 * registers are different. It works as such:
2829 * 1) Set page 769, register 17, bit 2 = 1
2830 * 2) Set page to 800 for host (801 if we were manageability)
2831 * 3) Write the address using the address opcode (0x11)
2832 * 4) Read or write the data using the data opcode (0x12)
2833 * 5) Restore 769_17.2 to its original value
2834 *
2835 * Assumes semaphore already acquired.
2836 */
2837 static s32
e1000_access_phy_wakeup_reg_bm(struct e1000_hw * hw,u32 offset,u16 * data,bool read)2838 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw,
2839 u32 offset, u16 *data, bool read)
2840 {
2841 s32 ret_val;
2842 u16 reg = BM_PHY_REG_NUM(offset);
2843 u16 phy_reg = 0;
2844
2845 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm");
2846
2847 /* Gig must be disabled for MDIO accesses to page 800 */
2848 if ((hw->mac.type == e1000_pchlan) &&
2849 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) &
2850 E1000_PHY_CTRL_GBE_DISABLE))) {
2851 /* EMPTY */
2852 DEBUGOUT("Attempting to access page 800 while gig enabled.\n");
2853 }
2854
2855 /* All operations in this function are phy address 1 */
2856 hw->phy.addr = 1;
2857
2858 /* Set page 769 */
2859 (void) e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
2860 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
2861
2862 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg);
2863 if (ret_val) {
2864 DEBUGOUT("Could not read PHY page 769\n");
2865 goto out;
2866 }
2867
2868 /* First clear bit 4 to avoid a power state change */
2869 phy_reg &= ~(BM_WUC_HOST_WU_BIT);
2870 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2871 if (ret_val) {
2872 DEBUGOUT("Could not clear PHY page 769 bit 4\n");
2873 goto out;
2874 }
2875
2876 /* Write bit 2 = 1, and clear bit 4 to 769_17 */
2877 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG,
2878 phy_reg | BM_WUC_ENABLE_BIT);
2879 if (ret_val) {
2880 DEBUGOUT("Could not write PHY page 769 bit 2\n");
2881 goto out;
2882 }
2883
2884 /* Select page 800 */
2885 ret_val = e1000_write_phy_reg_mdic(hw,
2886 IGP01E1000_PHY_PAGE_SELECT,
2887 (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2888
2889 /* Write the page 800 offset value using opcode 0x11 */
2890 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2891 if (ret_val) {
2892 DEBUGOUT("Could not write address opcode to page 800\n");
2893 goto out;
2894 }
2895
2896 if (read) {
2897 /* Read the page 800 value using opcode 0x12 */
2898 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2899 data);
2900 } else {
2901 /* Write the page 800 value using opcode 0x12 */
2902 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2903 *data);
2904 }
2905
2906 if (ret_val) {
2907 DEBUGOUT("Could not access data value from page 800\n");
2908 goto out;
2909 }
2910
2911 /*
2912 * Restore 769_17.2 to its original value Set page 769
2913 */
2914 (void) e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
2915 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
2916
2917 /* Clear 769_17.2 */
2918 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2919 if (ret_val) {
2920 DEBUGOUT("Could not clear PHY page 769 bit 2\n");
2921 goto out;
2922 }
2923
2924 out:
2925 return (ret_val);
2926 }
2927
2928 /*
2929 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2930 * @hw: pointer to the HW structure
2931 *
2932 * In the case of a PHY power down to save power, or to turn off link during a
2933 * driver unload, or wake on lan is not enabled, restore the link to previous
2934 * settings.
2935 */
2936 void
e1000_power_up_phy_copper(struct e1000_hw * hw)2937 e1000_power_up_phy_copper(struct e1000_hw *hw)
2938 {
2939 u16 mii_reg = 0;
2940
2941 /* The PHY will retain its settings across a power down/up cycle */
2942 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2943 mii_reg &= ~MII_CR_POWER_DOWN;
2944 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2945 }
2946
2947 /*
2948 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2949 * @hw: pointer to the HW structure
2950 *
2951 * In the case of a PHY power down to save power, or to turn off link during a
2952 * driver unload, or wake on lan is not enabled, restore the link to previous
2953 * settings.
2954 */
2955 void
e1000_power_down_phy_copper(struct e1000_hw * hw)2956 e1000_power_down_phy_copper(struct e1000_hw *hw)
2957 {
2958 u16 mii_reg = 0;
2959
2960 /* The PHY will retain its settings across a power down/up cycle */
2961 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2962 mii_reg |= MII_CR_POWER_DOWN;
2963 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2964 msec_delay(1);
2965 }
2966
2967 /*
2968 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2969 * @hw: pointer to the HW structure
2970 * @slow: true for slow mode, false for normal mode
2971 *
2972 * Assumes semaphore already acquired.
2973 */
2974 s32
e1000_set_mdio_slow_mode_hv(struct e1000_hw * hw,bool slow)2975 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw, bool slow)
2976 {
2977 s32 ret_val = E1000_SUCCESS;
2978 u16 data = 0;
2979
2980 /* Set MDIO mode - page 769, register 16: 0x2580==slow, 0x2180==fast */
2981 hw->phy.addr = 1;
2982 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
2983 (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2984 if (ret_val)
2985 goto out;
2986
2987 ret_val = e1000_write_phy_reg_mdic(hw, BM_CS_CTRL1,
2988 (0x2180 | (slow << 10)));
2989
2990 if (ret_val)
2991 goto out;
2992
2993 /* dummy read when reverting to fast mode - throw away result */
2994 if (!slow)
2995 ret_val = e1000_read_phy_reg_mdic(hw, BM_CS_CTRL1, &data);
2996
2997 out:
2998 return (ret_val);
2999 }
3000
3001 /*
3002 * __e1000_read_phy_reg_hv - Read HV PHY register
3003 * @hw: pointer to the HW structure
3004 * @offset: register offset to be read
3005 * @data: pointer to the read data
3006 * @locked: semaphore has already been acquired or not
3007 *
3008 * Acquires semaphore, if necessary, then reads the PHY register at offset
3009 * and stores the retrieved information in data. Release any acquired
3010 * semaphore before exiting.
3011 */
3012 static s32
__e1000_read_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 * data,bool locked)3013 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
3014 bool locked)
3015 {
3016 s32 ret_val;
3017 u16 page = BM_PHY_REG_PAGE(offset);
3018 u16 reg = BM_PHY_REG_NUM(offset);
3019 bool in_slow_mode = false;
3020
3021 DEBUGFUNC("e1000_read_phy_reg_hv");
3022
3023 if (!locked) {
3024 ret_val = hw->phy.ops.acquire(hw);
3025 if (ret_val)
3026 return (ret_val);
3027 }
3028
3029 /* Workaround failure in MDIO access while cable is disconnected */
3030 if ((hw->phy.type == e1000_phy_82577) &&
3031 !(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
3032 ret_val = e1000_set_mdio_slow_mode_hv(hw, true);
3033 if (ret_val)
3034 goto out;
3035
3036 in_slow_mode = true;
3037 }
3038
3039 /* Page 800 works differently than the rest so it has its own func */
3040 if (page == BM_WUC_PAGE) {
3041 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
3042 data, true);
3043 goto out;
3044 }
3045
3046 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3047 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3048 data, true);
3049 goto out;
3050 }
3051
3052 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3053
3054 if (page == HV_INTC_FC_PAGE_START)
3055 page = 0;
3056
3057 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3058 u32 phy_addr = hw->phy.addr;
3059
3060 hw->phy.addr = 1;
3061
3062 /* Page is shifted left, PHY expects (page x 32) */
3063 ret_val = e1000_write_phy_reg_mdic(hw,
3064 IGP01E1000_PHY_PAGE_SELECT, (page << IGP_PAGE_SHIFT));
3065 hw->phy.addr = phy_addr;
3066 }
3067
3068 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, data);
3069 out:
3070 /* Revert to MDIO fast mode, if applicable */
3071 if ((hw->phy.type == e1000_phy_82577) && in_slow_mode)
3072 ret_val = e1000_set_mdio_slow_mode_hv(hw, false);
3073
3074 if (!locked)
3075 hw->phy.ops.release(hw);
3076
3077 return (ret_val);
3078 }
3079
3080 /*
3081 * e1000_read_phy_reg_hv - Read HV PHY register
3082 * @hw: pointer to the HW structure
3083 * @offset: register offset to be read
3084 * @data: pointer to the read data
3085 *
3086 * Acquires semaphore then reads the PHY register at offset and stores
3087 * the retrieved information in data. Release the acquired semaphore
3088 * before exiting.
3089 */
3090 s32
e1000_read_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 * data)3091 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3092 {
3093 return (__e1000_read_phy_reg_hv(hw, offset, data, false));
3094 }
3095
3096 /*
3097 * e1000_read_phy_reg_hv_locked - Read HV PHY register
3098 * @hw: pointer to the HW structure
3099 * @offset: register offset to be read
3100 * @data: pointer to the read data
3101 *
3102 * Reads the PHY register at offset and stores the retrieved information
3103 * in data. Assumes semaphore already acquired.
3104 */
3105 s32
e1000_read_phy_reg_hv_locked(struct e1000_hw * hw,u32 offset,u16 * data)3106 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
3107 {
3108 return (__e1000_read_phy_reg_hv(hw, offset, data, true));
3109 }
3110
3111 /*
3112 * __e1000_write_phy_reg_hv - Write HV PHY register
3113 * @hw: pointer to the HW structure
3114 * @offset: register offset to write to
3115 * @data: data to write at register offset
3116 * @locked: semaphore has already been acquired or not
3117 *
3118 * Acquires semaphore, if necessary, then writes the data to PHY register
3119 * at the offset. Release any acquired semaphores before exiting.
3120 */
3121 static s32
__e1000_write_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 data,bool locked)3122 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
3123 bool locked)
3124 {
3125 s32 ret_val;
3126 u16 page = BM_PHY_REG_PAGE(offset);
3127 u16 reg = BM_PHY_REG_NUM(offset);
3128 bool in_slow_mode = false;
3129 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3130
3131 DEBUGFUNC("e1000_write_phy_reg_hv");
3132
3133 if (!locked) {
3134 ret_val = hw->phy.ops.acquire(hw);
3135 if (ret_val)
3136 return (ret_val);
3137 }
3138
3139 /* Workaround failure in MDIO access while cable is disconnected */
3140 if ((hw->phy.type == e1000_phy_82577) &&
3141 !(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
3142 ret_val = e1000_set_mdio_slow_mode_hv(hw, true);
3143 if (ret_val)
3144 goto out;
3145
3146 in_slow_mode = true;
3147 }
3148
3149 /* Page 800 works differently than the rest so it has its own func */
3150 if (page == BM_WUC_PAGE) {
3151 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
3152 &data, false);
3153 goto out;
3154 }
3155
3156 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3157 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3158 &data, false);
3159 goto out;
3160 }
3161
3162 /* The LCD Config workaround provides the phy address to use */
3163 if (dev_spec->nvm_lcd_config_enabled == false)
3164 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3165
3166 if (page == HV_INTC_FC_PAGE_START)
3167 page = 0;
3168
3169 /*
3170 * Workaround MDIO accesses being disabled after entering IEEE Power
3171 * Down (whenever bit 11 of the PHY Control register is set)
3172 */
3173 if ((hw->phy.type == e1000_phy_82578) &&
3174 (hw->phy.revision >= 1) &&
3175 (hw->phy.addr == 2) &&
3176 ((MAX_PHY_REG_ADDRESS & reg) == 0) &&
3177 (data & (1 << 11))) {
3178 u16 data2 = 0x7EFF;
3179 ret_val = e1000_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3,
3180 &data2, false);
3181 if (ret_val)
3182 goto out;
3183 }
3184
3185 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3186 u32 phy_addr = hw->phy.addr;
3187
3188 hw->phy.addr = 1;
3189
3190 /* Page is shifted left, PHY expects (page x 32) */
3191 ret_val = e1000_write_phy_reg_mdic(hw,
3192 IGP01E1000_PHY_PAGE_SELECT, (page << IGP_PAGE_SHIFT));
3193 hw->phy.addr = phy_addr;
3194 }
3195
3196 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3197 data);
3198
3199 out:
3200 /* Revert to MDIO fast mode, if applicable */
3201 if ((hw->phy.type == e1000_phy_82577) && in_slow_mode)
3202 ret_val = e1000_set_mdio_slow_mode_hv(hw, false);
3203
3204 if (!locked)
3205 hw->phy.ops.release(hw);
3206
3207 return (ret_val);
3208 }
3209
3210 /*
3211 * e1000_write_phy_reg_hv - Write HV PHY register
3212 * @hw: pointer to the HW structure
3213 * @offset: register offset to write to
3214 * @data: data to write at register offset
3215 *
3216 * Acquires semaphore then writes the data to PHY register at the offset.
3217 * Release the acquired semaphores before exiting.
3218 */
3219 s32
e1000_write_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 data)3220 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3221 {
3222 return (__e1000_write_phy_reg_hv(hw, offset, data, false));
3223 }
3224
3225 /*
3226 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3227 * @hw: pointer to the HW structure
3228 * @offset: register offset to write to
3229 * @data: data to write at register offset
3230 *
3231 * Writes the data to PHY register at the offset. Assumes semaphore
3232 * already acquired.
3233 */
3234 s32
e1000_write_phy_reg_hv_locked(struct e1000_hw * hw,u32 offset,u16 data)3235 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3236 {
3237 return (__e1000_write_phy_reg_hv(hw, offset, data, true));
3238 }
3239
3240 /*
3241 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
3242 * @page: page to be accessed
3243 */
3244 static u32
e1000_get_phy_addr_for_hv_page(u32 page)3245 e1000_get_phy_addr_for_hv_page(u32 page)
3246 {
3247 u32 phy_addr = 2;
3248
3249 if (page >= HV_INTC_FC_PAGE_START)
3250 phy_addr = 1;
3251
3252 return (phy_addr);
3253 }
3254
3255 /*
3256 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3257 * @hw: pointer to the HW structure
3258 * @offset: register offset to be read or written
3259 * @data: pointer to the data to be read or written
3260 * @read: determines if operation is read or written
3261 *
3262 * Reads the PHY register at offset and stores the retreived information
3263 * in data. Assumes semaphore already acquired. Note that the procedure
3264 * to read these regs uses the address port and data port to read/write.
3265 */
3266 static s32
e1000_access_phy_debug_regs_hv(struct e1000_hw * hw,u32 offset,u16 * data,bool read)3267 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3268 u16 *data, bool read)
3269 {
3270 s32 ret_val;
3271 u32 addr_reg = 0;
3272 u32 data_reg = 0;
3273
3274 DEBUGFUNC("e1000_access_phy_debug_regs_hv");
3275
3276 /* This takes care of the difference with desktop vs mobile phy */
3277 addr_reg = (hw->phy.type == e1000_phy_82578) ?
3278 I82578_ADDR_REG : I82577_ADDR_REG;
3279 data_reg = addr_reg + 1;
3280
3281 /* All operations in this function are phy address 2 */
3282 hw->phy.addr = 2;
3283
3284 /* masking with 0x3F to remove the page from offset */
3285 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3286 if (ret_val) {
3287 DEBUGOUT("Could not write PHY the HV address register\n");
3288 goto out;
3289 }
3290
3291 /* Read or write the data value next */
3292 if (read)
3293 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data);
3294 else
3295 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data);
3296
3297 if (ret_val) {
3298 DEBUGOUT("Could not read data value from HV data register\n");
3299 goto out;
3300 }
3301
3302 out:
3303 return (ret_val);
3304 }
3305
3306 /*
3307 * e1000_link_stall_workaround_hv - Si workaround
3308 * @hw: pointer to the HW structure
3309 *
3310 * This function works around a Si bug where the link partner can get
3311 * a link up indication before the PHY does. If small packets are sent
3312 * by the link partner they can be placed in the packet buffer without
3313 * being properly accounted for by the PHY and will stall preventing
3314 * further packets from being received. The workaround is to clear the
3315 * packet buffer after the PHY detects link up.
3316 */
3317 s32
e1000_link_stall_workaround_hv(struct e1000_hw * hw)3318 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3319 {
3320 s32 ret_val = E1000_SUCCESS;
3321 u16 data;
3322
3323 DEBUGFUNC("e1000_link_stall_workaround_hv");
3324
3325 if (hw->phy.type != e1000_phy_82578)
3326 goto out;
3327
3328 /* Do not apply workaround if in PHY loopback bit 14 set */
3329 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3330 if (data & PHY_CONTROL_LB)
3331 goto out;
3332
3333 /* check if link is up and at 1Gbps */
3334 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3335 if (ret_val)
3336 goto out;
3337
3338 data &= BM_CS_STATUS_LINK_UP |
3339 BM_CS_STATUS_RESOLVED |
3340 BM_CS_STATUS_SPEED_MASK;
3341
3342 if (data != (BM_CS_STATUS_LINK_UP |
3343 BM_CS_STATUS_RESOLVED |
3344 BM_CS_STATUS_SPEED_1000))
3345 goto out;
3346
3347 msec_delay(200);
3348
3349 /* flush the packets in the fifo buffer */
3350 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3351 HV_MUX_DATA_CTRL_GEN_TO_MAC | HV_MUX_DATA_CTRL_FORCE_SPEED);
3352 if (ret_val)
3353 goto out;
3354
3355 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3356 HV_MUX_DATA_CTRL_GEN_TO_MAC);
3357
3358 out:
3359 return (ret_val);
3360 }
3361
3362 /*
3363 * e1000_check_polarity_82577 - Checks the polarity.
3364 * @hw: pointer to the HW structure
3365 *
3366 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3367 *
3368 * Polarity is determined based on the PHY specific status register.
3369 */
3370 s32
e1000_check_polarity_82577(struct e1000_hw * hw)3371 e1000_check_polarity_82577(struct e1000_hw *hw)
3372 {
3373 struct e1000_phy_info *phy = &hw->phy;
3374 s32 ret_val;
3375 u16 data;
3376
3377 DEBUGFUNC("e1000_check_polarity_82577");
3378
3379 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3380
3381 if (!ret_val)
3382 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
3383 ? e1000_rev_polarity_reversed
3384 : e1000_rev_polarity_normal;
3385
3386 return (ret_val);
3387 }
3388
3389 /*
3390 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3391 * @hw: pointer to the HW structure
3392 *
3393 * Calls the PHY setup function to force speed and duplex. Clears the
3394 * auto-crossover to force MDI manually. Waits for link and returns
3395 * successful if link up is successful, else -E1000_ERR_PHY (-2).
3396 */
3397 s32
e1000_phy_force_speed_duplex_82577(struct e1000_hw * hw)3398 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3399 {
3400 struct e1000_phy_info *phy = &hw->phy;
3401 s32 ret_val;
3402 u16 phy_data;
3403 bool link;
3404
3405 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
3406
3407 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3408 if (ret_val)
3409 goto out;
3410
3411 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
3412
3413 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3414 if (ret_val)
3415 goto out;
3416
3417 /*
3418 * Clear Auto-Crossover to force MDI manually. 82577 requires MDI
3419 * forced whenever speed and duplex are forced.
3420 */
3421 ret_val = phy->ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
3422 if (ret_val)
3423 goto out;
3424
3425 phy_data &= ~I82577_PHY_CTRL2_AUTO_MDIX;
3426 phy_data &= ~I82577_PHY_CTRL2_FORCE_MDI_MDIX;
3427
3428 ret_val = phy->ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
3429 if (ret_val)
3430 goto out;
3431
3432 DEBUGOUT1("I82577_PHY_CTRL_2: %X\n", phy_data);
3433
3434 usec_delay(1);
3435
3436 if (phy->autoneg_wait_to_complete) {
3437 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3438
3439 ret_val = e1000_phy_has_link_generic(hw,
3440 PHY_FORCE_LIMIT, 100000, &link);
3441 if (ret_val)
3442 goto out;
3443
3444 if (!link) {
3445 /* EMPTY */
3446 DEBUGOUT("Link taking longer than expected.\n");
3447 }
3448
3449 /* Try once more */
3450 ret_val = e1000_phy_has_link_generic(hw,
3451 PHY_FORCE_LIMIT, 100000, &link);
3452 if (ret_val)
3453 goto out;
3454 }
3455
3456 out:
3457 return (ret_val);
3458 }
3459
3460 /*
3461 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3462 * @hw: pointer to the HW structure
3463 *
3464 * Read PHY status to determine if link is up. If link is up, then
3465 * set/determine 10base-T extended distance and polarity correction. Read
3466 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3467 * determine on the cable length, local and remote receiver.
3468 */
3469 s32
e1000_get_phy_info_82577(struct e1000_hw * hw)3470 e1000_get_phy_info_82577(struct e1000_hw *hw)
3471 {
3472 struct e1000_phy_info *phy = &hw->phy;
3473 s32 ret_val;
3474 u16 data;
3475 bool link;
3476
3477 DEBUGFUNC("e1000_get_phy_info_82577");
3478
3479 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3480 if (ret_val)
3481 goto out;
3482
3483 if (!link) {
3484 DEBUGOUT("Phy info is only valid if link is up\n");
3485 ret_val = -E1000_ERR_CONFIG;
3486 goto out;
3487 }
3488
3489 phy->polarity_correction = true;
3490
3491 ret_val = e1000_check_polarity_82577(hw);
3492 if (ret_val)
3493 goto out;
3494
3495 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3496 if (ret_val)
3497 goto out;
3498
3499 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? true : false;
3500
3501 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3502 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3503 ret_val = hw->phy.ops.get_cable_length(hw);
3504 if (ret_val)
3505 goto out;
3506
3507 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
3508 if (ret_val)
3509 goto out;
3510
3511 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3512 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3513
3514 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3515 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3516 } else {
3517 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3518 phy->local_rx = e1000_1000t_rx_status_undefined;
3519 phy->remote_rx = e1000_1000t_rx_status_undefined;
3520 }
3521
3522 out:
3523 return (ret_val);
3524 }
3525
3526 /*
3527 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3528 * @hw: pointer to the HW structure
3529 *
3530 * Reads the diagnostic status register and verifies result is valid before
3531 * placing it in the phy_cable_length field.
3532 */
3533 s32
e1000_get_cable_length_82577(struct e1000_hw * hw)3534 e1000_get_cable_length_82577(struct e1000_hw *hw)
3535 {
3536 struct e1000_phy_info *phy = &hw->phy;
3537 s32 ret_val;
3538 u16 phy_data, length;
3539
3540 DEBUGFUNC("e1000_get_cable_length_82577");
3541
3542 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3543 if (ret_val)
3544 goto out;
3545
3546 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3547 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
3548
3549 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3550 ret_val = E1000_ERR_PHY;
3551
3552 phy->cable_length = length;
3553
3554 out:
3555 return (ret_val);
3556 }
3557