1 /*
2 * This file is provided under a CDDLv1 license. When using or
3 * redistributing this file, you may do so under this license.
4 * In redistributing this file this license must be included
5 * and no other modification of this header file is permitted.
6 *
7 * CDDL LICENSE SUMMARY
8 *
9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved.
10 *
11 * The contents of this file are subject to the terms of Version
12 * 1.0 of the Common Development and Distribution License (the "License").
13 *
14 * You should have received a copy of the License with this software.
15 * You can obtain a copy of the License at
16 * http://www.opensolaris.org/os/licensing.
17 * See the License for the specific language governing permissions
18 * and limitations under the License.
19 */
20
21 /*
22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms of the CDDLv1.
24 */
25
26 /*
27 * IntelVersion: 1.186.2.1 v3-1-10-1_2009-9-18_Release14-6
28 */
29
30 /*
31 * 82562G 10/100 Network Connection
32 * 82562G-2 10/100 Network Connection
33 * 82562GT 10/100 Network Connection
34 * 82562GT-2 10/100 Network Connection
35 * 82562V 10/100 Network Connection
36 * 82562V-2 10/100 Network Connection
37 * 82566DC-2 Gigabit Network Connection
38 * 82566DC Gigabit Network Connection
39 * 82566DM-2 Gigabit Network Connection
40 * 82566DM Gigabit Network Connection
41 * 82566MC Gigabit Network Connection
42 * 82566MM Gigabit Network Connection
43 * 82567LM Gigabit Network Connection
44 * 82567LF Gigabit Network Connection
45 * 82567V Gigabit Network Connection
46 * 82567LM-2 Gigabit Network Connection
47 * 82567LF-2 Gigabit Network Connection
48 * 82567V-2 Gigabit Network Connection
49 * 82567LF-3 Gigabit Network Connection
50 * 82567LM-3 Gigabit Network Connection
51 * 82567LM-4 Gigabit Network Connection
52 * 82577LM Gigabit Network Connection
53 * 82577LC Gigabit Network Connection
54 * 82578DM Gigabit Network Connection
55 * 82578DC Gigabit Network Connection
56 */
57
58 #include "e1000_api.h"
59
60 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw);
61 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw);
62 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw);
63 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw);
64 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
65 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
66 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
67 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
68 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
69 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
70 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
71 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw);
72 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
73 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
74 bool active);
75 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
76 bool active);
77 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
78 u16 words, u16 *data);
79 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
80 u16 words, u16 *data);
81 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
82 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
83 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
84 u16 *data);
85 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
86 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
87 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
88 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
89 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
90 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
91 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
92 u16 *speed, u16 *duplex);
93 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
94 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
95 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
96 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
97 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
98 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
99 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
100 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
101 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
102 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
103 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout);
104 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw);
105 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw);
106 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
107 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
108 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
109 u32 offset, u8 *data);
110 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
111 u8 size, u16 *data);
112 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
113 u32 offset, u16 *data);
114 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
115 u32 offset, u8 byte);
116 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw,
117 u32 offset, u8 data);
118 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
119 u8 size, u16 data);
120 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
121 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
122 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
123 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
124 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
125
126 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
127 /* Offset 04h HSFSTS */
128 union ich8_hws_flash_status {
129 struct ich8_hsfsts {
130 u16 flcdone:1; /* bit 0 Flash Cycle Done */
131 u16 flcerr:1; /* bit 1 Flash Cycle Error */
132 u16 dael:1; /* bit 2 Direct Access error Log */
133 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
134 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
135 u16 reserved1:2; /* bit 13:6 Reserved */
136 u16 reserved2:6; /* bit 13:6 Reserved */
137 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
138 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
139 } hsf_status;
140 u16 regval;
141 };
142
143 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
144 /* Offset 06h FLCTL */
145 union ich8_hws_flash_ctrl {
146 struct ich8_hsflctl {
147 u16 flcgo:1; /* 0 Flash Cycle Go */
148 u16 flcycle:2; /* 2:1 Flash Cycle */
149 u16 reserved:5; /* 7:3 Reserved */
150 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
151 u16 flockdn:6; /* 15:10 Reserved */
152 } hsf_ctrl;
153 u16 regval;
154 };
155
156 /* ICH Flash Region Access Permissions */
157 union ich8_hws_flash_regacc {
158 struct ich8_flracc {
159 u32 grra:8; /* 0:7 GbE region Read Access */
160 u32 grwa:8; /* 8:15 GbE region Write Access */
161 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
162 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
163 } hsf_flregacc;
164 u16 regval;
165 };
166
167 /*
168 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
169 * @hw: pointer to the HW structure
170 *
171 * Initialize family-specific PHY parameters and function pointers.
172 */
173 static s32
e1000_init_phy_params_pchlan(struct e1000_hw * hw)174 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
175 {
176 struct e1000_phy_info *phy = &hw->phy;
177 s32 ret_val = E1000_SUCCESS;
178
179 DEBUGFUNC("e1000_init_phy_params_pchlan");
180
181 phy->addr = 1;
182 phy->reset_delay_us = 100;
183
184 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
185 phy->ops.check_polarity = e1000_check_polarity_ife;
186 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
187 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
188 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
189 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
190 phy->ops.get_info = e1000_get_phy_info_ich8lan;
191 phy->ops.read_reg = e1000_read_phy_reg_hv;
192 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
193 phy->ops.release = e1000_release_swflag_ich8lan;
194 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
195 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
196 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
197 phy->ops.write_reg = e1000_write_phy_reg_hv;
198 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
199 phy->ops.power_up = e1000_power_up_phy_copper;
200 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
201 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
202
203 phy->id = e1000_phy_unknown;
204 (void) e1000_get_phy_id(hw);
205 phy->type = e1000_get_phy_type_from_id(phy->id);
206
207 if (phy->type == e1000_phy_82577) {
208 phy->ops.check_polarity = e1000_check_polarity_82577;
209 phy->ops.force_speed_duplex =
210 e1000_phy_force_speed_duplex_82577;
211 phy->ops.get_cable_length = e1000_get_cable_length_82577;
212 phy->ops.get_info = e1000_get_phy_info_82577;
213 phy->ops.commit = e1000_phy_sw_reset_generic;
214 }
215
216 return (ret_val);
217 }
218
219 /*
220 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
221 * @hw: pointer to the HW structure
222 *
223 * Initialize family-specific PHY parameters and function pointers.
224 */
225 static s32
e1000_init_phy_params_ich8lan(struct e1000_hw * hw)226 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
227 {
228 struct e1000_phy_info *phy = &hw->phy;
229 s32 ret_val = E1000_SUCCESS;
230 u16 i = 0;
231
232 DEBUGFUNC("e1000_init_phy_params_ich8lan");
233
234 phy->addr = 1;
235 phy->reset_delay_us = 100;
236
237 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
238 phy->ops.check_polarity = e1000_check_polarity_ife;
239 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
240 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
241 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
242 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
243 phy->ops.get_info = e1000_get_phy_info_ich8lan;
244 phy->ops.read_reg = e1000_read_phy_reg_igp;
245 phy->ops.release = e1000_release_swflag_ich8lan;
246 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
247 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
248 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
249 phy->ops.write_reg = e1000_write_phy_reg_igp;
250 phy->ops.power_up = e1000_power_up_phy_copper;
251 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
252
253 /*
254 * We may need to do this twice - once for IGP and if that fails,
255 * we'll set BM func pointers and try again
256 */
257 ret_val = e1000_determine_phy_address(hw);
258 if (ret_val) {
259 phy->ops.write_reg = e1000_write_phy_reg_bm;
260 phy->ops.read_reg = e1000_read_phy_reg_bm;
261 ret_val = e1000_determine_phy_address(hw);
262 if (ret_val) {
263 DEBUGOUT("Can't determine PHY address. Erroring out\n");
264 goto out;
265 }
266 }
267
268 phy->id = 0;
269 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
270 (i++ < 100)) {
271 msec_delay(1);
272 ret_val = e1000_get_phy_id(hw);
273 if (ret_val)
274 goto out;
275 }
276
277 /* Verify phy id */
278 switch (phy->id) {
279 case IGP03E1000_E_PHY_ID:
280 phy->type = e1000_phy_igp_3;
281 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
282 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
283 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
284 break;
285 case IFE_E_PHY_ID:
286 case IFE_PLUS_E_PHY_ID:
287 case IFE_C_E_PHY_ID:
288 phy->type = e1000_phy_ife;
289 phy->autoneg_mask = E1000_ALL_NOT_GIG;
290 break;
291 case BME1000_E_PHY_ID:
292 phy->type = e1000_phy_bm;
293 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
294 phy->ops.read_reg = e1000_read_phy_reg_bm;
295 phy->ops.write_reg = e1000_write_phy_reg_bm;
296 phy->ops.commit = e1000_phy_sw_reset_generic;
297 break;
298 default:
299 ret_val = -E1000_ERR_PHY;
300 goto out;
301 }
302
303 out:
304 return (ret_val);
305 }
306
307 /*
308 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
309 * @hw: pointer to the HW structure
310 *
311 * Initialize family-specific NVM parameters and function
312 * pointers.
313 */
314 static s32
e1000_init_nvm_params_ich8lan(struct e1000_hw * hw)315 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
316 {
317 struct e1000_nvm_info *nvm = &hw->nvm;
318 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
319 u32 gfpreg, sector_base_addr, sector_end_addr;
320 s32 ret_val = E1000_SUCCESS;
321 u16 i;
322
323 DEBUGFUNC("e1000_init_nvm_params_ich8lan");
324
325 /* Can't read flash registers if the register set isn't mapped. */
326 if (!hw->flash_address) {
327 DEBUGOUT("ERROR: Flash registers not mapped\n");
328 ret_val = -E1000_ERR_CONFIG;
329 goto out;
330 }
331
332 nvm->type = e1000_nvm_flash_sw;
333
334 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
335
336 /*
337 * sector_X_addr is a "sector"-aligned address (4096 bytes) Add 1 to
338 * sector_end_addr since this sector is included in the overall size.
339 */
340 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
341 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
342
343 /* flash_base_addr is byte-aligned */
344 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
345
346 /*
347 * find total size of the NVM, then cut in half since the total size
348 * represents two separate NVM banks.
349 */
350 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
351 << FLASH_SECTOR_ADDR_SHIFT;
352 nvm->flash_bank_size /= 2;
353 /* Adjust to word count */
354 nvm->flash_bank_size /= sizeof (u16);
355
356 nvm->word_size = E1000_SHADOW_RAM_WORDS;
357
358 /* Clear shadow ram */
359 for (i = 0; i < nvm->word_size; i++) {
360 dev_spec->shadow_ram[i].modified = false;
361 dev_spec->shadow_ram[i].value = 0xFFFF;
362 }
363
364 E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
365 E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
366
367 /* Function Pointers */
368 nvm->ops.acquire = e1000_acquire_nvm_ich8lan;
369 nvm->ops.release = e1000_release_nvm_ich8lan;
370 nvm->ops.read = e1000_read_nvm_ich8lan;
371 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
372 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
373 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
374 nvm->ops.write = e1000_write_nvm_ich8lan;
375
376 out:
377 return (ret_val);
378 }
379
380 /*
381 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
382 * @hw: pointer to the HW structure
383 *
384 * Initialize family-specific MAC parameters and function
385 * pointers.
386 */
387 static s32
e1000_init_mac_params_ich8lan(struct e1000_hw * hw)388 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
389 {
390 struct e1000_mac_info *mac = &hw->mac;
391
392 DEBUGFUNC("e1000_init_mac_params_ich8lan");
393
394 /* Set media type function pointer */
395 hw->phy.media_type = e1000_media_type_copper;
396
397 /* Set mta register count */
398 mac->mta_reg_count = 32;
399 /* Set rar entry count */
400 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
401 if (mac->type == e1000_ich8lan)
402 mac->rar_entry_count--;
403 /* Set if part includes ASF firmware */
404 mac->asf_firmware_present = true;
405 /* Set if manageability features are enabled. */
406 mac->arc_subsystem_valid = true;
407
408 /* Function pointers */
409
410 /* bus type/speed/width */
411 mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
412 /* function id */
413 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
414 /* reset */
415 mac->ops.reset_hw = e1000_reset_hw_ich8lan;
416 /* hw initialization */
417 mac->ops.init_hw = e1000_init_hw_ich8lan;
418 /* link setup */
419 mac->ops.setup_link = e1000_setup_link_ich8lan;
420 /* physical interface setup */
421 mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
422 /* check for link */
423 mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
424 /* check management mode */
425 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
426 /* link info */
427 mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
428 /* multicast address update */
429 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
430 /* setting MTA */
431 mac->ops.mta_set = e1000_mta_set_generic;
432 /* clear hardware counters */
433 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
434
435 /* LED operations */
436 switch (mac->type) {
437 case e1000_ich8lan:
438 case e1000_ich9lan:
439 case e1000_ich10lan:
440 /* ID LED init */
441 mac->ops.id_led_init = e1000_id_led_init_generic;
442 /* blink LED */
443 mac->ops.blink_led = e1000_blink_led_generic;
444 /* setup LED */
445 mac->ops.setup_led = e1000_setup_led_generic;
446 /* cleanup LED */
447 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
448 /* turn on/off LED */
449 mac->ops.led_on = e1000_led_on_ich8lan;
450 mac->ops.led_off = e1000_led_off_ich8lan;
451 break;
452 case e1000_pchlan:
453 /* ID LED init */
454 mac->ops.id_led_init = e1000_id_led_init_pchlan;
455 /* setup LED */
456 mac->ops.setup_led = e1000_setup_led_pchlan;
457 /* cleanup LED */
458 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
459 /* turn on/off LED */
460 mac->ops.led_on = e1000_led_on_pchlan;
461 mac->ops.led_off = e1000_led_off_pchlan;
462 break;
463 default:
464 break;
465 }
466
467 /* Enable PCS Lock-loss workaround for ICH8 */
468 if (mac->type == e1000_ich8lan)
469 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
470
471 return (E1000_SUCCESS);
472 }
473
474 /*
475 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
476 * @hw: pointer to the HW structure
477 *
478 * Checks to see of the link status of the hardware has changed. If a
479 * change in link status has been detected, then we read the PHY registers
480 * to get the current speed/duplex if link exists.
481 */
482 static s32
e1000_check_for_copper_link_ich8lan(struct e1000_hw * hw)483 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
484 {
485 struct e1000_mac_info *mac = &hw->mac;
486 s32 ret_val;
487 bool link;
488
489 DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
490
491 /*
492 * We only want to go out to the PHY registers to see if Auto-Neg
493 * has completed and/or if our link status has changed. The
494 * get_link_status flag is set upon receiving a Link Status
495 * Change or Rx Sequence Error interrupt.
496 */
497 if (!mac->get_link_status) {
498 ret_val = E1000_SUCCESS;
499 goto out;
500 }
501
502 /*
503 * First we want to see if the MII Status Register reports
504 * link. If so, then we want to get the current speed/duplex
505 * of the PHY.
506 */
507 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
508 if (ret_val)
509 goto out;
510
511 if (hw->mac.type == e1000_pchlan) {
512 ret_val = e1000_k1_gig_workaround_hv(hw, link);
513 if (ret_val)
514 goto out;
515 }
516
517 if (!link)
518 goto out; /* No link detected */
519
520 mac->get_link_status = false;
521
522 if (hw->phy.type == e1000_phy_82578) {
523 ret_val = e1000_link_stall_workaround_hv(hw);
524 if (ret_val)
525 goto out;
526 }
527
528 /*
529 * Check if there was DownShift, must be checked
530 * immediately after link-up
531 */
532 (void) e1000_check_downshift_generic(hw);
533
534 /*
535 * If we are forcing speed/duplex, then we simply return since
536 * we have already determined whether we have link or not.
537 */
538 if (!mac->autoneg) {
539 ret_val = -E1000_ERR_CONFIG;
540 goto out;
541 }
542
543 /*
544 * Auto-Neg is enabled. Auto Speed Detection takes care
545 * of MAC speed/duplex configuration. So we only need to
546 * configure Collision Distance in the MAC.
547 */
548 e1000_config_collision_dist_generic(hw);
549
550 /*
551 * Configure Flow Control now that Auto-Neg has completed.
552 * First, we need to restore the desired flow control
553 * settings because we may have had to re-autoneg with a
554 * different link partner.
555 */
556 ret_val = e1000_config_fc_after_link_up_generic(hw);
557 if (ret_val) {
558 /* EMPTY */
559 DEBUGOUT("Error configuring flow control\n");
560 }
561
562 out:
563 return (ret_val);
564 }
565
566 /*
567 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
568 * @hw: pointer to the HW structure
569 *
570 * Initialize family-specific function pointers for PHY, MAC, and NVM.
571 */
572 void
e1000_init_function_pointers_ich8lan(struct e1000_hw * hw)573 e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
574 {
575 DEBUGFUNC("e1000_init_function_pointers_ich8lan");
576
577 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
578 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
579 switch (hw->mac.type) {
580 case e1000_ich8lan:
581 case e1000_ich9lan:
582 case e1000_ich10lan:
583 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
584 break;
585 case e1000_pchlan:
586 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
587 break;
588 default:
589 break;
590 }
591 }
592
593 /*
594 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
595 * @hw: pointer to the HW structure
596 *
597 * Acquires the mutex for performing NVM operations.
598 */
599 static s32
e1000_acquire_nvm_ich8lan(struct e1000_hw * hw)600 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
601 {
602 DEBUGFUNC("e1000_acquire_nvm_ich8lan");
603
604 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
605
606 return (E1000_SUCCESS);
607 }
608
609 /*
610 * e1000_release_nvm_ich8lan - Release NVM mutex
611 * @hw: pointer to the HW structure
612 *
613 * Releases the mutex used while performing NVM operations.
614 */
615 static void
e1000_release_nvm_ich8lan(struct e1000_hw * hw)616 e1000_release_nvm_ich8lan(struct e1000_hw *hw)
617 {
618 DEBUGFUNC("e1000_release_nvm_ich8lan");
619
620 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
621 }
622
623 /*
624 * e1000_acquire_swflag_ich8lan - Acquire software control flag
625 * @hw: pointer to the HW structure
626 *
627 * Acquires the software control flag for performing PHY and select
628 * MAC CSR accesses.
629 */
630 static s32
e1000_acquire_swflag_ich8lan(struct e1000_hw * hw)631 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
632 {
633 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
634 s32 ret_val = E1000_SUCCESS;
635
636 DEBUGFUNC("e1000_acquire_swflag_ich8lan");
637
638 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
639
640 while (timeout) {
641 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
642 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
643 break;
644
645 msec_delay_irq(1);
646 timeout--;
647 }
648
649 if (!timeout) {
650 DEBUGOUT("SW/FW/HW has locked the resource for too long.\n");
651 ret_val = -E1000_ERR_CONFIG;
652 goto out;
653 }
654
655 /* In some cases, hardware will take up to 400ms to set the SW flag. */
656 timeout = SW_FLAG_TIMEOUT;
657
658 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
659 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
660
661 while (timeout) {
662 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
663 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
664 break;
665
666 msec_delay_irq(1);
667 timeout--;
668 }
669
670 if (!timeout) {
671 DEBUGOUT("Failed to acquire the semaphore.\n");
672 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
673 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
674 ret_val = -E1000_ERR_CONFIG;
675 goto out;
676 }
677
678 out:
679 if (ret_val)
680 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
681
682 return (ret_val);
683 }
684
685 /*
686 * e1000_release_swflag_ich8lan - Release software control flag
687 * @hw: pointer to the HW structure
688 *
689 * Releases the software control flag for performing PHY and select
690 * MAC CSR accesses.
691 */
692 static void
e1000_release_swflag_ich8lan(struct e1000_hw * hw)693 e1000_release_swflag_ich8lan(struct e1000_hw *hw)
694 {
695 u32 extcnf_ctrl;
696
697 DEBUGFUNC("e1000_release_swflag_ich8lan");
698
699 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
700 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
701 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
702
703 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
704 }
705
706 /*
707 * e1000_check_mng_mode_ich8lan - Checks management mode
708 * @hw: pointer to the HW structure
709 *
710 * This checks if the adapter has manageability enabled.
711 * This is a function pointer entry point only called by read/write
712 * routines for the PHY and NVM parts.
713 */
714 static bool
e1000_check_mng_mode_ich8lan(struct e1000_hw * hw)715 e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
716 {
717 u32 fwsm;
718
719 DEBUGFUNC("e1000_check_mng_mode_ich8lan");
720
721 fwsm = E1000_READ_REG(hw, E1000_FWSM);
722
723 return ((fwsm & E1000_FWSM_MODE_MASK) ==
724 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
725 }
726
727 /*
728 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
729 * @hw: pointer to the HW structure
730 *
731 * Checks if firmware is blocking the reset of the PHY.
732 * This is a function pointer entry point only called by
733 * reset routines.
734 */
735 static s32
e1000_check_reset_block_ich8lan(struct e1000_hw * hw)736 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
737 {
738 u32 fwsm;
739
740 DEBUGFUNC("e1000_check_reset_block_ich8lan");
741
742 fwsm = E1000_READ_REG(hw, E1000_FWSM);
743
744 return ((fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS
745 : E1000_BLK_PHY_RESET);
746 }
747
748 /*
749 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
750 * @hw: pointer to the HW structure
751 *
752 * SW should configure the LCD from the NVM extended configuration region
753 * as a workaround for certain parts.
754 */
755 static s32
e1000_sw_lcd_config_ich8lan(struct e1000_hw * hw)756 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
757 {
758 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
759 struct e1000_phy_info *phy = &hw->phy;
760 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
761 s32 ret_val;
762 u16 word_addr, reg_data, reg_addr, phy_page = 0;
763
764 ret_val = hw->phy.ops.acquire(hw);
765 if (ret_val)
766 return (ret_val);
767
768 /*
769 * Initialize the PHY from the NVM on ICH platforms. This
770 * is needed due to an issue where the NVM configuration is
771 * not properly autoloaded after power transitions.
772 * Therefore, after each PHY reset, we will load the
773 * configuration data out of the NVM manually.
774 */
775 if ((hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) ||
776 (hw->mac.type == e1000_pchlan)) {
777 /* Check if SW needs to configure the PHY */
778 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
779 (hw->device_id == E1000_DEV_ID_ICH8_IGP_M) ||
780 (hw->mac.type == e1000_pchlan))
781 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
782 else
783 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
784
785 data = E1000_READ_REG(hw, E1000_FEXTNVM);
786 if (!(data & sw_cfg_mask))
787 goto out;
788
789 /* Wait for basic configuration completes before proceeding */
790 e1000_lan_init_done_ich8lan(hw);
791
792 /*
793 * Make sure HW does not configure LCD from PHY
794 * extended configuration before SW configuration
795 */
796 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
797 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
798 goto out;
799
800 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
801 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
802 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
803 if (!cnf_size)
804 goto out;
805
806 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
807 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
808
809 if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
810 hw->mac.type == e1000_pchlan) {
811 /*
812 * HW configures the SMBus address and LEDs when the
813 * OEM and LCD Write Enable bits are set in the NVM.
814 * When both NVM bits are cleared, SW will configure
815 * them instead.
816 */
817 data = E1000_READ_REG(hw, E1000_STRAP);
818 data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
819 reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
820 reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
821 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
822 reg_data);
823 if (ret_val)
824 goto out;
825
826 data = E1000_READ_REG(hw, E1000_LEDCTL);
827 ret_val = e1000_write_phy_reg_hv_locked(hw,
828 HV_LED_CONFIG, (u16)data);
829 if (ret_val)
830 goto out;
831
832 dev_spec->nvm_lcd_config_enabled = true;
833 }
834 /* Configure LCD from extended configuration region. */
835
836 /* cnf_base_addr is in DWORD */
837 word_addr = (u16)(cnf_base_addr << 1);
838
839 for (i = 0; i < cnf_size; i++) {
840 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
841 ®_data);
842 if (ret_val)
843 goto out;
844
845 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
846 1, ®_addr);
847 if (ret_val)
848 goto out;
849
850 /* Save off the PHY page for future writes. */
851 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
852 phy_page = reg_data;
853 continue;
854 }
855 /*
856 * Bit 5 in the LCD config word contains the phy
857 * address for PCH
858 */
859 if (hw->mac.type == e1000_pchlan) {
860 phy->addr = 1;
861 if (reg_addr & LCD_CFG_PHY_ADDR_BIT) {
862 phy->addr = 2;
863 reg_addr &= PHY_REG_MASK;
864 }
865 }
866
867 reg_addr |= phy_page;
868
869 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
870 reg_data);
871 if (ret_val)
872 goto out;
873 }
874
875 if (hw->mac.type == e1000_pchlan)
876 dev_spec->nvm_lcd_config_enabled = false;
877 }
878
879 out:
880 hw->phy.ops.release(hw);
881 return (ret_val);
882 }
883
884 /*
885 * e1000_k1_gig_workaround_hv - K1 Si workaround
886 * @hw: pointer to the HW structure
887 * @link: link up bool flag
888 *
889 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
890 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
891 * If link is down, the function will restore the default K1 setting located
892 * in the NVM.
893 */
894 static s32
e1000_k1_gig_workaround_hv(struct e1000_hw * hw,bool link)895 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
896 {
897 s32 ret_val = E1000_SUCCESS;
898 u16 status_reg = 0;
899 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
900
901 DEBUGFUNC("e1000_k1_gig_workaround_hv");
902
903 if (hw->mac.type != e1000_pchlan)
904 goto out;
905
906 /* Wrap the whole flow with the sw flag */
907 ret_val = hw->phy.ops.acquire(hw);
908 if (ret_val)
909 goto out;
910
911 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
912 if (link) {
913 if (hw->phy.type == e1000_phy_82578) {
914 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
915 &status_reg);
916 if (ret_val)
917 goto release;
918
919 status_reg &= BM_CS_STATUS_LINK_UP |
920 BM_CS_STATUS_RESOLVED |
921 BM_CS_STATUS_SPEED_MASK;
922
923 if (status_reg == (BM_CS_STATUS_LINK_UP |
924 BM_CS_STATUS_RESOLVED |
925 BM_CS_STATUS_SPEED_1000))
926 k1_enable = false;
927 }
928
929 if (hw->phy.type == e1000_phy_82577) {
930 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
931 &status_reg);
932 if (ret_val)
933 goto release;
934
935 status_reg &= HV_M_STATUS_LINK_UP |
936 HV_M_STATUS_AUTONEG_COMPLETE |
937 HV_M_STATUS_SPEED_MASK;
938
939 if (status_reg == (HV_M_STATUS_LINK_UP |
940 HV_M_STATUS_AUTONEG_COMPLETE |
941 HV_M_STATUS_SPEED_1000))
942 k1_enable = false;
943 }
944
945 /* Link stall fix for link up */
946 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
947 0x0100);
948 if (ret_val)
949 goto release;
950
951 } else {
952 /* Link stall fix for link down */
953 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
954 0x4100);
955 if (ret_val)
956 goto release;
957 }
958
959 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
960
961 release:
962 hw->phy.ops.release(hw);
963 out:
964 return (ret_val);
965 }
966
967 /*
968 * e1000_configure_k1_ich8lan - Configure K1 power state
969 * @hw: pointer to the HW structure
970 * @enable: K1 state to configure
971 *
972 * Configure the K1 power state based on the provided parameter.
973 * Assumes semaphore already acquired.
974 *
975 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
976 */
977 s32
e1000_configure_k1_ich8lan(struct e1000_hw * hw,bool k1_enable)978 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
979 {
980 s32 ret_val = E1000_SUCCESS;
981 u32 ctrl_reg = 0;
982 u32 ctrl_ext = 0;
983 u32 reg = 0;
984 u16 kmrn_reg = 0;
985
986 ret_val = e1000_read_kmrn_reg_locked(hw,
987 E1000_KMRNCTRLSTA_K1_CONFIG,
988 &kmrn_reg);
989 if (ret_val)
990 goto out;
991
992 if (k1_enable)
993 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
994 else
995 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
996
997 ret_val = e1000_write_kmrn_reg_locked(hw,
998 E1000_KMRNCTRLSTA_K1_CONFIG,
999 kmrn_reg);
1000 if (ret_val)
1001 goto out;
1002
1003 usec_delay(20);
1004 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1005 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1006
1007 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1008 reg |= E1000_CTRL_FRCSPD;
1009 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1010
1011 E1000_WRITE_REG(hw,
1012 E1000_CTRL_EXT,
1013 ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1014 usec_delay(20);
1015 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1016 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1017 usec_delay(20);
1018
1019 out:
1020 return (ret_val);
1021 }
1022
1023 /*
1024 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1025 * @hw: pointer to the HW structure
1026 * @d0_state: boolean if entering d0 or d3 device state
1027 *
1028 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1029 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1030 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1031 */
1032 s32
e1000_oem_bits_config_ich8lan(struct e1000_hw * hw,bool d0_state)1033 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1034 {
1035 s32 ret_val = 0;
1036 u32 mac_reg;
1037 u16 oem_reg;
1038
1039 if (hw->mac.type != e1000_pchlan)
1040 return (ret_val);
1041
1042 ret_val = hw->phy.ops.acquire(hw);
1043 if (ret_val)
1044 return (ret_val);
1045
1046 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1047 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1048 goto out;
1049
1050 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
1051 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1052 goto out;
1053
1054 mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
1055
1056 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1057 if (ret_val)
1058 goto out;
1059
1060 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1061
1062 if (d0_state) {
1063 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1064 oem_reg |= HV_OEM_BITS_GBE_DIS;
1065
1066 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1067 oem_reg |= HV_OEM_BITS_LPLU;
1068 } else {
1069 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1070 oem_reg |= HV_OEM_BITS_GBE_DIS;
1071
1072 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1073 oem_reg |= HV_OEM_BITS_LPLU;
1074 }
1075 /* Restart auto-neg to activate the bits */
1076 oem_reg |= HV_OEM_BITS_RESTART_AN;
1077 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1078
1079 out:
1080 hw->phy.ops.release(hw);
1081
1082 return (ret_val);
1083 }
1084
1085 /*
1086 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1087 * done after every PHY reset.
1088 */
1089 static s32
e1000_hv_phy_workarounds_ich8lan(struct e1000_hw * hw)1090 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1091 {
1092 s32 ret_val = E1000_SUCCESS;
1093
1094 if (hw->mac.type != e1000_pchlan)
1095 goto out;
1096
1097 if (((hw->phy.type == e1000_phy_82577) &&
1098 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1099 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1100 /* Disable generation of early preamble */
1101 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
1102 if (ret_val)
1103 goto out;
1104
1105 /* Preamble tuning for SSC */
1106 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(770, 16), 0xA204);
1107 if (ret_val)
1108 goto out;
1109 }
1110
1111 if (hw->phy.type == e1000_phy_82578) {
1112 /*
1113 * Return registers to default by doing a soft reset then
1114 * writing 0x3140 to the control register.
1115 */
1116 if (hw->phy.revision < 2) {
1117 (void) e1000_phy_sw_reset_generic(hw);
1118 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
1119 0x3140);
1120 }
1121 }
1122
1123 /* Select page 0 */
1124 ret_val = hw->phy.ops.acquire(hw);
1125 if (ret_val)
1126 goto out;
1127
1128 hw->phy.addr = 1;
1129 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1130 if (ret_val)
1131 goto out;
1132 hw->phy.ops.release(hw);
1133
1134 /*
1135 * Configure the K1 Si workaround during phy reset assuming there is
1136 * link so that it disables K1 if link is in 1Gbps.
1137 */
1138 ret_val = e1000_k1_gig_workaround_hv(hw, true);
1139
1140 out:
1141 return (ret_val);
1142 }
1143
1144 /*
1145 * e1000_hv_phy_tuning_workaround_ich8lan - This is a Phy tuning work around
1146 * needed for Nahum3 + Hanksville testing, requested by HW team
1147 */
1148 static s32
e1000_hv_phy_tuning_workaround_ich8lan(struct e1000_hw * hw)1149 e1000_hv_phy_tuning_workaround_ich8lan(struct e1000_hw *hw)
1150 {
1151 s32 ret_val = E1000_SUCCESS;
1152
1153 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
1154 if (ret_val)
1155 goto out;
1156
1157 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(770, 16), 0xA204);
1158 if (ret_val)
1159 goto out;
1160
1161 ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x29, 0x66C0);
1162 if (ret_val)
1163 goto out;
1164
1165 ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x1E, 0xFFFF);
1166
1167 out:
1168 return (ret_val);
1169 }
1170
1171 /*
1172 * e1000_lan_init_done_ich8lan - Check for PHY config completion
1173 * @hw: pointer to the HW structure
1174 *
1175 * Check the appropriate indication the MAC has finished configuring the
1176 * PHY after a software reset.
1177 */
1178 static void
e1000_lan_init_done_ich8lan(struct e1000_hw * hw)1179 e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1180 {
1181 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1182
1183 DEBUGFUNC("e1000_lan_init_done_ich8lan");
1184
1185 /* Wait for basic configuration completes before proceeding */
1186 do {
1187 data = E1000_READ_REG(hw, E1000_STATUS);
1188 data &= E1000_STATUS_LAN_INIT_DONE;
1189 usec_delay(100);
1190 } while ((!data) && --loop);
1191
1192 /*
1193 * If basic configuration is incomplete before the above loop
1194 * count reaches 0, loading the configuration from NVM will
1195 * leave the PHY in a bad state possibly resulting in no link.
1196 */
1197 if (loop == 0) {
1198 /* EMPTY */
1199 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
1200 }
1201
1202 /* Clear the Init Done bit for the next init event */
1203 data = E1000_READ_REG(hw, E1000_STATUS);
1204 data &= ~E1000_STATUS_LAN_INIT_DONE;
1205 E1000_WRITE_REG(hw, E1000_STATUS, data);
1206 }
1207
1208 /*
1209 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1210 * @hw: pointer to the HW structure
1211 *
1212 * Resets the PHY
1213 * This is a function pointer entry point called by drivers
1214 * or other shared routines.
1215 */
1216 static s32
e1000_phy_hw_reset_ich8lan(struct e1000_hw * hw)1217 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1218 {
1219 s32 ret_val = E1000_SUCCESS;
1220 u16 reg;
1221
1222 DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
1223
1224 ret_val = e1000_phy_hw_reset_generic(hw);
1225 if (ret_val)
1226 goto out;
1227
1228 /* Allow time for h/w to get to a quiescent state after reset */
1229 msec_delay(10);
1230
1231 if (hw->mac.type == e1000_pchlan) {
1232 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1233 if (ret_val)
1234 goto out;
1235 }
1236
1237 if (hw->device_id == E1000_DEV_ID_ICH10_HANKSVILLE) {
1238 ret_val = e1000_hv_phy_tuning_workaround_ich8lan(hw);
1239 if (ret_val)
1240 goto out;
1241 }
1242
1243 /* Dummy read to clear the phy wakeup bit after lcd reset */
1244 if (hw->mac.type == e1000_pchlan)
1245 hw->phy.ops.read_reg(hw, BM_WUC, ®);
1246
1247 /* Configure the LCD with the extended configuration region in NVM */
1248 ret_val = e1000_sw_lcd_config_ich8lan(hw);
1249 if (ret_val)
1250 goto out;
1251
1252 /* Configure the LCD with the OEM bits in NVM */
1253 if (hw->mac.type == e1000_pchlan)
1254 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1255
1256 out:
1257 return (ret_val);
1258 }
1259 /*
1260 * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
1261 * @hw: pointer to the HW structure
1262 *
1263 * Wrapper for calling the get_phy_info routines for the appropriate phy type.
1264 */
1265 static s32
e1000_get_phy_info_ich8lan(struct e1000_hw * hw)1266 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
1267 {
1268 s32 ret_val = -E1000_ERR_PHY_TYPE;
1269
1270 DEBUGFUNC("e1000_get_phy_info_ich8lan");
1271
1272 switch (hw->phy.type) {
1273 case e1000_phy_ife:
1274 ret_val = e1000_get_phy_info_ife_ich8lan(hw);
1275 break;
1276 case e1000_phy_igp_3:
1277 case e1000_phy_bm:
1278 case e1000_phy_82578:
1279 case e1000_phy_82577:
1280 ret_val = e1000_get_phy_info_igp(hw);
1281 break;
1282 default:
1283 break;
1284 }
1285
1286 return (ret_val);
1287 }
1288
1289 /*
1290 * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
1291 * @hw: pointer to the HW structure
1292 *
1293 * Populates "phy" structure with various feature states.
1294 * This function is only called by other family-specific
1295 * routines.
1296 */
1297 static s32
e1000_get_phy_info_ife_ich8lan(struct e1000_hw * hw)1298 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
1299 {
1300 struct e1000_phy_info *phy = &hw->phy;
1301 s32 ret_val;
1302 u16 data;
1303 bool link;
1304
1305 DEBUGFUNC("e1000_get_phy_info_ife_ich8lan");
1306
1307 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1308 if (ret_val)
1309 goto out;
1310
1311 if (!link) {
1312 DEBUGOUT("Phy info is only valid if link is up\n");
1313 ret_val = -E1000_ERR_CONFIG;
1314 goto out;
1315 }
1316
1317 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
1318 if (ret_val)
1319 goto out;
1320 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
1321 ? false : true;
1322
1323 if (phy->polarity_correction) {
1324 ret_val = e1000_check_polarity_ife(hw);
1325 if (ret_val)
1326 goto out;
1327 } else {
1328 /* Polarity is forced */
1329 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
1330 ? e1000_rev_polarity_reversed
1331 : e1000_rev_polarity_normal;
1332 }
1333
1334 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1335 if (ret_val)
1336 goto out;
1337
1338 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? true : false;
1339
1340 /* The following parameters are undefined for 10/100 operation. */
1341 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1342 phy->local_rx = e1000_1000t_rx_status_undefined;
1343 phy->remote_rx = e1000_1000t_rx_status_undefined;
1344
1345 out:
1346 return (ret_val);
1347 }
1348
1349 /*
1350 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1351 * @hw: pointer to the HW structure
1352 * @active: true to enable LPLU, false to disable
1353 *
1354 * Sets the LPLU state according to the active flag. For PCH, if OEM write
1355 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1356 * the phy speed. This function will manually set the LPLU bit and restart
1357 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
1358 * since it configures the same bit.
1359 */
1360 static s32
e1000_set_lplu_state_pchlan(struct e1000_hw * hw,bool active)1361 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1362 {
1363 s32 ret_val = E1000_SUCCESS;
1364 u16 oem_reg;
1365
1366 DEBUGFUNC("e1000_set_lplu_state_pchlan");
1367
1368 ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
1369 if (ret_val)
1370 goto out;
1371
1372 if (active)
1373 oem_reg |= HV_OEM_BITS_LPLU;
1374 else
1375 oem_reg &= ~HV_OEM_BITS_LPLU;
1376
1377 oem_reg |= HV_OEM_BITS_RESTART_AN;
1378 ret_val = hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
1379
1380 out:
1381 return (ret_val);
1382 }
1383
1384 /*
1385 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1386 * @hw: pointer to the HW structure
1387 * @active: true to enable LPLU, false to disable
1388 *
1389 * Sets the LPLU D0 state according to the active flag. When
1390 * activating LPLU this function also disables smart speed
1391 * and vice versa. LPLU will not be activated unless the
1392 * device autonegotiation advertisement meets standards of
1393 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1394 * This is a function pointer entry point only called by
1395 * PHY setup routines.
1396 */
1397 static s32
e1000_set_d0_lplu_state_ich8lan(struct e1000_hw * hw,bool active)1398 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1399 {
1400 struct e1000_phy_info *phy = &hw->phy;
1401 u32 phy_ctrl;
1402 s32 ret_val = E1000_SUCCESS;
1403 u16 data;
1404
1405 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
1406
1407 if (phy->type == e1000_phy_ife)
1408 goto out;
1409
1410 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
1411
1412 if (active) {
1413 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1414 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
1415
1416 if (phy->type != e1000_phy_igp_3)
1417 goto out;
1418
1419 /*
1420 * Call gig speed drop workaround on LPLU before accessing any
1421 * PHY registers
1422 */
1423 if (hw->mac.type == e1000_ich8lan)
1424 e1000_gig_downshift_workaround_ich8lan(hw);
1425
1426 /* When LPLU is enabled, we should disable SmartSpeed */
1427 ret_val = phy->ops.read_reg(hw,
1428 IGP01E1000_PHY_PORT_CONFIG,
1429 &data);
1430 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1431 ret_val = phy->ops.write_reg(hw,
1432 IGP01E1000_PHY_PORT_CONFIG,
1433 data);
1434 if (ret_val)
1435 goto out;
1436 } else {
1437 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1438 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
1439
1440 if (phy->type != e1000_phy_igp_3)
1441 goto out;
1442
1443 /*
1444 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1445 * during Dx states where the power conservation is most
1446 * important. During driver activity we should enable
1447 * SmartSpeed, so performance is maintained.
1448 */
1449 if (phy->smart_speed == e1000_smart_speed_on) {
1450 ret_val = phy->ops.read_reg(hw,
1451 IGP01E1000_PHY_PORT_CONFIG,
1452 &data);
1453 if (ret_val)
1454 goto out;
1455
1456 data |= IGP01E1000_PSCFR_SMART_SPEED;
1457 ret_val = phy->ops.write_reg(hw,
1458 IGP01E1000_PHY_PORT_CONFIG,
1459 data);
1460 if (ret_val)
1461 goto out;
1462 } else if (phy->smart_speed == e1000_smart_speed_off) {
1463 ret_val = phy->ops.read_reg(hw,
1464 IGP01E1000_PHY_PORT_CONFIG,
1465 &data);
1466 if (ret_val)
1467 goto out;
1468
1469 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1470 ret_val = phy->ops.write_reg(hw,
1471 IGP01E1000_PHY_PORT_CONFIG,
1472 data);
1473 if (ret_val)
1474 goto out;
1475 }
1476 }
1477
1478 out:
1479 return (ret_val);
1480 }
1481
1482 /*
1483 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1484 * @hw: pointer to the HW structure
1485 * @active: true to enable LPLU, false to disable
1486 *
1487 * Sets the LPLU D3 state according to the active flag. When
1488 * activating LPLU this function also disables smart speed
1489 * and vice versa. LPLU will not be activated unless the
1490 * device autonegotiation advertisement meets standards of
1491 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1492 * This is a function pointer entry point only called by
1493 * PHY setup routines.
1494 */
1495 static s32
e1000_set_d3_lplu_state_ich8lan(struct e1000_hw * hw,bool active)1496 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1497 {
1498 struct e1000_phy_info *phy = &hw->phy;
1499 u32 phy_ctrl;
1500 s32 ret_val = E1000_SUCCESS;
1501 u16 data;
1502
1503 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
1504
1505 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
1506
1507 if (!active) {
1508 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1509 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
1510
1511 if (phy->type != e1000_phy_igp_3)
1512 goto out;
1513
1514 /*
1515 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1516 * during Dx states where the power conservation is most
1517 * important. During driver activity we should enable
1518 * SmartSpeed, so performance is maintained.
1519 */
1520 if (phy->smart_speed == e1000_smart_speed_on) {
1521 ret_val = phy->ops.read_reg(hw,
1522 IGP01E1000_PHY_PORT_CONFIG,
1523 &data);
1524 if (ret_val)
1525 goto out;
1526
1527 data |= IGP01E1000_PSCFR_SMART_SPEED;
1528 ret_val = phy->ops.write_reg(hw,
1529 IGP01E1000_PHY_PORT_CONFIG,
1530 data);
1531 if (ret_val)
1532 goto out;
1533 } else if (phy->smart_speed == e1000_smart_speed_off) {
1534 ret_val = phy->ops.read_reg(hw,
1535 IGP01E1000_PHY_PORT_CONFIG,
1536 &data);
1537 if (ret_val)
1538 goto out;
1539
1540 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1541 ret_val = phy->ops.write_reg(hw,
1542 IGP01E1000_PHY_PORT_CONFIG,
1543 data);
1544 if (ret_val)
1545 goto out;
1546 }
1547 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1548 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1549 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1550 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1551 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
1552
1553 if (phy->type != e1000_phy_igp_3)
1554 goto out;
1555
1556 /*
1557 * Call gig speed drop workaround on LPLU before accessing any
1558 * PHY registers
1559 */
1560 if (hw->mac.type == e1000_ich8lan)
1561 e1000_gig_downshift_workaround_ich8lan(hw);
1562
1563 /* When LPLU is enabled, we should disable SmartSpeed */
1564 ret_val = phy->ops.read_reg(hw,
1565 IGP01E1000_PHY_PORT_CONFIG,
1566 &data);
1567 if (ret_val)
1568 goto out;
1569
1570 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1571 ret_val = phy->ops.write_reg(hw,
1572 IGP01E1000_PHY_PORT_CONFIG,
1573 data);
1574 }
1575
1576 out:
1577 return (ret_val);
1578 }
1579
1580 /*
1581 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1582 * @hw: pointer to the HW structure
1583 * @bank: pointer to the variable that returns the active bank
1584 *
1585 * Reads signature byte from the NVM using the flash access registers.
1586 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1587 */
1588 static s32
e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw * hw,u32 * bank)1589 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1590 {
1591 u32 eecd;
1592 struct e1000_nvm_info *nvm = &hw->nvm;
1593 u32 bank1_offset = nvm->flash_bank_size * sizeof (u16);
1594 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1595 u8 sig_byte = 0;
1596 s32 ret_val = E1000_SUCCESS;
1597
1598 switch (hw->mac.type) {
1599 case e1000_ich8lan:
1600 case e1000_ich9lan:
1601 eecd = E1000_READ_REG(hw, E1000_EECD);
1602 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1603 E1000_EECD_SEC1VAL_VALID_MASK) {
1604 if (eecd & E1000_EECD_SEC1VAL)
1605 *bank = 1;
1606 else
1607 *bank = 0;
1608
1609 goto out;
1610 }
1611 DEBUGOUT("Unable to determine valid NVM bank via EEC - "
1612 "reading flash signature\n");
1613 /* fall-thru */
1614 default:
1615 /* set bank to 0 in case flash read fails */
1616 *bank = 0;
1617
1618 /* Check bank 0 */
1619 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1620 &sig_byte);
1621 if (ret_val)
1622 goto out;
1623 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1624 E1000_ICH_NVM_SIG_VALUE) {
1625 *bank = 0;
1626 goto out;
1627 }
1628
1629 /* Check bank 1 */
1630 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1631 bank1_offset, &sig_byte);
1632 if (ret_val)
1633 goto out;
1634 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1635 E1000_ICH_NVM_SIG_VALUE) {
1636 *bank = 1;
1637 goto out;
1638 }
1639
1640 DEBUGOUT("ERROR: No valid NVM bank present\n");
1641 ret_val = -E1000_ERR_NVM;
1642 break;
1643 }
1644 out:
1645 return (ret_val);
1646 }
1647
1648 /*
1649 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
1650 * @hw: pointer to the HW structure
1651 * @offset: The offset (in bytes) of the word(s) to read.
1652 * @words: Size of data to read in words
1653 * @data: Pointer to the word(s) to read at offset.
1654 *
1655 * Reads a word(s) from the NVM using the flash access registers.
1656 */
1657 static s32
e1000_read_nvm_ich8lan(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)1658 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1659 u16 *data)
1660 {
1661 struct e1000_nvm_info *nvm = &hw->nvm;
1662 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1663 u32 act_offset;
1664 s32 ret_val = E1000_SUCCESS;
1665 u32 bank = 0;
1666 u16 i, word;
1667
1668 DEBUGFUNC("e1000_read_nvm_ich8lan");
1669
1670 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1671 (words == 0)) {
1672 DEBUGOUT("nvm parameter(s) out of bounds\n");
1673 ret_val = -E1000_ERR_NVM;
1674 goto out;
1675 }
1676
1677 nvm->ops.acquire(hw);
1678
1679 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1680 if (ret_val != E1000_SUCCESS) {
1681 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
1682 bank = 0;
1683 }
1684
1685 act_offset = (bank) ? nvm->flash_bank_size : 0;
1686 act_offset += offset;
1687
1688 ret_val = E1000_SUCCESS;
1689 for (i = 0; i < words; i++) {
1690 if ((dev_spec->shadow_ram) &&
1691 (dev_spec->shadow_ram[offset + i].modified)) {
1692 data[i] = dev_spec->shadow_ram[offset + i].value;
1693 } else {
1694 ret_val = e1000_read_flash_word_ich8lan(hw,
1695 act_offset + i,
1696 &word);
1697 if (ret_val)
1698 break;
1699 data[i] = word;
1700 }
1701 }
1702
1703 nvm->ops.release(hw);
1704
1705 out:
1706 if (ret_val) {
1707 /* EMPTY */
1708 DEBUGOUT1("NVM read error: %d\n", ret_val);
1709 }
1710
1711 return (ret_val);
1712 }
1713
1714 /*
1715 * e1000_flash_cycle_init_ich8lan - Initialize flash
1716 * @hw: pointer to the HW structure
1717 *
1718 * This function does initial flash setup so that a new read/write/erase cycle
1719 * can be started.
1720 */
1721 static s32
e1000_flash_cycle_init_ich8lan(struct e1000_hw * hw)1722 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1723 {
1724 union ich8_hws_flash_status hsfsts;
1725 s32 ret_val = -E1000_ERR_NVM;
1726 s32 i = 0;
1727
1728 DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
1729
1730 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
1731
1732 /* Check if the flash descriptor is valid */
1733 if (hsfsts.hsf_status.fldesvalid == 0) {
1734 DEBUGOUT("Flash descriptor invalid. "
1735 "SW Sequencing must be used.");
1736 goto out;
1737 }
1738
1739 /* Clear FCERR and DAEL in hw status by writing 1 */
1740 hsfsts.hsf_status.flcerr = 1;
1741 hsfsts.hsf_status.dael = 1;
1742
1743 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
1744
1745 /*
1746 * Either we should have a hardware SPI cycle in progress bit to check
1747 * against, in order to start a new cycle or FDONE bit should be
1748 * changed in the hardware so that it is 1 after hardware reset, which
1749 * can then be used as an indication whether a cycle is in progress or
1750 * has been completed.
1751 */
1752
1753 if (hsfsts.hsf_status.flcinprog == 0) {
1754 /*
1755 * There is no cycle running at present, so we can start a
1756 * cycle. Begin by setting Flash Cycle Done.
1757 */
1758 hsfsts.hsf_status.flcdone = 1;
1759 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
1760 ret_val = E1000_SUCCESS;
1761 } else {
1762 /*
1763 * Otherwise poll for sometime so the current cycle has a
1764 * chance to end before giving up.
1765 */
1766 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1767 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
1768 ICH_FLASH_HSFSTS);
1769 if (hsfsts.hsf_status.flcinprog == 0) {
1770 ret_val = E1000_SUCCESS;
1771 break;
1772 }
1773 usec_delay(1);
1774 }
1775 if (ret_val == E1000_SUCCESS) {
1776 /*
1777 * Successful in waiting for previous cycle to
1778 * timeout, now set the Flash Cycle Done.
1779 */
1780 hsfsts.hsf_status.flcdone = 1;
1781 E1000_WRITE_FLASH_REG16(hw,
1782 ICH_FLASH_HSFSTS,
1783 hsfsts.regval);
1784 } else {
1785 /* EMPTY */
1786 DEBUGOUT("Flash controller busy, cannot get access");
1787 }
1788 }
1789
1790 out:
1791 return (ret_val);
1792 }
1793
1794 /*
1795 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1796 * @hw: pointer to the HW structure
1797 * @timeout: maximum time to wait for completion
1798 *
1799 * This function starts a flash cycle and waits for its completion.
1800 */
1801 static s32
e1000_flash_cycle_ich8lan(struct e1000_hw * hw,u32 timeout)1802 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1803 {
1804 union ich8_hws_flash_ctrl hsflctl;
1805 union ich8_hws_flash_status hsfsts;
1806 s32 ret_val = -E1000_ERR_NVM;
1807 u32 i = 0;
1808
1809 DEBUGFUNC("e1000_flash_cycle_ich8lan");
1810
1811 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1812 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
1813 hsflctl.hsf_ctrl.flcgo = 1;
1814 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
1815
1816 /* wait till FDONE bit is set to 1 */
1817 do {
1818 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
1819 if (hsfsts.hsf_status.flcdone == 1)
1820 break;
1821 usec_delay(1);
1822 } while (i++ < timeout);
1823
1824 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1825 ret_val = E1000_SUCCESS;
1826
1827 return (ret_val);
1828 }
1829
1830 /*
1831 * e1000_read_flash_word_ich8lan - Read word from flash
1832 * @hw: pointer to the HW structure
1833 * @offset: offset to data location
1834 * @data: pointer to the location for storing the data
1835 *
1836 * Reads the flash word at offset into data. Offset is converted
1837 * to bytes before read.
1838 */
1839 static s32
e1000_read_flash_word_ich8lan(struct e1000_hw * hw,u32 offset,u16 * data)1840 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, u16 *data)
1841 {
1842 s32 ret_val;
1843
1844 DEBUGFUNC("e1000_read_flash_word_ich8lan");
1845
1846 if (!data) {
1847 ret_val = -E1000_ERR_NVM;
1848 goto out;
1849 }
1850
1851 /* Must convert offset into bytes. */
1852 offset <<= 1;
1853
1854 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1855
1856 out:
1857 return (ret_val);
1858 }
1859
1860 /*
1861 * e1000_read_flash_byte_ich8lan - Read byte from flash
1862 * @hw: pointer to the HW structure
1863 * @offset: The offset of the byte to read.
1864 * @data: Pointer to a byte to store the value read.
1865 *
1866 * Reads a single byte from the NVM using the flash access registers.
1867 */
1868 static s32
e1000_read_flash_byte_ich8lan(struct e1000_hw * hw,u32 offset,u8 * data)1869 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, u8 *data)
1870 {
1871 s32 ret_val = E1000_SUCCESS;
1872 u16 word = 0;
1873
1874 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1875 if (ret_val)
1876 goto out;
1877
1878 *data = (u8)word;
1879
1880 out:
1881 return (ret_val);
1882 }
1883
1884 /*
1885 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1886 * @hw: pointer to the HW structure
1887 * @offset: The offset (in bytes) of the byte or word to read.
1888 * @size: Size of data to read, 1=byte 2=word
1889 * @data: Pointer to the word to store the value read.
1890 *
1891 * Reads a byte or word from the NVM using the flash access registers.
1892 */
1893 static s32
e1000_read_flash_data_ich8lan(struct e1000_hw * hw,u32 offset,u8 size,u16 * data)1894 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1895 u8 size, u16 *data)
1896 {
1897 union ich8_hws_flash_status hsfsts;
1898 union ich8_hws_flash_ctrl hsflctl;
1899 u32 flash_linear_addr;
1900 u32 flash_data = 0;
1901 s32 ret_val = -E1000_ERR_NVM;
1902 u8 count = 0;
1903
1904 DEBUGFUNC("e1000_read_flash_data_ich8lan");
1905
1906 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1907 goto out;
1908
1909 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1910 hw->nvm.flash_base_addr;
1911
1912 do {
1913 usec_delay(1);
1914 /* Steps */
1915 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1916 if (ret_val != E1000_SUCCESS)
1917 break;
1918
1919 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
1920 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1921 hsflctl.hsf_ctrl.fldbcount = size - 1;
1922 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1923 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
1924
1925 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
1926
1927 ret_val = e1000_flash_cycle_ich8lan(hw,
1928 ICH_FLASH_READ_COMMAND_TIMEOUT);
1929
1930 /*
1931 * Check if FCERR is set to 1, if set to 1, clear it and try
1932 * the whole sequence a few more times, else read in (shift
1933 * in) the Flash Data0, the order is least significant byte
1934 * first msb to lsb
1935 */
1936 if (ret_val == E1000_SUCCESS) {
1937 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
1938 if (size == 1)
1939 *data = (u8)(flash_data & 0x000000FF);
1940 else if (size == 2)
1941 *data = (u16)(flash_data & 0x0000FFFF);
1942 break;
1943 } else {
1944 /*
1945 * If we've gotten here, then things are probably
1946 * completely hosed, but if the error condition is
1947 * detected, it won't hurt to give it another try...
1948 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1949 */
1950 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
1951 ICH_FLASH_HSFSTS);
1952 if (hsfsts.hsf_status.flcerr == 1) {
1953 /* Repeat for some time before giving up. */
1954 continue;
1955 } else if (hsfsts.hsf_status.flcdone == 0) {
1956 DEBUGOUT("Timeout error - flash cycle "
1957 "did not complete.");
1958 break;
1959 }
1960 }
1961 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1962
1963 out:
1964 return (ret_val);
1965 }
1966
1967 /*
1968 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1969 * @hw: pointer to the HW structure
1970 * @offset: The offset (in bytes) of the word(s) to write.
1971 * @words: Size of data to write in words
1972 * @data: Pointer to the word(s) to write at offset.
1973 *
1974 * Writes a byte or word to the NVM using the flash access registers.
1975 */
1976 static s32
e1000_write_nvm_ich8lan(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)1977 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
1978 {
1979 struct e1000_nvm_info *nvm = &hw->nvm;
1980 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1981 s32 ret_val = E1000_SUCCESS;
1982 u16 i;
1983
1984 DEBUGFUNC("e1000_write_nvm_ich8lan");
1985
1986 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1987 (words == 0)) {
1988 DEBUGOUT("nvm parameter(s) out of bounds\n");
1989 ret_val = -E1000_ERR_NVM;
1990 goto out;
1991 }
1992
1993 nvm->ops.acquire(hw);
1994
1995 for (i = 0; i < words; i++) {
1996 dev_spec->shadow_ram[offset + i].modified = true;
1997 dev_spec->shadow_ram[offset + i].value = data[i];
1998 }
1999
2000 nvm->ops.release(hw);
2001
2002 out:
2003 return (ret_val);
2004 }
2005
2006 /*
2007 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2008 * @hw: pointer to the HW structure
2009 *
2010 * The NVM checksum is updated by calling the generic update_nvm_checksum,
2011 * which writes the checksum to the shadow ram. The changes in the shadow
2012 * ram are then committed to the EEPROM by processing each bank at a time
2013 * checking for the modified bit and writing only the pending changes.
2014 * After a successful commit, the shadow ram is cleared and is ready for
2015 * future writes.
2016 */
2017 static s32
e1000_update_nvm_checksum_ich8lan(struct e1000_hw * hw)2018 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2019 {
2020 struct e1000_nvm_info *nvm = &hw->nvm;
2021 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2022 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2023 s32 ret_val;
2024 u16 data;
2025
2026 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
2027
2028 ret_val = e1000_update_nvm_checksum_generic(hw);
2029 if (ret_val)
2030 goto out;
2031
2032 if (nvm->type != e1000_nvm_flash_sw)
2033 goto out;
2034
2035 nvm->ops.acquire(hw);
2036
2037 /*
2038 * We're writing to the opposite bank so if we're on bank 1, write to
2039 * bank 0 etc. We also need to erase the segment that is going to be
2040 * written
2041 */
2042 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2043 if (ret_val != E1000_SUCCESS) {
2044 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
2045 bank = 0;
2046 }
2047
2048 if (bank == 0) {
2049 new_bank_offset = nvm->flash_bank_size;
2050 old_bank_offset = 0;
2051 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2052 if (ret_val) {
2053 nvm->ops.release(hw);
2054 goto out;
2055 }
2056 } else {
2057 old_bank_offset = nvm->flash_bank_size;
2058 new_bank_offset = 0;
2059 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2060 if (ret_val) {
2061 nvm->ops.release(hw);
2062 goto out;
2063 }
2064 }
2065
2066 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
2067 /*
2068 * Determine whether to write the value stored in the other
2069 * NVM bank or a modified value stored in the shadow RAM
2070 */
2071 if (dev_spec->shadow_ram[i].modified) {
2072 data = dev_spec->shadow_ram[i].value;
2073 } else {
2074 ret_val = e1000_read_flash_word_ich8lan(hw,
2075 i + old_bank_offset,
2076 &data);
2077 if (ret_val)
2078 break;
2079 }
2080
2081 /*
2082 * If the word is 0x13, then make sure the signature bits
2083 * (15:14) are 11b until the commit has completed. This will
2084 * allow us to write 10b which indicates the signature is
2085 * valid. We want to do this after the write has completed so
2086 * that we don't mark the segment valid while the write is
2087 * still in progress
2088 */
2089 if (i == E1000_ICH_NVM_SIG_WORD)
2090 data |= E1000_ICH_NVM_SIG_MASK;
2091
2092 /* Convert offset to bytes. */
2093 act_offset = (i + new_bank_offset) << 1;
2094
2095 usec_delay(100);
2096 /* Write the bytes to the new bank. */
2097 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2098 act_offset,
2099 (u8)data);
2100 if (ret_val)
2101 break;
2102
2103 usec_delay(100);
2104 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2105 act_offset + 1,
2106 (u8)(data >> 8));
2107 if (ret_val)
2108 break;
2109 }
2110
2111 /*
2112 * Don't bother writing the segment valid bits if sector programming
2113 * failed.
2114 */
2115 if (ret_val) {
2116 DEBUGOUT("Flash commit failed.\n");
2117 nvm->ops.release(hw);
2118 goto out;
2119 }
2120
2121 /*
2122 * Finally validate the new segment by setting bit 15:14 to 10b in
2123 * word 0x13 , this can be done without an erase as well since these
2124 * bits are 11 to start with and we need to change bit 14 to 0b
2125 */
2126 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2127 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2128 if (ret_val) {
2129 nvm->ops.release(hw);
2130 goto out;
2131 }
2132
2133 data &= 0xBFFF;
2134 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2135 act_offset * 2 + 1,
2136 (u8)(data >> 8));
2137 if (ret_val) {
2138 nvm->ops.release(hw);
2139 goto out;
2140 }
2141
2142 /*
2143 * And invalidate the previously valid segment by setting its
2144 * signature word (0x13) high_byte to 0b. This can be done without an
2145 * erase because flash erase sets all bits to 1's. We can write 1's to
2146 * 0's without an erase
2147 */
2148 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2149 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2150 if (ret_val) {
2151 nvm->ops.release(hw);
2152 goto out;
2153 }
2154
2155 /* Great! Everything worked, we can now clear the cached entries. */
2156 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
2157 dev_spec->shadow_ram[i].modified = false;
2158 dev_spec->shadow_ram[i].value = 0xFFFF;
2159 }
2160
2161 nvm->ops.release(hw);
2162
2163 /*
2164 * Reload the EEPROM, or else modifications will not appear until
2165 * after the next adapter reset.
2166 */
2167 nvm->ops.reload(hw);
2168 msec_delay(10);
2169
2170 out:
2171 if (ret_val) {
2172 /* EMPTY */
2173 DEBUGOUT1("NVM update error: %d\n", ret_val);
2174 }
2175
2176 return (ret_val);
2177 }
2178
2179 /*
2180 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2181 * @hw: pointer to the HW structure
2182 *
2183 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2184 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
2185 * calculated, in which case we need to calculate the checksum and set bit 6.
2186 */
2187 static s32
e1000_validate_nvm_checksum_ich8lan(struct e1000_hw * hw)2188 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2189 {
2190 s32 ret_val = E1000_SUCCESS;
2191 u16 data;
2192
2193 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
2194
2195 /*
2196 * Read 0x19 and check bit 6. If this bit is 0, the checksum needs to
2197 * be fixed. This bit is an indication that the NVM was prepared by
2198 * OEM software and did not calculate the checksum...a likely
2199 * scenario.
2200 */
2201 ret_val = hw->nvm.ops.read(hw, 0x19, 1, &data);
2202 if (ret_val)
2203 goto out;
2204
2205 if ((data & 0x40) == 0) {
2206 data |= 0x40;
2207 ret_val = hw->nvm.ops.write(hw, 0x19, 1, &data);
2208 if (ret_val)
2209 goto out;
2210 ret_val = hw->nvm.ops.update(hw);
2211 if (ret_val)
2212 goto out;
2213 }
2214
2215 ret_val = e1000_validate_nvm_checksum_generic(hw);
2216
2217 out:
2218 return (ret_val);
2219 }
2220
2221 /*
2222 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2223 * @hw: pointer to the HW structure
2224 * @offset: The offset (in bytes) of the byte/word to read.
2225 * @size: Size of data to read, 1=byte 2=word
2226 * @data: The byte(s) to write to the NVM.
2227 *
2228 * Writes one/two bytes to the NVM using the flash access registers.
2229 */
2230 static s32
e1000_write_flash_data_ich8lan(struct e1000_hw * hw,u32 offset,u8 size,u16 data)2231 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2232 u8 size, u16 data)
2233 {
2234 union ich8_hws_flash_status hsfsts;
2235 union ich8_hws_flash_ctrl hsflctl;
2236 u32 flash_linear_addr;
2237 u32 flash_data = 0;
2238 s32 ret_val = -E1000_ERR_NVM;
2239 u8 count = 0;
2240
2241 DEBUGFUNC("e1000_write_ich8_data");
2242
2243 if (size < 1 || size > 2 || data > size * 0xff ||
2244 offset > ICH_FLASH_LINEAR_ADDR_MASK)
2245 goto out;
2246
2247 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2248 hw->nvm.flash_base_addr;
2249
2250 do {
2251 usec_delay(1);
2252 /* Steps */
2253 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2254 if (ret_val != E1000_SUCCESS)
2255 break;
2256
2257 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
2258 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2259 hsflctl.hsf_ctrl.fldbcount = size - 1;
2260 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2261 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
2262
2263 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
2264
2265 if (size == 1)
2266 flash_data = (u32)data & 0x00FF;
2267 else
2268 flash_data = (u32)data;
2269
2270 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
2271
2272 /*
2273 * check if FCERR is set to 1 , if set to 1, clear it and try
2274 * the whole sequence a few more times else done
2275 */
2276 ret_val = e1000_flash_cycle_ich8lan(hw,
2277 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2278 if (ret_val == E1000_SUCCESS)
2279 break;
2280
2281 /*
2282 * If we're here, then things are most likely
2283 * completely hosed, but if the error condition is
2284 * detected, it won't hurt to give it another
2285 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2286 */
2287 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
2288 if (hsfsts.hsf_status.flcerr == 1) {
2289 /* Repeat for some time before giving up. */
2290 continue;
2291 } else if (hsfsts.hsf_status.flcdone == 0) {
2292 DEBUGOUT("Timeout error - flash cycle "
2293 "did not complete.");
2294 break;
2295 }
2296 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2297
2298 out:
2299 return (ret_val);
2300 }
2301
2302 /*
2303 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2304 * @hw: pointer to the HW structure
2305 * @offset: The index of the byte to read.
2306 * @data: The byte to write to the NVM.
2307 *
2308 * Writes a single byte to the NVM using the flash access registers.
2309 */
2310 static s32
e1000_write_flash_byte_ich8lan(struct e1000_hw * hw,u32 offset,u8 data)2311 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, u8 data)
2312 {
2313 u16 word = (u16)data;
2314
2315 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
2316
2317 return (e1000_write_flash_data_ich8lan(hw, offset, 1, word));
2318 }
2319
2320 /*
2321 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2322 * @hw: pointer to the HW structure
2323 * @offset: The offset of the byte to write.
2324 * @byte: The byte to write to the NVM.
2325 *
2326 * Writes a single byte to the NVM using the flash access registers.
2327 * Goes through a retry algorithm before giving up.
2328 */
2329 static s32
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw * hw,u32 offset,u8 byte)2330 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2331 u32 offset, u8 byte)
2332 {
2333 s32 ret_val;
2334 u16 program_retries;
2335
2336 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
2337
2338 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2339 if (ret_val == E1000_SUCCESS)
2340 goto out;
2341
2342 for (program_retries = 0; program_retries < 100; program_retries++) {
2343 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
2344 usec_delay(100);
2345 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2346 if (ret_val == E1000_SUCCESS)
2347 break;
2348 }
2349 if (program_retries == 100) {
2350 ret_val = -E1000_ERR_NVM;
2351 goto out;
2352 }
2353
2354 out:
2355 return (ret_val);
2356 }
2357
2358 /*
2359 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2360 * @hw: pointer to the HW structure
2361 * @bank: 0 for first bank, 1 for second bank, etc.
2362 *
2363 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2364 * bank N is 4096 * N + flash_reg_addr.
2365 */
2366 static s32
e1000_erase_flash_bank_ich8lan(struct e1000_hw * hw,u32 bank)2367 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2368 {
2369 struct e1000_nvm_info *nvm = &hw->nvm;
2370 union ich8_hws_flash_status hsfsts;
2371 union ich8_hws_flash_ctrl hsflctl;
2372 u32 flash_linear_addr;
2373
2374 /* bank size is in 16bit words - adjust to bytes */
2375 u32 flash_bank_size = nvm->flash_bank_size * 2;
2376 s32 ret_val = E1000_SUCCESS;
2377 s32 count = 0;
2378 s32 j, iteration, sector_size;
2379
2380 DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
2381
2382 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
2383
2384 /*
2385 * Determine HW Sector size: Read BERASE bits of hw flash status
2386 * register
2387 * 00: The Hw sector is 256 bytes, hence we need to erase 16
2388 * consecutive sectors. The start index for the nth Hw sector
2389 * can be calculated as = bank * 4096 + n * 256
2390 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2391 * The start index for the nth Hw sector can be calculated
2392 * as = bank * 4096
2393 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2394 * (ich9 only, otherwise error condition)
2395 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2396 */
2397 switch (hsfsts.hsf_status.berasesz) {
2398 case 0:
2399 /* Hw sector size 256 */
2400 sector_size = ICH_FLASH_SEG_SIZE_256;
2401 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2402 break;
2403 case 1:
2404 sector_size = ICH_FLASH_SEG_SIZE_4K;
2405 iteration = 1;
2406 break;
2407 case 2:
2408 sector_size = ICH_FLASH_SEG_SIZE_8K;
2409 iteration = 1;
2410 break;
2411 case 3:
2412 sector_size = ICH_FLASH_SEG_SIZE_64K;
2413 iteration = 1;
2414 break;
2415 default:
2416 ret_val = -E1000_ERR_NVM;
2417 goto out;
2418 }
2419
2420 /* Start with the base address, then add the sector offset. */
2421 flash_linear_addr = hw->nvm.flash_base_addr;
2422 flash_linear_addr += (bank) ? flash_bank_size : 0;
2423
2424 for (j = 0; j < iteration; j++) {
2425 do {
2426 /* Steps */
2427 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2428 if (ret_val)
2429 goto out;
2430
2431 /*
2432 * Write a value 11 (block Erase) in Flash Cycle field
2433 * in hw flash control
2434 */
2435 hsflctl.regval = E1000_READ_FLASH_REG16(hw,
2436 ICH_FLASH_HSFCTL);
2437 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2438 E1000_WRITE_FLASH_REG16(hw,
2439 ICH_FLASH_HSFCTL,
2440 hsflctl.regval);
2441
2442 /*
2443 * Write the last 24 bits of an index within the block
2444 * into Flash Linear address field in Flash Address.
2445 */
2446 flash_linear_addr += (j * sector_size);
2447 E1000_WRITE_FLASH_REG(hw,
2448 ICH_FLASH_FADDR,
2449 flash_linear_addr);
2450
2451 ret_val = e1000_flash_cycle_ich8lan(hw,
2452 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2453 if (ret_val == E1000_SUCCESS)
2454 break;
2455
2456 /*
2457 * Check if FCERR is set to 1. If 1,
2458 * clear it and try the whole sequence
2459 * a few more times else Done
2460 */
2461 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
2462 ICH_FLASH_HSFSTS);
2463 if (hsfsts.hsf_status.flcerr == 1)
2464 /* repeat for some time before giving up */
2465 continue;
2466 else if (hsfsts.hsf_status.flcdone == 0)
2467 goto out;
2468 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2469 }
2470
2471 out:
2472 return (ret_val);
2473 }
2474
2475 /*
2476 * e1000_valid_led_default_ich8lan - Set the default LED settings
2477 * @hw: pointer to the HW structure
2478 * @data: Pointer to the LED settings
2479 *
2480 * Reads the LED default settings from the NVM to data. If the NVM LED
2481 * settings is all 0's or F's, set the LED default to a valid LED default
2482 * setting.
2483 */
2484 static s32
e1000_valid_led_default_ich8lan(struct e1000_hw * hw,u16 * data)2485 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2486 {
2487 s32 ret_val;
2488
2489 DEBUGFUNC("e1000_valid_led_default_ich8lan");
2490
2491 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
2492 if (ret_val) {
2493 DEBUGOUT("NVM Read Error\n");
2494 goto out;
2495 }
2496
2497 if (*data == ID_LED_RESERVED_0000 ||
2498 *data == ID_LED_RESERVED_FFFF)
2499 *data = ID_LED_DEFAULT_ICH8LAN;
2500
2501 out:
2502 return (ret_val);
2503 }
2504
2505 /*
2506 * e1000_id_led_init_pchlan - store LED configurations
2507 * @hw: pointer to the HW structure
2508 *
2509 * PCH does not control LEDs via the LEDCTL register, rather it uses
2510 * the PHY LED configuration register.
2511 *
2512 * PCH also does not have an "always on" or "always off" mode which
2513 * complicates the ID feature. Instead of using the "on" mode to indicate
2514 * in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
2515 * use "link_up" mode. The LEDs will still ID on request if there is no
2516 * link based on logic in e1000_led_[on|off]_pchlan().
2517 */
2518 static s32
e1000_id_led_init_pchlan(struct e1000_hw * hw)2519 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2520 {
2521 struct e1000_mac_info *mac = &hw->mac;
2522 s32 ret_val;
2523 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2524 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2525 u16 data, i, temp, shift;
2526
2527 DEBUGFUNC("e1000_id_led_init_pchlan");
2528
2529 /* Get default ID LED modes */
2530 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2531 if (ret_val)
2532 goto out;
2533
2534 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
2535 mac->ledctl_mode1 = mac->ledctl_default;
2536 mac->ledctl_mode2 = mac->ledctl_default;
2537
2538 for (i = 0; i < 4; i++) {
2539 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2540 shift = (i * 5);
2541 switch (temp) {
2542 case ID_LED_ON1_DEF2:
2543 case ID_LED_ON1_ON2:
2544 case ID_LED_ON1_OFF2:
2545 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2546 mac->ledctl_mode1 |= (ledctl_on << shift);
2547 break;
2548 case ID_LED_OFF1_DEF2:
2549 case ID_LED_OFF1_ON2:
2550 case ID_LED_OFF1_OFF2:
2551 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2552 mac->ledctl_mode1 |= (ledctl_off << shift);
2553 break;
2554 default:
2555 /* Do nothing */
2556 break;
2557 }
2558 switch (temp) {
2559 case ID_LED_DEF1_ON2:
2560 case ID_LED_ON1_ON2:
2561 case ID_LED_OFF1_ON2:
2562 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2563 mac->ledctl_mode2 |= (ledctl_on << shift);
2564 break;
2565 case ID_LED_DEF1_OFF2:
2566 case ID_LED_ON1_OFF2:
2567 case ID_LED_OFF1_OFF2:
2568 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2569 mac->ledctl_mode2 |= (ledctl_off << shift);
2570 break;
2571 default:
2572 /* Do nothing */
2573 break;
2574 }
2575 }
2576
2577 out:
2578 return (ret_val);
2579 }
2580
2581 /*
2582 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2583 * @hw: pointer to the HW structure
2584 *
2585 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2586 * register, so the the bus width is hard coded.
2587 */
2588 static s32
e1000_get_bus_info_ich8lan(struct e1000_hw * hw)2589 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2590 {
2591 struct e1000_bus_info *bus = &hw->bus;
2592 s32 ret_val;
2593
2594 DEBUGFUNC("e1000_get_bus_info_ich8lan");
2595
2596 ret_val = e1000_get_bus_info_pcie_generic(hw);
2597
2598 /*
2599 * ICH devices are "PCI Express"-ish. They have a configuration
2600 * space, but do not contain PCI Express Capability registers, so bus
2601 * width must be hardcoded.
2602 */
2603 if (bus->width == e1000_bus_width_unknown)
2604 bus->width = e1000_bus_width_pcie_x1;
2605
2606 return (ret_val);
2607 }
2608
2609 /*
2610 * e1000_reset_hw_ich8lan - Reset the hardware
2611 * @hw: pointer to the HW structure
2612 *
2613 * Does a full reset of the hardware which includes a reset of the PHY and
2614 * MAC.
2615 */
2616 static s32
e1000_reset_hw_ich8lan(struct e1000_hw * hw)2617 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2618 {
2619 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2620 u16 reg;
2621 u32 ctrl, kab;
2622 s32 ret_val;
2623
2624 DEBUGFUNC("e1000_reset_hw_ich8lan");
2625
2626 /*
2627 * Prevent the PCI-E bus from sticking if there is no TLP connection
2628 * on the last TLP read/write transaction when MAC is reset.
2629 */
2630 ret_val = e1000_disable_pcie_master_generic(hw);
2631 if (ret_val) {
2632 /* EMPTY */
2633 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2634 }
2635
2636 DEBUGOUT("Masking off all interrupts\n");
2637 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2638
2639 /*
2640 * Disable the Transmit and Receive units. Then delay to allow any
2641 * pending transactions to complete before we hit the MAC with the
2642 * global reset.
2643 */
2644 E1000_WRITE_REG(hw, E1000_RCTL, 0);
2645 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2646 E1000_WRITE_FLUSH(hw);
2647
2648 msec_delay(10);
2649
2650 /* Workaround for ICH8 bit corruption issue in FIFO memory */
2651 if (hw->mac.type == e1000_ich8lan) {
2652 /* Set Tx and Rx buffer allocation to 8k apiece. */
2653 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
2654 /* Set Packet Buffer Size to 16k. */
2655 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
2656 }
2657
2658 if (hw->mac.type == e1000_pchlan) {
2659 /* Save the NVM K1 bit setting */
2660 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, ®);
2661 if (ret_val)
2662 return (ret_val);
2663
2664 if (reg & E1000_NVM_K1_ENABLE)
2665 dev_spec->nvm_k1_enabled = true;
2666 else
2667 dev_spec->nvm_k1_enabled = false;
2668 }
2669
2670 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2671
2672 if (!hw->phy.ops.check_reset_block(hw) && !hw->phy.reset_disable) {
2673 /* Clear PHY Reset Asserted bit */
2674 if (hw->mac.type >= e1000_pchlan) {
2675 u32 status = E1000_READ_REG(hw, E1000_STATUS);
2676 E1000_WRITE_REG(hw, E1000_STATUS, status &
2677 ~E1000_STATUS_PHYRA);
2678 }
2679
2680 /*
2681 * PHY HW reset requires MAC CORE reset at the same time to
2682 * make sure the interface between MAC and the external PHY is
2683 * reset.
2684 */
2685 ctrl |= E1000_CTRL_PHY_RST;
2686 }
2687
2688 ret_val = e1000_acquire_swflag_ich8lan(hw);
2689
2690 DEBUGOUT("Issuing a global reset to ich8lan\n");
2691 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
2692 msec_delay(20);
2693
2694 if (!ret_val)
2695 e1000_release_swflag_ich8lan(hw);
2696
2697 if (ctrl & E1000_CTRL_PHY_RST)
2698 ret_val = hw->phy.ops.get_cfg_done(hw);
2699
2700 if (hw->mac.type >= e1000_ich10lan) {
2701 e1000_lan_init_done_ich8lan(hw);
2702 } else {
2703 ret_val = e1000_get_auto_rd_done_generic(hw);
2704 if (ret_val) {
2705 /* EMPTY */
2706 /*
2707 * When auto config read does not complete, do not
2708 * return with an error. This can happen in situations
2709 * where there is no eeprom and prevents getting link.
2710 */
2711 DEBUGOUT("Auto Read Done did not complete\n");
2712 }
2713 }
2714
2715 /* Dummy read to clear the phy wakeup bit after lcd reset */
2716 if (hw->mac.type == e1000_pchlan)
2717 hw->phy.ops.read_reg(hw, BM_WUC, ®);
2718
2719 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2720 if (ret_val)
2721 goto out;
2722
2723 if (hw->mac.type == e1000_pchlan) {
2724 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2725 if (ret_val)
2726 goto out;
2727 }
2728
2729 /*
2730 * For PCH, this write will make sure that any noise
2731 * will be detected as a CRC error and be dropped rather than show up
2732 * as a bad packet to the DMA engine.
2733 */
2734 if (hw->mac.type == e1000_pchlan)
2735 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
2736
2737 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2738 (void) E1000_READ_REG(hw, E1000_ICR);
2739
2740 kab = E1000_READ_REG(hw, E1000_KABGTXD);
2741 kab |= E1000_KABGTXD_BGSQLBIAS;
2742 E1000_WRITE_REG(hw, E1000_KABGTXD, kab);
2743
2744 if (hw->mac.type == e1000_pchlan)
2745 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2746
2747 if (ret_val)
2748 goto out;
2749
2750 if (hw->device_id == E1000_DEV_ID_ICH10_HANKSVILLE)
2751 ret_val = e1000_hv_phy_tuning_workaround_ich8lan(hw);
2752
2753 out:
2754 return (ret_val);
2755 }
2756
2757 /*
2758 * e1000_init_hw_ich8lan - Initialize the hardware
2759 * @hw: pointer to the HW structure
2760 *
2761 * Prepares the hardware for transmit and receive by doing the following:
2762 * - initialize hardware bits
2763 * - initialize LED identification
2764 * - setup receive address registers
2765 * - setup flow control
2766 * - setup transmit descriptors
2767 * - clear statistics
2768 */
2769 static s32
e1000_init_hw_ich8lan(struct e1000_hw * hw)2770 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2771 {
2772 struct e1000_mac_info *mac = &hw->mac;
2773 u32 ctrl_ext, txdctl, snoop;
2774 s32 ret_val;
2775 u16 i;
2776
2777 DEBUGFUNC("e1000_init_hw_ich8lan");
2778
2779 e1000_initialize_hw_bits_ich8lan(hw);
2780
2781 /* Initialize identification LED */
2782 ret_val = mac->ops.id_led_init(hw);
2783 if (ret_val) {
2784 /* EMPTY */
2785 /* This is not fatal and we should not stop init due to this */
2786 DEBUGOUT("Error initializing identification LED\n");
2787 }
2788
2789 /* Setup the receive address. */
2790 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
2791
2792 /* Zero out the Multicast HASH table */
2793 DEBUGOUT("Zeroing the MTA\n");
2794 for (i = 0; i < mac->mta_reg_count; i++)
2795 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2796
2797 /*
2798 * The 82578 Rx buffer will stall if wakeup is enabled in host and
2799 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
2800 * Reset the phy after disabling host wakeup to reset the Rx buffer.
2801 */
2802 if (hw->phy.type == e1000_phy_82578) {
2803 hw->phy.ops.read_reg(hw, BM_WUC, &i);
2804 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2805 if (ret_val)
2806 return (ret_val);
2807 }
2808
2809 /* Setup link and flow control */
2810 ret_val = mac->ops.setup_link(hw);
2811
2812 /* Set the transmit descriptor write-back policy for both queues */
2813 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
2814 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2815 E1000_TXDCTL_FULL_TX_DESC_WB;
2816 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2817 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2818 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
2819 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
2820 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2821 E1000_TXDCTL_FULL_TX_DESC_WB;
2822 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2823 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2824 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
2825
2826 /*
2827 * ICH8 has opposite polarity of no_snoop bits. By default, we should
2828 * use snoop behavior.
2829 */
2830 if (mac->type == e1000_ich8lan)
2831 snoop = PCIE_ICH8_SNOOP_ALL;
2832 else
2833 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
2834 e1000_set_pcie_no_snoop_generic(hw, snoop);
2835
2836 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2837 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2838 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2839
2840 /*
2841 * Clear all of the statistics registers (clear on read). It is
2842 * important that we do this after we have tried to establish link
2843 * because the symbol error count will increment wildly if there
2844 * is no link.
2845 */
2846 e1000_clear_hw_cntrs_ich8lan(hw);
2847
2848 return (ret_val);
2849 }
2850
2851 /*
2852 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2853 * @hw: pointer to the HW structure
2854 *
2855 * Sets/Clears required hardware bits necessary for correctly setting up the
2856 * hardware for transmit and receive.
2857 */
2858 static void
e1000_initialize_hw_bits_ich8lan(struct e1000_hw * hw)2859 e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2860 {
2861 u32 reg;
2862
2863 DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
2864
2865 /* Extended Device Control */
2866 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2867 reg |= (1 << 22);
2868 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2869 if (hw->mac.type >= e1000_pchlan)
2870 reg |= E1000_CTRL_EXT_PHYPDEN;
2871 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2872
2873 /* Transmit Descriptor Control 0 */
2874 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
2875 reg |= (1 << 22);
2876 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
2877
2878 /* Transmit Descriptor Control 1 */
2879 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
2880 reg |= (1 << 22);
2881 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
2882
2883 /* Transmit Arbitration Control 0 */
2884 reg = E1000_READ_REG(hw, E1000_TARC(0));
2885 if (hw->mac.type == e1000_ich8lan)
2886 reg |= (1 << 28) | (1 << 29);
2887 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2888 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
2889
2890 /* Transmit Arbitration Control 1 */
2891 reg = E1000_READ_REG(hw, E1000_TARC(1));
2892 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
2893 reg &= ~(1 << 28);
2894 else
2895 reg |= (1 << 28);
2896 reg |= (1 << 24) | (1 << 26) | (1 << 30);
2897 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
2898
2899 /* Device Status */
2900 if (hw->mac.type == e1000_ich8lan) {
2901 reg = E1000_READ_REG(hw, E1000_STATUS);
2902 reg &= ~((u32)1 << 31);
2903 E1000_WRITE_REG(hw, E1000_STATUS, reg);
2904 }
2905 }
2906
2907 /*
2908 * e1000_setup_link_ich8lan - Setup flow control and link settings
2909 * @hw: pointer to the HW structure
2910 *
2911 * Determines which flow control settings to use, then configures flow
2912 * control. Calls the appropriate media-specific link configuration
2913 * function. Assuming the adapter has a valid link partner, a valid link
2914 * should be established. Assumes the hardware has previously been reset
2915 * and the transmitter and receiver are not enabled.
2916 */
2917 static s32
e1000_setup_link_ich8lan(struct e1000_hw * hw)2918 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2919 {
2920 s32 ret_val = E1000_SUCCESS;
2921
2922 DEBUGFUNC("e1000_setup_link_ich8lan");
2923
2924 if (hw->phy.ops.check_reset_block(hw))
2925 goto out;
2926
2927 /*
2928 * ICH parts do not have a word in the NVM to determine the default
2929 * flow control setting, so we explicitly set it to full.
2930 */
2931 if (hw->fc.requested_mode == e1000_fc_default)
2932 hw->fc.requested_mode = e1000_fc_full;
2933
2934 /*
2935 * Save off the requested flow control mode for use later. Depending
2936 * on the link partner's capabilities, we may or may not use this mode.
2937 */
2938 hw->fc.current_mode = hw->fc.requested_mode;
2939 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
2940 hw->fc.current_mode);
2941
2942 /* Continue to configure the copper link. */
2943 ret_val = hw->mac.ops.setup_physical_interface(hw);
2944 if (ret_val)
2945 goto out;
2946
2947 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
2948 if ((hw->phy.type == e1000_phy_82578) ||
2949 (hw->phy.type == e1000_phy_82577)) {
2950 ret_val = hw->phy.ops.write_reg(hw,
2951 PHY_REG(BM_PORT_CTRL_PAGE, 27),
2952 hw->fc.pause_time);
2953 if (ret_val)
2954 goto out;
2955 }
2956
2957 ret_val = e1000_set_fc_watermarks_generic(hw);
2958
2959 out:
2960 return (ret_val);
2961 }
2962
2963 /*
2964 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2965 * @hw: pointer to the HW structure
2966 *
2967 * Configures the kumeran interface to the PHY to wait the appropriate time
2968 * when polling the PHY, then call the generic setup_copper_link to finish
2969 * configuring the copper link.
2970 */
2971 static s32
e1000_setup_copper_link_ich8lan(struct e1000_hw * hw)2972 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2973 {
2974 u32 ctrl;
2975 s32 ret_val;
2976 u16 reg_data;
2977
2978 DEBUGFUNC("e1000_setup_copper_link_ich8lan");
2979
2980 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2981 ctrl |= E1000_CTRL_SLU;
2982 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2983 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2984
2985 /*
2986 * Set the mac to wait the maximum time between each iteration and
2987 * increase the max iterations when polling the phy; this fixes
2988 * erroneous timeouts at 10Mbps.
2989 */
2990 ret_val = e1000_write_kmrn_reg_generic(hw,
2991 E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
2992 if (ret_val)
2993 goto out;
2994 ret_val = e1000_read_kmrn_reg_generic(hw,
2995 E1000_KMRNCTRLSTA_INBAND_PARAM, ®_data);
2996 if (ret_val)
2997 goto out;
2998 reg_data |= 0x3F;
2999 ret_val = e1000_write_kmrn_reg_generic(hw,
3000 E1000_KMRNCTRLSTA_INBAND_PARAM, reg_data);
3001 if (ret_val)
3002 goto out;
3003
3004 switch (hw->phy.type) {
3005 case e1000_phy_igp_3:
3006 ret_val = e1000_copper_link_setup_igp(hw);
3007 if (ret_val)
3008 goto out;
3009 break;
3010 case e1000_phy_bm:
3011 case e1000_phy_82578:
3012 ret_val = e1000_copper_link_setup_m88(hw);
3013 if (ret_val)
3014 goto out;
3015 break;
3016 case e1000_phy_82577:
3017 ret_val = e1000_copper_link_setup_82577(hw);
3018 if (ret_val)
3019 goto out;
3020 break;
3021 case e1000_phy_ife:
3022 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
3023 ®_data);
3024 if (ret_val)
3025 goto out;
3026
3027 reg_data &= ~IFE_PMC_AUTO_MDIX;
3028
3029 switch (hw->phy.mdix) {
3030 case 1:
3031 reg_data &= ~IFE_PMC_FORCE_MDIX;
3032 break;
3033 case 2:
3034 reg_data |= IFE_PMC_FORCE_MDIX;
3035 break;
3036 case 0:
3037 default:
3038 reg_data |= IFE_PMC_AUTO_MDIX;
3039 break;
3040 }
3041 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
3042 reg_data);
3043 if (ret_val)
3044 goto out;
3045 break;
3046 default:
3047 break;
3048 }
3049 ret_val = e1000_setup_copper_link_generic(hw);
3050
3051 out:
3052 return (ret_val);
3053 }
3054
3055 /*
3056 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3057 * @hw: pointer to the HW structure
3058 * @speed: pointer to store current link speed
3059 * @duplex: pointer to store the current link duplex
3060 *
3061 * Calls the generic get_speed_and_duplex to retrieve the current link
3062 * information and then calls the Kumeran lock loss workaround for links at
3063 * gigabit speeds.
3064 */
3065 static s32
e1000_get_link_up_info_ich8lan(struct e1000_hw * hw,u16 * speed,u16 * duplex)3066 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, u16 *duplex)
3067 {
3068 s32 ret_val;
3069
3070 DEBUGFUNC("e1000_get_link_up_info_ich8lan");
3071
3072 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
3073 if (ret_val)
3074 goto out;
3075
3076 if ((hw->mac.type == e1000_ich8lan) &&
3077 (hw->phy.type == e1000_phy_igp_3) &&
3078 (*speed == SPEED_1000)) {
3079 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3080 }
3081
3082 out:
3083 return (ret_val);
3084 }
3085
3086 /*
3087 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3088 * @hw: pointer to the HW structure
3089 *
3090 * Work-around for 82566 Kumeran PCS lock loss:
3091 * On link status change (i.e. PCI reset, speed change) and link is up and
3092 * speed is gigabit-
3093 * 0) if workaround is optionally disabled do nothing
3094 * 1) wait 1ms for Kumeran link to come up
3095 * 2) check Kumeran Diagnostic register PCS lock loss bit
3096 * 3) if not set the link is locked (all is good), otherwise...
3097 * 4) reset the PHY
3098 * 5) repeat up to 10 times
3099 * Note: this is only called for IGP3 copper when speed is 1gb.
3100 */
3101 static s32
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw * hw)3102 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3103 {
3104 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3105 u32 phy_ctrl;
3106 s32 ret_val = E1000_SUCCESS;
3107 u16 i, data;
3108 bool link;
3109
3110 DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
3111
3112 if (!(dev_spec->kmrn_lock_loss_workaround_enabled))
3113 goto out;
3114
3115 /*
3116 * Make sure link is up before proceeding. If not just return.
3117 * Attempting this while link is negotiating fouled up link stability
3118 */
3119 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3120 if (!link) {
3121 ret_val = E1000_SUCCESS;
3122 goto out;
3123 }
3124
3125 for (i = 0; i < 10; i++) {
3126 /* read once to clear */
3127 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
3128 if (ret_val)
3129 goto out;
3130 /* and again to get new status */
3131 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
3132 if (ret_val)
3133 goto out;
3134
3135 /* check for PCS lock */
3136 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) {
3137 ret_val = E1000_SUCCESS;
3138 goto out;
3139 }
3140
3141 /* Issue PHY reset */
3142 hw->phy.ops.reset(hw);
3143 msec_delay_irq(5);
3144 }
3145 /* Disable GigE link negotiation */
3146 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3147 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3148 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3149 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3150
3151 /*
3152 * Call gig speed drop workaround on Gig disable before accessing any
3153 * PHY registers
3154 */
3155 e1000_gig_downshift_workaround_ich8lan(hw);
3156
3157 /* unable to acquire PCS lock */
3158 ret_val = -E1000_ERR_PHY;
3159
3160 out:
3161 return (ret_val);
3162 }
3163
3164 /*
3165 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3166 * @hw: pointer to the HW structure
3167 * @state: boolean value used to set the current Kumeran workaround state
3168 *
3169 * If ICH8, set the current Kumeran workaround state (enabled - true
3170 * /disabled - false).
3171 */
3172 void
e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw * hw,bool state)3173 e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3174 bool state)
3175 {
3176 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3177
3178 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
3179
3180 if (hw->mac.type != e1000_ich8lan) {
3181 DEBUGOUT("Workaround applies to ICH8 only.\n");
3182 return;
3183 }
3184
3185 dev_spec->kmrn_lock_loss_workaround_enabled = state;
3186 }
3187
3188 /*
3189 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3190 * @hw: pointer to the HW structure
3191 *
3192 * Workaround for 82566 power-down on D3 entry:
3193 * 1) disable gigabit link
3194 * 2) write VR power-down enable
3195 * 3) read it back
3196 * Continue if successful, else issue LCD reset and repeat
3197 */
3198 void
e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw * hw)3199 e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3200 {
3201 u32 reg;
3202 u16 data;
3203 u8 retry = 0;
3204
3205 DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
3206
3207 if (hw->phy.type != e1000_phy_igp_3)
3208 return;
3209
3210 /* Try the workaround twice (if needed) */
3211 do {
3212 /* Disable link */
3213 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
3214 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3215 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3216 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
3217
3218 /*
3219 * Call gig speed drop workaround on Gig disable before
3220 * accessing any PHY registers
3221 */
3222 if (hw->mac.type == e1000_ich8lan)
3223 e1000_gig_downshift_workaround_ich8lan(hw);
3224
3225 /* Write VR power-down enable */
3226 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
3227 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3228 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
3229 data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3230
3231 /* Read it back and test */
3232 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
3233 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3234 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3235 break;
3236
3237 /* Issue PHY reset and repeat at most one more time */
3238 reg = E1000_READ_REG(hw, E1000_CTRL);
3239 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
3240 retry++;
3241 } while (retry);
3242 }
3243
3244 /*
3245 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3246 * @hw: pointer to the HW structure
3247 *
3248 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3249 * LPLU, Gig disable, MDIC PHY reset):
3250 * 1) Set Kumeran Near-end loopback
3251 * 2) Clear Kumeran Near-end loopback
3252 * Should only be called for ICH8[m] devices with IGP_3 Phy.
3253 */
3254 void
e1000_gig_downshift_workaround_ich8lan(struct e1000_hw * hw)3255 e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3256 {
3257 s32 ret_val = E1000_SUCCESS;
3258 u16 reg_data;
3259
3260 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
3261
3262 if ((hw->mac.type != e1000_ich8lan) ||
3263 (hw->phy.type != e1000_phy_igp_3))
3264 return;
3265
3266 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3267 ®_data);
3268 if (ret_val)
3269 return;
3270 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3271 ret_val = e1000_write_kmrn_reg_generic(hw,
3272 E1000_KMRNCTRLSTA_DIAG_OFFSET,
3273 reg_data);
3274 if (ret_val)
3275 return;
3276 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3277 ret_val = e1000_write_kmrn_reg_generic(hw,
3278 E1000_KMRNCTRLSTA_DIAG_OFFSET,
3279 reg_data);
3280 }
3281
3282 /*
3283 * e1000_disable_gig_wol_ich8lan - disable gig during WoL
3284 * @hw: pointer to the HW structure
3285 *
3286 * During S0 to Sx transition, it is possible the link remains at gig
3287 * instead of negotiating to a lower speed. Before going to Sx, set
3288 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3289 * to a lower speed.
3290 *
3291 * Should only be called for applicable parts.
3292 */
3293 void
e1000_disable_gig_wol_ich8lan(struct e1000_hw * hw)3294 e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3295 {
3296 u32 phy_ctrl;
3297
3298 switch (hw->mac.type) {
3299 case e1000_ich9lan:
3300 case e1000_ich10lan:
3301 case e1000_pchlan:
3302 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3303 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
3304 E1000_PHY_CTRL_GBE_DISABLE;
3305 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3306
3307 if (hw->mac.type == e1000_pchlan)
3308 (void) e1000_phy_hw_reset_ich8lan(hw);
3309 default:
3310 break;
3311 }
3312 }
3313
3314 /*
3315 * e1000_cleanup_led_ich8lan - Restore the default LED operation
3316 * @hw: pointer to the HW structure
3317 *
3318 * Return the LED back to the default configuration.
3319 */
3320 static s32
e1000_cleanup_led_ich8lan(struct e1000_hw * hw)3321 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3322 {
3323 s32 ret_val = E1000_SUCCESS;
3324
3325 DEBUGFUNC("e1000_cleanup_led_ich8lan");
3326
3327 if (hw->phy.type == e1000_phy_ife)
3328 ret_val = hw->phy.ops.write_reg(hw,
3329 IFE_PHY_SPECIAL_CONTROL_LED,
3330 0);
3331 else
3332 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
3333
3334 return (ret_val);
3335 }
3336
3337 /*
3338 * e1000_led_on_ich8lan - Turn LEDs on
3339 * @hw: pointer to the HW structure
3340 *
3341 * Turn on the LEDs.
3342 */
3343 static s32
e1000_led_on_ich8lan(struct e1000_hw * hw)3344 e1000_led_on_ich8lan(struct e1000_hw *hw)
3345 {
3346 s32 ret_val = E1000_SUCCESS;
3347
3348 DEBUGFUNC("e1000_led_on_ich8lan");
3349
3350 if (hw->phy.type == e1000_phy_ife)
3351 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3352 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3353 else
3354 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
3355
3356 return (ret_val);
3357 }
3358
3359 /*
3360 * e1000_led_off_ich8lan - Turn LEDs off
3361 * @hw: pointer to the HW structure
3362 *
3363 * Turn off the LEDs.
3364 */
3365 static s32
e1000_led_off_ich8lan(struct e1000_hw * hw)3366 e1000_led_off_ich8lan(struct e1000_hw *hw)
3367 {
3368 s32 ret_val = E1000_SUCCESS;
3369
3370 DEBUGFUNC("e1000_led_off_ich8lan");
3371
3372 if (hw->phy.type == e1000_phy_ife)
3373 ret_val = hw->phy.ops.write_reg(hw,
3374 IFE_PHY_SPECIAL_CONTROL_LED,
3375 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
3376 else
3377 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
3378
3379 return (ret_val);
3380 }
3381
3382 /*
3383 * e1000_setup_led_pchlan - Configures SW controllable LED
3384 * @hw: pointer to the HW structure
3385 *
3386 * This prepares the SW controllable LED for use.
3387 */
3388 static s32
e1000_setup_led_pchlan(struct e1000_hw * hw)3389 e1000_setup_led_pchlan(struct e1000_hw *hw)
3390 {
3391 DEBUGFUNC("e1000_setup_led_pchlan");
3392
3393 return (hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3394 (u16)hw->mac.ledctl_mode1));
3395 }
3396
3397 /*
3398 * e1000_cleanup_led_pchlan - Restore the default LED operation
3399 * @hw: pointer to the HW structure
3400 *
3401 * Return the LED back to the default configuration.
3402 */
3403 static s32
e1000_cleanup_led_pchlan(struct e1000_hw * hw)3404 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3405 {
3406 DEBUGFUNC("e1000_cleanup_led_pchlan");
3407
3408 return (hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3409 (u16)hw->mac.ledctl_default));
3410 }
3411
3412 /*
3413 * e1000_led_on_pchlan - Turn LEDs on
3414 * @hw: pointer to the HW structure
3415 *
3416 * Turn on the LEDs.
3417 */
3418 static s32
e1000_led_on_pchlan(struct e1000_hw * hw)3419 e1000_led_on_pchlan(struct e1000_hw *hw)
3420 {
3421 u16 data = (u16)hw->mac.ledctl_mode2;
3422 u32 i, led;
3423
3424 DEBUGFUNC("e1000_led_on_pchlan");
3425
3426 /*
3427 * If no link, then turn LED on by setting the invert bit
3428 * for each LED that's mode is "link_up" in ledctl_mode2.
3429 */
3430 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
3431 for (i = 0; i < 3; i++) {
3432 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3433 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3434 E1000_LEDCTL_MODE_LINK_UP)
3435 continue;
3436 if (led & E1000_PHY_LED0_IVRT)
3437 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3438 else
3439 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3440 }
3441 }
3442
3443 return (hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data));
3444 }
3445
3446 /*
3447 * e1000_led_off_pchlan - Turn LEDs off
3448 * @hw: pointer to the HW structure
3449 *
3450 * Turn off the LEDs.
3451 */
3452 static s32
e1000_led_off_pchlan(struct e1000_hw * hw)3453 e1000_led_off_pchlan(struct e1000_hw *hw)
3454 {
3455 u16 data = (u16)hw->mac.ledctl_mode1;
3456 u32 i, led;
3457
3458 DEBUGFUNC("e1000_led_off_pchlan");
3459
3460 /*
3461 * If no link, then turn LED off by clearing the invert bit
3462 * for each LED that's mode is "link_up" in ledctl_mode1.
3463 */
3464 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
3465 for (i = 0; i < 3; i++) {
3466 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3467 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3468 E1000_LEDCTL_MODE_LINK_UP)
3469 continue;
3470 if (led & E1000_PHY_LED0_IVRT)
3471 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3472 else
3473 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3474 }
3475 }
3476
3477 return (hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data));
3478 }
3479
3480 /*
3481 * e1000_get_cfg_done_ich8lan - Read config done bit
3482 * @hw: pointer to the HW structure
3483 *
3484 * Read the management control register for the config done bit for
3485 * completion status. NOTE: silicon which is EEPROM-less will fail trying
3486 * to read the config done bit, so an error is *ONLY* logged and returns
3487 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
3488 * would not be able to be reset or change link.
3489 */
3490 static s32
e1000_get_cfg_done_ich8lan(struct e1000_hw * hw)3491 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3492 {
3493 s32 ret_val = E1000_SUCCESS;
3494 u32 bank = 0;
3495
3496 if (hw->mac.type >= e1000_pchlan) {
3497 u32 status = E1000_READ_REG(hw, E1000_STATUS);
3498
3499 if (status & E1000_STATUS_PHYRA) {
3500 E1000_WRITE_REG(hw, E1000_STATUS, status &
3501 ~E1000_STATUS_PHYRA);
3502 } else
3503 /* EMPTY */
3504 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
3505 }
3506
3507 (void) e1000_get_cfg_done_generic(hw);
3508
3509 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3510 if ((hw->mac.type != e1000_ich10lan) &&
3511 (hw->mac.type != e1000_pchlan)) {
3512 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) &&
3513 (hw->phy.type == e1000_phy_igp_3)) {
3514 (void) e1000_phy_init_script_igp3(hw);
3515 }
3516 } else {
3517 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3518 /* Maybe we should do a basic PHY config */
3519 DEBUGOUT("EEPROM not present\n");
3520 ret_val = -E1000_ERR_CONFIG;
3521 }
3522 }
3523
3524 return (ret_val);
3525 }
3526
3527 /*
3528 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3529 * @hw: pointer to the HW structure
3530 *
3531 * In the case of a PHY power down to save power, or to turn off link during a
3532 * driver unload, or wake on lan is not enabled, remove the link.
3533 */
3534 static void
e1000_power_down_phy_copper_ich8lan(struct e1000_hw * hw)3535 e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3536 {
3537 /* If the management interface is not enabled, then power down */
3538 if (!(hw->mac.ops.check_mng_mode(hw) ||
3539 hw->phy.ops.check_reset_block(hw)))
3540 e1000_power_down_phy_copper(hw);
3541 }
3542
3543 /*
3544 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3545 * @hw: pointer to the HW structure
3546 *
3547 * Clears hardware counters specific to the silicon family and calls
3548 * clear_hw_cntrs_generic to clear all general purpose counters.
3549 */
3550 static void
e1000_clear_hw_cntrs_ich8lan(struct e1000_hw * hw)3551 e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3552 {
3553 u16 phy_data;
3554
3555 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
3556
3557 e1000_clear_hw_cntrs_base_generic(hw);
3558
3559 (void) E1000_READ_REG(hw, E1000_ALGNERRC);
3560 (void) E1000_READ_REG(hw, E1000_RXERRC);
3561 (void) E1000_READ_REG(hw, E1000_TNCRS);
3562 (void) E1000_READ_REG(hw, E1000_CEXTERR);
3563 (void) E1000_READ_REG(hw, E1000_TSCTC);
3564 (void) E1000_READ_REG(hw, E1000_TSCTFC);
3565
3566 (void) E1000_READ_REG(hw, E1000_MGTPRC);
3567 (void) E1000_READ_REG(hw, E1000_MGTPDC);
3568 (void) E1000_READ_REG(hw, E1000_MGTPTC);
3569
3570 (void) E1000_READ_REG(hw, E1000_IAC);
3571 (void) E1000_READ_REG(hw, E1000_ICRXOC);
3572
3573 /* Clear PHY statistics registers */
3574 if ((hw->phy.type == e1000_phy_82578) ||
3575 (hw->phy.type == e1000_phy_82577)) {
3576 (void) hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
3577 (void) hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
3578 (void) hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
3579 (void) hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
3580 (void) hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
3581 (void) hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
3582 (void) hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
3583 (void) hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
3584 (void) hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
3585 (void) hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
3586 (void) hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
3587 (void) hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
3588 (void) hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
3589 (void) hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
3590 }
3591 }
3592