1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24 */
25
26 /*
27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 */
29
30 /* IntelVersion: 1.161 v3_3_14_3_BHSW1 */
31
32 #include "igb_api.h"
33
34 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw);
35 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw);
36
37 /* Cable length tables */
38 static const u16 e1000_m88_cable_length_table[] =
39 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
40
41 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
42 (sizeof (e1000_m88_cable_length_table) / \
43 sizeof (e1000_m88_cable_length_table[0]))
44
45 static const u16 e1000_igp_2_cable_length_table[] =
46 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
47 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
48 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
49 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
50 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
51 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
52 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
53 104, 109, 114, 118, 121, 124};
54
55 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
56 (sizeof (e1000_igp_2_cable_length_table) / \
57 sizeof (e1000_igp_2_cable_length_table[0]))
58
59 /*
60 * e1000_init_phy_ops_generic - Initialize PHY function pointers
61 * @hw: pointer to the HW structure
62 *
63 * Setups up the function pointers to no-op functions
64 */
65 void
e1000_init_phy_ops_generic(struct e1000_hw * hw)66 e1000_init_phy_ops_generic(struct e1000_hw *hw)
67 {
68 struct e1000_phy_info *phy = &hw->phy;
69 DEBUGFUNC("e1000_init_phy_ops_generic");
70
71 /* Initialize function pointers */
72 phy->ops.init_params = e1000_null_ops_generic;
73 phy->ops.acquire = e1000_null_ops_generic;
74 phy->ops.check_polarity = e1000_null_ops_generic;
75 phy->ops.check_reset_block = e1000_null_ops_generic;
76 phy->ops.commit = e1000_null_ops_generic;
77 phy->ops.force_speed_duplex = e1000_null_ops_generic;
78 phy->ops.get_cfg_done = e1000_null_ops_generic;
79 phy->ops.get_cable_length = e1000_null_ops_generic;
80 phy->ops.get_info = e1000_null_ops_generic;
81 phy->ops.read_reg = e1000_null_read_reg;
82 phy->ops.read_reg_locked = e1000_null_read_reg;
83 phy->ops.release = e1000_null_phy_generic;
84 phy->ops.reset = e1000_null_ops_generic;
85 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
86 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
87 phy->ops.write_reg = e1000_null_write_reg;
88 phy->ops.write_reg_locked = e1000_null_write_reg;
89 phy->ops.power_up = e1000_null_phy_generic;
90 phy->ops.power_down = e1000_null_phy_generic;
91 }
92
93 /*
94 * e1000_null_read_reg - No-op function, return 0
95 * @hw: pointer to the HW structure
96 */
97 s32
e1000_null_read_reg(struct e1000_hw * hw,u32 offset,u16 * data)98 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data)
99 {
100 DEBUGFUNC("e1000_null_read_reg");
101 UNREFERENCED_3PARAMETER(hw, offset, data);
102 return (E1000_SUCCESS);
103 }
104
105 /*
106 * e1000_null_phy_generic - No-op function, return void
107 * @hw: pointer to the HW structure
108 */
109 void
e1000_null_phy_generic(struct e1000_hw * hw)110 e1000_null_phy_generic(struct e1000_hw *hw)
111 {
112 DEBUGFUNC("e1000_null_phy_generic");
113 UNREFERENCED_1PARAMETER(hw);
114 }
115
116 /*
117 * e1000_null_lplu_state - No-op function, return 0
118 * @hw: pointer to the HW structure
119 */
120 s32
e1000_null_lplu_state(struct e1000_hw * hw,bool active)121 e1000_null_lplu_state(struct e1000_hw *hw, bool active)
122 {
123 DEBUGFUNC("e1000_null_lplu_state");
124 UNREFERENCED_2PARAMETER(hw, active);
125 return (E1000_SUCCESS);
126 }
127
128 /*
129 * e1000_null_write_reg - No-op function, return 0
130 * @hw: pointer to the HW structure
131 */
132 s32
e1000_null_write_reg(struct e1000_hw * hw,u32 offset,u16 data)133 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data)
134 {
135 DEBUGFUNC("e1000_null_write_reg");
136 UNREFERENCED_3PARAMETER(hw, offset, data);
137 return (E1000_SUCCESS);
138 }
139
140 /*
141 * e1000_check_reset_block_generic - Check if PHY reset is blocked
142 * @hw: pointer to the HW structure
143 *
144 * Read the PHY management control register and check whether a PHY reset
145 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
146 * return E1000_BLK_PHY_RESET (12).
147 */
148 s32
e1000_check_reset_block_generic(struct e1000_hw * hw)149 e1000_check_reset_block_generic(struct e1000_hw *hw)
150 {
151 u32 manc;
152
153 DEBUGFUNC("e1000_check_reset_block");
154
155 manc = E1000_READ_REG(hw, E1000_MANC);
156
157 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
158 E1000_BLK_PHY_RESET : E1000_SUCCESS;
159 }
160
161 /*
162 * e1000_get_phy_id - Retrieve the PHY ID and revision
163 * @hw: pointer to the HW structure
164 *
165 * Reads the PHY registers and stores the PHY ID and possibly the PHY
166 * revision in the hardware structure.
167 */
168 s32
e1000_get_phy_id(struct e1000_hw * hw)169 e1000_get_phy_id(struct e1000_hw *hw)
170 {
171 struct e1000_phy_info *phy = &hw->phy;
172 s32 ret_val = E1000_SUCCESS;
173 u16 phy_id;
174
175 DEBUGFUNC("e1000_get_phy_id");
176
177 if (!(phy->ops.read_reg))
178 goto out;
179
180 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
181 if (ret_val)
182 goto out;
183
184 phy->id = (u32)(phy_id << 16);
185 usec_delay(20);
186 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
187 if (ret_val)
188 goto out;
189
190 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
191 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
192
193 out:
194 return (ret_val);
195 }
196
197 /*
198 * e1000_phy_reset_dsp_generic - Reset PHY DSP
199 * @hw: pointer to the HW structure
200 *
201 * Reset the digital signal processor.
202 */
203 s32
e1000_phy_reset_dsp_generic(struct e1000_hw * hw)204 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
205 {
206 s32 ret_val = E1000_SUCCESS;
207
208 DEBUGFUNC("e1000_phy_reset_dsp_generic");
209
210 if (!(hw->phy.ops.write_reg))
211 goto out;
212
213 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
214 if (ret_val)
215 goto out;
216
217 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
218
219 out:
220 return (ret_val);
221 }
222
223 /*
224 * e1000_read_phy_reg_mdic - Read MDI control register
225 * @hw: pointer to the HW structure
226 * @offset: register offset to be read
227 * @data: pointer to the read data
228 *
229 * Reads the MDI control register in the PHY at offset and stores the
230 * information read to data.
231 */
232 s32
e1000_read_phy_reg_mdic(struct e1000_hw * hw,u32 offset,u16 * data)233 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
234 {
235 struct e1000_phy_info *phy = &hw->phy;
236 u32 i, mdic = 0;
237 s32 ret_val = E1000_SUCCESS;
238
239 DEBUGFUNC("e1000_read_phy_reg_mdic");
240
241 /*
242 * Set up Op-code, Phy Address, and register offset in the MDI
243 * Control register. The MAC will take care of interfacing with the
244 * PHY to retrieve the desired data.
245 */
246 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
247 (phy->addr << E1000_MDIC_PHY_SHIFT) |
248 (E1000_MDIC_OP_READ));
249
250 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
251
252 /*
253 * Poll the ready bit to see if the MDI read completed
254 * Increasing the time out as testing showed failures with
255 * the lower time out
256 */
257 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
258 usec_delay(50);
259 mdic = E1000_READ_REG(hw, E1000_MDIC);
260 if (mdic & E1000_MDIC_READY)
261 break;
262 }
263 if (!(mdic & E1000_MDIC_READY)) {
264 DEBUGOUT("MDI Read did not complete\n");
265 ret_val = -E1000_ERR_PHY;
266 goto out;
267 }
268 if (mdic & E1000_MDIC_ERROR) {
269 DEBUGOUT("MDI Error\n");
270 ret_val = -E1000_ERR_PHY;
271 goto out;
272 }
273 *data = (u16) mdic;
274
275 out:
276 return (ret_val);
277 }
278
279 /*
280 * e1000_write_phy_reg_mdic - Write MDI control register
281 * @hw: pointer to the HW structure
282 * @offset: register offset to write to
283 * @data: data to write to register at offset
284 *
285 * Writes data to MDI control register in the PHY at offset.
286 */
287 s32
e1000_write_phy_reg_mdic(struct e1000_hw * hw,u32 offset,u16 data)288 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
289 {
290 struct e1000_phy_info *phy = &hw->phy;
291 u32 i, mdic = 0;
292 s32 ret_val = E1000_SUCCESS;
293
294 DEBUGFUNC("e1000_write_phy_reg_mdic");
295
296 /*
297 * Set up Op-code, Phy Address, and register offset in the MDI
298 * Control register. The MAC will take care of interfacing with the
299 * PHY to retrieve the desired data.
300 */
301 mdic = (((u32)data) |
302 (offset << E1000_MDIC_REG_SHIFT) |
303 (phy->addr << E1000_MDIC_PHY_SHIFT) |
304 (E1000_MDIC_OP_WRITE));
305
306 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
307
308 /*
309 * Poll the ready bit to see if the MDI read completed
310 * Increasing the time out as testing showed failures with
311 * the lower time out
312 */
313 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
314 usec_delay(50);
315 mdic = E1000_READ_REG(hw, E1000_MDIC);
316 if (mdic & E1000_MDIC_READY)
317 break;
318 }
319 if (!(mdic & E1000_MDIC_READY)) {
320 DEBUGOUT("MDI Write did not complete\n");
321 ret_val = -E1000_ERR_PHY;
322 goto out;
323 }
324 if (mdic & E1000_MDIC_ERROR) {
325 DEBUGOUT("MDI Error\n");
326 ret_val = -E1000_ERR_PHY;
327 goto out;
328 }
329
330 out:
331 return (ret_val);
332 }
333
334 /*
335 * e1000_read_phy_reg_i2c - Read PHY register using i2c
336 * @hw: pointer to the HW structure
337 * @offset: register offset to be read
338 * @data: pointer to the read data
339 *
340 * Reads the PHY register at offset using the i2c interface and stores the
341 * retrieved information in data.
342 */
343 s32
e1000_read_phy_reg_i2c(struct e1000_hw * hw,u32 offset,u16 * data)344 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
345 {
346 struct e1000_phy_info *phy = &hw->phy;
347 u32 i, i2ccmd = 0;
348
349 DEBUGFUNC("e1000_read_phy_reg_i2c");
350
351 /*
352 * Set up Op-code, Phy Address, and register address in the I2CCMD
353 * register. The MAC will take care of interfacing with the
354 * PHY to retrieve the desired data.
355 */
356 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
357 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
358 (E1000_I2CCMD_OPCODE_READ));
359
360 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
361
362 /* Poll the ready bit to see if the I2C read completed */
363 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
364 usec_delay(50);
365 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
366 if (i2ccmd & E1000_I2CCMD_READY)
367 break;
368 }
369 if (!(i2ccmd & E1000_I2CCMD_READY)) {
370 DEBUGOUT("I2CCMD Read did not complete\n");
371 return (-E1000_ERR_PHY);
372 }
373 if (i2ccmd & E1000_I2CCMD_ERROR) {
374 DEBUGOUT("I2CCMD Error bit set\n");
375 return (-E1000_ERR_PHY);
376 }
377
378 /* Need to byte-swap the 16-bit value. */
379 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
380
381 return (E1000_SUCCESS);
382 }
383
384 /*
385 * e1000_write_phy_reg_i2c - Write PHY register using i2c
386 * @hw: pointer to the HW structure
387 * @offset: register offset to write to
388 * @data: data to write at register offset
389 *
390 * Writes the data to PHY register at the offset using the i2c interface.
391 */
392 s32
e1000_write_phy_reg_i2c(struct e1000_hw * hw,u32 offset,u16 data)393 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
394 {
395 struct e1000_phy_info *phy = &hw->phy;
396 u32 i, i2ccmd = 0;
397 u16 phy_data_swapped;
398
399 DEBUGFUNC("e1000_write_phy_reg_i2c");
400
401 /* Swap the data bytes for the I2C interface */
402 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
403
404 /*
405 * Set up Op-code, Phy Address, and register address in the I2CCMD
406 * register. The MAC will take care of interfacing with the
407 * PHY to retrieve the desired data.
408 */
409 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
410 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
411 E1000_I2CCMD_OPCODE_WRITE |
412 phy_data_swapped);
413
414 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
415
416 /* Poll the ready bit to see if the I2C read completed */
417 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
418 usec_delay(50);
419 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
420 if (i2ccmd & E1000_I2CCMD_READY)
421 break;
422 }
423 if (!(i2ccmd & E1000_I2CCMD_READY)) {
424 DEBUGOUT("I2CCMD Write did not complete\n");
425 return (-E1000_ERR_PHY);
426 }
427 if (i2ccmd & E1000_I2CCMD_ERROR) {
428 DEBUGOUT("I2CCMD Error bit set\n");
429 return (-E1000_ERR_PHY);
430 }
431
432 return (E1000_SUCCESS);
433 }
434
435 /*
436 * e1000_read_phy_reg_m88 - Read m88 PHY register
437 * @hw: pointer to the HW structure
438 * @offset: register offset to be read
439 * @data: pointer to the read data
440 *
441 * Acquires semaphore, if necessary, then reads the PHY register at offset
442 * and storing the retrieved information in data. Release any acquired
443 * semaphores before exiting.
444 */
445 s32
e1000_read_phy_reg_m88(struct e1000_hw * hw,u32 offset,u16 * data)446 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
447 {
448 s32 ret_val = E1000_SUCCESS;
449
450 DEBUGFUNC("e1000_read_phy_reg_m88");
451
452 if (!(hw->phy.ops.acquire))
453 goto out;
454
455 ret_val = hw->phy.ops.acquire(hw);
456 if (ret_val)
457 goto out;
458
459 ret_val = e1000_read_phy_reg_mdic(hw,
460 MAX_PHY_REG_ADDRESS & offset, data);
461
462 hw->phy.ops.release(hw);
463
464 out:
465 return (ret_val);
466 }
467
468 /*
469 * e1000_write_phy_reg_m88 - Write m88 PHY register
470 * @hw: pointer to the HW structure
471 * @offset: register offset to write to
472 * @data: data to write at register offset
473 *
474 * Acquires semaphore, if necessary, then writes the data to PHY register
475 * at the offset. Release any acquired semaphores before exiting.
476 */
477 s32
e1000_write_phy_reg_m88(struct e1000_hw * hw,u32 offset,u16 data)478 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
479 {
480 s32 ret_val = E1000_SUCCESS;
481
482 DEBUGFUNC("e1000_write_phy_reg_m88");
483
484 if (!(hw->phy.ops.acquire))
485 goto out;
486
487 ret_val = hw->phy.ops.acquire(hw);
488 if (ret_val)
489 goto out;
490
491 ret_val = e1000_write_phy_reg_mdic(hw,
492 MAX_PHY_REG_ADDRESS & offset, data);
493
494 hw->phy.ops.release(hw);
495
496 out:
497 return (ret_val);
498 }
499
500 /*
501 * __e1000_read_phy_reg_igp - Read igp PHY register
502 * @hw: pointer to the HW structure
503 * @offset: register offset to be read
504 * @data: pointer to the read data
505 * @locked: semaphore has already been acquired or not
506 *
507 * Acquires semaphore, if necessary, then reads the PHY register at offset
508 * and stores the retrieved information in data. Release any acquired
509 * semaphores before exiting.
510 */
511 static s32
__e1000_read_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 * data,bool locked)512 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
513 bool locked)
514 {
515 s32 ret_val = E1000_SUCCESS;
516
517 DEBUGFUNC("__e1000_read_phy_reg_igp");
518
519 if (!locked) {
520 if (!(hw->phy.ops.acquire))
521 goto out;
522
523 ret_val = hw->phy.ops.acquire(hw);
524 if (ret_val)
525 goto out;
526 }
527
528 if (offset > MAX_PHY_MULTI_PAGE_REG) {
529 ret_val = e1000_write_phy_reg_mdic(hw,
530 IGP01E1000_PHY_PAGE_SELECT, (u16)offset);
531 if (ret_val)
532 goto release;
533 }
534
535 ret_val = e1000_read_phy_reg_mdic(hw,
536 MAX_PHY_REG_ADDRESS & offset, data);
537
538 release:
539 if (!locked)
540 hw->phy.ops.release(hw);
541
542 out:
543 return (ret_val);
544 }
545
546 /*
547 * e1000_read_phy_reg_igp - Read igp PHY register
548 * @hw: pointer to the HW structure
549 * @offset: register offset to be read
550 * @data: pointer to the read data
551 *
552 * Acquires semaphore then reads the PHY register at offset and stores the
553 * retrieved information in data.
554 * Release the acquired semaphore before exiting.
555 */
556 s32
e1000_read_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 * data)557 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
558 {
559 return (__e1000_read_phy_reg_igp(hw, offset, data, false));
560 }
561
562 /*
563 * e1000_read_phy_reg_igp_locked - Read igp PHY register
564 * @hw: pointer to the HW structure
565 * @offset: register offset to be read
566 * @data: pointer to the read data
567 *
568 * Reads the PHY register at offset and stores the retrieved information
569 * in data. Assumes semaphore already acquired.
570 */
571 s32
e1000_read_phy_reg_igp_locked(struct e1000_hw * hw,u32 offset,u16 * data)572 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
573 {
574 return (__e1000_read_phy_reg_igp(hw, offset, data, true));
575 }
576
577 /*
578 * __e1000_write_phy_reg_igp - Write igp PHY register
579 * @hw: pointer to the HW structure
580 * @offset: register offset to write to
581 * @data: data to write at register offset
582 * @locked: semaphore has already been acquired or not
583 *
584 * Acquires semaphore, if necessary, then writes the data to PHY register
585 * at the offset. Release any acquired semaphores before exiting.
586 */
587 static s32
__e1000_write_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 data,bool locked)588 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
589 bool locked)
590 {
591 s32 ret_val = E1000_SUCCESS;
592
593 DEBUGFUNC("__e1000_write_phy_reg_igp");
594
595 if (!locked) {
596 if (!(hw->phy.ops.acquire))
597 goto out;
598
599 ret_val = hw->phy.ops.acquire(hw);
600 if (ret_val)
601 goto out;
602 }
603
604 if (offset > MAX_PHY_MULTI_PAGE_REG) {
605 ret_val = e1000_write_phy_reg_mdic(hw,
606 IGP01E1000_PHY_PAGE_SELECT, (u16)offset);
607 if (ret_val)
608 goto release;
609 }
610
611 ret_val = e1000_write_phy_reg_mdic(hw,
612 MAX_PHY_REG_ADDRESS & offset, data);
613
614 release:
615 if (!locked)
616 hw->phy.ops.release(hw);
617
618 out:
619 return (ret_val);
620 }
621
622 /*
623 * e1000_write_phy_reg_igp - Write igp PHY register
624 * @hw: pointer to the HW structure
625 * @offset: register offset to write to
626 * @data: data to write at register offset
627 *
628 * Acquires semaphore then writes the data to PHY register
629 * at the offset. Release any acquired semaphores before exiting.
630 */
631 s32
e1000_write_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 data)632 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
633 {
634 return (__e1000_write_phy_reg_igp(hw, offset, data, false));
635 }
636
637 /*
638 * e1000_write_phy_reg_igp_locked - Write igp PHY register
639 * @hw: pointer to the HW structure
640 * @offset: register offset to write to
641 * @data: data to write at register offset
642 *
643 * Writes the data to PHY register at the offset.
644 * Assumes semaphore already acquired.
645 */
646 s32
e1000_write_phy_reg_igp_locked(struct e1000_hw * hw,u32 offset,u16 data)647 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
648 {
649 return (__e1000_write_phy_reg_igp(hw, offset, data, true));
650 }
651
652 /*
653 * __e1000_read_kmrn_reg - Read kumeran register
654 * @hw: pointer to the HW structure
655 * @offset: register offset to be read
656 * @data: pointer to the read data
657 * @locked: semaphore has already been acquired or not
658 *
659 * Acquires semaphore, if necessary. Then reads the PHY register at offset
660 * using the kumeran interface. The information retrieved is stored in data.
661 * Release any acquired semaphores before exiting.
662 */
663 static s32
__e1000_read_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 * data,bool locked)664 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, bool locked)
665 {
666 u32 kmrnctrlsta;
667 s32 ret_val = E1000_SUCCESS;
668
669 DEBUGFUNC("__e1000_read_kmrn_reg_generic");
670
671 if (!locked) {
672 if (!(hw->phy.ops.acquire))
673 goto out;
674
675 ret_val = hw->phy.ops.acquire(hw);
676 if (ret_val)
677 goto out;
678 }
679
680 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
681 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
682 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
683
684 usec_delay(2);
685
686 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
687 *data = (u16)kmrnctrlsta;
688
689 if (!locked)
690 hw->phy.ops.release(hw);
691
692 out:
693 return (ret_val);
694 }
695
696 /*
697 * e1000_read_kmrn_reg_generic - Read kumeran register
698 * @hw: pointer to the HW structure
699 * @offset: register offset to be read
700 * @data: pointer to the read data
701 *
702 * Acquires semaphore then reads the PHY register at offset using the
703 * kumeran interface. The information retrieved is stored in data.
704 * Release the acquired semaphore before exiting.
705 */
706 s32
e1000_read_kmrn_reg_generic(struct e1000_hw * hw,u32 offset,u16 * data)707 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
708 {
709 return (__e1000_read_kmrn_reg(hw, offset, data, false));
710 }
711
712 /*
713 * e1000_read_kmrn_reg_locked - Read kumeran register
714 * @hw: pointer to the HW structure
715 * @offset: register offset to be read
716 * @data: pointer to the read data
717 *
718 * Reads the PHY register at offset using the kumeran interface. The
719 * information retrieved is stored in data.
720 * Assumes semaphore already acquired.
721 */
722 s32
e1000_read_kmrn_reg_locked(struct e1000_hw * hw,u32 offset,u16 * data)723 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
724 {
725 return (__e1000_read_kmrn_reg(hw, offset, data, true));
726 }
727
728 /*
729 * __e1000_write_kmrn_reg - Write kumeran register
730 * @hw: pointer to the HW structure
731 * @offset: register offset to write to
732 * @data: data to write at register offset
733 * @locked: semaphore has already been acquired or not
734 *
735 * Acquires semaphore, if necessary. Then write the data to PHY register
736 * at the offset using the kumeran interface. Release any acquired semaphores
737 * before exiting.
738 */
739 static s32
__e1000_write_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 data,bool locked)740 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, bool locked)
741 {
742 u32 kmrnctrlsta;
743 s32 ret_val = E1000_SUCCESS;
744
745 DEBUGFUNC("e1000_write_kmrn_reg_generic");
746
747 if (!locked) {
748 if (!(hw->phy.ops.acquire))
749 goto out;
750
751 ret_val = hw->phy.ops.acquire(hw);
752 if (ret_val)
753 goto out;
754 }
755
756 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
757 E1000_KMRNCTRLSTA_OFFSET) | data;
758 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
759
760 usec_delay(2);
761
762 if (!locked)
763 hw->phy.ops.release(hw);
764
765 out:
766 return (ret_val);
767 }
768
769 /*
770 * e1000_write_kmrn_reg_generic - Write kumeran register
771 * @hw: pointer to the HW structure
772 * @offset: register offset to write to
773 * @data: data to write at register offset
774 *
775 * Acquires semaphore then writes the data to the PHY register at the offset
776 * using the kumeran interface. Release the acquired semaphore before exiting.
777 */
778 s32
e1000_write_kmrn_reg_generic(struct e1000_hw * hw,u32 offset,u16 data)779 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
780 {
781 return (__e1000_write_kmrn_reg(hw, offset, data, false));
782 }
783
784 /*
785 * e1000_write_kmrn_reg_locked - Write kumeran register
786 * @hw: pointer to the HW structure
787 * @offset: register offset to write to
788 * @data: data to write at register offset
789 *
790 * Write the data to PHY register at the offset using the kumeran interface.
791 * Assumes semaphore already acquired.
792 */
793 s32
e1000_write_kmrn_reg_locked(struct e1000_hw * hw,u32 offset,u16 data)794 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
795 {
796 return (__e1000_write_kmrn_reg(hw, offset, data, true));
797 }
798
799 /*
800 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
801 * @hw: pointer to the HW structure
802 *
803 * Sets up Carrier-sense on Transmit and downshift values.
804 */
805 s32
e1000_copper_link_setup_82577(struct e1000_hw * hw)806 e1000_copper_link_setup_82577(struct e1000_hw *hw)
807 {
808 struct e1000_phy_info *phy = &hw->phy;
809 s32 ret_val;
810 u16 phy_data;
811
812 DEBUGFUNC("e1000_copper_link_setup_82577");
813
814 if (phy->reset_disable) {
815 ret_val = E1000_SUCCESS;
816 goto out;
817 }
818
819 if (phy->type == e1000_phy_82580) {
820 ret_val = hw->phy.ops.reset(hw);
821 if (ret_val) {
822 DEBUGOUT("Error resetting the PHY.\n");
823 goto out;
824 }
825 }
826
827 /* Enable CRS on TX. This must be set for half-duplex operation. */
828 ret_val = phy->ops.read_reg(hw, I82577_CFG_REG, &phy_data);
829 if (ret_val)
830 goto out;
831
832 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
833
834 /* Enable downshift */
835 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
836
837 ret_val = phy->ops.write_reg(hw, I82577_CFG_REG, phy_data);
838
839 out:
840 return (ret_val);
841 }
842
843 /*
844 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
845 * @hw: pointer to the HW structure
846 *
847 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
848 * and downshift values are set also.
849 */
850 s32
e1000_copper_link_setup_m88(struct e1000_hw * hw)851 e1000_copper_link_setup_m88(struct e1000_hw *hw)
852 {
853 struct e1000_phy_info *phy = &hw->phy;
854 s32 ret_val;
855 u16 phy_data;
856
857 DEBUGFUNC("e1000_copper_link_setup_m88");
858
859 if (phy->reset_disable) {
860 ret_val = E1000_SUCCESS;
861 goto out;
862 }
863
864 /* Enable CRS on TX. This must be set for half-duplex operation. */
865 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
866 if (ret_val)
867 goto out;
868
869 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
870
871 /*
872 * Options:
873 * MDI/MDI-X = 0 (default)
874 * 0 - Auto for all speeds
875 * 1 - MDI mode
876 * 2 - MDI-X mode
877 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
878 */
879 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
880
881 switch (phy->mdix) {
882 case 1:
883 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
884 break;
885 case 2:
886 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
887 break;
888 case 3:
889 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
890 break;
891 case 0:
892 default:
893 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
894 break;
895 }
896
897 /*
898 * Options:
899 * disable_polarity_correction = 0 (default)
900 * Automatic Correction for Reversed Cable Polarity
901 * 0 - Disabled
902 * 1 - Enabled
903 */
904 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
905 if (phy->disable_polarity_correction == 1)
906 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
907
908 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
909 if (ret_val)
910 goto out;
911
912 if (phy->revision < E1000_REVISION_4) {
913 /*
914 * Force TX_CLK in the Extended PHY Specific Control Register
915 * to 25MHz clock.
916 */
917 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
918 &phy_data);
919 if (ret_val)
920 goto out;
921
922 phy_data |= M88E1000_EPSCR_TX_CLK_25;
923
924 if ((phy->revision == E1000_REVISION_2) &&
925 (phy->id == M88E1111_I_PHY_ID)) {
926 /* 82573L PHY - set the downshift counter to 5x. */
927 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
928 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
929 } else {
930 /* Configure Master and Slave downshift values */
931 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
932 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
933 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
934 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
935 }
936 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
937 phy_data);
938 if (ret_val)
939 goto out;
940 }
941
942 /* Commit the changes. */
943 ret_val = phy->ops.commit(hw);
944 if (ret_val) {
945 DEBUGOUT("Error committing the PHY changes\n");
946 goto out;
947 }
948
949 out:
950 return (ret_val);
951 }
952
953 /*
954 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
955 * @hw: pointer to the HW structure
956 *
957 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
958 * igp PHY's.
959 */
960 s32
e1000_copper_link_setup_igp(struct e1000_hw * hw)961 e1000_copper_link_setup_igp(struct e1000_hw *hw)
962 {
963 struct e1000_phy_info *phy = &hw->phy;
964 s32 ret_val;
965 u16 data;
966
967 DEBUGFUNC("e1000_copper_link_setup_igp");
968
969 if (phy->reset_disable) {
970 ret_val = E1000_SUCCESS;
971 goto out;
972 }
973
974 ret_val = hw->phy.ops.reset(hw);
975 if (ret_val) {
976 DEBUGOUT("Error resetting the PHY.\n");
977 goto out;
978 }
979
980 /*
981 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
982 * timeout issues when LFS is enabled.
983 */
984 msec_delay(100);
985
986 /*
987 * The NVM settings will configure LPLU in D3 for
988 * non-IGP1 PHYs.
989 */
990 if (phy->type == e1000_phy_igp) {
991 /* disable lplu d3 during driver init */
992 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);
993 if (ret_val) {
994 DEBUGOUT("Error Disabling LPLU D3\n");
995 goto out;
996 }
997 }
998
999 /* disable lplu d0 during driver init */
1000 if (hw->phy.ops.set_d0_lplu_state) {
1001 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
1002 if (ret_val) {
1003 DEBUGOUT("Error Disabling LPLU D0\n");
1004 goto out;
1005 }
1006 }
1007 /* Configure mdi-mdix settings */
1008 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1009 if (ret_val)
1010 goto out;
1011
1012 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1013
1014 switch (phy->mdix) {
1015 case 1:
1016 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1017 break;
1018 case 2:
1019 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1020 break;
1021 case 0:
1022 default:
1023 data |= IGP01E1000_PSCR_AUTO_MDIX;
1024 break;
1025 }
1026 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1027 if (ret_val)
1028 goto out;
1029
1030 /* set auto-master slave resolution settings */
1031 if (hw->mac.autoneg) {
1032 /*
1033 * when autonegotiation advertisement is only 1000Mbps then we
1034 * should disable SmartSpeed and enable Auto MasterSlave
1035 * resolution as hardware default.
1036 */
1037 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1038 /* Disable SmartSpeed */
1039 ret_val = phy->ops.read_reg(hw,
1040 IGP01E1000_PHY_PORT_CONFIG, &data);
1041 if (ret_val)
1042 goto out;
1043
1044 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1045 ret_val = phy->ops.write_reg(hw,
1046 IGP01E1000_PHY_PORT_CONFIG, data);
1047 if (ret_val)
1048 goto out;
1049
1050 /* Set auto Master/Slave resolution process */
1051 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1052 if (ret_val)
1053 goto out;
1054
1055 data &= ~CR_1000T_MS_ENABLE;
1056 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1057 if (ret_val)
1058 goto out;
1059 }
1060
1061 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1062 if (ret_val)
1063 goto out;
1064
1065 /* load defaults for future use */
1066 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
1067 ((data & CR_1000T_MS_VALUE) ?
1068 e1000_ms_force_master :
1069 e1000_ms_force_slave) :
1070 e1000_ms_auto;
1071
1072 switch (phy->ms_type) {
1073 case e1000_ms_force_master:
1074 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1075 break;
1076 case e1000_ms_force_slave:
1077 data |= CR_1000T_MS_ENABLE;
1078 data &= ~(CR_1000T_MS_VALUE);
1079 break;
1080 case e1000_ms_auto:
1081 data &= ~CR_1000T_MS_ENABLE;
1082 default:
1083 break;
1084 }
1085 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1086 if (ret_val)
1087 goto out;
1088 }
1089
1090 out:
1091 return (ret_val);
1092 }
1093
1094 /*
1095 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1096 * @hw: pointer to the HW structure
1097 *
1098 * Performs initial bounds checking on autoneg advertisement parameter, then
1099 * configure to advertise the full capability. Setup the PHY to autoneg
1100 * and restart the negotiation process between the link partner. If
1101 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1102 */
1103 static s32
e1000_copper_link_autoneg(struct e1000_hw * hw)1104 e1000_copper_link_autoneg(struct e1000_hw *hw)
1105 {
1106 struct e1000_phy_info *phy = &hw->phy;
1107 s32 ret_val;
1108 u16 phy_ctrl;
1109
1110 DEBUGFUNC("e1000_copper_link_autoneg");
1111
1112 /*
1113 * Perform some bounds checking on the autoneg advertisement
1114 * parameter.
1115 */
1116 phy->autoneg_advertised &= phy->autoneg_mask;
1117
1118 /*
1119 * If autoneg_advertised is zero, we assume it was not defaulted
1120 * by the calling code so we set to advertise full capability.
1121 */
1122 if (phy->autoneg_advertised == 0)
1123 phy->autoneg_advertised = phy->autoneg_mask;
1124
1125 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1126 ret_val = e1000_phy_setup_autoneg(hw);
1127 if (ret_val) {
1128 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1129 goto out;
1130 }
1131 DEBUGOUT("Restarting Auto-Neg\n");
1132
1133 /*
1134 * Restart auto-negotiation by setting the Auto Neg Enable bit and
1135 * the Auto Neg Restart bit in the PHY control register.
1136 */
1137 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1138 if (ret_val)
1139 goto out;
1140
1141 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1142 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1143 if (ret_val)
1144 goto out;
1145
1146 /*
1147 * Does the user want to wait for Auto-Neg to complete here, or
1148 * check at a later time (for example, callback routine).
1149 */
1150 if (phy->autoneg_wait_to_complete) {
1151 ret_val = hw->mac.ops.wait_autoneg(hw);
1152 if (ret_val) {
1153 DEBUGOUT("Error while waiting for "
1154 "autoneg to complete\n");
1155 goto out;
1156 }
1157 }
1158
1159 hw->mac.get_link_status = true;
1160
1161 out:
1162 return (ret_val);
1163 }
1164
1165 /*
1166 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1167 * @hw: pointer to the HW structure
1168 *
1169 * Reads the MII auto-neg advertisement register and/or the 1000T control
1170 * register and if the PHY is already setup for auto-negotiation, then
1171 * return successful. Otherwise, setup advertisement and flow control to
1172 * the appropriate values for the wanted auto-negotiation.
1173 */
1174 static s32
e1000_phy_setup_autoneg(struct e1000_hw * hw)1175 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1176 {
1177 struct e1000_phy_info *phy = &hw->phy;
1178 s32 ret_val;
1179 u16 mii_autoneg_adv_reg;
1180 u16 mii_1000t_ctrl_reg = 0;
1181
1182 DEBUGFUNC("e1000_phy_setup_autoneg");
1183
1184 phy->autoneg_advertised &= phy->autoneg_mask;
1185
1186 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1187 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1188 if (ret_val)
1189 goto out;
1190
1191 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1192 /* Read the MII 1000Base-T Control Register (Address 9). */
1193 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1194 &mii_1000t_ctrl_reg);
1195 if (ret_val)
1196 goto out;
1197 }
1198
1199 /*
1200 * Need to parse both autoneg_advertised and fc and set up
1201 * the appropriate PHY registers. First we will parse for
1202 * autoneg_advertised software override. Since we can advertise
1203 * a plethora of combinations, we need to check each bit
1204 * individually.
1205 */
1206
1207 /*
1208 * First we clear all the 10/100 mb speed bits in the Auto-Neg
1209 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1210 * the 1000Base-T Control Register (Address 9).
1211 */
1212 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1213 NWAY_AR_100TX_HD_CAPS |
1214 NWAY_AR_10T_FD_CAPS |
1215 NWAY_AR_10T_HD_CAPS);
1216 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1217
1218 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1219
1220 /* Do we want to advertise 10 Mb Half Duplex? */
1221 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1222 DEBUGOUT("Advertise 10mb Half duplex\n");
1223 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1224 }
1225
1226 /* Do we want to advertise 10 Mb Full Duplex? */
1227 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1228 DEBUGOUT("Advertise 10mb Full duplex\n");
1229 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1230 }
1231
1232 /* Do we want to advertise 100 Mb Half Duplex? */
1233 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1234 DEBUGOUT("Advertise 100mb Half duplex\n");
1235 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1236 }
1237
1238 /* Do we want to advertise 100 Mb Full Duplex? */
1239 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1240 DEBUGOUT("Advertise 100mb Full duplex\n");
1241 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1242 }
1243
1244 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1245 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1246 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1247
1248 /* Do we want to advertise 1000 Mb Full Duplex? */
1249 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1250 DEBUGOUT("Advertise 1000mb Full duplex\n");
1251 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1252 }
1253
1254 /*
1255 * Check for a software override of the flow control settings, and
1256 * setup the PHY advertisement registers accordingly. If
1257 * auto-negotiation is enabled, then software will have to set the
1258 * "PAUSE" bits to the correct value in the Auto-Negotiation
1259 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1260 * negotiation.
1261 *
1262 * The possible values of the "fc" parameter are:
1263 * 0: Flow control is completely disabled
1264 * 1: Rx flow control is enabled (we can receive pause frames
1265 * but not send pause frames).
1266 * 2: Tx flow control is enabled (we can send pause frames
1267 * but we do not support receiving pause frames).
1268 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1269 * other: No software override. The flow control configuration
1270 * in the EEPROM is used.
1271 */
1272 switch (hw->fc.current_mode) {
1273 case e1000_fc_none:
1274 /*
1275 * Flow control (Rx & Tx) is completely disabled by a
1276 * software over-ride.
1277 */
1278 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1279 break;
1280 case e1000_fc_rx_pause:
1281 /*
1282 * Rx Flow control is enabled, and Tx Flow control is
1283 * disabled, by a software over-ride.
1284 *
1285 * Since there really isn't a way to advertise that we are
1286 * capable of Rx Pause ONLY, we will advertise that we
1287 * support both symmetric and asymmetric Rx PAUSE. Later
1288 * (in e1000_config_fc_after_link_up) we will disable the
1289 * hw's ability to send PAUSE frames.
1290 */
1291 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1292 break;
1293 case e1000_fc_tx_pause:
1294 /*
1295 * Tx Flow control is enabled, and Rx Flow control is
1296 * disabled, by a software over-ride.
1297 */
1298 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1299 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1300 break;
1301 case e1000_fc_full:
1302 /*
1303 * Flow control (both Rx and Tx) is enabled by a software
1304 * over-ride.
1305 */
1306 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1307 break;
1308 default:
1309 DEBUGOUT("Flow control param set incorrectly\n");
1310 ret_val = -E1000_ERR_CONFIG;
1311 goto out;
1312 }
1313
1314 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1315 if (ret_val)
1316 goto out;
1317
1318 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1319
1320 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1321 ret_val = phy->ops.write_reg(hw,
1322 PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1323 if (ret_val)
1324 goto out;
1325 }
1326
1327 out:
1328 return (ret_val);
1329 }
1330
1331 /*
1332 * e1000_setup_copper_link_generic - Configure copper link settings
1333 * @hw: pointer to the HW structure
1334 *
1335 * Calls the appropriate function to configure the link for auto-neg or forced
1336 * speed and duplex. Then we check for link, once link is established calls
1337 * to configure collision distance and flow control are called. If link is
1338 * not established, we return -E1000_ERR_PHY (-2).
1339 */
1340 s32
e1000_setup_copper_link_generic(struct e1000_hw * hw)1341 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1342 {
1343 s32 ret_val;
1344 bool link;
1345
1346 DEBUGFUNC("e1000_setup_copper_link_generic");
1347
1348 if (hw->mac.autoneg) {
1349 /*
1350 * Setup autoneg and flow control advertisement and perform
1351 * autonegotiation.
1352 */
1353 ret_val = e1000_copper_link_autoneg(hw);
1354 if (ret_val)
1355 goto out;
1356 } else {
1357 /*
1358 * PHY will be set to 10H, 10F, 100H or 100F
1359 * depending on user settings.
1360 */
1361 DEBUGOUT("Forcing Speed and Duplex\n");
1362 ret_val = hw->phy.ops.force_speed_duplex(hw);
1363 if (ret_val) {
1364 DEBUGOUT("Error Forcing Speed and Duplex\n");
1365 goto out;
1366 }
1367 }
1368
1369 /*
1370 * Check link status. Wait up to 100 microseconds for link to become
1371 * valid.
1372 */
1373 ret_val = e1000_phy_has_link_generic(hw,
1374 COPPER_LINK_UP_LIMIT,
1375 10,
1376 &link);
1377 if (ret_val)
1378 goto out;
1379
1380 if (link) {
1381 DEBUGOUT("Valid link established!!!\n");
1382 e1000_config_collision_dist_generic(hw);
1383 ret_val = e1000_config_fc_after_link_up_generic(hw);
1384 } else {
1385 DEBUGOUT("Unable to establish link!!!\n");
1386 }
1387
1388 out:
1389 return (ret_val);
1390 }
1391
1392 /*
1393 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1394 * @hw: pointer to the HW structure
1395 *
1396 * Calls the PHY setup function to force speed and duplex. Clears the
1397 * auto-crossover to force MDI manually. Waits for link and returns
1398 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1399 */
1400 s32
e1000_phy_force_speed_duplex_igp(struct e1000_hw * hw)1401 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1402 {
1403 struct e1000_phy_info *phy = &hw->phy;
1404 s32 ret_val;
1405 u16 phy_data;
1406 bool link;
1407
1408 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1409
1410 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1411 if (ret_val)
1412 goto out;
1413
1414 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1415
1416 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1417 if (ret_val)
1418 goto out;
1419
1420 /*
1421 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1422 * forced whenever speed and duplex are forced.
1423 */
1424 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1425 if (ret_val)
1426 goto out;
1427
1428 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1429 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1430
1431 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1432 if (ret_val)
1433 goto out;
1434
1435 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1436
1437 usec_delay(1);
1438
1439 if (phy->autoneg_wait_to_complete) {
1440 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1441
1442 ret_val = e1000_phy_has_link_generic(hw,
1443 PHY_FORCE_LIMIT,
1444 100000,
1445 &link);
1446 if (ret_val)
1447 goto out;
1448
1449 if (!link)
1450 DEBUGOUT("Link taking longer than expected.\n");
1451
1452 /* Try once more */
1453 ret_val = e1000_phy_has_link_generic(hw,
1454 PHY_FORCE_LIMIT,
1455 100000,
1456 &link);
1457 if (ret_val)
1458 goto out;
1459 }
1460
1461 out:
1462 return (ret_val);
1463 }
1464
1465 /*
1466 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1467 * @hw: pointer to the HW structure
1468 *
1469 * Calls the PHY setup function to force speed and duplex. Clears the
1470 * auto-crossover to force MDI manually. Resets the PHY to commit the
1471 * changes. If time expires while waiting for link up, we reset the DSP.
1472 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1473 * successful completion, else return corresponding error code.
1474 */
1475 s32
e1000_phy_force_speed_duplex_m88(struct e1000_hw * hw)1476 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1477 {
1478 struct e1000_phy_info *phy = &hw->phy;
1479 s32 ret_val;
1480 u16 phy_data;
1481 bool link;
1482
1483 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1484
1485 /*
1486 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1487 * forced whenever speed and duplex are forced.
1488 */
1489 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1490 if (ret_val)
1491 goto out;
1492
1493 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1494 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1495 if (ret_val)
1496 goto out;
1497
1498 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1499
1500 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1501 if (ret_val)
1502 goto out;
1503
1504 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1505
1506 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1507 if (ret_val)
1508 goto out;
1509
1510 /* Reset the phy to commit changes. */
1511 ret_val = hw->phy.ops.commit(hw);
1512 if (ret_val)
1513 goto out;
1514
1515 if (phy->autoneg_wait_to_complete) {
1516 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1517
1518 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1519 100000, &link);
1520 if (ret_val)
1521 goto out;
1522
1523 if (!link) {
1524 /*
1525 * We didn't get link.
1526 * Reset the DSP and cross our fingers.
1527 */
1528 ret_val = phy->ops.write_reg(hw,
1529 M88E1000_PHY_PAGE_SELECT,
1530 0x001d);
1531 if (ret_val)
1532 goto out;
1533 ret_val = e1000_phy_reset_dsp_generic(hw);
1534 if (ret_val)
1535 goto out;
1536 }
1537
1538 /* Try once more */
1539 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1540 100000, &link);
1541 if (ret_val)
1542 goto out;
1543 }
1544
1545 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1546 if (ret_val)
1547 goto out;
1548
1549 /*
1550 * Resetting the phy means we need to re-force TX_CLK in the
1551 * Extended PHY Specific Control Register to 25MHz clock from
1552 * the reset value of 2.5MHz.
1553 */
1554 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1555 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1556 if (ret_val)
1557 goto out;
1558
1559 /*
1560 * In addition, we must re-enable CRS on Tx for both half and full
1561 * duplex.
1562 */
1563 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1564 if (ret_val)
1565 goto out;
1566
1567 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1568 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1569
1570 out:
1571 return (ret_val);
1572 }
1573
1574 /*
1575 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1576 * @hw: pointer to the HW structure
1577 *
1578 * Forces the speed and duplex settings of the PHY.
1579 * This is a function pointer entry point only called by
1580 * PHY setup routines.
1581 */
1582 s32
e1000_phy_force_speed_duplex_ife(struct e1000_hw * hw)1583 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1584 {
1585 struct e1000_phy_info *phy = &hw->phy;
1586 s32 ret_val;
1587 u16 data;
1588 bool link;
1589
1590 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1591
1592 if (phy->type != e1000_phy_ife) {
1593 ret_val = e1000_phy_force_speed_duplex_igp(hw);
1594 goto out;
1595 }
1596
1597 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1598 if (ret_val)
1599 goto out;
1600
1601 e1000_phy_force_speed_duplex_setup(hw, &data);
1602
1603 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1604 if (ret_val)
1605 goto out;
1606
1607 /* Disable MDI-X support for 10/100 */
1608 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1609 if (ret_val)
1610 goto out;
1611
1612 data &= ~IFE_PMC_AUTO_MDIX;
1613 data &= ~IFE_PMC_FORCE_MDIX;
1614
1615 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1616 if (ret_val)
1617 goto out;
1618
1619 DEBUGOUT1("IFE PMC: %X\n", data);
1620
1621 usec_delay(1);
1622
1623 if (phy->autoneg_wait_to_complete) {
1624 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1625
1626 ret_val = e1000_phy_has_link_generic(hw,
1627 PHY_FORCE_LIMIT, 100000, &link);
1628 if (ret_val)
1629 goto out;
1630
1631 if (!link)
1632 DEBUGOUT("Link taking longer than expected.\n");
1633
1634 /* Try once more */
1635 ret_val = e1000_phy_has_link_generic(hw,
1636 PHY_FORCE_LIMIT, 100000, &link);
1637 if (ret_val)
1638 goto out;
1639 }
1640
1641 out:
1642 return (ret_val);
1643 }
1644 /*
1645 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1646 * @hw: pointer to the HW structure
1647 * @phy_ctrl: pointer to current value of PHY_CONTROL
1648 *
1649 * Forces speed and duplex on the PHY by doing the following: disable flow
1650 * control, force speed/duplex on the MAC, disable auto speed detection,
1651 * disable auto-negotiation, configure duplex, configure speed, configure
1652 * the collision distance, write configuration to CTRL register. The
1653 * caller must write to the PHY_CONTROL register for these settings to
1654 * take affect.
1655 */
1656 void
e1000_phy_force_speed_duplex_setup(struct e1000_hw * hw,u16 * phy_ctrl)1657 e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1658 {
1659 struct e1000_mac_info *mac = &hw->mac;
1660 u32 ctrl;
1661
1662 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
1663
1664 /* Turn off flow control when forcing speed/duplex */
1665 hw->fc.current_mode = e1000_fc_none;
1666
1667 /* Force speed/duplex on the mac */
1668 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1669 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1670 ctrl &= ~E1000_CTRL_SPD_SEL;
1671
1672 /* Disable Auto Speed Detection */
1673 ctrl &= ~E1000_CTRL_ASDE;
1674
1675 /* Disable autoneg on the phy */
1676 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1677
1678 /* Forcing Full or Half Duplex? */
1679 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1680 ctrl &= ~E1000_CTRL_FD;
1681 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1682 DEBUGOUT("Half Duplex\n");
1683 } else {
1684 ctrl |= E1000_CTRL_FD;
1685 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1686 DEBUGOUT("Full Duplex\n");
1687 }
1688
1689 /* Forcing 10mb or 100mb? */
1690 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1691 ctrl |= E1000_CTRL_SPD_100;
1692 *phy_ctrl |= MII_CR_SPEED_100;
1693 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1694 DEBUGOUT("Forcing 100mb\n");
1695 } else {
1696 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1697 /* LINTED */
1698 *phy_ctrl |= MII_CR_SPEED_10;
1699 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1700 DEBUGOUT("Forcing 10mb\n");
1701 }
1702
1703 e1000_config_collision_dist_generic(hw);
1704
1705 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1706 }
1707
1708 /*
1709 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
1710 * @hw: pointer to the HW structure
1711 * @active: boolean used to enable/disable lplu
1712 *
1713 * Success returns 0, Failure returns 1
1714 *
1715 * The low power link up (lplu) state is set to the power management level D3
1716 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1717 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1718 * is used during Dx states where the power conservation is most important.
1719 * During driver activity, SmartSpeed should be enabled so performance is
1720 * maintained.
1721 */
1722 s32
e1000_set_d3_lplu_state_generic(struct e1000_hw * hw,bool active)1723 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
1724 {
1725 struct e1000_phy_info *phy = &hw->phy;
1726 s32 ret_val = E1000_SUCCESS;
1727 u16 data;
1728
1729 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
1730
1731 if (!(hw->phy.ops.read_reg))
1732 goto out;
1733
1734 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1735 if (ret_val)
1736 goto out;
1737
1738 if (!active) {
1739 data &= ~IGP02E1000_PM_D3_LPLU;
1740 ret_val = phy->ops.write_reg(hw,
1741 IGP02E1000_PHY_POWER_MGMT,
1742 data);
1743 if (ret_val)
1744 goto out;
1745 /*
1746 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1747 * during Dx states where the power conservation is most
1748 * important. During driver activity we should enable
1749 * SmartSpeed, so performance is maintained.
1750 */
1751 if (phy->smart_speed == e1000_smart_speed_on) {
1752 ret_val = phy->ops.read_reg(hw,
1753 IGP01E1000_PHY_PORT_CONFIG,
1754 &data);
1755 if (ret_val)
1756 goto out;
1757
1758 data |= IGP01E1000_PSCFR_SMART_SPEED;
1759 ret_val = phy->ops.write_reg(hw,
1760 IGP01E1000_PHY_PORT_CONFIG,
1761 data);
1762 if (ret_val)
1763 goto out;
1764 } else if (phy->smart_speed == e1000_smart_speed_off) {
1765 ret_val = phy->ops.read_reg(hw,
1766 IGP01E1000_PHY_PORT_CONFIG,
1767 &data);
1768 if (ret_val)
1769 goto out;
1770
1771 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1772 ret_val = phy->ops.write_reg(hw,
1773 IGP01E1000_PHY_PORT_CONFIG,
1774 data);
1775 if (ret_val)
1776 goto out;
1777 }
1778 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1779 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1780 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1781 data |= IGP02E1000_PM_D3_LPLU;
1782 ret_val = phy->ops.write_reg(hw,
1783 IGP02E1000_PHY_POWER_MGMT,
1784 data);
1785 if (ret_val)
1786 goto out;
1787
1788 /* When LPLU is enabled, we should disable SmartSpeed */
1789 ret_val = phy->ops.read_reg(hw,
1790 IGP01E1000_PHY_PORT_CONFIG,
1791 &data);
1792 if (ret_val)
1793 goto out;
1794
1795 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1796 ret_val = phy->ops.write_reg(hw,
1797 IGP01E1000_PHY_PORT_CONFIG,
1798 data);
1799 }
1800
1801 out:
1802 return (ret_val);
1803 }
1804
1805 /*
1806 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
1807 * @hw: pointer to the HW structure
1808 *
1809 * Success returns 0, Failure returns 1
1810 *
1811 * A downshift is detected by querying the PHY link health.
1812 */
1813 s32
e1000_check_downshift_generic(struct e1000_hw * hw)1814 e1000_check_downshift_generic(struct e1000_hw *hw)
1815 {
1816 struct e1000_phy_info *phy = &hw->phy;
1817 s32 ret_val;
1818 u16 phy_data, offset, mask;
1819
1820 DEBUGFUNC("e1000_check_downshift_generic");
1821
1822 switch (phy->type) {
1823 case e1000_phy_m88:
1824 case e1000_phy_gg82563:
1825 offset = M88E1000_PHY_SPEC_STATUS;
1826 mask = M88E1000_PSSR_DOWNSHIFT;
1827 break;
1828 case e1000_phy_igp_2:
1829 case e1000_phy_igp:
1830 case e1000_phy_igp_3:
1831 offset = IGP01E1000_PHY_LINK_HEALTH;
1832 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1833 break;
1834 default:
1835 /* speed downshift not supported */
1836 phy->speed_downgraded = false;
1837 ret_val = E1000_SUCCESS;
1838 goto out;
1839 }
1840
1841 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1842
1843 if (!ret_val)
1844 phy->speed_downgraded = (phy_data & mask) ? true : false;
1845
1846 out:
1847 return (ret_val);
1848 }
1849
1850 /*
1851 * e1000_check_polarity_m88 - Checks the polarity.
1852 * @hw: pointer to the HW structure
1853 *
1854 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1855 *
1856 * Polarity is determined based on the PHY specific status register.
1857 */
1858 s32
e1000_check_polarity_m88(struct e1000_hw * hw)1859 e1000_check_polarity_m88(struct e1000_hw *hw)
1860 {
1861 struct e1000_phy_info *phy = &hw->phy;
1862 s32 ret_val;
1863 u16 data;
1864
1865 DEBUGFUNC("e1000_check_polarity_m88");
1866
1867 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
1868
1869 if (!ret_val)
1870 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1871 ? e1000_rev_polarity_reversed
1872 : e1000_rev_polarity_normal;
1873
1874 return (ret_val);
1875 }
1876
1877 /*
1878 * e1000_check_polarity_igp - Checks the polarity.
1879 * @hw: pointer to the HW structure
1880 *
1881 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1882 *
1883 * Polarity is determined based on the PHY port status register, and the
1884 * current speed (since there is no polarity at 100Mbps).
1885 */
1886 s32
e1000_check_polarity_igp(struct e1000_hw * hw)1887 e1000_check_polarity_igp(struct e1000_hw *hw)
1888 {
1889 struct e1000_phy_info *phy = &hw->phy;
1890 s32 ret_val;
1891 u16 data, offset, mask;
1892
1893 DEBUGFUNC("e1000_check_polarity_igp");
1894
1895 /*
1896 * Polarity is determined based on the speed of
1897 * our connection.
1898 */
1899 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1900 if (ret_val)
1901 goto out;
1902
1903 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1904 IGP01E1000_PSSR_SPEED_1000MBPS) {
1905 offset = IGP01E1000_PHY_PCS_INIT_REG;
1906 mask = IGP01E1000_PHY_POLARITY_MASK;
1907 } else {
1908 /*
1909 * This really only applies to 10Mbps since
1910 * there is no polarity for 100Mbps (always 0).
1911 */
1912 offset = IGP01E1000_PHY_PORT_STATUS;
1913 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1914 }
1915
1916 ret_val = phy->ops.read_reg(hw, offset, &data);
1917
1918 if (!ret_val)
1919 phy->cable_polarity = (data & mask)
1920 ? e1000_rev_polarity_reversed
1921 : e1000_rev_polarity_normal;
1922
1923 out:
1924 return (ret_val);
1925 }
1926
1927 /*
1928 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1929 * @hw: pointer to the HW structure
1930 *
1931 * Polarity is determined on the polarity reversal feature being enabled.
1932 */
1933 s32
e1000_check_polarity_ife(struct e1000_hw * hw)1934 e1000_check_polarity_ife(struct e1000_hw *hw)
1935 {
1936 struct e1000_phy_info *phy = &hw->phy;
1937 s32 ret_val;
1938 u16 phy_data, offset, mask;
1939
1940 DEBUGFUNC("e1000_check_polarity_ife");
1941
1942 /*
1943 * Polarity is determined based on the reversal feature being enabled.
1944 */
1945 if (phy->polarity_correction) {
1946 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1947 mask = IFE_PESC_POLARITY_REVERSED;
1948 } else {
1949 offset = IFE_PHY_SPECIAL_CONTROL;
1950 mask = IFE_PSC_FORCE_POLARITY;
1951 }
1952
1953 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1954
1955 if (!ret_val)
1956 phy->cable_polarity = (phy_data & mask)
1957 ? e1000_rev_polarity_reversed
1958 : e1000_rev_polarity_normal;
1959
1960 return (ret_val);
1961 }
1962 /*
1963 * e1000_wait_autoneg_generic - Wait for auto-neg completion
1964 * @hw: pointer to the HW structure
1965 *
1966 * Waits for auto-negotiation to complete or for the auto-negotiation time
1967 * limit to expire, which ever happens first.
1968 */
1969 s32
e1000_wait_autoneg_generic(struct e1000_hw * hw)1970 e1000_wait_autoneg_generic(struct e1000_hw *hw)
1971 {
1972 s32 ret_val = E1000_SUCCESS;
1973 u16 i, phy_status;
1974
1975 DEBUGFUNC("e1000_wait_autoneg_generic");
1976
1977 if (!(hw->phy.ops.read_reg))
1978 return (E1000_SUCCESS);
1979
1980 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1981 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1982 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1983 if (ret_val)
1984 break;
1985 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1986 if (ret_val)
1987 break;
1988 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1989 break;
1990 msec_delay(100);
1991 }
1992
1993 /*
1994 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1995 * has completed.
1996 */
1997 return (ret_val);
1998 }
1999
2000 /*
2001 * e1000_phy_has_link_generic - Polls PHY for link
2002 * @hw: pointer to the HW structure
2003 * @iterations: number of times to poll for link
2004 * @usec_interval: delay between polling attempts
2005 * @success: pointer to whether polling was successful or not
2006 *
2007 * Polls the PHY status register for link, 'iterations' number of times.
2008 */
2009 s32
e1000_phy_has_link_generic(struct e1000_hw * hw,u32 iterations,u32 usec_interval,bool * success)2010 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2011 u32 usec_interval, bool *success)
2012 {
2013 s32 ret_val = E1000_SUCCESS;
2014 u16 i, phy_status;
2015
2016 DEBUGFUNC("e1000_phy_has_link_generic");
2017
2018 if (!(hw->phy.ops.read_reg))
2019 return (E1000_SUCCESS);
2020
2021 for (i = 0; i < iterations; i++) {
2022 /*
2023 * Some PHYs require the PHY_STATUS register to be read
2024 * twice due to the link bit being sticky. No harm doing
2025 * it across the board.
2026 */
2027 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2028 if (ret_val) {
2029 /*
2030 * If the first read fails, another entity may have
2031 * ownership of the resources, wait and try again to
2032 * see if they have relinquished the resources yet.
2033 */
2034 usec_delay(usec_interval);
2035 }
2036 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2037 if (ret_val)
2038 break;
2039 if (phy_status & MII_SR_LINK_STATUS)
2040 break;
2041 if (usec_interval >= 1000)
2042 msec_delay_irq(usec_interval/1000);
2043 else
2044 usec_delay(usec_interval);
2045 }
2046
2047 *success = (i < iterations) ? true : false;
2048
2049 return (ret_val);
2050 }
2051
2052 /*
2053 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2054 * @hw: pointer to the HW structure
2055 *
2056 * Reads the PHY specific status register to retrieve the cable length
2057 * information. The cable length is determined by averaging the minimum and
2058 * maximum values to get the "average" cable length. The m88 PHY has four
2059 * possible cable length values, which are:
2060 * Register Value Cable Length
2061 * 0 < 50 meters
2062 * 1 50 - 80 meters
2063 * 2 80 - 110 meters
2064 * 3 110 - 140 meters
2065 * 4 > 140 meters
2066 */
2067 s32
e1000_get_cable_length_m88(struct e1000_hw * hw)2068 e1000_get_cable_length_m88(struct e1000_hw *hw)
2069 {
2070 struct e1000_phy_info *phy = &hw->phy;
2071 s32 ret_val;
2072 u16 phy_data, index;
2073
2074 DEBUGFUNC("e1000_get_cable_length_m88");
2075
2076 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2077 if (ret_val)
2078 goto out;
2079
2080 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2081 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2082 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
2083 ret_val = -E1000_ERR_PHY;
2084 goto out;
2085 }
2086
2087 phy->min_cable_length = e1000_m88_cable_length_table[index];
2088 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2089
2090 phy->cable_length = (phy->min_cable_length +
2091 phy->max_cable_length) / 2;
2092
2093 out:
2094 return (ret_val);
2095 }
2096
2097 /*
2098 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2099 * @hw: pointer to the HW structure
2100 *
2101 * The automatic gain control (agc) normalizes the amplitude of the
2102 * received signal, adjusting for the attenuation produced by the
2103 * cable. By reading the AGC registers, which represent the
2104 * combination of coarse and fine gain value, the value can be put
2105 * into a lookup table to obtain the approximate cable length
2106 * for each channel.
2107 */
2108 s32
e1000_get_cable_length_igp_2(struct e1000_hw * hw)2109 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2110 {
2111 struct e1000_phy_info *phy = &hw->phy;
2112 s32 ret_val = E1000_SUCCESS;
2113 u16 phy_data, i, agc_value = 0;
2114 u16 cur_agc_index, max_agc_index = 0;
2115 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2116 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
2117 {IGP02E1000_PHY_AGC_A,
2118 IGP02E1000_PHY_AGC_B,
2119 IGP02E1000_PHY_AGC_C,
2120 IGP02E1000_PHY_AGC_D};
2121
2122 DEBUGFUNC("e1000_get_cable_length_igp_2");
2123
2124 /* Read the AGC registers for all channels */
2125 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2126 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2127 if (ret_val)
2128 goto out;
2129
2130 /*
2131 * Getting bits 15:9, which represent the combination of
2132 * coarse and fine gain values. The result is a number
2133 * that can be put into the lookup table to obtain the
2134 * approximate cable length.
2135 */
2136 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2137 IGP02E1000_AGC_LENGTH_MASK;
2138
2139 /* Array index bound check. */
2140 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2141 (cur_agc_index == 0)) {
2142 ret_val = -E1000_ERR_PHY;
2143 goto out;
2144 }
2145
2146 /* Remove min & max AGC values from calculation. */
2147 if (e1000_igp_2_cable_length_table[min_agc_index] >
2148 e1000_igp_2_cable_length_table[cur_agc_index])
2149 min_agc_index = cur_agc_index;
2150 if (e1000_igp_2_cable_length_table[max_agc_index] <
2151 e1000_igp_2_cable_length_table[cur_agc_index])
2152 max_agc_index = cur_agc_index;
2153
2154 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
2155 }
2156
2157 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2158 e1000_igp_2_cable_length_table[max_agc_index]);
2159 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2160
2161 /* Calculate cable length with the error range of +/- 10 meters. */
2162 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2163 (agc_value - IGP02E1000_AGC_RANGE) : 0;
2164 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2165
2166 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2167
2168 out:
2169 return (ret_val);
2170 }
2171
2172 /*
2173 * e1000_get_phy_info_m88 - Retrieve PHY information
2174 * @hw: pointer to the HW structure
2175 *
2176 * Valid for only copper links. Read the PHY status register (sticky read)
2177 * to verify that link is up. Read the PHY special control register to
2178 * determine the polarity and 10base-T extended distance. Read the PHY
2179 * special status register to determine MDI/MDIx and current speed. If
2180 * speed is 1000, then determine cable length, local and remote receiver.
2181 */
2182 s32
e1000_get_phy_info_m88(struct e1000_hw * hw)2183 e1000_get_phy_info_m88(struct e1000_hw *hw)
2184 {
2185 struct e1000_phy_info *phy = &hw->phy;
2186 s32 ret_val;
2187 u16 phy_data;
2188 bool link;
2189
2190 DEBUGFUNC("e1000_get_phy_info_m88");
2191
2192 if (phy->media_type != e1000_media_type_copper) {
2193 DEBUGOUT("Phy info is only valid for copper media\n");
2194 ret_val = -E1000_ERR_CONFIG;
2195 goto out;
2196 }
2197
2198 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2199 if (ret_val)
2200 goto out;
2201
2202 if (!link) {
2203 DEBUGOUT("Phy info is only valid if link is up\n");
2204 ret_val = -E1000_ERR_CONFIG;
2205 goto out;
2206 }
2207
2208 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2209 if (ret_val)
2210 goto out;
2211
2212 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
2213 ? true : false;
2214
2215 ret_val = e1000_check_polarity_m88(hw);
2216 if (ret_val)
2217 goto out;
2218
2219 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2220 if (ret_val)
2221 goto out;
2222
2223 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false;
2224
2225 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2226 ret_val = hw->phy.ops.get_cable_length(hw);
2227 if (ret_val)
2228 goto out;
2229
2230 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2231 if (ret_val)
2232 goto out;
2233
2234 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2235 ? e1000_1000t_rx_status_ok
2236 : e1000_1000t_rx_status_not_ok;
2237
2238 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2239 ? e1000_1000t_rx_status_ok
2240 : e1000_1000t_rx_status_not_ok;
2241 } else {
2242 /* Set values to "undefined" */
2243 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2244 phy->local_rx = e1000_1000t_rx_status_undefined;
2245 phy->remote_rx = e1000_1000t_rx_status_undefined;
2246 }
2247
2248 out:
2249 return (ret_val);
2250 }
2251
2252 /*
2253 * e1000_get_phy_info_igp - Retrieve igp PHY information
2254 * @hw: pointer to the HW structure
2255 *
2256 * Read PHY status to determine if link is up. If link is up, then
2257 * set/determine 10base-T extended distance and polarity correction. Read
2258 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2259 * determine on the cable length, local and remote receiver.
2260 */
2261 s32
e1000_get_phy_info_igp(struct e1000_hw * hw)2262 e1000_get_phy_info_igp(struct e1000_hw *hw)
2263 {
2264 struct e1000_phy_info *phy = &hw->phy;
2265 s32 ret_val;
2266 u16 data;
2267 bool link;
2268
2269 DEBUGFUNC("e1000_get_phy_info_igp");
2270
2271 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2272 if (ret_val)
2273 goto out;
2274
2275 if (!link) {
2276 DEBUGOUT("Phy info is only valid if link is up\n");
2277 ret_val = -E1000_ERR_CONFIG;
2278 goto out;
2279 }
2280
2281 phy->polarity_correction = true;
2282
2283 ret_val = e1000_check_polarity_igp(hw);
2284 if (ret_val)
2285 goto out;
2286
2287 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2288 if (ret_val)
2289 goto out;
2290
2291 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false;
2292
2293 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2294 IGP01E1000_PSSR_SPEED_1000MBPS) {
2295 ret_val = phy->ops.get_cable_length(hw);
2296 if (ret_val)
2297 goto out;
2298
2299 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2300 if (ret_val)
2301 goto out;
2302
2303 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2304 ? e1000_1000t_rx_status_ok
2305 : e1000_1000t_rx_status_not_ok;
2306
2307 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2308 ? e1000_1000t_rx_status_ok
2309 : e1000_1000t_rx_status_not_ok;
2310 } else {
2311 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2312 phy->local_rx = e1000_1000t_rx_status_undefined;
2313 phy->remote_rx = e1000_1000t_rx_status_undefined;
2314 }
2315
2316 out:
2317 return (ret_val);
2318 }
2319
2320 /*
2321 * e1000_phy_sw_reset_generic - PHY software reset
2322 * @hw: pointer to the HW structure
2323 *
2324 * Does a software reset of the PHY by reading the PHY control register and
2325 * setting/write the control register reset bit to the PHY.
2326 */
2327 s32
e1000_phy_sw_reset_generic(struct e1000_hw * hw)2328 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2329 {
2330 s32 ret_val = E1000_SUCCESS;
2331 u16 phy_ctrl;
2332
2333 DEBUGFUNC("e1000_phy_sw_reset_generic");
2334
2335 if (!(hw->phy.ops.read_reg))
2336 goto out;
2337
2338 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2339 if (ret_val)
2340 goto out;
2341
2342 phy_ctrl |= MII_CR_RESET;
2343 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2344 if (ret_val)
2345 goto out;
2346
2347 usec_delay(1);
2348
2349 out:
2350 return (ret_val);
2351 }
2352
2353 /*
2354 * e1000_phy_hw_reset_generic - PHY hardware reset
2355 * @hw: pointer to the HW structure
2356 *
2357 * Verify the reset block is not blocking us from resetting. Acquire
2358 * semaphore (if necessary) and read/set/write the device control reset
2359 * bit in the PHY. Wait the appropriate delay time for the device to
2360 * reset and release the semaphore (if necessary).
2361 */
2362 s32
e1000_phy_hw_reset_generic(struct e1000_hw * hw)2363 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2364 {
2365 struct e1000_phy_info *phy = &hw->phy;
2366 s32 ret_val = E1000_SUCCESS;
2367 u32 ctrl;
2368
2369 DEBUGFUNC("e1000_phy_hw_reset_generic");
2370
2371 ret_val = phy->ops.check_reset_block(hw);
2372 if (ret_val) {
2373 ret_val = E1000_SUCCESS;
2374 goto out;
2375 }
2376
2377 ret_val = phy->ops.acquire(hw);
2378 if (ret_val)
2379 goto out;
2380
2381 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2382 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2383 E1000_WRITE_FLUSH(hw);
2384
2385 usec_delay(phy->reset_delay_us);
2386
2387 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2388 E1000_WRITE_FLUSH(hw);
2389
2390 usec_delay(150);
2391
2392 phy->ops.release(hw);
2393
2394 ret_val = phy->ops.get_cfg_done(hw);
2395
2396 out:
2397 return (ret_val);
2398 }
2399
2400 /*
2401 * e1000_get_cfg_done_generic - Generic configuration done
2402 * @hw: pointer to the HW structure
2403 *
2404 * Generic function to wait 10 milli-seconds for configuration to complete
2405 * and return success.
2406 */
2407 s32
e1000_get_cfg_done_generic(struct e1000_hw * hw)2408 e1000_get_cfg_done_generic(struct e1000_hw *hw)
2409 {
2410 DEBUGFUNC("e1000_get_cfg_done_generic");
2411 UNREFERENCED_1PARAMETER(hw);
2412
2413 msec_delay_irq(10);
2414
2415 return (E1000_SUCCESS);
2416 }
2417
2418 /*
2419 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2420 * @hw: pointer to the HW structure
2421 *
2422 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2423 */
2424 s32
e1000_phy_init_script_igp3(struct e1000_hw * hw)2425 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2426 {
2427 DEBUGOUT("Running IGP 3 PHY init script\n");
2428
2429 /* PHY init IGP 3 */
2430 /* Enable rise/fall, 10-mode work in class-A */
2431 (void) hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2432 /* Remove all caps from Replica path filter */
2433 (void) hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2434 /* Bias trimming for ADC, AFE and Driver (Default) */
2435 (void) hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2436 /* Increase Hybrid poly bias */
2437 (void) hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2438 /* Add 4% to Tx amplitude in Gig mode */
2439 (void) hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2440 /* Disable trimming (TTT) */
2441 (void) hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2442 /* Poly DC correction to 94.6% + 2% for all channels */
2443 (void) hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2444 /* ABS DC correction to 95.9% */
2445 (void) hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2446 /* BG temp curve trim */
2447 (void) hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2448 /* Increasing ADC OPAMP stage 1 currents to max */
2449 (void) hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2450 /* Force 1000 ( required for enabling PHY regs configuration) */
2451 (void) hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2452 /* Set upd_freq to 6 */
2453 (void) hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2454 /* Disable NPDFE */
2455 (void) hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2456 /* Disable adaptive fixed FFE (Default) */
2457 (void) hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2458 /* Enable FFE hysteresis */
2459 (void) hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2460 /* Fixed FFE for short cable lengths */
2461 (void) hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2462 /* Fixed FFE for medium cable lengths */
2463 (void) hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2464 /* Fixed FFE for long cable lengths */
2465 (void) hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2466 /* Enable Adaptive Clip Threshold */
2467 (void) hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2468 /* AHT reset limit to 1 */
2469 (void) hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2470 /* Set AHT master delay to 127 msec */
2471 (void) hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2472 /* Set scan bits for AHT */
2473 (void) hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2474 /* Set AHT Preset bits */
2475 (void) hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2476 /* Change integ_factor of channel A to 3 */
2477 (void) hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2478 /* Change prop_factor of channels BCD to 8 */
2479 (void) hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2480 /* Change cg_icount + enable integbp for channels BCD */
2481 (void) hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2482 /*
2483 * Change cg_icount + enable integbp + change prop_factor_master
2484 * to 8 for channel A
2485 */
2486 (void) hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2487 /* Disable AHT in Slave mode on channel A */
2488 (void) hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2489 /*
2490 * Enable LPLU and disable AN to 1000 in non-D0a states,
2491 * Enable SPD+B2B
2492 */
2493 (void) hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2494 /* Enable restart AN on an1000_dis change */
2495 (void) hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2496 /* Enable wh_fifo read clock in 10/100 modes */
2497 (void) hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2498 /* Restart AN, Speed selection is 1000 */
2499 (void) hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2500
2501 return (E1000_SUCCESS);
2502 }
2503
2504 /*
2505 * e1000_get_phy_type_from_id - Get PHY type from id
2506 * @phy_id: phy_id read from the phy
2507 *
2508 * Returns the phy type from the id.
2509 */
2510 enum e1000_phy_type
e1000_get_phy_type_from_id(u32 phy_id)2511 e1000_get_phy_type_from_id(u32 phy_id)
2512 {
2513 enum e1000_phy_type phy_type = e1000_phy_unknown;
2514
2515 switch (phy_id) {
2516 case M88E1000_I_PHY_ID:
2517 case M88E1000_E_PHY_ID:
2518 case M88E1111_I_PHY_ID:
2519 case M88E1011_I_PHY_ID:
2520 phy_type = e1000_phy_m88;
2521 break;
2522 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2523 phy_type = e1000_phy_igp_2;
2524 break;
2525 case GG82563_E_PHY_ID:
2526 phy_type = e1000_phy_gg82563;
2527 break;
2528 case IGP03E1000_E_PHY_ID:
2529 phy_type = e1000_phy_igp_3;
2530 break;
2531 case IFE_E_PHY_ID:
2532 case IFE_PLUS_E_PHY_ID:
2533 case IFE_C_E_PHY_ID:
2534 phy_type = e1000_phy_ife;
2535 break;
2536 case I82580_I_PHY_ID:
2537 phy_type = e1000_phy_82580;
2538 break;
2539 default:
2540 phy_type = e1000_phy_unknown;
2541 break;
2542 }
2543 return (phy_type);
2544 }
2545
2546 /*
2547 * e1000_determine_phy_address - Determines PHY address.
2548 * @hw: pointer to the HW structure
2549 *
2550 * This uses a trial and error method to loop through possible PHY
2551 * addresses. It tests each by reading the PHY ID registers and
2552 * checking for a match.
2553 */
2554 s32
e1000_determine_phy_address(struct e1000_hw * hw)2555 e1000_determine_phy_address(struct e1000_hw *hw)
2556 {
2557 s32 ret_val = -E1000_ERR_PHY_TYPE;
2558 u32 phy_addr = 0;
2559 u32 i;
2560 enum e1000_phy_type phy_type = e1000_phy_unknown;
2561
2562 hw->phy.id = phy_type;
2563
2564 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2565 hw->phy.addr = phy_addr;
2566 i = 0;
2567
2568 do {
2569 (void) e1000_get_phy_id(hw);
2570 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
2571
2572 /*
2573 * If phy_type is valid, break - we found our
2574 * PHY address
2575 */
2576 if (phy_type != e1000_phy_unknown) {
2577 ret_val = E1000_SUCCESS;
2578 goto out;
2579 }
2580 msec_delay(1);
2581 i++;
2582 } while (i < 10);
2583 }
2584
2585 out:
2586 return (ret_val);
2587 }
2588 /*
2589 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2590 * @hw: pointer to the HW structure
2591 *
2592 * In the case of a PHY power down to save power, or to turn off link during a
2593 * driver unload, or wake on lan is not enabled, restore the link to previous
2594 * settings.
2595 */
2596 void
e1000_power_up_phy_copper(struct e1000_hw * hw)2597 e1000_power_up_phy_copper(struct e1000_hw *hw)
2598 {
2599 u16 mii_reg = 0;
2600
2601 /* The PHY will retain its settings across a power down/up cycle */
2602 (void) hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2603 mii_reg &= ~MII_CR_POWER_DOWN;
2604 (void) hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2605 }
2606
2607 /*
2608 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2609 * @hw: pointer to the HW structure
2610 *
2611 * In the case of a PHY power down to save power, or to turn off link during a
2612 * driver unload, or wake on lan is not enabled, restore the link to previous
2613 * settings.
2614 */
2615 void
e1000_power_down_phy_copper(struct e1000_hw * hw)2616 e1000_power_down_phy_copper(struct e1000_hw *hw)
2617 {
2618 u16 mii_reg = 0;
2619
2620 /* The PHY will retain its settings across a power down/up cycle */
2621 (void) hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2622 mii_reg |= MII_CR_POWER_DOWN;
2623 (void) hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2624 msec_delay(1);
2625 }
2626
2627 /*
2628 * e1000_check_polarity_82577 - Checks the polarity.
2629 * @hw: pointer to the HW structure
2630 *
2631 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2632 *
2633 * Polarity is determined based on the PHY specific status register.
2634 */
2635 s32
e1000_check_polarity_82577(struct e1000_hw * hw)2636 e1000_check_polarity_82577(struct e1000_hw *hw)
2637 {
2638 struct e1000_phy_info *phy = &hw->phy;
2639 s32 ret_val;
2640 u16 data;
2641
2642 DEBUGFUNC("e1000_check_polarity_82577");
2643
2644 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
2645
2646 if (!ret_val)
2647 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
2648 ? e1000_rev_polarity_reversed
2649 : e1000_rev_polarity_normal;
2650
2651 return (ret_val);
2652 }
2653
2654 /*
2655 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
2656 * @hw: pointer to the HW structure
2657 *
2658 * Calls the PHY setup function to force speed and duplex. Clears the
2659 * auto-crossover to force MDI manually. Waits for link and returns
2660 * successful if link up is successful, else -E1000_ERR_PHY (-2).
2661 */
2662 s32
e1000_phy_force_speed_duplex_82577(struct e1000_hw * hw)2663 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
2664 {
2665 struct e1000_phy_info *phy = &hw->phy;
2666 s32 ret_val;
2667 u16 phy_data;
2668 bool link;
2669
2670 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
2671
2672 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
2673 if (ret_val)
2674 goto out;
2675
2676 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
2677
2678 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
2679 if (ret_val)
2680 goto out;
2681
2682 /*
2683 * Clear Auto-Crossover to force MDI manually. 82577 requires MDI
2684 * forced whenever speed and duplex are forced.
2685 */
2686 ret_val = phy->ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
2687 if (ret_val)
2688 goto out;
2689
2690 phy_data &= ~I82577_PHY_CTRL2_AUTO_MDIX;
2691 phy_data &= ~I82577_PHY_CTRL2_FORCE_MDI_MDIX;
2692
2693 ret_val = phy->ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
2694 if (ret_val)
2695 goto out;
2696
2697 DEBUGOUT1("I82577_PHY_CTRL_2: %X\n", phy_data);
2698
2699 usec_delay(1);
2700
2701 if (phy->autoneg_wait_to_complete) {
2702 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
2703
2704 ret_val = e1000_phy_has_link_generic(hw,
2705 PHY_FORCE_LIMIT,
2706 100000,
2707 &link);
2708 if (ret_val)
2709 goto out;
2710
2711 if (!link)
2712 DEBUGOUT("Link taking longer than expected.\n");
2713
2714 /* Try once more */
2715 ret_val = e1000_phy_has_link_generic(hw,
2716 PHY_FORCE_LIMIT,
2717 100000,
2718 &link);
2719 if (ret_val)
2720 goto out;
2721 }
2722
2723 out:
2724 return (ret_val);
2725 }
2726
2727 /*
2728 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
2729 * @hw: pointer to the HW structure
2730 *
2731 * Read PHY status to determine if link is up. If link is up, then
2732 * set/determine 10base-T extended distance and polarity correction. Read
2733 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2734 * determine on the cable length, local and remote receiver.
2735 */
2736 s32
e1000_get_phy_info_82577(struct e1000_hw * hw)2737 e1000_get_phy_info_82577(struct e1000_hw *hw)
2738 {
2739 struct e1000_phy_info *phy = &hw->phy;
2740 s32 ret_val;
2741 u16 data;
2742 bool link;
2743
2744 DEBUGFUNC("e1000_get_phy_info_82577");
2745
2746 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2747 if (ret_val)
2748 goto out;
2749
2750 if (!link) {
2751 DEBUGOUT("Phy info is only valid if link is up\n");
2752 ret_val = -E1000_ERR_CONFIG;
2753 goto out;
2754 }
2755
2756 phy->polarity_correction = true;
2757
2758 ret_val = e1000_check_polarity_82577(hw);
2759 if (ret_val)
2760 goto out;
2761
2762 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
2763 if (ret_val)
2764 goto out;
2765
2766 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? true : false;
2767
2768 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
2769 I82577_PHY_STATUS2_SPEED_1000MBPS) {
2770 ret_val = hw->phy.ops.get_cable_length(hw);
2771 if (ret_val)
2772 goto out;
2773
2774 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2775 if (ret_val)
2776 goto out;
2777
2778 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2779 ? e1000_1000t_rx_status_ok
2780 : e1000_1000t_rx_status_not_ok;
2781
2782 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2783 ? e1000_1000t_rx_status_ok
2784 : e1000_1000t_rx_status_not_ok;
2785 } else {
2786 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2787 phy->local_rx = e1000_1000t_rx_status_undefined;
2788 phy->remote_rx = e1000_1000t_rx_status_undefined;
2789 }
2790
2791 out:
2792 return (ret_val);
2793 }
2794
2795 /*
2796 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
2797 * @hw: pointer to the HW structure
2798 *
2799 * Reads the diagnostic status register and verifies result is valid before
2800 * placing it in the phy_cable_length field.
2801 */
2802 s32
e1000_get_cable_length_82577(struct e1000_hw * hw)2803 e1000_get_cable_length_82577(struct e1000_hw *hw)
2804 {
2805 struct e1000_phy_info *phy = &hw->phy;
2806 s32 ret_val;
2807 u16 phy_data, length;
2808
2809 DEBUGFUNC("e1000_get_cable_length_82577");
2810
2811 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
2812 if (ret_val)
2813 goto out;
2814
2815 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
2816 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
2817
2818 if (length == E1000_CABLE_LENGTH_UNDEFINED)
2819 ret_val = -E1000_ERR_PHY;
2820
2821 phy->cable_length = length;
2822
2823 out:
2824
2825 return (ret_val);
2826 }
2827