/llvm-project/llvm/test/CodeGen/RISCV/rvv/ |
H A D | fixed-vectors-setcc-fp-vp.ll |
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H A D | half-round-conv.ll | 87 ; CHECK-NEXT: flh fa5, %lo(.LCPI6_0)(a0) 108 ; CHECK-NEXT: flh fa5, %lo(.LCPI7_0)(a0) 205 ; CHECK-NEXT: flh fa5, %lo(.LCPI14_0)(a0) 226 ; CHECK-NEXT: flh fa5, %lo(.LCPI15_0)(a0) 335 ; CHECK-NEXT: flh fa5, %lo(.LCPI22_0)(a0) 352 ; RV32-NEXT: flh fa5, %lo(.LCPI22_0)(a0) 369 ; RV64-NEXT: flh fa5, %lo(.LCPI22_0)(a0) 392 ; CHECK-NEXT: flh fa5, %lo(.LCPI23_0)(a0) 409 ; RV32-NEXT: flh fa5, %lo(.LCPI23_0)(a0) 426 ; RV64-NEXT: flh fa [all...] |
H A D | fixed-vectors-expandload-fp.ll |
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H A D | frint-sdnode.ll | 157 ; ZVFH-NEXT: flh fa5, %lo(.LCPI6_0)(a0) 192 ; ZVFH-NEXT: flh fa5, %lo(.LCPI7_0)(a0) 227 ; ZVFH-NEXT: flh fa5, %lo(.LCPI8_0)(a0) 262 ; ZVFH-NEXT: flh fa5, %lo(.LCPI9_0)(a0) 297 ; ZVFH-NEXT: flh fa5, %lo(.LCPI10_0)(a0) 332 ; ZVFH-NEXT: flh fa5, %lo(.LCPI11_0)(a0)
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H A D | ftrunc-sdnode.ll | 157 ; ZVFH-NEXT: flh fa5, %lo(.LCPI6_0)(a0) 192 ; ZVFH-NEXT: flh fa5, %lo(.LCPI7_0)(a0) 227 ; ZVFH-NEXT: flh fa5, %lo(.LCPI8_0)(a0) 262 ; ZVFH-NEXT: flh fa5, %lo(.LCPI9_0)(a0) 297 ; ZVFH-NEXT: flh fa5, %lo(.LCPI10_0)(a0) 332 ; ZVFH-NEXT: flh fa5, %lo(.LCPI11_0)(a0)
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H A D | ffloor-sdnode.ll | 177 ; ZVFH-NEXT: flh fa5, %lo(.LCPI6_0)(a0) 216 ; ZVFH-NEXT: flh fa5, %lo(.LCPI7_0)(a0) 255 ; ZVFH-NEXT: flh fa5, %lo(.LCPI8_0)(a0) 294 ; ZVFH-NEXT: flh fa5, %lo(.LCPI9_0)(a0) 333 ; ZVFH-NEXT: flh fa5, %lo(.LCPI10_0)(a0) 372 ; ZVFH-NEXT: flh fa5, %lo(.LCPI11_0)(a0)
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H A D | froundeven-sdnode.ll | 172 ; ZVFH-NEXT: flh fa5, %lo(.LCPI6_0)(a0) 211 ; ZVFH-NEXT: flh fa5, %lo(.LCPI7_0)(a0) 250 ; ZVFH-NEXT: flh fa5, %lo(.LCPI8_0)(a0) 289 ; ZVFH-NEXT: flh fa5, %lo(.LCPI9_0)(a0) 328 ; ZVFH-NEXT: flh fa5, %lo(.LCPI10_0)(a0) 367 ; ZVFH-NEXT: flh fa5, %lo(.LCPI11_0)(a0)
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/llvm-project/llvm/test/MC/RISCV/ |
H A D | rv32zfbfmin-valid.s |
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H A D | rv32zfhmin-valid.s |
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H A D | rv32zfh-valid.s |
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H A D | rv32zfhmin-invalid.s |
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H A D | rv32zfbfmin-invalid.s |
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H A D | rv32zfh-invalid.s | 6 flh ft1, -2049(a0) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo/%tpre… label 10 flh ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction label 14 flh ft15, 100(a0) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction label 15 flh ft1, 100(a10) # CHECK: :[[@LINE]]:14: error: expected register label
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H A D | rvzfh-pseudos.s | 6 # CHECK: flh fa2, %pcrel_lo(.Lpcrel_hi0)(a2) 7 flh fa2, a_symbol, a2 label
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H A D | rvzfh-aliases-valid.s | 50 # CHECK-INST: flh ft0, 0(a0) 51 # CHECK-ALIAS: flh ft0, 0(a0) 52 flh f0, (x10) label
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/llvm-project/llvm/test/CodeGen/RISCV/ |
H A D | half-zfa-fli.ll | 20 ; ZFHMIN-NEXT: flh fa0, %lo(.LCPI0_0)(a0) 34 ; ZFHMIN-NEXT: flh fa0, %lo(.LCPI1_0)(a0) 48 ; ZFHMIN-NEXT: flh fa0, %lo(.LCPI2_0)(a0) 62 ; ZFHMIN-NEXT: flh fa0, %lo(.LCPI3_0)(a0) 76 ; ZFHMIN-NEXT: flh fa0, %lo(.LCPI4_0)(a0) 90 ; ZFHMIN-NEXT: flh fa0, %lo(.LCPI5_0)(a0) 104 ; ZFHMIN-NEXT: flh fa0, %lo(.LCPI6_0)(a0) 127 ; CHECK-NEXT: flh fa0, %lo(.LCPI8_0)(a0) 133 ; ZFHMIN-NEXT: flh fa0, %lo(.LCPI8_0)(a0) 173 ; CHECK-NEXT: flh fa0, %lo(.LCPI11_0)(a0) [all …]
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H A D | bfloat-mem.ll | 7 define bfloat @flh(ptr %a) nounwind { 8 ; CHECK-LABEL: flh: 10 ; CHECK-NEXT: flh fa5, 6(a0) 11 ; CHECK-NEXT: flh fa4, 0(a0) 20 ; Use both loaded values in an FP op to ensure an flh is used, even for the 55 ; CHECK-NEXT: flh fa4, %lo(G)(a0) 59 ; CHECK-NEXT: flh fa5, 18(a1) 76 ; RV32IZFBFMIN-NEXT: flh fa5, -273(a0) 88 ; RV64IZFBFMIN-NEXT: flh fa5, -273(a0) 113 ; RV32IZFBFMIN-NEXT: flh fa [all...] |
H A D | inline-asm-zfh-constraint-f.ll | 17 ; RV32ZFH-NEXT: flh fa5, %lo(gh)(a0) 26 ; RV64ZFH-NEXT: flh fa5, %lo(gh)(a0) 35 ; RV32DZFH-NEXT: flh fa5, %lo(gh)(a0) 44 ; RV64DZFH-NEXT: flh fa5, %lo(gh)(a0) 58 ; RV32ZFH-NEXT: flh fa5, %lo(gh)(a0) 67 ; RV64ZFH-NEXT: flh fa5, %lo(gh)(a0) 76 ; RV32DZFH-NEXT: flh fa5, %lo(gh)(a0) 85 ; RV64DZFH-NEXT: flh fa5, %lo(gh)(a0) 101 ; RV32ZFH-NEXT: flh fs0, %lo(gh)(a0) 115 ; RV64ZFH-NEXT: flh fs [all...] |
H A D | half-mem.ll | 19 define half @flh(ptr %a) nounwind { 20 ; CHECKIZFH-LABEL: flh: 22 ; CHECKIZFH-NEXT: flh fa5, 0(a0) 23 ; CHECKIZFH-NEXT: flh fa4, 6(a0) 27 ; CHECKIZHINX-LABEL: flh: 34 ; CHECKIZFHMIN-LABEL: flh: 36 ; CHECKIZFHMIN-NEXT: flh fa5, 6(a0) 37 ; CHECKIZFHMIN-NEXT: flh fa4, 0(a0) 44 ; CHECKIZHINXMIN-LABEL: flh: 56 ; Use both loaded values in an FP op to ensure an flh i [all...] |
H A D | half-imm.ll | 28 ; CHECK-NEXT: flh fa0, %lo(.LCPI0_0)(a0) 48 ; CHECKIZFHMIN-NEXT: flh fa0, %lo(.LCPI0_0)(a0) 71 ; CHECK-NEXT: flh fa5, %lo(.LCPI1_0)(a0)
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H A D | spill-fpr-scalar.ll | 10 ; CHECK-NEXT: flh fa5, 0(a0) 14 ; CHECK-NEXT: flh fa5, 14(sp) # 2-byte Folded Reload
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H A D | zfbfmin.ll |
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/llvm-project/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/ |
H A D | load.s | 7 flh ft0, 0(a0) label 32 # CHECK-NEXT: 1 5 1.00 * flh ft0, 0(a0) 59 # CHECK-NEXT: - - - - - - 1.00 - - - - - - flh ft0, 0(a0)
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/llvm-project/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/ |
H A D | load.s | 7 flh ft0, 0(a0) label 32 # CHECK-NEXT: 1 5 0.50 * flh ft0, 0(a0) 62 … - - - - - 1.00 - - - - - - flh ft0, 0(a0)
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/llvm-project/llvm/test/MC/RISCV/rvv/ |
H A D | zvfbfwma.s | 46 # CHECK-INST: flh ft0, 12(a0) 50 flh f0, 12(a0) label
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