xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll (revision 1cb599835ccf7ee8b2d1d5a7f3107e19a26fc6f5) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+zvfh,+v -verify-machineinstrs < %s | \
3; RUN:   FileCheck %s
4; RUN: llc -mtriple=riscv64 -mattr=+zvfh,+v -verify-machineinstrs < %s | \
5; RUN:   FileCheck %s
6
7; ================================================================================
8; trunc <vscale x 1 x half>
9; ================================================================================
10
11declare <vscale x 1 x half> @llvm.trunc.nxv1f16(<vscale x 1 x half>)
12
13define <vscale x 1 x i8> @trunc_nxv1f16_to_si8(<vscale x 1 x half> %x) {
14; CHECK-LABEL: trunc_nxv1f16_to_si8:
15; CHECK:       # %bb.0:
16; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
17; CHECK-NEXT:    vfncvt.rtz.x.f.w v9, v8
18; CHECK-NEXT:    vmv1r.v v8, v9
19; CHECK-NEXT:    ret
20  %a = call <vscale x 1 x half> @llvm.trunc.nxv1f16(<vscale x 1 x half> %x)
21  %b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i8>
22  ret <vscale x 1 x i8> %b
23}
24
25define <vscale x 1 x i8> @trunc_nxv1f16_to_ui8(<vscale x 1 x half> %x) {
26; CHECK-LABEL: trunc_nxv1f16_to_ui8:
27; CHECK:       # %bb.0:
28; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
29; CHECK-NEXT:    vfncvt.rtz.xu.f.w v9, v8
30; CHECK-NEXT:    vmv1r.v v8, v9
31; CHECK-NEXT:    ret
32  %a = call <vscale x 1 x half> @llvm.trunc.nxv1f16(<vscale x 1 x half> %x)
33  %b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i8>
34  ret <vscale x 1 x i8> %b
35}
36
37define <vscale x 1 x i16> @trunc_nxv1f16_to_si16(<vscale x 1 x half> %x) {
38; CHECK-LABEL: trunc_nxv1f16_to_si16:
39; CHECK:       # %bb.0:
40; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
41; CHECK-NEXT:    vfcvt.rtz.x.f.v v8, v8
42; CHECK-NEXT:    ret
43  %a = call <vscale x 1 x half> @llvm.trunc.nxv1f16(<vscale x 1 x half> %x)
44  %b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i16>
45  ret <vscale x 1 x i16> %b
46}
47
48define <vscale x 1 x i16> @trunc_nxv1f16_to_ui16(<vscale x 1 x half> %x) {
49; CHECK-LABEL: trunc_nxv1f16_to_ui16:
50; CHECK:       # %bb.0:
51; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
52; CHECK-NEXT:    vfcvt.rtz.xu.f.v v8, v8
53; CHECK-NEXT:    ret
54  %a = call <vscale x 1 x half> @llvm.trunc.nxv1f16(<vscale x 1 x half> %x)
55  %b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i16>
56  ret <vscale x 1 x i16> %b
57}
58
59define <vscale x 1 x i32> @trunc_nxv1f16_to_si32(<vscale x 1 x half> %x) {
60; CHECK-LABEL: trunc_nxv1f16_to_si32:
61; CHECK:       # %bb.0:
62; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
63; CHECK-NEXT:    vfwcvt.rtz.x.f.v v9, v8
64; CHECK-NEXT:    vmv1r.v v8, v9
65; CHECK-NEXT:    ret
66  %a = call <vscale x 1 x half> @llvm.trunc.nxv1f16(<vscale x 1 x half> %x)
67  %b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i32>
68  ret <vscale x 1 x i32> %b
69}
70
71define <vscale x 1 x i32> @trunc_nxv1f16_to_ui32(<vscale x 1 x half> %x) {
72; CHECK-LABEL: trunc_nxv1f16_to_ui32:
73; CHECK:       # %bb.0:
74; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
75; CHECK-NEXT:    vfwcvt.rtz.xu.f.v v9, v8
76; CHECK-NEXT:    vmv1r.v v8, v9
77; CHECK-NEXT:    ret
78  %a = call <vscale x 1 x half> @llvm.trunc.nxv1f16(<vscale x 1 x half> %x)
79  %b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i32>
80  ret <vscale x 1 x i32> %b
81}
82
83define <vscale x 1 x i64> @trunc_nxv1f16_to_si64(<vscale x 1 x half> %x) {
84; CHECK-LABEL: trunc_nxv1f16_to_si64:
85; CHECK:       # %bb.0:
86; CHECK-NEXT:    lui a0, %hi(.LCPI6_0)
87; CHECK-NEXT:    flh fa5, %lo(.LCPI6_0)(a0)
88; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
89; CHECK-NEXT:    vfabs.v v9, v8
90; CHECK-NEXT:    vmflt.vf v0, v9, fa5
91; CHECK-NEXT:    vfcvt.rtz.x.f.v v9, v8, v0.t
92; CHECK-NEXT:    vfcvt.f.x.v v9, v9, v0.t
93; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
94; CHECK-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
95; CHECK-NEXT:    vfwcvt.f.f.v v9, v8
96; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
97; CHECK-NEXT:    vfwcvt.rtz.x.f.v v8, v9
98; CHECK-NEXT:    ret
99  %a = call <vscale x 1 x half> @llvm.trunc.nxv1f16(<vscale x 1 x half> %x)
100  %b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i64>
101  ret <vscale x 1 x i64> %b
102}
103
104define <vscale x 1 x i64> @trunc_nxv1f16_to_ui64(<vscale x 1 x half> %x) {
105; CHECK-LABEL: trunc_nxv1f16_to_ui64:
106; CHECK:       # %bb.0:
107; CHECK-NEXT:    lui a0, %hi(.LCPI7_0)
108; CHECK-NEXT:    flh fa5, %lo(.LCPI7_0)(a0)
109; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
110; CHECK-NEXT:    vfabs.v v9, v8
111; CHECK-NEXT:    vmflt.vf v0, v9, fa5
112; CHECK-NEXT:    vfcvt.rtz.x.f.v v9, v8, v0.t
113; CHECK-NEXT:    vfcvt.f.x.v v9, v9, v0.t
114; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
115; CHECK-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
116; CHECK-NEXT:    vfwcvt.f.f.v v9, v8
117; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
118; CHECK-NEXT:    vfwcvt.rtz.xu.f.v v8, v9
119; CHECK-NEXT:    ret
120  %a = call <vscale x 1 x half> @llvm.trunc.nxv1f16(<vscale x 1 x half> %x)
121  %b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i64>
122  ret <vscale x 1 x i64> %b
123}
124
125; ================================================================================
126; trunc <vscale x 4 x half>
127; ================================================================================
128
129declare <vscale x 4 x half> @llvm.trunc.nxv4f16(<vscale x 4 x half>)
130
131define <vscale x 4 x i8> @trunc_nxv4f16_to_si8(<vscale x 4 x half> %x) {
132; CHECK-LABEL: trunc_nxv4f16_to_si8:
133; CHECK:       # %bb.0:
134; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
135; CHECK-NEXT:    vfncvt.rtz.x.f.w v9, v8
136; CHECK-NEXT:    vmv1r.v v8, v9
137; CHECK-NEXT:    ret
138  %a = call <vscale x 4 x half> @llvm.trunc.nxv4f16(<vscale x 4 x half> %x)
139  %b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i8>
140  ret <vscale x 4 x i8> %b
141}
142
143define <vscale x 4 x i8> @trunc_nxv4f16_to_ui8(<vscale x 4 x half> %x) {
144; CHECK-LABEL: trunc_nxv4f16_to_ui8:
145; CHECK:       # %bb.0:
146; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
147; CHECK-NEXT:    vfncvt.rtz.xu.f.w v9, v8
148; CHECK-NEXT:    vmv1r.v v8, v9
149; CHECK-NEXT:    ret
150  %a = call <vscale x 4 x half> @llvm.trunc.nxv4f16(<vscale x 4 x half> %x)
151  %b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i8>
152  ret <vscale x 4 x i8> %b
153}
154
155define <vscale x 4 x i16> @trunc_nxv4f16_to_si16(<vscale x 4 x half> %x) {
156; CHECK-LABEL: trunc_nxv4f16_to_si16:
157; CHECK:       # %bb.0:
158; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
159; CHECK-NEXT:    vfcvt.rtz.x.f.v v8, v8
160; CHECK-NEXT:    ret
161  %a = call <vscale x 4 x half> @llvm.trunc.nxv4f16(<vscale x 4 x half> %x)
162  %b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i16>
163  ret <vscale x 4 x i16> %b
164}
165
166define <vscale x 4 x i16> @trunc_nxv4f16_to_ui16(<vscale x 4 x half> %x) {
167; CHECK-LABEL: trunc_nxv4f16_to_ui16:
168; CHECK:       # %bb.0:
169; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
170; CHECK-NEXT:    vfcvt.rtz.xu.f.v v8, v8
171; CHECK-NEXT:    ret
172  %a = call <vscale x 4 x half> @llvm.trunc.nxv4f16(<vscale x 4 x half> %x)
173  %b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i16>
174  ret <vscale x 4 x i16> %b
175}
176
177define <vscale x 4 x i32> @trunc_nxv4f16_to_si32(<vscale x 4 x half> %x) {
178; CHECK-LABEL: trunc_nxv4f16_to_si32:
179; CHECK:       # %bb.0:
180; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
181; CHECK-NEXT:    vfwcvt.rtz.x.f.v v10, v8
182; CHECK-NEXT:    vmv2r.v v8, v10
183; CHECK-NEXT:    ret
184  %a = call <vscale x 4 x half> @llvm.trunc.nxv4f16(<vscale x 4 x half> %x)
185  %b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i32>
186  ret <vscale x 4 x i32> %b
187}
188
189define <vscale x 4 x i32> @trunc_nxv4f16_to_ui32(<vscale x 4 x half> %x) {
190; CHECK-LABEL: trunc_nxv4f16_to_ui32:
191; CHECK:       # %bb.0:
192; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
193; CHECK-NEXT:    vfwcvt.rtz.xu.f.v v10, v8
194; CHECK-NEXT:    vmv2r.v v8, v10
195; CHECK-NEXT:    ret
196  %a = call <vscale x 4 x half> @llvm.trunc.nxv4f16(<vscale x 4 x half> %x)
197  %b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i32>
198  ret <vscale x 4 x i32> %b
199}
200
201define <vscale x 4 x i64> @trunc_nxv4f16_to_si64(<vscale x 4 x half> %x) {
202; CHECK-LABEL: trunc_nxv4f16_to_si64:
203; CHECK:       # %bb.0:
204; CHECK-NEXT:    lui a0, %hi(.LCPI14_0)
205; CHECK-NEXT:    flh fa5, %lo(.LCPI14_0)(a0)
206; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
207; CHECK-NEXT:    vfabs.v v9, v8
208; CHECK-NEXT:    vmflt.vf v0, v9, fa5
209; CHECK-NEXT:    vfcvt.rtz.x.f.v v9, v8, v0.t
210; CHECK-NEXT:    vfcvt.f.x.v v9, v9, v0.t
211; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
212; CHECK-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
213; CHECK-NEXT:    vfwcvt.f.f.v v12, v8
214; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
215; CHECK-NEXT:    vfwcvt.rtz.x.f.v v8, v12
216; CHECK-NEXT:    ret
217  %a = call <vscale x 4 x half> @llvm.trunc.nxv4f16(<vscale x 4 x half> %x)
218  %b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i64>
219  ret <vscale x 4 x i64> %b
220}
221
222define <vscale x 4 x i64> @trunc_nxv4f16_to_ui64(<vscale x 4 x half> %x) {
223; CHECK-LABEL: trunc_nxv4f16_to_ui64:
224; CHECK:       # %bb.0:
225; CHECK-NEXT:    lui a0, %hi(.LCPI15_0)
226; CHECK-NEXT:    flh fa5, %lo(.LCPI15_0)(a0)
227; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
228; CHECK-NEXT:    vfabs.v v9, v8
229; CHECK-NEXT:    vmflt.vf v0, v9, fa5
230; CHECK-NEXT:    vfcvt.rtz.x.f.v v9, v8, v0.t
231; CHECK-NEXT:    vfcvt.f.x.v v9, v9, v0.t
232; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
233; CHECK-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
234; CHECK-NEXT:    vfwcvt.f.f.v v12, v8
235; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
236; CHECK-NEXT:    vfwcvt.rtz.xu.f.v v8, v12
237; CHECK-NEXT:    ret
238  %a = call <vscale x 4 x half> @llvm.trunc.nxv4f16(<vscale x 4 x half> %x)
239  %b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i64>
240  ret <vscale x 4 x i64> %b
241}
242
243; ================================================================================
244; ceil <vscale x 1 x half>
245; ================================================================================
246
247declare <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half>)
248
249define <vscale x 1 x i8> @ceil_nxv1f16_to_si8(<vscale x 1 x half> %x) {
250; CHECK-LABEL: ceil_nxv1f16_to_si8:
251; CHECK:       # %bb.0:
252; CHECK-NEXT:    fsrmi a0, 3
253; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
254; CHECK-NEXT:    vfncvt.x.f.w v9, v8
255; CHECK-NEXT:    fsrm a0
256; CHECK-NEXT:    vmv1r.v v8, v9
257; CHECK-NEXT:    ret
258  %a = call <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half> %x)
259  %b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i8>
260  ret <vscale x 1 x i8> %b
261}
262
263define <vscale x 1 x i8> @ceil_nxv1f16_to_ui8(<vscale x 1 x half> %x) {
264; CHECK-LABEL: ceil_nxv1f16_to_ui8:
265; CHECK:       # %bb.0:
266; CHECK-NEXT:    fsrmi a0, 3
267; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
268; CHECK-NEXT:    vfncvt.xu.f.w v9, v8
269; CHECK-NEXT:    fsrm a0
270; CHECK-NEXT:    vmv1r.v v8, v9
271; CHECK-NEXT:    ret
272  %a = call <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half> %x)
273  %b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i8>
274  ret <vscale x 1 x i8> %b
275}
276
277define <vscale x 1 x i16> @ceil_nxv1f16_to_si16(<vscale x 1 x half> %x) {
278; CHECK-LABEL: ceil_nxv1f16_to_si16:
279; CHECK:       # %bb.0:
280; CHECK-NEXT:    fsrmi a0, 3
281; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
282; CHECK-NEXT:    vfcvt.x.f.v v8, v8
283; CHECK-NEXT:    fsrm a0
284; CHECK-NEXT:    ret
285  %a = call <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half> %x)
286  %b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i16>
287  ret <vscale x 1 x i16> %b
288}
289
290define <vscale x 1 x i16> @ceil_nxv1f16_to_ui16(<vscale x 1 x half> %x) {
291; CHECK-LABEL: ceil_nxv1f16_to_ui16:
292; CHECK:       # %bb.0:
293; CHECK-NEXT:    fsrmi a0, 3
294; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
295; CHECK-NEXT:    vfcvt.xu.f.v v8, v8
296; CHECK-NEXT:    fsrm a0
297; CHECK-NEXT:    ret
298  %a = call <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half> %x)
299  %b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i16>
300  ret <vscale x 1 x i16> %b
301}
302
303define <vscale x 1 x i32> @ceil_nxv1f16_to_si32(<vscale x 1 x half> %x) {
304; CHECK-LABEL: ceil_nxv1f16_to_si32:
305; CHECK:       # %bb.0:
306; CHECK-NEXT:    fsrmi a0, 3
307; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
308; CHECK-NEXT:    vfwcvt.x.f.v v9, v8
309; CHECK-NEXT:    fsrm a0
310; CHECK-NEXT:    vmv1r.v v8, v9
311; CHECK-NEXT:    ret
312  %a = call <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half> %x)
313  %b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i32>
314  ret <vscale x 1 x i32> %b
315}
316
317define <vscale x 1 x i32> @ceil_nxv1f16_to_ui32(<vscale x 1 x half> %x) {
318; CHECK-LABEL: ceil_nxv1f16_to_ui32:
319; CHECK:       # %bb.0:
320; CHECK-NEXT:    fsrmi a0, 3
321; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
322; CHECK-NEXT:    vfwcvt.xu.f.v v9, v8
323; CHECK-NEXT:    fsrm a0
324; CHECK-NEXT:    vmv1r.v v8, v9
325; CHECK-NEXT:    ret
326  %a = call <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half> %x)
327  %b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i32>
328  ret <vscale x 1 x i32> %b
329}
330
331define <vscale x 1 x i64> @ceil_nxv1f16_to_si64(<vscale x 1 x half> %x) {
332; CHECK-LABEL: ceil_nxv1f16_to_si64:
333; CHECK:       # %bb.0:
334; CHECK-NEXT:    lui a0, %hi(.LCPI22_0)
335; CHECK-NEXT:    flh fa5, %lo(.LCPI22_0)(a0)
336; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
337; CHECK-NEXT:    vfabs.v v9, v8
338; CHECK-NEXT:    vmflt.vf v0, v9, fa5
339; CHECK-NEXT:    fsrmi a0, 3
340; CHECK-NEXT:    vfcvt.x.f.v v9, v8, v0.t
341; CHECK-NEXT:    fsrm a0
342; CHECK-NEXT:    vfcvt.f.x.v v9, v9, v0.t
343; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
344; CHECK-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
345; CHECK-NEXT:    vfwcvt.f.f.v v9, v8
346; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
347; CHECK-NEXT:    vfwcvt.rtz.x.f.v v8, v9
348; CHECK-NEXT:    ret
349; RV32-LABEL: ceil_nxv1f16_to_si64:
350; RV32:       # %bb.0:
351; RV32-NEXT:    lui a0, %hi(.LCPI22_0)
352; RV32-NEXT:    flh fa5, %lo(.LCPI22_0)(a0)
353; RV32-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
354; RV32-NEXT:    vfabs.v v9, v8
355; RV32-NEXT:    vmflt.vf v0, v9, fa5
356; RV32-NEXT:    fsrmi a0, 3
357; RV32-NEXT:    vfcvt.x.f.v v9, v8, v0.t
358; RV32-NEXT:    vfcvt.f.x.v v9, v9, v0.t
359; RV32-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
360; RV32-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
361; RV32-NEXT:    vfwcvt.f.f.v v9, v8
362; RV32-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
363; RV32-NEXT:    vfwcvt.rtz.x.f.v v8, v9
364; RV32-NEXT:    fsrm a0
365; RV32-NEXT:    ret
366; RV64-LABEL: ceil_nxv1f16_to_si64:
367; RV64:       # %bb.0:
368; RV64-NEXT:    lui a0, %hi(.LCPI22_0)
369; RV64-NEXT:    flh fa5, %lo(.LCPI22_0)(a0)
370; RV64-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
371; RV64-NEXT:    vfabs.v v9, v8
372; RV64-NEXT:    vmflt.vf v0, v9, fa5
373; RV64-NEXT:    fsrmi a0, 3
374; RV64-NEXT:    vfcvt.x.f.v v9, v8, v0.t
375; RV64-NEXT:    vfcvt.f.x.v v9, v9, v0.t
376; RV64-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
377; RV64-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
378; RV64-NEXT:    vfwcvt.f.f.v v9, v8
379; RV64-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
380; RV64-NEXT:    vfwcvt.rtz.x.f.v v8, v9
381; RV64-NEXT:    fsrm a0
382; RV64-NEXT:    ret
383  %a = call <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half> %x)
384  %b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i64>
385  ret <vscale x 1 x i64> %b
386}
387
388define <vscale x 1 x i64> @ceil_nxv1f16_to_ui64(<vscale x 1 x half> %x) {
389; CHECK-LABEL: ceil_nxv1f16_to_ui64:
390; CHECK:       # %bb.0:
391; CHECK-NEXT:    lui a0, %hi(.LCPI23_0)
392; CHECK-NEXT:    flh fa5, %lo(.LCPI23_0)(a0)
393; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
394; CHECK-NEXT:    vfabs.v v9, v8
395; CHECK-NEXT:    vmflt.vf v0, v9, fa5
396; CHECK-NEXT:    fsrmi a0, 3
397; CHECK-NEXT:    vfcvt.x.f.v v9, v8, v0.t
398; CHECK-NEXT:    fsrm a0
399; CHECK-NEXT:    vfcvt.f.x.v v9, v9, v0.t
400; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
401; CHECK-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
402; CHECK-NEXT:    vfwcvt.f.f.v v9, v8
403; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
404; CHECK-NEXT:    vfwcvt.rtz.xu.f.v v8, v9
405; CHECK-NEXT:    ret
406; RV32-LABEL: ceil_nxv1f16_to_ui64:
407; RV32:       # %bb.0:
408; RV32-NEXT:    lui a0, %hi(.LCPI23_0)
409; RV32-NEXT:    flh fa5, %lo(.LCPI23_0)(a0)
410; RV32-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
411; RV32-NEXT:    vfabs.v v9, v8
412; RV32-NEXT:    vmflt.vf v0, v9, fa5
413; RV32-NEXT:    fsrmi a0, 3
414; RV32-NEXT:    vfcvt.x.f.v v9, v8, v0.t
415; RV32-NEXT:    vfcvt.f.x.v v9, v9, v0.t
416; RV32-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
417; RV32-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
418; RV32-NEXT:    vfwcvt.f.f.v v9, v8
419; RV32-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
420; RV32-NEXT:    vfwcvt.rtz.xu.f.v v8, v9
421; RV32-NEXT:    fsrm a0
422; RV32-NEXT:    ret
423; RV64-LABEL: ceil_nxv1f16_to_ui64:
424; RV64:       # %bb.0:
425; RV64-NEXT:    lui a0, %hi(.LCPI23_0)
426; RV64-NEXT:    flh fa5, %lo(.LCPI23_0)(a0)
427; RV64-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
428; RV64-NEXT:    vfabs.v v9, v8
429; RV64-NEXT:    vmflt.vf v0, v9, fa5
430; RV64-NEXT:    fsrmi a0, 3
431; RV64-NEXT:    vfcvt.x.f.v v9, v8, v0.t
432; RV64-NEXT:    vfcvt.f.x.v v9, v9, v0.t
433; RV64-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
434; RV64-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
435; RV64-NEXT:    vfwcvt.f.f.v v9, v8
436; RV64-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
437; RV64-NEXT:    vfwcvt.rtz.xu.f.v v8, v9
438; RV64-NEXT:    fsrm a0
439; RV64-NEXT:    ret
440  %a = call <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half> %x)
441  %b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i64>
442  ret <vscale x 1 x i64> %b
443}
444
445; ================================================================================
446; ceil <vscale x 4 x half>
447; ================================================================================
448
449declare <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half>)
450
451define <vscale x 4 x i8> @ceil_nxv4f16_to_si8(<vscale x 4 x half> %x) {
452; CHECK-LABEL: ceil_nxv4f16_to_si8:
453; CHECK:       # %bb.0:
454; CHECK-NEXT:    fsrmi a0, 3
455; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
456; CHECK-NEXT:    vfncvt.x.f.w v9, v8
457; CHECK-NEXT:    fsrm a0
458; CHECK-NEXT:    vmv1r.v v8, v9
459; CHECK-NEXT:    ret
460  %a = call <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half> %x)
461  %b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i8>
462  ret <vscale x 4 x i8> %b
463}
464
465define <vscale x 4 x i8> @ceil_nxv4f16_to_ui8(<vscale x 4 x half> %x) {
466; CHECK-LABEL: ceil_nxv4f16_to_ui8:
467; CHECK:       # %bb.0:
468; CHECK-NEXT:    fsrmi a0, 3
469; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
470; CHECK-NEXT:    vfncvt.xu.f.w v9, v8
471; CHECK-NEXT:    fsrm a0
472; CHECK-NEXT:    vmv1r.v v8, v9
473; CHECK-NEXT:    ret
474  %a = call <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half> %x)
475  %b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i8>
476  ret <vscale x 4 x i8> %b
477}
478
479define <vscale x 4 x i16> @ceil_nxv4f16_to_si16(<vscale x 4 x half> %x) {
480; CHECK-LABEL: ceil_nxv4f16_to_si16:
481; CHECK:       # %bb.0:
482; CHECK-NEXT:    fsrmi a0, 3
483; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
484; CHECK-NEXT:    vfcvt.x.f.v v8, v8
485; CHECK-NEXT:    fsrm a0
486; CHECK-NEXT:    ret
487  %a = call <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half> %x)
488  %b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i16>
489  ret <vscale x 4 x i16> %b
490}
491
492define <vscale x 4 x i16> @ceil_nxv4f16_to_ui16(<vscale x 4 x half> %x) {
493; CHECK-LABEL: ceil_nxv4f16_to_ui16:
494; CHECK:       # %bb.0:
495; CHECK-NEXT:    fsrmi a0, 3
496; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
497; CHECK-NEXT:    vfcvt.xu.f.v v8, v8
498; CHECK-NEXT:    fsrm a0
499; CHECK-NEXT:    ret
500  %a = call <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half> %x)
501  %b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i16>
502  ret <vscale x 4 x i16> %b
503}
504
505define <vscale x 4 x i32> @ceil_nxv4f16_to_si32(<vscale x 4 x half> %x) {
506; CHECK-LABEL: ceil_nxv4f16_to_si32:
507; CHECK:       # %bb.0:
508; CHECK-NEXT:    fsrmi a0, 3
509; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
510; CHECK-NEXT:    vfwcvt.x.f.v v10, v8
511; CHECK-NEXT:    fsrm a0
512; CHECK-NEXT:    vmv2r.v v8, v10
513; CHECK-NEXT:    ret
514  %a = call <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half> %x)
515  %b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i32>
516  ret <vscale x 4 x i32> %b
517}
518
519define <vscale x 4 x i32> @ceil_nxv4f16_to_ui32(<vscale x 4 x half> %x) {
520; CHECK-LABEL: ceil_nxv4f16_to_ui32:
521; CHECK:       # %bb.0:
522; CHECK-NEXT:    fsrmi a0, 3
523; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
524; CHECK-NEXT:    vfwcvt.xu.f.v v10, v8
525; CHECK-NEXT:    fsrm a0
526; CHECK-NEXT:    vmv2r.v v8, v10
527; CHECK-NEXT:    ret
528  %a = call <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half> %x)
529  %b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i32>
530  ret <vscale x 4 x i32> %b
531}
532
533define <vscale x 4 x i64> @ceil_nxv4f16_to_si64(<vscale x 4 x half> %x) {
534; CHECK-LABEL: ceil_nxv4f16_to_si64:
535; CHECK:       # %bb.0:
536; CHECK-NEXT:    lui a0, %hi(.LCPI30_0)
537; CHECK-NEXT:    flh fa5, %lo(.LCPI30_0)(a0)
538; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
539; CHECK-NEXT:    vfabs.v v9, v8
540; CHECK-NEXT:    vmflt.vf v0, v9, fa5
541; CHECK-NEXT:    fsrmi a0, 3
542; CHECK-NEXT:    vfcvt.x.f.v v9, v8, v0.t
543; CHECK-NEXT:    fsrm a0
544; CHECK-NEXT:    vfcvt.f.x.v v9, v9, v0.t
545; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
546; CHECK-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
547; CHECK-NEXT:    vfwcvt.f.f.v v12, v8
548; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
549; CHECK-NEXT:    vfwcvt.rtz.x.f.v v8, v12
550; CHECK-NEXT:    ret
551; RV32-LABEL: ceil_nxv4f16_to_si64:
552; RV32:       # %bb.0:
553; RV32-NEXT:    lui a0, %hi(.LCPI30_0)
554; RV32-NEXT:    flh fa5, %lo(.LCPI30_0)(a0)
555; RV32-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
556; RV32-NEXT:    vfabs.v v9, v8
557; RV32-NEXT:    vmflt.vf v0, v9, fa5
558; RV32-NEXT:    fsrmi a0, 3
559; RV32-NEXT:    vfcvt.x.f.v v9, v8, v0.t
560; RV32-NEXT:    vfcvt.f.x.v v9, v9, v0.t
561; RV32-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
562; RV32-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
563; RV32-NEXT:    vfwcvt.f.f.v v12, v8
564; RV32-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
565; RV32-NEXT:    vfwcvt.rtz.x.f.v v8, v12
566; RV32-NEXT:    fsrm a0
567; RV32-NEXT:    ret
568; RV64-LABEL: ceil_nxv4f16_to_si64:
569; RV64:       # %bb.0:
570; RV64-NEXT:    lui a0, %hi(.LCPI30_0)
571; RV64-NEXT:    flh fa5, %lo(.LCPI30_0)(a0)
572; RV64-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
573; RV64-NEXT:    vfabs.v v9, v8
574; RV64-NEXT:    vmflt.vf v0, v9, fa5
575; RV64-NEXT:    fsrmi a0, 3
576; RV64-NEXT:    vfcvt.x.f.v v9, v8, v0.t
577; RV64-NEXT:    vfcvt.f.x.v v9, v9, v0.t
578; RV64-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
579; RV64-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
580; RV64-NEXT:    vfwcvt.f.f.v v12, v8
581; RV64-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
582; RV64-NEXT:    vfwcvt.rtz.x.f.v v8, v12
583; RV64-NEXT:    fsrm a0
584; RV64-NEXT:    ret
585  %a = call <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half> %x)
586  %b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i64>
587  ret <vscale x 4 x i64> %b
588}
589
590define <vscale x 4 x i64> @ceil_nxv4f16_to_ui64(<vscale x 4 x half> %x) {
591; CHECK-LABEL: ceil_nxv4f16_to_ui64:
592; CHECK:       # %bb.0:
593; CHECK-NEXT:    lui a0, %hi(.LCPI31_0)
594; CHECK-NEXT:    flh fa5, %lo(.LCPI31_0)(a0)
595; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
596; CHECK-NEXT:    vfabs.v v9, v8
597; CHECK-NEXT:    vmflt.vf v0, v9, fa5
598; CHECK-NEXT:    fsrmi a0, 3
599; CHECK-NEXT:    vfcvt.x.f.v v9, v8, v0.t
600; CHECK-NEXT:    fsrm a0
601; CHECK-NEXT:    vfcvt.f.x.v v9, v9, v0.t
602; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
603; CHECK-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
604; CHECK-NEXT:    vfwcvt.f.f.v v12, v8
605; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
606; CHECK-NEXT:    vfwcvt.rtz.xu.f.v v8, v12
607; CHECK-NEXT:    ret
608; RV32-LABEL: ceil_nxv4f16_to_ui64:
609; RV32:       # %bb.0:
610; RV32-NEXT:    lui a0, %hi(.LCPI31_0)
611; RV32-NEXT:    flh fa5, %lo(.LCPI31_0)(a0)
612; RV32-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
613; RV32-NEXT:    vfabs.v v9, v8
614; RV32-NEXT:    vmflt.vf v0, v9, fa5
615; RV32-NEXT:    fsrmi a0, 3
616; RV32-NEXT:    vfcvt.x.f.v v9, v8, v0.t
617; RV32-NEXT:    vfcvt.f.x.v v9, v9, v0.t
618; RV32-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
619; RV32-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
620; RV32-NEXT:    vfwcvt.f.f.v v12, v8
621; RV32-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
622; RV32-NEXT:    vfwcvt.rtz.xu.f.v v8, v12
623; RV32-NEXT:    fsrm a0
624; RV32-NEXT:    ret
625; RV64-LABEL: ceil_nxv4f16_to_ui64:
626; RV64:       # %bb.0:
627; RV64-NEXT:    lui a0, %hi(.LCPI31_0)
628; RV64-NEXT:    flh fa5, %lo(.LCPI31_0)(a0)
629; RV64-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
630; RV64-NEXT:    vfabs.v v9, v8
631; RV64-NEXT:    vmflt.vf v0, v9, fa5
632; RV64-NEXT:    fsrmi a0, 3
633; RV64-NEXT:    vfcvt.x.f.v v9, v8, v0.t
634; RV64-NEXT:    vfcvt.f.x.v v9, v9, v0.t
635; RV64-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
636; RV64-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
637; RV64-NEXT:    vfwcvt.f.f.v v12, v8
638; RV64-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
639; RV64-NEXT:    vfwcvt.rtz.xu.f.v v8, v12
640; RV64-NEXT:    fsrm a0
641; RV64-NEXT:    ret
642  %a = call <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half> %x)
643  %b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i64>
644  ret <vscale x 4 x i64> %b
645}
646
647; ================================================================================
648; rint <vscale x 1 x half>
649; ================================================================================
650
651declare <vscale x 1 x half> @llvm.rint.nxv1f16(<vscale x 1 x half>)
652
653define <vscale x 1 x i8> @rint_nxv1f16_to_si8(<vscale x 1 x half> %x) {
654; CHECK-LABEL: rint_nxv1f16_to_si8:
655; CHECK:       # %bb.0:
656; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
657; CHECK-NEXT:    vfncvt.x.f.w v9, v8
658; CHECK-NEXT:    vmv1r.v v8, v9
659; CHECK-NEXT:    ret
660  %a = call <vscale x 1 x half> @llvm.rint.nxv1f16(<vscale x 1 x half> %x)
661  %b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i8>
662  ret <vscale x 1 x i8> %b
663}
664
665define <vscale x 1 x i8> @rint_nxv1f16_to_ui8(<vscale x 1 x half> %x) {
666; CHECK-LABEL: rint_nxv1f16_to_ui8:
667; CHECK:       # %bb.0:
668; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
669; CHECK-NEXT:    vfncvt.xu.f.w v9, v8
670; CHECK-NEXT:    vmv1r.v v8, v9
671; CHECK-NEXT:    ret
672  %a = call <vscale x 1 x half> @llvm.rint.nxv1f16(<vscale x 1 x half> %x)
673  %b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i8>
674  ret <vscale x 1 x i8> %b
675}
676
677define <vscale x 1 x i16> @rint_nxv1f16_to_si16(<vscale x 1 x half> %x) {
678; CHECK-LABEL: rint_nxv1f16_to_si16:
679; CHECK:       # %bb.0:
680; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
681; CHECK-NEXT:    vfcvt.x.f.v v8, v8
682; CHECK-NEXT:    ret
683  %a = call <vscale x 1 x half> @llvm.rint.nxv1f16(<vscale x 1 x half> %x)
684  %b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i16>
685  ret <vscale x 1 x i16> %b
686}
687
688define <vscale x 1 x i16> @rint_nxv1f16_to_ui16(<vscale x 1 x half> %x) {
689; CHECK-LABEL: rint_nxv1f16_to_ui16:
690; CHECK:       # %bb.0:
691; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
692; CHECK-NEXT:    vfcvt.xu.f.v v8, v8
693; CHECK-NEXT:    ret
694  %a = call <vscale x 1 x half> @llvm.rint.nxv1f16(<vscale x 1 x half> %x)
695  %b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i16>
696  ret <vscale x 1 x i16> %b
697}
698
699define <vscale x 1 x i32> @rint_nxv1f16_to_si32(<vscale x 1 x half> %x) {
700; CHECK-LABEL: rint_nxv1f16_to_si32:
701; CHECK:       # %bb.0:
702; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
703; CHECK-NEXT:    vfwcvt.x.f.v v9, v8
704; CHECK-NEXT:    vmv1r.v v8, v9
705; CHECK-NEXT:    ret
706  %a = call <vscale x 1 x half> @llvm.rint.nxv1f16(<vscale x 1 x half> %x)
707  %b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i32>
708  ret <vscale x 1 x i32> %b
709}
710
711define <vscale x 1 x i32> @rint_nxv1f16_to_ui32(<vscale x 1 x half> %x) {
712; CHECK-LABEL: rint_nxv1f16_to_ui32:
713; CHECK:       # %bb.0:
714; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
715; CHECK-NEXT:    vfwcvt.xu.f.v v9, v8
716; CHECK-NEXT:    vmv1r.v v8, v9
717; CHECK-NEXT:    ret
718  %a = call <vscale x 1 x half> @llvm.rint.nxv1f16(<vscale x 1 x half> %x)
719  %b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i32>
720  ret <vscale x 1 x i32> %b
721}
722
723define <vscale x 1 x i64> @rint_nxv1f16_to_si64(<vscale x 1 x half> %x) {
724; CHECK-LABEL: rint_nxv1f16_to_si64:
725; CHECK:       # %bb.0:
726; CHECK-NEXT:    lui a0, %hi(.LCPI38_0)
727; CHECK-NEXT:    flh fa5, %lo(.LCPI38_0)(a0)
728; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
729; CHECK-NEXT:    vfabs.v v9, v8
730; CHECK-NEXT:    vmflt.vf v0, v9, fa5
731; CHECK-NEXT:    vfcvt.x.f.v v9, v8, v0.t
732; CHECK-NEXT:    vfcvt.f.x.v v9, v9, v0.t
733; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
734; CHECK-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
735; CHECK-NEXT:    vfwcvt.f.f.v v9, v8
736; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
737; CHECK-NEXT:    vfwcvt.rtz.x.f.v v8, v9
738; CHECK-NEXT:    ret
739; RV32-LABEL: rint_nxv1f16_to_si64:
740; RV32:       # %bb.0:
741; RV32-NEXT:    lui a0, %hi(.LCPI22_0)
742; RV32-NEXT:    flh fa5, %lo(.LCPI22_0)(a0)
743; RV32-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
744; RV32-NEXT:    vfabs.v v9, v8
745; RV32-NEXT:    vmflt.vf v0, v9, fa5
746; RV32-NEXT:    fsrmi a0, 3
747; RV32-NEXT:    vfcvt.x.f.v v9, v8, v0.t
748; RV32-NEXT:    vfcvt.f.x.v v9, v9, v0.t
749; RV32-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
750; RV32-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
751; RV32-NEXT:    vfwcvt.f.f.v v9, v8
752; RV32-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
753; RV32-NEXT:    vfwcvt.rtz.x.f.v v8, v9
754; RV32-NEXT:    fsrm a0
755; RV32-NEXT:    ret
756; RV64-LABEL: rint_nxv1f16_to_si64:
757; RV64:       # %bb.0:
758; RV64-NEXT:    lui a0, %hi(.LCPI22_0)
759; RV64-NEXT:    flh fa5, %lo(.LCPI22_0)(a0)
760; RV64-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
761; RV64-NEXT:    vfabs.v v9, v8
762; RV64-NEXT:    vmflt.vf v0, v9, fa5
763; RV64-NEXT:    fsrmi a0, 3
764; RV64-NEXT:    vfcvt.x.f.v v9, v8, v0.t
765; RV64-NEXT:    vfcvt.f.x.v v9, v9, v0.t
766; RV64-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
767; RV64-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
768; RV64-NEXT:    vfwcvt.f.f.v v9, v8
769; RV64-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
770; RV64-NEXT:    vfwcvt.rtz.x.f.v v8, v9
771; RV64-NEXT:    fsrm a0
772; RV64-NEXT:    ret
773  %a = call <vscale x 1 x half> @llvm.rint.nxv1f16(<vscale x 1 x half> %x)
774  %b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i64>
775  ret <vscale x 1 x i64> %b
776}
777
778define <vscale x 1 x i64> @rint_nxv1f16_to_ui64(<vscale x 1 x half> %x) {
779; CHECK-LABEL: rint_nxv1f16_to_ui64:
780; CHECK:       # %bb.0:
781; CHECK-NEXT:    lui a0, %hi(.LCPI39_0)
782; CHECK-NEXT:    flh fa5, %lo(.LCPI39_0)(a0)
783; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
784; CHECK-NEXT:    vfabs.v v9, v8
785; CHECK-NEXT:    vmflt.vf v0, v9, fa5
786; CHECK-NEXT:    vfcvt.x.f.v v9, v8, v0.t
787; CHECK-NEXT:    vfcvt.f.x.v v9, v9, v0.t
788; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
789; CHECK-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
790; CHECK-NEXT:    vfwcvt.f.f.v v9, v8
791; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
792; CHECK-NEXT:    vfwcvt.rtz.xu.f.v v8, v9
793; CHECK-NEXT:    ret
794; RV32-LABEL: rint_nxv1f16_to_ui64:
795; RV32:       # %bb.0:
796; RV32-NEXT:    lui a0, %hi(.LCPI23_0)
797; RV32-NEXT:    flh fa5, %lo(.LCPI23_0)(a0)
798; RV32-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
799; RV32-NEXT:    vfabs.v v9, v8
800; RV32-NEXT:    vmflt.vf v0, v9, fa5
801; RV32-NEXT:    fsrmi a0, 3
802; RV32-NEXT:    vfcvt.x.f.v v9, v8, v0.t
803; RV32-NEXT:    vfcvt.f.x.v v9, v9, v0.t
804; RV32-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
805; RV32-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
806; RV32-NEXT:    vfwcvt.f.f.v v9, v8
807; RV32-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
808; RV32-NEXT:    vfwcvt.rtz.xu.f.v v8, v9
809; RV32-NEXT:    fsrm a0
810; RV32-NEXT:    ret
811; RV64-LABEL: rint_nxv1f16_to_ui64:
812; RV64:       # %bb.0:
813; RV64-NEXT:    lui a0, %hi(.LCPI23_0)
814; RV64-NEXT:    flh fa5, %lo(.LCPI23_0)(a0)
815; RV64-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
816; RV64-NEXT:    vfabs.v v9, v8
817; RV64-NEXT:    vmflt.vf v0, v9, fa5
818; RV64-NEXT:    fsrmi a0, 3
819; RV64-NEXT:    vfcvt.x.f.v v9, v8, v0.t
820; RV64-NEXT:    vfcvt.f.x.v v9, v9, v0.t
821; RV64-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
822; RV64-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
823; RV64-NEXT:    vfwcvt.f.f.v v9, v8
824; RV64-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
825; RV64-NEXT:    vfwcvt.rtz.xu.f.v v8, v9
826; RV64-NEXT:    fsrm a0
827; RV64-NEXT:    ret
828  %a = call <vscale x 1 x half> @llvm.rint.nxv1f16(<vscale x 1 x half> %x)
829  %b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i64>
830  ret <vscale x 1 x i64> %b
831}
832
833; ================================================================================
834; rint <vscale x 4 x half>
835; ================================================================================
836
837declare <vscale x 4 x half> @llvm.rint.nxv4f16(<vscale x 4 x half>)
838
839define <vscale x 4 x i8> @rint_nxv4f16_to_si8(<vscale x 4 x half> %x) {
840; CHECK-LABEL: rint_nxv4f16_to_si8:
841; CHECK:       # %bb.0:
842; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
843; CHECK-NEXT:    vfncvt.x.f.w v9, v8
844; CHECK-NEXT:    vmv1r.v v8, v9
845; CHECK-NEXT:    ret
846  %a = call <vscale x 4 x half> @llvm.rint.nxv4f16(<vscale x 4 x half> %x)
847  %b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i8>
848  ret <vscale x 4 x i8> %b
849}
850
851define <vscale x 4 x i8> @rint_nxv4f16_to_ui8(<vscale x 4 x half> %x) {
852; CHECK-LABEL: rint_nxv4f16_to_ui8:
853; CHECK:       # %bb.0:
854; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
855; CHECK-NEXT:    vfncvt.xu.f.w v9, v8
856; CHECK-NEXT:    vmv1r.v v8, v9
857; CHECK-NEXT:    ret
858  %a = call <vscale x 4 x half> @llvm.rint.nxv4f16(<vscale x 4 x half> %x)
859  %b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i8>
860  ret <vscale x 4 x i8> %b
861}
862
863define <vscale x 4 x i16> @rint_nxv4f16_to_si16(<vscale x 4 x half> %x) {
864; CHECK-LABEL: rint_nxv4f16_to_si16:
865; CHECK:       # %bb.0:
866; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
867; CHECK-NEXT:    vfcvt.x.f.v v8, v8
868; CHECK-NEXT:    ret
869  %a = call <vscale x 4 x half> @llvm.rint.nxv4f16(<vscale x 4 x half> %x)
870  %b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i16>
871  ret <vscale x 4 x i16> %b
872}
873
874define <vscale x 4 x i16> @rint_nxv4f16_to_ui16(<vscale x 4 x half> %x) {
875; CHECK-LABEL: rint_nxv4f16_to_ui16:
876; CHECK:       # %bb.0:
877; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
878; CHECK-NEXT:    vfcvt.xu.f.v v8, v8
879; CHECK-NEXT:    ret
880  %a = call <vscale x 4 x half> @llvm.rint.nxv4f16(<vscale x 4 x half> %x)
881  %b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i16>
882  ret <vscale x 4 x i16> %b
883}
884
885define <vscale x 4 x i32> @rint_nxv4f16_to_si32(<vscale x 4 x half> %x) {
886; CHECK-LABEL: rint_nxv4f16_to_si32:
887; CHECK:       # %bb.0:
888; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
889; CHECK-NEXT:    vfwcvt.x.f.v v10, v8
890; CHECK-NEXT:    vmv2r.v v8, v10
891; CHECK-NEXT:    ret
892  %a = call <vscale x 4 x half> @llvm.rint.nxv4f16(<vscale x 4 x half> %x)
893  %b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i32>
894  ret <vscale x 4 x i32> %b
895}
896
897define <vscale x 4 x i32> @rint_nxv4f16_to_ui32(<vscale x 4 x half> %x) {
898; CHECK-LABEL: rint_nxv4f16_to_ui32:
899; CHECK:       # %bb.0:
900; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
901; CHECK-NEXT:    vfwcvt.xu.f.v v10, v8
902; CHECK-NEXT:    vmv2r.v v8, v10
903; CHECK-NEXT:    ret
904  %a = call <vscale x 4 x half> @llvm.rint.nxv4f16(<vscale x 4 x half> %x)
905  %b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i32>
906  ret <vscale x 4 x i32> %b
907}
908
909define <vscale x 4 x i64> @rint_nxv4f16_to_si64(<vscale x 4 x half> %x) {
910; CHECK-LABEL: rint_nxv4f16_to_si64:
911; CHECK:       # %bb.0:
912; CHECK-NEXT:    lui a0, %hi(.LCPI46_0)
913; CHECK-NEXT:    flh fa5, %lo(.LCPI46_0)(a0)
914; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
915; CHECK-NEXT:    vfabs.v v9, v8
916; CHECK-NEXT:    vmflt.vf v0, v9, fa5
917; CHECK-NEXT:    vfcvt.x.f.v v9, v8, v0.t
918; CHECK-NEXT:    vfcvt.f.x.v v9, v9, v0.t
919; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
920; CHECK-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
921; CHECK-NEXT:    vfwcvt.f.f.v v12, v8
922; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
923; CHECK-NEXT:    vfwcvt.rtz.x.f.v v8, v12
924; CHECK-NEXT:    ret
925; RV32-LABEL: rint_nxv4f16_to_si64:
926; RV32:       # %bb.0:
927; RV32-NEXT:    lui a0, %hi(.LCPI30_0)
928; RV32-NEXT:    flh fa5, %lo(.LCPI30_0)(a0)
929; RV32-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
930; RV32-NEXT:    vfabs.v v9, v8
931; RV32-NEXT:    vmflt.vf v0, v9, fa5
932; RV32-NEXT:    fsrmi a0, 3
933; RV32-NEXT:    vfcvt.x.f.v v9, v8, v0.t
934; RV32-NEXT:    vfcvt.f.x.v v9, v9, v0.t
935; RV32-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
936; RV32-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
937; RV32-NEXT:    vfwcvt.f.f.v v12, v8
938; RV32-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
939; RV32-NEXT:    vfwcvt.rtz.x.f.v v8, v12
940; RV32-NEXT:    fsrm a0
941; RV32-NEXT:    ret
942; RV64-LABEL: rint_nxv4f16_to_si64:
943; RV64:       # %bb.0:
944; RV64-NEXT:    lui a0, %hi(.LCPI30_0)
945; RV64-NEXT:    flh fa5, %lo(.LCPI30_0)(a0)
946; RV64-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
947; RV64-NEXT:    vfabs.v v9, v8
948; RV64-NEXT:    vmflt.vf v0, v9, fa5
949; RV64-NEXT:    fsrmi a0, 3
950; RV64-NEXT:    vfcvt.x.f.v v9, v8, v0.t
951; RV64-NEXT:    vfcvt.f.x.v v9, v9, v0.t
952; RV64-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
953; RV64-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
954; RV64-NEXT:    vfwcvt.f.f.v v12, v8
955; RV64-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
956; RV64-NEXT:    vfwcvt.rtz.x.f.v v8, v12
957; RV64-NEXT:    fsrm a0
958; RV64-NEXT:    ret
959  %a = call <vscale x 4 x half> @llvm.rint.nxv4f16(<vscale x 4 x half> %x)
960  %b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i64>
961  ret <vscale x 4 x i64> %b
962}
963
964define <vscale x 4 x i64> @rint_nxv4f16_to_ui64(<vscale x 4 x half> %x) {
965; CHECK-LABEL: rint_nxv4f16_to_ui64:
966; CHECK:       # %bb.0:
967; CHECK-NEXT:    lui a0, %hi(.LCPI47_0)
968; CHECK-NEXT:    flh fa5, %lo(.LCPI47_0)(a0)
969; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
970; CHECK-NEXT:    vfabs.v v9, v8
971; CHECK-NEXT:    vmflt.vf v0, v9, fa5
972; CHECK-NEXT:    vfcvt.x.f.v v9, v8, v0.t
973; CHECK-NEXT:    vfcvt.f.x.v v9, v9, v0.t
974; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
975; CHECK-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
976; CHECK-NEXT:    vfwcvt.f.f.v v12, v8
977; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
978; CHECK-NEXT:    vfwcvt.rtz.xu.f.v v8, v12
979; CHECK-NEXT:    ret
980; RV32-LABEL: rint_nxv4f16_to_ui64:
981; RV32:       # %bb.0:
982; RV32-NEXT:    lui a0, %hi(.LCPI31_0)
983; RV32-NEXT:    flh fa5, %lo(.LCPI31_0)(a0)
984; RV32-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
985; RV32-NEXT:    vfabs.v v9, v8
986; RV32-NEXT:    vmflt.vf v0, v9, fa5
987; RV32-NEXT:    fsrmi a0, 3
988; RV32-NEXT:    vfcvt.x.f.v v9, v8, v0.t
989; RV32-NEXT:    vfcvt.f.x.v v9, v9, v0.t
990; RV32-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
991; RV32-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
992; RV32-NEXT:    vfwcvt.f.f.v v12, v8
993; RV32-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
994; RV32-NEXT:    vfwcvt.rtz.xu.f.v v8, v12
995; RV32-NEXT:    fsrm a0
996; RV32-NEXT:    ret
997; RV64-LABEL: rint_nxv4f16_to_ui64:
998; RV64:       # %bb.0:
999; RV64-NEXT:    lui a0, %hi(.LCPI31_0)
1000; RV64-NEXT:    flh fa5, %lo(.LCPI31_0)(a0)
1001; RV64-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
1002; RV64-NEXT:    vfabs.v v9, v8
1003; RV64-NEXT:    vmflt.vf v0, v9, fa5
1004; RV64-NEXT:    fsrmi a0, 3
1005; RV64-NEXT:    vfcvt.x.f.v v9, v8, v0.t
1006; RV64-NEXT:    vfcvt.f.x.v v9, v9, v0.t
1007; RV64-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
1008; RV64-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
1009; RV64-NEXT:    vfwcvt.f.f.v v12, v8
1010; RV64-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
1011; RV64-NEXT:    vfwcvt.rtz.xu.f.v v8, v12
1012; RV64-NEXT:    fsrm a0
1013; RV64-NEXT:    ret
1014  %a = call <vscale x 4 x half> @llvm.rint.nxv4f16(<vscale x 4 x half> %x)
1015  %b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i64>
1016  ret <vscale x 4 x i64> %b
1017}
1018