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/dpdk/drivers/net/bnx2x/
H A Dbnx2x.h88 #define BRB_SIZE(sc) (CHIP_IS_E3(sc) ? 1024 : 512) argument
89 #define MAX_AGG_QS(sc) ETH_MAX_AGGREGATION_QUEUES_E1H_E2 argument
90 #define FW_DROP_LEVEL(sc) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc)) argument
176 #define NUM_BD_REQ(sc) \ argument
177 BRB_SIZE(sc)
178 #define NUM_BD_PG_REQ(sc) \ argument
179 ((NUM_BD_REQ(sc) + USABLE_RX_BD_PER_PAGE - 1) / USABLE_RX_BD_PER_PAGE)
180 #define BD_TH_LO(sc) \ argument
181 (NUM_BD_REQ(sc) + \
182 NUM_BD_PG_REQ(sc) * RX_BD_NEXT_PAGE_DESC_CNT + \
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H A Dbnx2x_vfpf.c23 bnx2x_check_bull(struct bnx2x_softc *sc) in bnx2x_check_bull() argument
27 uint16_t old_version = sc->old_bulletin.version; in bnx2x_check_bull()
30 bull = sc->pf2vf_bulletin; in bnx2x_check_bull()
36 bull = sc->pf2vf_bulletin; in bnx2x_check_bull()
40 PMD_DRV_LOG(ERR, sc, "bad crc on bulletin board. contained %x computed %x", in bnx2x_check_bull()
45 PMD_DRV_LOG(ERR, sc, "pf to vf bulletin board crc was wrong %d consecutive times. Aborting", in bnx2x_check_bull()
54 if (valid_bitmap & (1 << MAC_ADDR_VALID) && memcmp(bull->mac, sc->old_bulletin.mac, ETH_ALEN)) in bnx2x_check_bull()
55 memcpy(&sc->link_params.mac_addr, bull->mac, ETH_ALEN); in bnx2x_check_bull()
57 memcpy(&bull->vlan, &sc->old_bulletin.vlan, sizeof(bull->vlan)); in bnx2x_check_bull()
59 sc->old_bulletin = *bull; in bnx2x_check_bull()
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H A Dbnx2x_ethdev.c87 struct bnx2x_softc *sc = dev->data->dev_private; in bnx2x_link_update() local
90 PMD_INIT_FUNC_TRACE(sc); in bnx2x_link_update()
94 link.link_speed = sc->link_vars.line_speed; in bnx2x_link_update()
95 switch (sc->link_vars.duplex) { in bnx2x_link_update()
105 link.link_status = sc->link_vars.link_up; in bnx2x_link_update()
113 struct bnx2x_softc *sc = dev->data->dev_private; in bnx2x_interrupt_action() local
116 bnx2x_intr_legacy(sc); in bnx2x_interrupt_action()
118 if ((atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_GO) && in bnx2x_interrupt_action()
120 bnx2x_periodic_callout(sc); in bnx2x_interrupt_action()
121 link_status = REG_RD(sc, sc->link_params.shmem_base + in bnx2x_interrupt_action()
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H A Decore_init_ops.h17 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t *zbuf, int len);
18 static void ecore_write_dmae_phys_len(struct bnx2x_softc *sc,
22 static void ecore_init_str_wr(struct bnx2x_softc *sc, uint32_t addr, in ecore_init_str_wr() argument
28 REG_WR(sc, addr + i*4, data[i]); in ecore_init_str_wr()
31 static void ecore_write_big_buf(struct bnx2x_softc *sc, uint32_t addr, in ecore_write_big_buf() argument
34 if (DMAE_READY(sc)) in ecore_write_big_buf()
35 ecore_write_dmae_phys_len(sc, GUNZIP_PHYS(sc), addr, len); in ecore_write_big_buf()
39 ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len); in ecore_write_big_buf()
42 static void ecore_init_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, in ecore_init_fill() argument
49 ECORE_MEMSET(GUNZIP_BUF(sc), (uint8_t)fill, buf_len); in ecore_init_fill()
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H A Delink.c937 static uint32_t elink_bits_en(struct bnx2x_softc *sc, uint32_t reg, uint32_t bits) in elink_bits_en() argument
939 uint32_t val = REG_RD(sc, reg); in elink_bits_en()
942 REG_WR(sc, reg, val); in elink_bits_en()
946 static uint32_t elink_bits_dis(struct bnx2x_softc *sc, uint32_t reg, in elink_bits_dis() argument
949 uint32_t val = REG_RD(sc, reg); in elink_bits_dis()
952 REG_WR(sc, reg, val); in elink_bits_dis()
969 struct bnx2x_softc *sc = params->sc; in elink_check_lfa() local
972 REG_RD(sc, params->lfa_base + in elink_check_lfa()
979 ELINK_DEBUG_P0(sc, "No LFA due to DCC flap after clp exit"); in elink_check_lfa()
980 REG_WR(sc, params->lfa_base + in elink_check_lfa()
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H A Decore_sp.c31 ecore_exe_queue_init(struct bnx2x_softc *sc __rte_unused, in ecore_exe_queue_init()
44 ECORE_SPIN_LOCK_INIT(&o->lock, sc); in ecore_exe_queue_init()
56 ECORE_MSG(sc, "Setup the execution queue with the chunk length of %d", in ecore_exe_queue_init()
60 static void ecore_exe_queue_free_elem(struct bnx2x_softc *sc __rte_unused, in ecore_exe_queue_free_elem()
63 ECORE_MSG(sc, "Deleting an exe_queue element"); in ecore_exe_queue_free_elem()
64 ECORE_FREE(sc, elem, sizeof(*elem)); in ecore_exe_queue_free_elem()
92 static int ecore_exe_queue_add(struct bnx2x_softc *sc, in ecore_exe_queue_add() argument
102 rc = o->optimize(sc, o->owner, elem); in ecore_exe_queue_add()
107 rc = o->validate(sc, o->owner, elem); in ecore_exe_queue_add()
109 ECORE_MSG(sc, "Preamble failed: %d", rc); in ecore_exe_queue_add()
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H A Decore_init.h207 static inline void ecore_map_q_cos(struct bnx2x_softc *sc, uint32_t q_num, uint32_t new_cos) in ecore_map_q_cos() argument
210 uint32_t curr_cos = REG_RD(sc, QM_REG_QVOQIDX_0 + q_num * 4); in ecore_map_q_cos()
218 if (INIT_MODE_FLAGS(sc) & MODE_PORT4) { in ecore_map_q_cos()
220 if (SC_PORT(sc)) { in ecore_map_q_cos()
229 ECORE_PF_Q_NUM(q_num, SC_PORT(sc), vnic); in ecore_map_q_cos()
233 REG_WR(sc, ECORE_Q_VOQ_REG_ADDR(pf_q_num), new_cos); in ecore_map_q_cos()
237 reg_bit_map = REG_RD(sc, reg_addr); in ecore_map_q_cos()
238 REG_WR(sc, reg_addr, reg_bit_map & (~q_bit_map)); in ecore_map_q_cos()
242 reg_bit_map = REG_RD(sc, reg_addr); in ecore_map_q_cos()
243 REG_WR(sc, reg_addr, reg_bit_map | q_bit_map); in ecore_map_q_cos()
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H A Delink.h30 extern uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr);
31 extern void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val);
33 extern void elink_cb_reg_wb_write(struct bnx2x_softc *sc, uint32_t offset,
35 extern void elink_cb_reg_wb_read(struct bnx2x_softc *sc, uint32_t offset,
39 extern uint8_t elink_cb_gpio_write(struct bnx2x_softc *sc,
42 extern uint8_t elink_cb_gpio_mult_write(struct bnx2x_softc *sc,
46 extern uint32_t elink_cb_gpio_read(struct bnx2x_softc *sc, uint16_t gpio_num, uint8_t port);
47 extern uint8_t elink_cb_gpio_int_write(struct bnx2x_softc *sc,
51 extern uint32_t elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param);
54 extern void elink_cb_udelay(struct bnx2x_softc *sc, uint32_t microsecond);
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H A Decore_sp.h48 #define ECORE_MC_HASH_OFFSET(sc, i) \ argument
50 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(FUNC_ID(sc)) + i*4)
55 #define IRO sc->iro_array
113 #define ECORE_FCOE_CID(sc) ((sc)->fp[FCOE_IDX(sc)].cl_id) argument
137 #define SC_ILT(sc) ((sc)->ilt) argument
144 if (bnx2x_dma_alloc((struct bnx2x_softc *)sc, \
221 #define ECORE_MSG(sc, m, ...) \ argument
222 PMD_DRV_LOG(DEBUG, sc, m, ##__VA_ARGS__)
494 int (*wait_comp)(struct bnx2x_softc *sc,
577 typedef int (*exe_q_validate)(struct bnx2x_softc *sc,
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H A Dbnx2x_rxtx.c57 struct bnx2x_softc *sc = dev->data->dev_private; in bnx2x_dev_rx_queue_setup() local
58 struct bnx2x_fastpath *fp = &sc->fp[queue_idx]; in bnx2x_dev_rx_queue_setup()
67 PMD_DRV_LOG(ERR, sc, "rte_zmalloc for rxq failed!"); in bnx2x_dev_rx_queue_setup()
70 rxq->sc = sc; in bnx2x_dev_rx_queue_setup()
80 sc->rx_ring_size = USABLE_RX_BD(rxq); in bnx2x_dev_rx_queue_setup()
83 PMD_DRV_LOG(DEBUG, sc, "fp[%02d] req_bd=%u, usable_bd=%lu, " in bnx2x_dev_rx_queue_setup()
158 if (!sc->rx_queues) sc->rx_queues = dev->data->rx_queues; in bnx2x_dev_rx_queue_setup()
192 struct bnx2x_softc *sc; in bnx2x_xmit_pkts() local
199 sc = txq->sc; in bnx2x_xmit_pkts()
200 fp = &sc->fp[txq->queue_id]; in bnx2x_xmit_pkts()
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H A Dbnx2x_vfpf.h329 int bnx2x_vf_teardown_queue(struct bnx2x_softc *sc, int qid);
330 int bnx2x_vf_set_mac(struct bnx2x_softc *sc, int set);
331 int bnx2x_vf_config_rss(struct bnx2x_softc *sc, struct ecore_config_rss_params *params);
332 int bnx2x_vfpf_set_mcast(struct bnx2x_softc *sc,
H A Dbnx2x_rxtx.h42 struct bnx2x_softc *sc; /**< Ptr to dev_private data. */ member
63 struct bnx2x_softc *sc; /**< Ptr to dev_private data */ member
H A Dbnx2x_stats.h604 void bnx2x_stats_init(struct bnx2x_softc *sc);
605 void bnx2x_stats_handle(struct bnx2x_softc *sc, enum bnx2x_stats_event event);
606 void bnx2x_save_statistics(struct bnx2x_softc *sc);
607 void bnx2x_memset_stats(struct bnx2x_softc *sc);
/dpdk/kernel/freebsd/nic_uio/
H A Dnic_uio.c108 struct nic_uio_softc *sc = cdev->si_drv1; in nic_uio_mmap_single() local
113 if (sc->bar_res[bar] == NULL) { in nic_uio_mmap_single()
114 sc->bar_id[bar] = PCIR_BAR(bar); in nic_uio_mmap_single()
116 if (PCI_BAR_IO(pci_read_config(sc->dev_t, sc->bar_id[bar], 4))) in nic_uio_mmap_single()
117 sc->bar_res[bar] = bus_alloc_resource_any(sc->dev_t, SYS_RES_IOPORT, in nic_uio_mmap_single()
118 &sc->bar_id[bar], RF_ACTIVE); in nic_uio_mmap_single()
120 sc->bar_res[bar] = bus_alloc_resource_any(sc->dev_t, SYS_RES_MEMORY, in nic_uio_mmap_single()
121 &sc->bar_id[bar], RF_ACTIVE); in nic_uio_mmap_single()
123 if (sc->bar_res[bar] == NULL) in nic_uio_mmap_single()
126 sc->bar_start[bar] = rman_get_start(sc->bar_res[bar]); in nic_uio_mmap_single()
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/dpdk/lib/bpf/
H A Dbpf_load_elf.c137 Elf_Scn *sc; in find_elf_code() local
156 for (sc = elf_nextscn(elf, NULL); sc != NULL; in find_elf_code()
157 sc = elf_nextscn(elf, sc)) { in find_elf_code()
158 sh = elf64_getshdr(sc); in find_elf_code()
166 sd = elf_getdata(sc, NULL); in find_elf_code()
176 *pidx = elf_ndxscn(sc); in find_elf_code()
192 Elf_Scn *sc; in process_reloc() local
199 sc = elf_getscn(elf, sym_idx); in process_reloc()
200 sd = elf_getdata(sc, NULL); in process_reloc()
238 Elf_Scn *sc; in elf_reloc_code() local
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/dpdk/drivers/net/softnic/
H A Drte_eth_softnic_thread.c100 if (softnic->params.sc && rte_lcore_has_role(thread_id, ROLE_SERVICE)) in thread_is_valid()
102 if (!softnic->params.sc && rte_lcore_has_role(thread_id, ROLE_RTE)) in thread_is_valid()
201 if (softnic->params.sc && td->n_pipelines) in softnic_thread_pipeline_disable_all()
297 if (softnic->params.sc && (n_pipelines == 0)) { in softnic_thread_pipeline_enable()
384 if (softnic->params.sc && (td->n_pipelines == 0)) in softnic_thread_pipeline_disable()
415 if (softnic->params.sc && (n_pipelines == 0)) in softnic_thread_pipeline_disable()
H A Drte_eth_softnic_internals.h37 int sc; /**< Service cores. */ member
/dpdk/drivers/net/cxgbe/
H A Dcxgbe_filter.c218 struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1); in mk_set_tcb_field_ulp() local
223 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM)); in mk_set_tcb_field_ulp()
224 sc->len = cpu_to_be32(sizeof(*req) - sizeof(struct work_request_hdr)); in mk_set_tcb_field_ulp()
231 sc = (struct ulptx_idata *)(req + 1); in mk_set_tcb_field_ulp()
232 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP)); in mk_set_tcb_field_ulp()
233 sc->len = cpu_to_be32(0); in mk_set_tcb_field_ulp()
370 struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1); in mk_abort_req_ulp() local
375 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM)); in mk_abort_req_ulp()
376 sc->len = cpu_to_be32(sizeof(*abort_req) - in mk_abort_req_ulp()
382 sc = (struct ulptx_idata *)(abort_req + 1); in mk_abort_req_ulp()
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/dpdk/drivers/net/mlx5/
H A Dmlx5_tx_nompw.c42 MLX5_TXOFF_DECL(sc,
/dpdk/doc/guides/bbdevs/
H A Dturbo_sw.rst102 …ICX is available `here <https://docs.o-ran-sc.org/projects/o-ran-sc-o-du-phy/en/latest/build_prere…
/dpdk/app/test/
H A Dtest_dmadev.c139 enum rte_dma_status_code sc[32]; in do_multi_copies() local
189 int n = rte_dma_completed_status(dev_id, vchan, RTE_DIM(srcs), NULL, sc); in do_multi_copies()
195 if (sc[j] != RTE_DMA_STATUS_SUCCESSFUL) in do_multi_copies()
197 j, sc[j]); in do_multi_copies()
203 rte_dma_completed_status(dev_id, vchan, RTE_DIM(srcs), NULL, sc) : in do_multi_copies()
H A Dtest_rcu_qsbr.c816 uint64_t sc = 200; in test_rcu_qsbr_dq_functional() local
862 e[j] = sc++; in test_rcu_qsbr_dq_functional()
881 e[j] = sc++; in test_rcu_qsbr_dq_functional()
901 e[j] = sc++; in test_rcu_qsbr_dq_functional()