1688654bfSRasesh Mody /* SPDX-License-Identifier: BSD-3-Clause 2540a2110SStephen Hemminger * Copyright (c) 2013-2015 Brocade Communications Systems, Inc. 3e3de5dadSRasesh Mody * Copyright (c) 2015-2018 Cavium Inc. 4540a2110SStephen Hemminger * All rights reserved. 5e3de5dadSRasesh Mody * www.cavium.com 6540a2110SStephen Hemminger */ 7540a2110SStephen Hemminger 8540a2110SStephen Hemminger #ifndef _BNX2X_RXTX_H_ 9540a2110SStephen Hemminger #define _BNX2X_RXTX_H_ 10540a2110SStephen Hemminger 11f0785651SChas Williams #define DEFAULT_TX_FREE_THRESH 64 12540a2110SStephen Hemminger #define RTE_PMD_BNX2X_TX_MAX_BURST 1 13540a2110SStephen Hemminger 14540a2110SStephen Hemminger /** 15540a2110SStephen Hemminger * Structure associated with each descriptor of the RX ring of a RX queue. 16540a2110SStephen Hemminger */ 17540a2110SStephen Hemminger struct bnx2x_rx_entry { 18540a2110SStephen Hemminger struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */ 19540a2110SStephen Hemminger }; 20540a2110SStephen Hemminger 21540a2110SStephen Hemminger /** 22540a2110SStephen Hemminger * Structure associated with each RX queue. 23540a2110SStephen Hemminger */ 24540a2110SStephen Hemminger struct bnx2x_rx_queue { 25540a2110SStephen Hemminger struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */ 26540a2110SStephen Hemminger union eth_rx_cqe *cq_ring; /**< RCQ ring virtual address. */ 27540a2110SStephen Hemminger uint64_t cq_ring_phys_addr; /**< RCQ ring DMA address. */ 28540a2110SStephen Hemminger uint64_t *rx_ring; /**< RX ring virtual address. */ 29540a2110SStephen Hemminger uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */ 30540a2110SStephen Hemminger struct rte_mbuf **sw_ring; /**< address of RX software ring. */ 31540a2110SStephen Hemminger struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */ 32540a2110SStephen Hemminger struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */ 33540a2110SStephen Hemminger uint16_t nb_cq_pages; /**< number of RCQ pages. */ 34540a2110SStephen Hemminger uint16_t nb_rx_desc; /**< number of RX descriptors. */ 35540a2110SStephen Hemminger uint16_t nb_rx_pages; /**< number of RX pages. */ 36540a2110SStephen Hemminger uint16_t rx_bd_head; /**< Index of current rx bd. */ 37540a2110SStephen Hemminger uint16_t rx_bd_tail; /**< Index of last rx bd. */ 38540a2110SStephen Hemminger uint16_t rx_cq_head; /**< Index of current rcq bd. */ 39540a2110SStephen Hemminger uint16_t rx_cq_tail; /**< Index of last rcq bd. */ 40540a2110SStephen Hemminger uint16_t queue_id; /**< RX queue index. */ 41f8244c63SZhiyong Yang uint16_t port_id; /**< Device port identifier. */ 42540a2110SStephen Hemminger struct bnx2x_softc *sc; /**< Ptr to dev_private data. */ 43540a2110SStephen Hemminger }; 44540a2110SStephen Hemminger 45540a2110SStephen Hemminger /** 46540a2110SStephen Hemminger * Structure associated with each TX queue. 47540a2110SStephen Hemminger */ 48540a2110SStephen Hemminger struct bnx2x_tx_queue { 49540a2110SStephen Hemminger /** TX ring virtual address. */ 50540a2110SStephen Hemminger union eth_tx_bd_types *tx_ring; /**< TX ring virtual address. */ 51540a2110SStephen Hemminger uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */ 52540a2110SStephen Hemminger struct rte_mbuf **sw_ring; /**< virtual address of SW ring. */ 53540a2110SStephen Hemminger uint16_t tx_pkt_tail; /**< Index of current tx pkt. */ 54540a2110SStephen Hemminger uint16_t tx_pkt_head; /**< Index of last pkt counted by txeof. */ 55540a2110SStephen Hemminger uint16_t tx_bd_tail; /**< Index of current tx bd. */ 56540a2110SStephen Hemminger uint16_t tx_bd_head; /**< Index of last bd counted by txeof. */ 57540a2110SStephen Hemminger uint16_t nb_tx_desc; /**< number of TX descriptors. */ 58540a2110SStephen Hemminger uint16_t tx_free_thresh; /**< minimum TX before freeing. */ 59540a2110SStephen Hemminger uint16_t nb_tx_avail; /**< Number of TX descriptors available. */ 60540a2110SStephen Hemminger uint16_t nb_tx_pages; /**< number of TX pages */ 61540a2110SStephen Hemminger uint16_t queue_id; /**< TX queue index. */ 62f8244c63SZhiyong Yang uint16_t port_id; /**< Device port identifier. */ 63540a2110SStephen Hemminger struct bnx2x_softc *sc; /**< Ptr to dev_private data */ 64540a2110SStephen Hemminger }; 65540a2110SStephen Hemminger 66540a2110SStephen Hemminger int bnx2x_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, 67540a2110SStephen Hemminger uint16_t nb_rx_desc, unsigned int socket_id, 68540a2110SStephen Hemminger const struct rte_eth_rxconf *rx_conf, 69540a2110SStephen Hemminger struct rte_mempool *mb_pool); 70540a2110SStephen Hemminger 71540a2110SStephen Hemminger int bnx2x_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, 72540a2110SStephen Hemminger uint16_t nb_tx_desc, unsigned int socket_id, 73540a2110SStephen Hemminger const struct rte_eth_txconf *tx_conf); 74540a2110SStephen Hemminger 75*7483341aSXueming Li void bnx2x_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t queue_idx); 76*7483341aSXueming Li void bnx2x_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t queue_idx); 77e166e0dbSShahed Shaikh void bnx2x_dev_rxtx_init(struct rte_eth_dev *dev); 78e166e0dbSShahed Shaikh void bnx2x_dev_rxtx_init_dummy(struct rte_eth_dev *dev); 79540a2110SStephen Hemminger void bnx2x_dev_clear_queues(struct rte_eth_dev *dev); 80540a2110SStephen Hemminger 81540a2110SStephen Hemminger #endif /* _BNX2X_RXTX_H_ */ 82