1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2007-2013 Broadcom Corporation. 3 * 4 * Eric Davis <edavis@broadcom.com> 5 * David Christensen <davidch@broadcom.com> 6 * Gary Zambrano <zambrano@broadcom.com> 7 * 8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc. 9 * Copyright (c) 2015-2018 Cavium Inc. 10 * All rights reserved. 11 * www.cavium.com 12 */ 13 14 #ifndef ELINK_H 15 #define ELINK_H 16 17 #include "bnx2x_logs.h" 18 19 20 21 22 23 24 /***********************************************************/ 25 /* CLC Call backs functions */ 26 /***********************************************************/ 27 /* CLC device structure */ 28 struct bnx2x_softc; 29 30 extern uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr); 31 extern void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val); 32 /* wb_write - pointer to 2 32 bits vars to be passed to the DMAE*/ 33 extern void elink_cb_reg_wb_write(struct bnx2x_softc *sc, uint32_t offset, 34 uint32_t *wb_write, uint16_t len); 35 extern void elink_cb_reg_wb_read(struct bnx2x_softc *sc, uint32_t offset, 36 uint32_t *wb_write, uint16_t len); 37 38 /* mode - 0( LOW ) /1(HIGH)*/ 39 extern uint8_t elink_cb_gpio_write(struct bnx2x_softc *sc, 40 uint16_t gpio_num, 41 uint8_t mode, uint8_t port); 42 extern uint8_t elink_cb_gpio_mult_write(struct bnx2x_softc *sc, 43 uint8_t pins, 44 uint8_t mode); 45 46 extern uint32_t elink_cb_gpio_read(struct bnx2x_softc *sc, uint16_t gpio_num, uint8_t port); 47 extern uint8_t elink_cb_gpio_int_write(struct bnx2x_softc *sc, 48 uint16_t gpio_num, 49 uint8_t mode, uint8_t port); 50 51 extern uint32_t elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param); 52 53 /* Delay */ 54 extern void elink_cb_udelay(struct bnx2x_softc *sc, uint32_t microsecond); 55 56 /* This function is called every 1024 bytes downloading of phy firmware. 57 Driver can use it to print to screen indication for download progress */ 58 extern void elink_cb_download_progress(struct bnx2x_softc *sc, uint32_t cur, uint32_t total); 59 60 /* Each log type has its own parameters */ 61 typedef enum elink_log_id { 62 ELINK_LOG_ID_UNQUAL_IO_MODULE = 0, /* uint8_t port, const char* vendor_name, const char* vendor_pn */ 63 ELINK_LOG_ID_OVER_CURRENT = 1, /* uint8_t port */ 64 ELINK_LOG_ID_PHY_UNINITIALIZED = 2, /* uint8_t port */ 65 ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT= 3, /* No params */ 66 ELINK_LOG_ID_NON_10G_MODULE = 4, /* uint8_t port */ 67 }elink_log_id_t; 68 69 typedef enum elink_status { 70 ELINK_STATUS_OK = 0, 71 ELINK_STATUS_ERROR, 72 ELINK_STATUS_TIMEOUT, 73 ELINK_STATUS_NO_LINK, 74 ELINK_STATUS_INVALID_IMAGE, 75 ELINK_OP_NOT_SUPPORTED = 122 76 } elink_status_t; 77 extern void elink_cb_event_log(struct bnx2x_softc *sc, const elink_log_id_t log_id, ...); 78 extern void elink_cb_load_warpcore_microcode(void); 79 80 extern uint8_t elink_cb_path_id(struct bnx2x_softc *sc); 81 82 extern void elink_cb_notify_link_changed(struct bnx2x_softc *sc); 83 84 #define ELINK_EVENT_LOG_LEVEL_ERROR 1 85 #define ELINK_EVENT_LOG_LEVEL_WARNING 2 86 #define ELINK_EVENT_ID_SFP_UNQUALIFIED_MODULE 1 87 #define ELINK_EVENT_ID_SFP_POWER_FAULT 2 88 89 #define ARRAY_SIZE(x) RTE_DIM(x) 90 /* Debug prints */ 91 #ifdef ELINK_DEBUG 92 93 extern void elink_cb_dbg(struct bnx2x_softc *sc, const char *fmt); 94 extern void elink_cb_dbg1(struct bnx2x_softc *sc, const char *fmt, 95 uint32_t arg1); 96 extern void elink_cb_dbg2(struct bnx2x_softc *sc, const char *fmt, 97 uint32_t arg1, uint32_t arg2); 98 extern void elink_cb_dbg3(struct bnx2x_softc *sc, const char *fmt, 99 uint32_t arg1, uint32_t arg2, 100 uint32_t arg3); 101 102 #define ELINK_DEBUG_P0(sc, fmt) elink_cb_dbg(sc, fmt) 103 #define ELINK_DEBUG_P1(sc, fmt, arg1) elink_cb_dbg1(sc, fmt, arg1) 104 #define ELINK_DEBUG_P2(sc, fmt, arg1, arg2) \ 105 elink_cb_dbg2(sc, fmt, arg1, arg2) 106 #define ELINK_DEBUG_P3(sc, fmt, arg1, arg2, arg3) \ 107 elink_cb_dbg3(sc, fmt, arg1, arg2, arg3) 108 #else 109 #define ELINK_DEBUG_P0(sc, fmt) PMD_DRV_LOG(DEBUG, sc, fmt) 110 #define ELINK_DEBUG_P1(sc, fmt, arg1) \ 111 PMD_DRV_LOG(DEBUG, sc, fmt, arg1) 112 #define ELINK_DEBUG_P2(sc, fmt, arg1, arg2) \ 113 PMD_DRV_LOG(DEBUG, sc, fmt, arg1, arg2) 114 #define ELINK_DEBUG_P3(sc, fmt, arg1, arg2, arg3) \ 115 PMD_DRV_LOG(DEBUG, sc, fmt, arg1, arg2, arg3) 116 #endif 117 118 /***********************************************************/ 119 /* Defines */ 120 /***********************************************************/ 121 #define ELINK_DEFAULT_PHY_DEV_ADDR 3 122 #define ELINK_E2_DEFAULT_PHY_DEV_ADDR 5 123 124 125 #define DUPLEX_FULL 1 126 #define DUPLEX_HALF 2 127 128 #define ELINK_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO 129 #define ELINK_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX 130 #define ELINK_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX 131 #define ELINK_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH 132 #define ELINK_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE 133 134 #define ELINK_NET_SERDES_IF_XFI 1 135 #define ELINK_NET_SERDES_IF_SFI 2 136 #define ELINK_NET_SERDES_IF_KR 3 137 #define ELINK_NET_SERDES_IF_DXGXS 4 138 139 #define ELINK_SPEED_AUTO_NEG 0 140 #define ELINK_SPEED_10 10 141 #define ELINK_SPEED_100 100 142 #define ELINK_SPEED_1000 1000 143 #define ELINK_SPEED_2500 2500 144 #define ELINK_SPEED_10000 10000 145 #define ELINK_SPEED_20000 20000 146 147 #define ELINK_I2C_DEV_ADDR_A0 0xa0 148 #define ELINK_I2C_DEV_ADDR_A2 0xa2 149 150 #define ELINK_SFP_EEPROM_PAGE_SIZE 16 151 #define ELINK_SFP_EEPROM_VENDOR_NAME_ADDR 0x14 152 #define ELINK_SFP_EEPROM_VENDOR_NAME_SIZE 16 153 #define ELINK_SFP_EEPROM_VENDOR_OUI_ADDR 0x25 154 #define ELINK_SFP_EEPROM_VENDOR_OUI_SIZE 3 155 #define ELINK_SFP_EEPROM_PART_NO_ADDR 0x28 156 #define ELINK_SFP_EEPROM_PART_NO_SIZE 16 157 #define ELINK_SFP_EEPROM_REVISION_ADDR 0x38 158 #define ELINK_SFP_EEPROM_REVISION_SIZE 4 159 #define ELINK_SFP_EEPROM_SERIAL_ADDR 0x44 160 #define ELINK_SFP_EEPROM_SERIAL_SIZE 16 161 #define ELINK_SFP_EEPROM_DATE_ADDR 0x54 /* ASCII YYMMDD */ 162 #define ELINK_SFP_EEPROM_DATE_SIZE 6 163 #define ELINK_SFP_EEPROM_DIAG_TYPE_ADDR 0x5c 164 #define ELINK_SFP_EEPROM_DIAG_TYPE_SIZE 1 165 #define ELINK_SFP_EEPROM_DIAG_ADDR_CHANGE_REQ (1 << 2) 166 #define ELINK_SFP_EEPROM_SFF_8472_COMP_ADDR 0x5e 167 #define ELINK_SFP_EEPROM_SFF_8472_COMP_SIZE 1 168 #define ELINK_SFP_EEPROM_VENDOR_SPECIFIC_ADDR 0x60 169 #define ELINK_SFP_EEPROM_VENDOR_SPECIFIC_SIZE 16 170 171 172 #define ELINK_SFP_EEPROM_A2_CHECKSUM_RANGE 0x5e 173 #define ELINK_SFP_EEPROM_A2_CC_DMI_ADDR 0x5f 174 175 #define ELINK_PWR_FLT_ERR_MSG_LEN 250 176 177 #define ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config) \ 178 ((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) 179 #define ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config) \ 180 (((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \ 181 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT) 182 #define ELINK_SERDES_EXT_PHY_TYPE(ext_phy_config) \ 183 ((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK) 184 185 /* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */ 186 #define ELINK_SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1) 187 /* Single Media board contains single external phy */ 188 #define ELINK_SINGLE_MEDIA(params) (params->num_phys == 2) 189 /* Dual Media board contains two external phy with different media */ 190 #define ELINK_DUAL_MEDIA(params) (params->num_phys == 3) 191 192 #define ELINK_FW_PARAM_PHY_ADDR_MASK 0x000000FF 193 #define ELINK_FW_PARAM_PHY_TYPE_MASK 0x0000FF00 194 #define ELINK_FW_PARAM_MDIO_CTRL_MASK 0xFFFF0000 195 #define ELINK_FW_PARAM_MDIO_CTRL_OFFSET 16 196 #define ELINK_FW_PARAM_PHY_ADDR(fw_param) (fw_param & \ 197 ELINK_FW_PARAM_PHY_ADDR_MASK) 198 #define ELINK_FW_PARAM_PHY_TYPE(fw_param) (fw_param & \ 199 ELINK_FW_PARAM_PHY_TYPE_MASK) 200 #define ELINK_FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \ 201 ELINK_FW_PARAM_MDIO_CTRL_MASK) >> \ 202 ELINK_FW_PARAM_MDIO_CTRL_OFFSET) 203 #define ELINK_FW_PARAM_SET(phy_addr, phy_type, mdio_access) \ 204 (phy_addr | phy_type | mdio_access << ELINK_FW_PARAM_MDIO_CTRL_OFFSET) 205 206 207 #define ELINK_PFC_BRB_FULL_LB_XOFF_THRESHOLD 170 208 #define ELINK_PFC_BRB_FULL_LB_XON_THRESHOLD 250 209 210 #define ELINK_MAXVAL(a, b) (((a) > (b)) ? (a) : (b)) 211 212 #define ELINK_BMAC_CONTROL_RX_ENABLE 2 213 /***********************************************************/ 214 /* Structs */ 215 /***********************************************************/ 216 #define ELINK_INT_PHY 0 217 #define ELINK_EXT_PHY1 1 218 #define ELINK_EXT_PHY2 2 219 #define ELINK_MAX_PHYS 3 220 221 /* Same configuration is shared between the XGXS and the first external phy */ 222 #define ELINK_LINK_CONFIG_SIZE (ELINK_MAX_PHYS - 1) 223 #define ELINK_LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == ELINK_INT_PHY) ? \ 224 0 : (_phy_idx - 1)) 225 /***********************************************************/ 226 /* elink_phy struct */ 227 /* Defines the required arguments and function per phy */ 228 /***********************************************************/ 229 struct elink_vars; 230 struct elink_params; 231 struct elink_phy; 232 233 typedef uint8_t (*config_init_t)(struct elink_phy *phy, struct elink_params *params, 234 struct elink_vars *vars); 235 typedef uint8_t (*read_status_t)(struct elink_phy *phy, struct elink_params *params, 236 struct elink_vars *vars); 237 typedef void (*link_reset_t)(struct elink_phy *phy, 238 struct elink_params *params); 239 typedef void (*config_loopback_t)(struct elink_phy *phy, 240 struct elink_params *params); 241 typedef elink_status_t (*format_fw_ver_t)(uint32_t raw, uint8_t *str, uint16_t *len); 242 typedef void (*hw_reset_t)(struct elink_phy *phy, struct elink_params *params); 243 typedef void (*set_link_led_t)(struct elink_phy *phy, 244 struct elink_params *params, uint8_t mode); 245 typedef void (*phy_specific_func_t)(struct elink_phy *phy, 246 struct elink_params *params, uint32_t action); 247 struct elink_reg_set { 248 uint8_t devad; 249 uint16_t reg; 250 uint16_t val; 251 }; 252 253 struct elink_phy { 254 uint32_t type; 255 256 /* Loaded during init */ 257 uint8_t addr; 258 uint8_t def_md_devad; 259 uint16_t flags; 260 /* No Over-Current detection */ 261 #define ELINK_FLAGS_NOC (1 << 1) 262 /* Fan failure detection required */ 263 #define ELINK_FLAGS_FAN_FAILURE_DET_REQ (1 << 2) 264 /* Initialize first the XGXS and only then the phy itself */ 265 #define ELINK_FLAGS_INIT_XGXS_FIRST (1 << 3) 266 #define ELINK_FLAGS_WC_DUAL_MODE (1 << 4) 267 #define ELINK_FLAGS_4_PORT_MODE (1 << 5) 268 #define ELINK_FLAGS_REARM_LATCH_SIGNAL (1 << 6) 269 #define ELINK_FLAGS_SFP_NOT_APPROVED (1 << 7) 270 #define ELINK_FLAGS_MDC_MDIO_WA (1 << 8) 271 #define ELINK_FLAGS_DUMMY_READ (1 << 9) 272 #define ELINK_FLAGS_MDC_MDIO_WA_B0 (1 << 10) 273 #define ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC (1 << 11) 274 #define ELINK_FLAGS_TX_ERROR_CHECK (1 << 12) 275 #define ELINK_FLAGS_EEE (1 << 13) 276 #define ELINK_FLAGS_TEMPERATURE (1 << 14) 277 #define ELINK_FLAGS_MDC_MDIO_WA_G (1 << 15) 278 279 /* preemphasis values for the rx side */ 280 uint16_t rx_preemphasis[4]; 281 282 /* preemphasis values for the tx side */ 283 uint16_t tx_preemphasis[4]; 284 285 /* EMAC address for access MDIO */ 286 uint32_t mdio_ctrl; 287 288 uint32_t supported; 289 #define ELINK_SUPPORTED_10baseT_Half (1 << 0) 290 #define ELINK_SUPPORTED_10baseT_Full (1 << 1) 291 #define ELINK_SUPPORTED_100baseT_Half (1 << 2) 292 #define ELINK_SUPPORTED_100baseT_Full (1 << 3) 293 #define ELINK_SUPPORTED_1000baseT_Full (1 << 4) 294 #define ELINK_SUPPORTED_2500baseX_Full (1 << 5) 295 #define ELINK_SUPPORTED_10000baseT_Full (1 << 6) 296 #define ELINK_SUPPORTED_TP (1 << 7) 297 #define ELINK_SUPPORTED_FIBRE (1 << 8) 298 #define ELINK_SUPPORTED_Autoneg (1 << 9) 299 #define ELINK_SUPPORTED_Pause (1 << 10) 300 #define ELINK_SUPPORTED_Asym_Pause (1 << 11) 301 #define ELINK_SUPPORTED_1000baseKX_Full (1 << 17) 302 #define ELINK_SUPPORTED_10000baseKR_Full (1 << 19) 303 #define ELINK_SUPPORTED_20000baseMLD2_Full (1 << 21) 304 #define ELINK_SUPPORTED_20000baseKR2_Full (1 << 22) 305 306 uint32_t media_type; 307 #define ELINK_ETH_PHY_UNSPECIFIED 0x0 308 #define ELINK_ETH_PHY_SFPP_10G_FIBER 0x1 309 #define ELINK_ETH_PHY_XFP_FIBER 0x2 310 #define ELINK_ETH_PHY_DA_TWINAX 0x3 311 #define ELINK_ETH_PHY_BASE_T 0x4 312 #define ELINK_ETH_PHY_SFP_1G_FIBER 0x5 313 #define ELINK_ETH_PHY_KR 0xf0 314 #define ELINK_ETH_PHY_CX4 0xf1 315 #define ELINK_ETH_PHY_NOT_PRESENT 0xff 316 317 /* The address in which version is located*/ 318 uint32_t ver_addr; 319 320 uint16_t req_flow_ctrl; 321 322 uint16_t req_line_speed; 323 324 uint32_t speed_cap_mask; 325 326 uint16_t req_duplex; 327 uint16_t rsrv; 328 /* Called per phy/port init, and it configures LASI, speed, autoneg, 329 duplex, flow control negotiation, etc. */ 330 config_init_t config_init; 331 332 /* Called due to interrupt. It determines the link, speed */ 333 read_status_t read_status; 334 335 /* Called when driver is unloading. Should reset the phy */ 336 link_reset_t link_reset; 337 338 /* Set the loopback configuration for the phy */ 339 config_loopback_t config_loopback; 340 341 /* Format the given raw number into str up to len */ 342 format_fw_ver_t format_fw_ver; 343 344 /* Reset the phy (both ports) */ 345 hw_reset_t hw_reset; 346 347 /* Set link led mode (on/off/oper)*/ 348 set_link_led_t set_link_led; 349 350 /* PHY Specific tasks */ 351 phy_specific_func_t phy_specific_func; 352 #define ELINK_DISABLE_TX 1 353 #define ELINK_ENABLE_TX 2 354 #define ELINK_PHY_INIT 3 355 }; 356 357 /* Inputs parameters to the CLC */ 358 struct elink_params { 359 360 uint8_t port; 361 362 /* Default / User Configuration */ 363 uint8_t loopback_mode; 364 #define ELINK_LOOPBACK_NONE 0 365 #define ELINK_LOOPBACK_EMAC 1 366 #define ELINK_LOOPBACK_BMAC 2 367 #define ELINK_LOOPBACK_XGXS 3 368 #define ELINK_LOOPBACK_EXT_PHY 4 369 #define ELINK_LOOPBACK_EXT 5 370 #define ELINK_LOOPBACK_UMAC 6 371 #define ELINK_LOOPBACK_XMAC 7 372 373 /* Device parameters */ 374 uint8_t mac_addr[6]; 375 376 uint16_t req_duplex[ELINK_LINK_CONFIG_SIZE]; 377 uint16_t req_flow_ctrl[ELINK_LINK_CONFIG_SIZE]; 378 379 uint16_t req_line_speed[ELINK_LINK_CONFIG_SIZE]; /* Also determine AutoNeg */ 380 381 /* shmem parameters */ 382 uint32_t shmem_base; 383 uint32_t shmem2_base; 384 uint32_t speed_cap_mask[ELINK_LINK_CONFIG_SIZE]; 385 uint32_t switch_cfg; 386 #define ELINK_SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH 387 #define ELINK_SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH 388 #define ELINK_SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT 389 390 uint32_t lane_config; 391 392 /* Phy register parameter */ 393 uint32_t chip_id; 394 395 /* features */ 396 uint32_t feature_config_flags; 397 #define ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1 << 0) 398 #define ELINK_FEATURE_CONFIG_PFC_ENABLED (1 << 1) 399 #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1 << 2) 400 #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1 << 3) 401 #define ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC (1 << 4) 402 #define ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC (1 << 5) 403 #define ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC (1 << 6) 404 #define ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC (1 << 7) 405 #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX (1 << 8) 406 #define ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED (1 << 9) 407 #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED (1 << 10) 408 #define ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET (1 << 11) 409 #define ELINK_FEATURE_CONFIG_IEEE_PHY_TEST (1 << 12) 410 #define ELINK_FEATURE_CONFIG_MT_SUPPORT (1 << 13) 411 #define ELINK_FEATURE_CONFIG_BOOT_FROM_SAN (1 << 14) 412 #define ELINK_FEATURE_CONFIG_DISABLE_PD (1 << 15) 413 414 /* Will be populated during common init */ 415 struct elink_phy phy[ELINK_MAX_PHYS]; 416 417 /* Will be populated during common init */ 418 uint8_t num_phys; 419 420 uint8_t rsrv; 421 422 /* Used to configure the EEE Tx LPI timer, has several modes of 423 * operation, according to bits 29:28 - 424 * 2'b00: Timer will be configured by nvram, output will be the value 425 * from nvram. 426 * 2'b01: Timer will be configured by nvram, output will be in 427 * microseconds. 428 * 2'b10: bits 1:0 contain an nvram value which will be used instead 429 * of the one located in the nvram. Output will be that value. 430 * 2'b11: bits 19:0 contain the idle timer in microseconds; output 431 * will be in microseconds. 432 * Bits 31:30 should be 2'b11 in order for EEE to be enabled. 433 */ 434 uint32_t eee_mode; 435 #define ELINK_EEE_MODE_NVRAM_BALANCED_TIME (0xa00) 436 #define ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME (0x100) 437 #define ELINK_EEE_MODE_NVRAM_LATENCY_TIME (0x6000) 438 #define ELINK_EEE_MODE_NVRAM_MASK (0x3) 439 #define ELINK_EEE_MODE_TIMER_MASK (0xfffff) 440 #define ELINK_EEE_MODE_OUTPUT_TIME (1 << 28) 441 #define ELINK_EEE_MODE_OVERRIDE_NVRAM (1 << 29) 442 #define ELINK_EEE_MODE_ENABLE_LPI (1 << 30) 443 #define ELINK_EEE_MODE_ADV_LPI (1U << 31) 444 445 uint16_t hw_led_mode; /* part of the hw_config read from the shmem */ 446 uint32_t multi_phy_config; 447 448 /* Device pointer passed to all callback functions */ 449 struct bnx2x_softc *sc; 450 uint16_t req_fc_auto_adv; /* Should be set to TX / BOTH when 451 req_flow_ctrl is set to AUTO */ 452 uint16_t link_flags; 453 #define ELINK_LINK_FLAGS_INT_DISABLED (1 << 0) 454 #define ELINK_PHY_INITIALIZED (1 << 1) 455 uint32_t lfa_base; 456 457 /* The same definitions as the shmem2 parameter */ 458 uint32_t link_attr_sync; 459 }; 460 461 /* Output parameters */ 462 struct elink_vars { 463 uint8_t phy_flags; 464 #define PHY_XGXS_FLAG (1 << 0) 465 #define PHY_SGMII_FLAG (1 << 1) 466 #define PHY_PHYSICAL_LINK_FLAG (1 << 2) 467 #define PHY_HALF_OPEN_CONN_FLAG (1 << 3) 468 #define PHY_OVER_CURRENT_FLAG (1 << 4) 469 #define PHY_SFP_TX_FAULT_FLAG (1 << 5) 470 471 uint8_t mac_type; 472 #define ELINK_MAC_TYPE_NONE 0 473 #define ELINK_MAC_TYPE_EMAC 1 474 #define ELINK_MAC_TYPE_BMAC 2 475 #define ELINK_MAC_TYPE_UMAC 3 476 #define ELINK_MAC_TYPE_XMAC 4 477 478 uint8_t phy_link_up; /* internal phy link indication */ 479 uint8_t link_up; 480 481 uint16_t line_speed; 482 uint16_t duplex; 483 484 uint16_t flow_ctrl; 485 uint16_t ieee_fc; 486 487 /* The same definitions as the shmem parameter */ 488 uint32_t link_status; 489 uint32_t eee_status; 490 uint8_t fault_detected; 491 uint8_t check_kr2_recovery_cnt; 492 #define ELINK_CHECK_KR2_RECOVERY_CNT 5 493 uint16_t periodic_flags; 494 #define ELINK_PERIODIC_FLAGS_LINK_EVENT 0x0001 495 496 uint32_t aeu_int_mask; 497 uint8_t rx_tx_asic_rst; 498 uint8_t turn_to_run_wc_rt; 499 uint16_t rsrv2; 500 501 }; 502 503 /***********************************************************/ 504 /* Functions */ 505 /***********************************************************/ 506 elink_status_t elink_phy_init(struct elink_params *params, struct elink_vars *vars); 507 508 /* Reset the link. Should be called when driver or interface goes down 509 Before calling phy firmware upgrade, the reset_ext_phy should be set 510 to 0 */ 511 elink_status_t elink_link_reset(struct elink_params *params, 512 struct elink_vars *vars, 513 uint8_t reset_ext_phy); 514 elink_status_t elink_lfa_reset(struct elink_params *params, struct elink_vars *vars); 515 /* elink_link_update should be called upon link interrupt */ 516 elink_status_t elink_link_update(struct elink_params *params, struct elink_vars *vars); 517 518 /* use the following phy functions to read/write from external_phy 519 * In order to use it to read/write internal phy registers, use 520 * ELINK_DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as 521 * the register 522 */ 523 elink_status_t elink_phy_read(struct elink_params *params, uint8_t phy_addr, 524 uint8_t devad, uint16_t reg, uint16_t *ret_val); 525 526 elink_status_t elink_phy_write(struct elink_params *params, uint8_t phy_addr, 527 uint8_t devad, uint16_t reg, uint16_t val); 528 529 /* Reads the link_status from the shmem, 530 and update the link vars accordingly */ 531 void elink_link_status_update(struct elink_params *input, 532 struct elink_vars *output); 533 /* returns string representing the fw_version of the external phy */ 534 elink_status_t elink_get_ext_phy_fw_version(struct elink_params *params, 535 uint8_t *version, 536 uint16_t len); 537 538 /* Set/Unset the led 539 Basically, the CLC takes care of the led for the link, but in case one needs 540 to set/unset the led unnaturally, set the "mode" to ELINK_LED_MODE_OPER to 541 blink the led, and ELINK_LED_MODE_OFF to set the led off.*/ 542 elink_status_t elink_set_led(struct elink_params *params, 543 struct elink_vars *vars, uint8_t mode, uint32_t speed); 544 #define ELINK_LED_MODE_OFF 0 545 #define ELINK_LED_MODE_ON 1 546 #define ELINK_LED_MODE_OPER 2 547 #define ELINK_LED_MODE_FRONT_PANEL_OFF 3 548 549 /* elink_handle_module_detect_int should be called upon module detection 550 * interrupt 551 */ 552 void elink_handle_module_detect_int(struct elink_params *params); 553 554 /* Get the actual link status. In case it returns ELINK_STATUS_OK, link is up, 555 * otherwise link is down 556 */ 557 elink_status_t elink_test_link(struct elink_params *params, 558 struct elink_vars *vars, 559 uint8_t is_serdes); 560 561 562 /* One-time initialization for external phy after power up */ 563 elink_status_t elink_common_init_phy(struct bnx2x_softc *sc, uint32_t shmem_base_path[], 564 uint32_t shmem2_base_path[], uint32_t chip_id, 565 uint8_t one_port_enabled); 566 567 /* Reset the external PHY using GPIO */ 568 void elink_ext_phy_hw_reset(struct bnx2x_softc *sc, uint8_t port); 569 570 /* Reset the external of SFX7101 */ 571 void elink_sfx7101_sp_sw_reset(struct bnx2x_softc *sc, struct elink_phy *phy); 572 573 /* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */ 574 elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy, 575 struct elink_params *params, uint8_t dev_addr, 576 uint16_t addr, uint16_t byte_cnt, 577 uint8_t *o_buf); 578 579 void elink_hw_reset_phy(struct elink_params *params); 580 581 /* Check swap bit and adjust PHY order */ 582 uint32_t elink_phy_selection(struct elink_params *params); 583 584 /* Probe the phys on board, and populate them in "params" */ 585 elink_status_t elink_phy_probe(struct elink_params *params); 586 587 /* Checks if fan failure detection is required on one of the phys on board */ 588 uint8_t elink_fan_failure_det_req(struct bnx2x_softc *sc, uint32_t shmem_base, 589 uint32_t shmem2_base, uint8_t port); 590 591 /* Open / close the gate between the NIG and the BRB */ 592 void elink_set_rx_filter(struct elink_params *params, uint8_t en); 593 594 /* DCBX structs */ 595 596 /* Number of maximum COS per chip */ 597 #define ELINK_DCBX_E2E3_MAX_NUM_COS (2) 598 #define ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0 (6) 599 #define ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 (3) 600 #define ELINK_DCBX_E3B0_MAX_NUM_COS ( \ 601 ELINK_MAXVAL(ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0, \ 602 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1)) 603 604 #define ELINK_DCBX_MAX_NUM_COS ( \ 605 ELINK_MAXVAL(ELINK_DCBX_E3B0_MAX_NUM_COS, \ 606 ELINK_DCBX_E2E3_MAX_NUM_COS)) 607 608 /* PFC port configuration params */ 609 struct elink_nig_brb_pfc_port_params { 610 /* NIG */ 611 uint32_t pause_enable; 612 uint32_t llfc_out_en; 613 uint32_t llfc_enable; 614 uint32_t pkt_priority_to_cos; 615 uint8_t num_of_rx_cos_priority_mask; 616 uint32_t rx_cos_priority_mask[ELINK_DCBX_MAX_NUM_COS]; 617 uint32_t llfc_high_priority_classes; 618 uint32_t llfc_low_priority_classes; 619 }; 620 621 622 /* ETS port configuration params */ 623 struct elink_ets_bw_params { 624 uint8_t bw; 625 }; 626 627 struct elink_ets_sp_params { 628 /** 629 * valid values are 0 - 5. 0 is highest strict priority. 630 * There can't be two COS's with the same pri. 631 */ 632 uint8_t pri; 633 }; 634 635 enum elink_cos_state { 636 elink_cos_state_strict = 0, 637 elink_cos_state_bw = 1, 638 }; 639 640 struct elink_ets_cos_params { 641 enum elink_cos_state state ; 642 union { 643 struct elink_ets_bw_params bw_params; 644 struct elink_ets_sp_params sp_params; 645 } params; 646 }; 647 648 struct elink_ets_params { 649 uint8_t num_of_cos; /* Number of valid COS entries*/ 650 struct elink_ets_cos_params cos[ELINK_DCBX_MAX_NUM_COS]; 651 }; 652 653 /* Used to update the PFC attributes in EMAC, BMAC, NIG and BRB 654 * when link is already up 655 */ 656 elink_status_t elink_update_pfc(struct elink_params *params, 657 struct elink_vars *vars, 658 struct elink_nig_brb_pfc_port_params *pfc_params); 659 660 661 /* Used to configure the ETS to disable */ 662 elink_status_t elink_ets_disabled(struct elink_params *params, 663 struct elink_vars *vars); 664 665 /* Used to configure the ETS to BW limited */ 666 void elink_ets_bw_limit(const struct elink_params *params, 667 const uint32_t cos0_bw, 668 const uint32_t cos1_bw); 669 670 /* Used to configure the ETS to strict */ 671 elink_status_t elink_ets_strict(const struct elink_params *params, 672 const uint8_t strict_cos); 673 674 675 /* Configure the COS to ETS according to BW and SP settings.*/ 676 elink_status_t elink_ets_e3b0_config(const struct elink_params *params, 677 const struct elink_vars *vars, 678 struct elink_ets_params *ets_params); 679 /* Read pfc statistic*/ 680 void elink_pfc_statistic(struct elink_params *params, struct elink_vars *vars, 681 uint32_t pfc_frames_sent[2], 682 uint32_t pfc_frames_received[2]); 683 void elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars, 684 uint32_t chip_id, uint32_t shmem_base, uint32_t shmem2_base, 685 uint8_t port); 686 /* elink_status_t elink_sfp_module_detection(struct elink_phy *phy, 687 * struct elink_params *params); 688 */ 689 690 void elink_period_func(struct elink_params *params, struct elink_vars *vars); 691 692 /*elink_status_t elink_check_half_open_conn(struct elink_params *params, 693 * struct elink_vars *vars, uint8_t notify); 694 */ 695 696 void elink_enable_pmd_tx(struct elink_params *params); 697 698 699 700 #endif /* ELINK_H */ 701