1688654bfSRasesh Mody /* SPDX-License-Identifier: BSD-3-Clause 2540a2110SStephen Hemminger * Copyright (c) 2013-2015 Brocade Communications Systems, Inc. 3e3de5dadSRasesh Mody * Copyright (c) 2015-2018 Cavium Inc. 4540a2110SStephen Hemminger * All rights reserved. 5e3de5dadSRasesh Mody * www.cavium.com 6540a2110SStephen Hemminger */ 7540a2110SStephen Hemminger 8540a2110SStephen Hemminger #ifndef BNX2X_VFPF_H 9540a2110SStephen Hemminger #define BNX2X_VFPF_H 10540a2110SStephen Hemminger 11540a2110SStephen Hemminger #include "ecore_sp.h" 12540a2110SStephen Hemminger 13540a2110SStephen Hemminger struct vf_resource_query { 14540a2110SStephen Hemminger uint8_t num_rxqs; 15540a2110SStephen Hemminger uint8_t num_txqs; 16540a2110SStephen Hemminger uint8_t num_sbs; 17540a2110SStephen Hemminger uint8_t num_mac_filters; 18540a2110SStephen Hemminger uint8_t num_vlan_filters; 19540a2110SStephen Hemminger uint8_t num_mc_filters; 20540a2110SStephen Hemminger }; 21540a2110SStephen Hemminger 22540a2110SStephen Hemminger #define BNX2X_VF_STATUS_SUCCESS 1 23540a2110SStephen Hemminger #define BNX2X_VF_STATUS_FAILURE 2 24540a2110SStephen Hemminger #define BNX2X_VF_STATUS_NO_RESOURCES 4 25540a2110SStephen Hemminger #define BNX2X_VF_BULLETIN_TRIES 5 26540a2110SStephen Hemminger 27540a2110SStephen Hemminger #define BNX2X_VF_Q_FLAG_CACHE_ALIGN 0x0008 28540a2110SStephen Hemminger #define BNX2X_VF_Q_FLAG_STATS 0x0010 29540a2110SStephen Hemminger #define BNX2X_VF_Q_FLAG_OV 0x0020 30540a2110SStephen Hemminger #define BNX2X_VF_Q_FLAG_VLAN 0x0040 31540a2110SStephen Hemminger #define BNX2X_VF_Q_FLAG_COS 0x0080 32540a2110SStephen Hemminger #define BNX2X_VF_Q_FLAG_HC 0x0100 33540a2110SStephen Hemminger #define BNX2X_VF_Q_FLAG_DHC 0x0200 34540a2110SStephen Hemminger #define BNX2X_VF_Q_FLAG_LEADING_RSS 0x0400 35540a2110SStephen Hemminger 36a5724ff9SHarish Patil #define TLV_BUFFER_SIZE 1024 37a5724ff9SHarish Patil 385dbc53d7SChas Williams #define VFPF_RX_MASK_ACCEPT_NONE 0x00000000 395dbc53d7SChas Williams #define VFPF_RX_MASK_ACCEPT_MATCHED_UNICAST 0x00000001 405dbc53d7SChas Williams #define VFPF_RX_MASK_ACCEPT_MATCHED_MULTICAST 0x00000002 415dbc53d7SChas Williams #define VFPF_RX_MASK_ACCEPT_ALL_UNICAST 0x00000004 425dbc53d7SChas Williams #define VFPF_RX_MASK_ACCEPT_ALL_MULTICAST 0x00000008 435dbc53d7SChas Williams #define VFPF_RX_MASK_ACCEPT_BROADCAST 0x00000010 445dbc53d7SChas Williams 45a5724ff9SHarish Patil /* general tlv header (used for both vf->pf request and pf->vf response) */ 46a5724ff9SHarish Patil struct channel_tlv { 47a5724ff9SHarish Patil uint16_t type; 48a5724ff9SHarish Patil uint16_t length; 49a5724ff9SHarish Patil }; 50a5724ff9SHarish Patil 51540a2110SStephen Hemminger struct vf_first_tlv { 521b437b97SChas Williams struct channel_tlv tl; 53540a2110SStephen Hemminger uint32_t reply_offset; 54540a2110SStephen Hemminger }; 55540a2110SStephen Hemminger 56a5724ff9SHarish Patil struct tlv_buffer_size { 57a5724ff9SHarish Patil uint8_t tlv_buffer[TLV_BUFFER_SIZE]; 58a5724ff9SHarish Patil }; 59a5724ff9SHarish Patil 60540a2110SStephen Hemminger /* tlv struct for all PF replies except acquire */ 61540a2110SStephen Hemminger struct vf_common_reply_tlv { 621b437b97SChas Williams struct channel_tlv tl; 63540a2110SStephen Hemminger uint8_t status; 64540a2110SStephen Hemminger uint8_t pad[3]; 65540a2110SStephen Hemminger }; 66540a2110SStephen Hemminger 67540a2110SStephen Hemminger /* used to terminate and pad a tlv list */ 68540a2110SStephen Hemminger struct channel_list_end_tlv { 691b437b97SChas Williams struct channel_tlv tl; 70540a2110SStephen Hemminger uint32_t pad; 71540a2110SStephen Hemminger }; 72540a2110SStephen Hemminger 73540a2110SStephen Hemminger /* Acquire */ 74540a2110SStephen Hemminger struct vf_acquire_tlv { 75540a2110SStephen Hemminger struct vf_first_tlv first_tlv; 76540a2110SStephen Hemminger 77540a2110SStephen Hemminger uint8_t vf_id; 78540a2110SStephen Hemminger uint8_t pad[3]; 79540a2110SStephen Hemminger 80540a2110SStephen Hemminger struct vf_resource_query res_query; 81540a2110SStephen Hemminger 82540a2110SStephen Hemminger uint64_t bulletin_addr; 83540a2110SStephen Hemminger }; 84540a2110SStephen Hemminger 85540a2110SStephen Hemminger /* simple operation request on queue */ 86540a2110SStephen Hemminger struct vf_q_op_tlv { 87540a2110SStephen Hemminger struct vf_first_tlv first_tlv; 88540a2110SStephen Hemminger uint8_t vf_qid; 89540a2110SStephen Hemminger uint8_t pad[3]; 90540a2110SStephen Hemminger }; 91540a2110SStephen Hemminger 92540a2110SStephen Hemminger /* receive side scaling tlv */ 93540a2110SStephen Hemminger struct vf_rss_tlv { 94540a2110SStephen Hemminger struct vf_first_tlv first_tlv; 95540a2110SStephen Hemminger uint32_t rss_flags; 96540a2110SStephen Hemminger uint8_t rss_result_mask; 97540a2110SStephen Hemminger uint8_t ind_table_size; 98540a2110SStephen Hemminger uint8_t rss_key_size; 99540a2110SStephen Hemminger uint8_t pad; 100540a2110SStephen Hemminger uint8_t ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 101540a2110SStephen Hemminger uint32_t rss_key[T_ETH_RSS_KEY]; /* hash values */ 102540a2110SStephen Hemminger }; 103540a2110SStephen Hemminger 104540a2110SStephen Hemminger struct vf_resc { 105540a2110SStephen Hemminger #define BNX2X_VF_MAX_QUEUES_PER_VF 16 106540a2110SStephen Hemminger #define BNX2X_VF_MAX_SBS_PER_VF 16 107540a2110SStephen Hemminger uint16_t hw_sbs[BNX2X_VF_MAX_SBS_PER_VF]; 108540a2110SStephen Hemminger uint8_t hw_qid[BNX2X_VF_MAX_QUEUES_PER_VF]; 109540a2110SStephen Hemminger uint8_t num_rxqs; 110540a2110SStephen Hemminger uint8_t num_txqs; 111540a2110SStephen Hemminger uint8_t num_sbs; 112540a2110SStephen Hemminger uint8_t num_mac_filters; 113540a2110SStephen Hemminger uint8_t num_vlan_filters; 114540a2110SStephen Hemminger uint8_t num_mc_filters; 115540a2110SStephen Hemminger uint8_t permanent_mac_addr[ETH_ALEN]; 1166d13ea8eSOlivier Matz struct rte_ether_addr current_mac_addr; 117540a2110SStephen Hemminger uint16_t pf_link_speed; 118540a2110SStephen Hemminger uint32_t pf_link_supported; 119540a2110SStephen Hemminger }; 120540a2110SStephen Hemminger 121540a2110SStephen Hemminger /* tlv struct holding reply for acquire */ 122540a2110SStephen Hemminger struct vf_acquire_resp_tlv { 123540a2110SStephen Hemminger uint16_t type; 124540a2110SStephen Hemminger uint16_t length; 125540a2110SStephen Hemminger uint8_t status; 126540a2110SStephen Hemminger uint8_t pad1[3]; 127540a2110SStephen Hemminger uint32_t chip_num; 128540a2110SStephen Hemminger uint8_t pad2[4]; 129540a2110SStephen Hemminger char fw_ver[32]; 130540a2110SStephen Hemminger uint16_t db_size; 131540a2110SStephen Hemminger uint8_t pad3[2]; 132540a2110SStephen Hemminger struct vf_resc resc; 133540a2110SStephen Hemminger }; 134540a2110SStephen Hemminger 135540a2110SStephen Hemminger /* Init VF */ 136540a2110SStephen Hemminger struct vf_init_tlv { 137540a2110SStephen Hemminger struct vf_first_tlv first_tlv; 138540a2110SStephen Hemminger uint64_t sb_addr[BNX2X_VF_MAX_SBS_PER_VF]; 139540a2110SStephen Hemminger uint64_t spq_addr; 140540a2110SStephen Hemminger uint64_t stats_addr; 141540a2110SStephen Hemminger uint16_t stats_step; 142540a2110SStephen Hemminger uint32_t flags; 143540a2110SStephen Hemminger uint32_t pad[2]; 144540a2110SStephen Hemminger }; 145540a2110SStephen Hemminger 146540a2110SStephen Hemminger struct vf_rxq_params { 147540a2110SStephen Hemminger /* physical addresses */ 148540a2110SStephen Hemminger uint64_t rcq_addr; 149540a2110SStephen Hemminger uint64_t rcq_np_addr; 150540a2110SStephen Hemminger uint64_t rxq_addr; 151540a2110SStephen Hemminger uint64_t pad1; 152540a2110SStephen Hemminger 153540a2110SStephen Hemminger /* sb + hc info */ 154540a2110SStephen Hemminger uint8_t vf_sb_id; 155540a2110SStephen Hemminger uint8_t sb_cq_index; 156540a2110SStephen Hemminger uint16_t hc_rate; /* desired interrupts per sec. */ 157540a2110SStephen Hemminger /* rx buffer info */ 158540a2110SStephen Hemminger uint16_t mtu; 159540a2110SStephen Hemminger uint16_t buf_sz; 160540a2110SStephen Hemminger uint16_t flags; /* for BNX2X_VF_Q_FLAG_X flags */ 161540a2110SStephen Hemminger uint16_t stat_id; /* valid if BNX2X_VF_Q_FLAG_STATS */ 162540a2110SStephen Hemminger 163540a2110SStephen Hemminger uint8_t pad2[5]; 164540a2110SStephen Hemminger 165540a2110SStephen Hemminger uint8_t drop_flags; 166540a2110SStephen Hemminger uint8_t cache_line_log; /* BNX2X_VF_Q_FLAG_CACHE_ALIGN */ 167540a2110SStephen Hemminger uint8_t pad3; 168540a2110SStephen Hemminger }; 169540a2110SStephen Hemminger 170540a2110SStephen Hemminger struct vf_txq_params { 171540a2110SStephen Hemminger /* physical addresses */ 172540a2110SStephen Hemminger uint64_t txq_addr; 173540a2110SStephen Hemminger 174540a2110SStephen Hemminger /* sb + hc info */ 175540a2110SStephen Hemminger uint8_t vf_sb_id; /* index in hw_sbs[] */ 176540a2110SStephen Hemminger uint8_t sb_index; /* Index in the SB */ 177540a2110SStephen Hemminger uint16_t hc_rate; /* desired interrupts per sec. */ 178540a2110SStephen Hemminger uint32_t flags; /* for BNX2X_VF_Q_FLAG_X flags */ 179540a2110SStephen Hemminger uint16_t stat_id; /* valid if BNX2X_VF_Q_FLAG_STATS */ 180540a2110SStephen Hemminger uint8_t traffic_type; /* see in setup_context() */ 181540a2110SStephen Hemminger uint8_t pad; 182540a2110SStephen Hemminger }; 183540a2110SStephen Hemminger 184540a2110SStephen Hemminger /* Setup Queue */ 185540a2110SStephen Hemminger struct vf_setup_q_tlv { 186540a2110SStephen Hemminger struct vf_first_tlv first_tlv; 187540a2110SStephen Hemminger 188540a2110SStephen Hemminger struct vf_rxq_params rxq; 189540a2110SStephen Hemminger struct vf_txq_params txq; 190540a2110SStephen Hemminger 191540a2110SStephen Hemminger uint8_t vf_qid; /* index in hw_qid[] */ 192540a2110SStephen Hemminger uint8_t param_valid; 193540a2110SStephen Hemminger #define VF_RXQ_VALID 0x01 194540a2110SStephen Hemminger #define VF_TXQ_VALID 0x02 195540a2110SStephen Hemminger uint8_t pad[2]; 196540a2110SStephen Hemminger }; 197540a2110SStephen Hemminger 198540a2110SStephen Hemminger /* Set Queue Filters */ 199540a2110SStephen Hemminger struct vf_q_mac_vlan_filter { 200540a2110SStephen Hemminger uint32_t flags; 201540a2110SStephen Hemminger #define BNX2X_VF_Q_FILTER_DEST_MAC_VALID 0x01 202540a2110SStephen Hemminger #define BNX2X_VF_Q_FILTER_VLAN_TAG_VALID 0x02 203540a2110SStephen Hemminger #define BNX2X_VF_Q_FILTER_SET_MAC 0x100 /* set/clear */ 204540a2110SStephen Hemminger uint8_t mac[ETH_ALEN]; 205540a2110SStephen Hemminger uint16_t vlan_tag; 206540a2110SStephen Hemminger }; 207540a2110SStephen Hemminger 208540a2110SStephen Hemminger 209540a2110SStephen Hemminger #define _UP_ETH_ALEN (6) 210540a2110SStephen Hemminger 211540a2110SStephen Hemminger /* configure queue filters */ 212540a2110SStephen Hemminger struct vf_set_q_filters_tlv { 213540a2110SStephen Hemminger struct vf_first_tlv first_tlv; 214540a2110SStephen Hemminger 215540a2110SStephen Hemminger uint32_t flags; 216540a2110SStephen Hemminger #define BNX2X_VF_MAC_VLAN_CHANGED 0x01 217540a2110SStephen Hemminger #define BNX2X_VF_MULTICAST_CHANGED 0x02 218540a2110SStephen Hemminger #define BNX2X_VF_RX_MASK_CHANGED 0x04 219540a2110SStephen Hemminger 220540a2110SStephen Hemminger uint8_t vf_qid; /* index in hw_qid[] */ 221540a2110SStephen Hemminger uint8_t mac_filters_cnt; 222540a2110SStephen Hemminger uint8_t multicast_cnt; 223540a2110SStephen Hemminger uint8_t pad; 224540a2110SStephen Hemminger 225540a2110SStephen Hemminger #define VF_MAX_MAC_FILTERS 16 226540a2110SStephen Hemminger #define VF_MAX_VLAN_FILTERS 16 227540a2110SStephen Hemminger #define VF_MAX_FILTERS (VF_MAX_MAC_FILTERS +\ 228540a2110SStephen Hemminger VF_MAX_VLAN_FILTERS) 229540a2110SStephen Hemminger struct vf_q_mac_vlan_filter filters[VF_MAX_FILTERS]; 230540a2110SStephen Hemminger 231540a2110SStephen Hemminger #define VF_MAX_MULTICAST_PER_VF 32 232540a2110SStephen Hemminger uint8_t multicast[VF_MAX_MULTICAST_PER_VF][_UP_ETH_ALEN]; 233540a2110SStephen Hemminger unsigned long rx_mask; 234540a2110SStephen Hemminger }; 235540a2110SStephen Hemminger 236540a2110SStephen Hemminger 237540a2110SStephen Hemminger /* close VF (disable VF) */ 238540a2110SStephen Hemminger struct vf_close_tlv { 239540a2110SStephen Hemminger struct vf_first_tlv first_tlv; 240540a2110SStephen Hemminger uint16_t vf_id; /* for debug */ 241540a2110SStephen Hemminger uint8_t pad[2]; 242540a2110SStephen Hemminger }; 243540a2110SStephen Hemminger 244*7be78d02SJosh Soref /* release the VF's acquired resources */ 245540a2110SStephen Hemminger struct vf_release_tlv { 246540a2110SStephen Hemminger struct vf_first_tlv first_tlv; 247540a2110SStephen Hemminger uint16_t vf_id; /* for debug */ 248540a2110SStephen Hemminger uint8_t pad[2]; 249540a2110SStephen Hemminger }; 250540a2110SStephen Hemminger 251540a2110SStephen Hemminger union query_tlvs { 252540a2110SStephen Hemminger struct vf_first_tlv first_tlv; 253540a2110SStephen Hemminger struct vf_acquire_tlv acquire; 254540a2110SStephen Hemminger struct vf_init_tlv init; 255540a2110SStephen Hemminger struct vf_close_tlv close; 256540a2110SStephen Hemminger struct vf_q_op_tlv q_op; 257540a2110SStephen Hemminger struct vf_setup_q_tlv setup_q; 258540a2110SStephen Hemminger struct vf_set_q_filters_tlv set_q_filters; 259540a2110SStephen Hemminger struct vf_release_tlv release; 260540a2110SStephen Hemminger struct vf_rss_tlv update_rss; 261540a2110SStephen Hemminger struct channel_list_end_tlv list_end; 262a5724ff9SHarish Patil struct tlv_buffer_size tlv_buf_size; 263540a2110SStephen Hemminger }; 264540a2110SStephen Hemminger 265540a2110SStephen Hemminger union resp_tlvs { 266540a2110SStephen Hemminger struct vf_common_reply_tlv common_reply; 267540a2110SStephen Hemminger struct vf_acquire_resp_tlv acquire_resp; 268540a2110SStephen Hemminger struct channel_list_end_tlv list_end; 269a5724ff9SHarish Patil struct tlv_buffer_size tlv_buf_size; 270540a2110SStephen Hemminger }; 271540a2110SStephen Hemminger 272540a2110SStephen Hemminger /* struct allocated by VF driver, PF sends updates to VF via bulletin */ 273540a2110SStephen Hemminger struct bnx2x_vf_bulletin { 274540a2110SStephen Hemminger uint32_t crc; /* crc of structure to ensure is not in 275540a2110SStephen Hemminger * mid-update 276540a2110SStephen Hemminger */ 277540a2110SStephen Hemminger uint16_t version; 278540a2110SStephen Hemminger uint16_t length; 279540a2110SStephen Hemminger 28098a7ea33SJerin Jacob uint64_t valid_bitmap; /* bitmap indicating which fields 281540a2110SStephen Hemminger * hold valid values 282540a2110SStephen Hemminger */ 283540a2110SStephen Hemminger 284540a2110SStephen Hemminger #define MAC_ADDR_VALID 0 /* alert the vf that a new mac address 285540a2110SStephen Hemminger * is available for it 286540a2110SStephen Hemminger */ 287540a2110SStephen Hemminger #define VLAN_VALID 1 /* when set, the vf should no access the 288540a2110SStephen Hemminger * vf channel 289540a2110SStephen Hemminger */ 290540a2110SStephen Hemminger #define CHANNEL_DOWN 2 /* vf channel is disabled. VFs are not 291540a2110SStephen Hemminger * to attempt to send messages on the 292540a2110SStephen Hemminger * channel after this bit is set 293540a2110SStephen Hemminger */ 294540a2110SStephen Hemminger uint8_t mac[ETH_ALEN]; 295540a2110SStephen Hemminger uint8_t mac_pad[2]; 296540a2110SStephen Hemminger 297540a2110SStephen Hemminger uint16_t vlan; 298540a2110SStephen Hemminger uint8_t vlan_pad[6]; 299540a2110SStephen Hemminger }; 300540a2110SStephen Hemminger 301540a2110SStephen Hemminger #define MAX_TLVS_IN_LIST 50 302540a2110SStephen Hemminger enum channel_tlvs { 303540a2110SStephen Hemminger BNX2X_VF_TLV_NONE, /* ends tlv sequence */ 304540a2110SStephen Hemminger BNX2X_VF_TLV_ACQUIRE, 305540a2110SStephen Hemminger BNX2X_VF_TLV_INIT, 306540a2110SStephen Hemminger BNX2X_VF_TLV_SETUP_Q, 307540a2110SStephen Hemminger BNX2X_VF_TLV_SET_Q_FILTERS, 308540a2110SStephen Hemminger BNX2X_VF_TLV_ACTIVATE_Q, 309540a2110SStephen Hemminger BNX2X_VF_TLV_DEACTIVATE_Q, 310540a2110SStephen Hemminger BNX2X_VF_TLV_TEARDOWN_Q, 311540a2110SStephen Hemminger BNX2X_VF_TLV_CLOSE, 312540a2110SStephen Hemminger BNX2X_VF_TLV_RELEASE, 313540a2110SStephen Hemminger BNX2X_VF_TLV_UPDATE_RSS_OLD, 314540a2110SStephen Hemminger BNX2X_VF_TLV_PF_RELEASE_VF, 315540a2110SStephen Hemminger BNX2X_VF_TLV_LIST_END, 316540a2110SStephen Hemminger BNX2X_VF_TLV_FLR, 317540a2110SStephen Hemminger BNX2X_VF_TLV_PF_SET_MAC, 318540a2110SStephen Hemminger BNX2X_VF_TLV_PF_SET_VLAN, 319540a2110SStephen Hemminger BNX2X_VF_TLV_UPDATE_RSS, 320a5724ff9SHarish Patil BNX2X_VF_TLV_PHYS_PORT_ID, 321540a2110SStephen Hemminger BNX2X_VF_TLV_MAX 322540a2110SStephen Hemminger }; 323540a2110SStephen Hemminger 324540a2110SStephen Hemminger struct bnx2x_vf_mbx_msg { 325540a2110SStephen Hemminger union query_tlvs query[BNX2X_VF_MAX_QUEUES_PER_VF]; 326540a2110SStephen Hemminger union resp_tlvs resp; 327540a2110SStephen Hemminger }; 328540a2110SStephen Hemminger 329e0c103a7SRasesh Mody int bnx2x_vf_teardown_queue(struct bnx2x_softc *sc, int qid); 330540a2110SStephen Hemminger int bnx2x_vf_set_mac(struct bnx2x_softc *sc, int set); 331540a2110SStephen Hemminger int bnx2x_vf_config_rss(struct bnx2x_softc *sc, struct ecore_config_rss_params *params); 3320d2870c4SSouvik Dey int bnx2x_vfpf_set_mcast(struct bnx2x_softc *sc, 3330d2870c4SSouvik Dey struct rte_ether_addr *mc_addrs, 3340d2870c4SSouvik Dey uint32_t mc_addrs_num); 335540a2110SStephen Hemminger 336540a2110SStephen Hemminger #endif /* BNX2X_VFPF_H */ 337