/llvm-project/llvm/test/CodeGen/AMDGPU/ |
H A D | xor-r600.ll | 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=r600 -mcpu=redwood < %s | FileCheck -enabl… 5 ; R600-LABEL: xor_v2i32: 6 ; R600: ; %bb.0: 7 ; R600-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[] 8 ; R600-NEXT: TEX 1 @6 9 ; R600-NEXT: ALU 3, @12, KC0[CB0:0-32], KC1[] 10 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 11 ; R600-NEXT: CF_END 12 ; R600-NEXT: PAD [all …]
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H A D | fsqrt.r600.ll | 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=r600 -mcpu=redwood < %s | FileCheck -che… 4 ; Run with unsafe-fp-math to make sure nothing tries to turn this into 1 / rsqrt(x) 7 ; R600-LABEL: v_safe_fsqrt_f32: 8 ; R600: ; %bb.0: 9 ; R600-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] 10 ; R600-NEXT: TEX 0 @6 11 ; R600-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[] 12 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 13 ; R600-NEXT: CF_END [all …]
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H A D | bfi_int.r600.ll | 2 ; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -enable-var-scope -check-prefixes=R600 %s 8 ; R600-LABEL: bfi_def: 9 ; R600: ; %bb.0: ; %entry 10 ; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[] 11 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1 12 ; R600-NEXT: CF_END 13 ; R600-NEXT: PAD 14 ; R600-NEXT: ALU clause starting at 4: 15 ; R600-NEXT: LSHR * T0.X, KC0[2].Y, literal.x, 16 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00) [all …]
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H A D | fneg-fabs-r600.ll | 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck --check… 5 ; R600-LABEL: fneg_fabsf_fadd_f32: 6 ; R600: ; %bb.0: 7 ; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[] 8 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1 9 ; R600-NEXT: CF_END 10 ; R600-NEXT: PAD 11 ; R600-NEXT: ALU clause starting at 4: 12 ; R600-NEXT: LSHR T0.X, KC0[2].Y, literal.x, [all …]
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H A D | fabs-r600.ll | 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s 9 ; R600-LABEL: s_fabsf_fn_free: 10 ; R600: ; %bb.0: 11 ; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[] 12 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 13 ; R600-NEXT: CF_END 14 ; R600-NEXT: PAD 15 ; R600-NEXT: ALU clause starting at 4: 16 ; R600-NEXT: MOV * T0.W, KC0[2].Z, [all …]
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H A D | build_vector-r600.ll | 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2 ; RUN: llc < %s -mtriple=r600-- -mcpu=redwood | FileCheck %s --check-prefixes=R600 5 ; R600-LABEL: build_vector2: 6 ; R600: ; %bb.0: ; %entry 7 ; R600-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[] 8 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 9 ; R600-NEXT: CF_END 10 ; R600-NEXT: PAD 11 ; R600-NEXT: ALU clause starting at 4: 12 ; R600-NEXT: MOV * T0.Y, literal.x, [all …]
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H A D | llvm.r600.read.local.size.ll | 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2 ; RUN: llc -mtriple=amdgcn < %s | FileCheck --check-prefixes=SI,GCN,FUNC %s 3 ; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck --chec [all...] |
H A D | udivrem.ll | 2 ; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck --check-prefix=R600 %s 3 ; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verif [all...] |
H A D | rotr.ll | 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2 ; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck --check-prefixes=R600 %s 3 ; RUN: llc -mtripl [all...] |
H A D | rotl.ll | 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2 ; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck --check-prefixes=R600 %s 3 ; RUN: llc -mtripl [all...] |
H A D | llvm.round.ll | 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2 ; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck --check-prefixes=GFX6 %s 3 ; RUN: llc -mtriple=amdgcn -mcpu=tonga -matt [all...] |
H A D | nullptr.ll | 1 ;RUN: llc < %s -mtriple=amdgcn-- -verify-machineinstrs | FileCheck -check-prefixes=CHECK,GCN %s 2 ;RUN: llc < %s -mtriple=r600-- -verify-machineinstrs | FileCheck -check-prefixes=CHECK,R600 %s 6 ; CHECK-LABEL: nullptr_priv: 7 ; CHECK-NEXT: .long -1 10 ; CHECK-LABEL: nullptr_glob: 11 ; GCN-NEXT: .quad 0 12 ; R600-NEXT: .long 0 15 ; CHECK-LABEL: nullptr_const: 16 ; GCN-NEXT: .quad 0 17 ; R600-NEXT: .long 0 [all …]
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H A D | annotate-kernel-features.ll | 1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals 2 ; RUN: opt -S -mtriple=amdgcn-unknown-unknow [all...] |
H A D | wrong-transalu-pos-fix.ll | 1 ; RUN: llc -mtriple=r600-- -mcpu=redwood < %s | FileCheck %s 5 ;CHECK-NOT: MULLO_INT T[0-9]+ 9 %x.i = tail call i32 @llvm.r600.read.global.size.x() #1 10 %y.i18 = tail call i32 @llvm.r600.read.global.size.y() #1 12 %z.i17 = tail call i32 @llvm.r600.read.global.size.z() #1 14 %x.i.i = tail call i32 @llvm.r600.read.tgid.x() #1 15 %x.i12.i = tail call i32 @llvm.r600.read.local.size.x() #1 17 %x.i4.i = tail call i32 @llvm.r600.read.tidig.x() #1 20 %y.i.i = tail call i32 @llvm.r600.read.tgid.y() #1 21 %y.i14.i = tail call i32 @llvm.r600.read.local.size.y() #1 [all …]
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H A D | load-global-f32.ll | 1 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn < %s | FileCheck --check-prefixes=GCN-NOHSA,FUNC,SI-NOHS [all...] |
H A D | fshl.ll | 2 ; RUN: llc < %s -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs | FileCheck %s --check-prefix=SI 3 ; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -verif [all...] |
/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600RegisterInfo.cpp | 1 //===-- R600RegisterInfo.cpp - R600 Register Information ------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 10 /// R600 implementation of the TargetRegisterInfo class. 12 //===----------------------------------------------------------------------===// 26 R600::sub0, R600::sub1, R600::sub2, R600::sub3, in getSubRegFromChannel() 27 R600::sub4, R600::sub5, R600::sub6, R600::sub7, in getSubRegFromChannel() 28 R600::sub8, R600::sub9, R600::sub10, R600::sub11, in getSubRegFromChannel() 29 R600::sub12, R600::sub13, R600::sub14, R600::sub15 in getSubRegFromChannel() 42 reserveRegisterTuples(Reserved, R600::ZERO); in getReservedRegs() [all …]
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H A D | R600InstrInfo.cpp | 1 //===-- R600InstrInfo.cpp - R600 Instruction Information ------ [all...] |
H A D | R600ControlFlowFinalizer.cpp | 1 //===- R600ControlFlowFinalizer.cpp - Finalize Control Flow Inst -------- [all...] |
H A D | R600ExpandSpecialInstrs.cpp | 1 //===- R600ExpandSpecialInstrs.cpp - Expand special instructions ----------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 14 //===----------------------------------------------------------------------===// 17 #include "R600.h" 25 #define DEBUG_TYPE "r600-expand-special-instrs" 44 return "R600 Expand special instructions pass"; in getPassName() 51 "R600 Expand Special Instrs", false, false) 65 int OpIdx = TII->getOperandIdx(*OldMI, Op); in SetFlagInNewMI() 66 if (OpIdx > -1) { in SetFlagInNewMI() [all …]
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H A D | R600ClauseMergePass.cpp | 1 //===-- R600ClauseMergePass - Merge consecutive CF_ALU -------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 13 //===----------------------------------------------------------------------===// 16 #include "R600.h" 28 case R600::CF_ALU: in isCFAlu() 29 case R600::CF_ALU_PUSH_BEFORE: in isCFAlu() 68 "R600 Clause Merge", false, false) 70 "R600 Clause Merge", false, false) 79 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::COUNT)) in getCFAluSize() [all …]
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/llvm-project/llvm/test/Transforms/AtomicExpand/AMDGPU/ |
H A D | expand-atomic-i8.ll | 2 ; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -passes=atomic-expand %s | FileCheck %s --check-prefixes=C… 3 ; RUN: opt -mtriple=r600-mesa-mesa3d -S -passes=atomic-expand %s | FileCheck %s --check-prefixes=CH… 6 ; GCN-LABEL: @test_atomicrmw_xchg_i8_global_agent( 7 ; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[… 8 ; GCN-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 9 ; GCN-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 10 ; GCN-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 11 ; GCN-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 12 ; GCN-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]] 13 ; GCN-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 [all …]
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/llvm-project/llvm/test/Object/AMDGPU/ |
H A D | elf-header-flags-mach.yaml | 1 # RUN: sed -e 's/<BITS>/32/' -e 's/<MACH>/R600_R600/' %s | yaml2obj -o %t.o.R600_R600 2 # RUN: llvm-readobj -S --file-headers %t.o.R600_R600 | FileCheck --chec [all...] |
/llvm-project/clang/test/Driver/ |
H A D | amdgpu-macros.cl | 2 // "-target" and "-mcpu" options. 5 // R600-based processors. 8 // RUN: %clang -E -dM -target r600 -mcpu=r600 [all...] |
/llvm-project/clang/test/SemaCUDA/ |
H A D | amdgpu-bf16.cu | 1 // REQUIRES: amdgpu-registered-target 2 // REQUIRES: x86-registered-target 4 // RUN: %clang_cc1 "-aux-triple" "x86_64-unknown-linux-gnu" "-triple" "r600-unknown-unknown"\ 5 // RUN: -fcuda-is-device "-aux-target-cpu" "x86-64" -fsyntax-only -verify=r600 %s 7 // AMDGCN has storage-only support for bf16. R600 does not support it should error out when 13 // r600 should error on all uses of the type. 15 // r600-error@+1 {{__bf16 is not supported on this target}} 17 // r600-error@+1 {{__bf16 is not supported on this target}} 19 // r600-error@+1 {{__bf16 is not supported on this target}} 21 // r600-error@+1 {{__bf16 is not supported on this target}} [all …]
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