Lines Matching +full:r600 +full:- +full:-
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2 ; RUN: llc < %s -mtriple=r600-- -mcpu=redwood | FileCheck %s --check-prefixes=R600
5 ; R600-LABEL: build_vector2:
6 ; R600: ; %bb.0: ; %entry
7 ; R600-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]
8 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
9 ; R600-NEXT: CF_END
10 ; R600-NEXT: PAD
11 ; R600-NEXT: ALU clause starting at 4:
12 ; R600-NEXT: MOV * T0.Y, literal.x,
13 ; R600-NEXT: 6(8.407791e-45), 0(0.000000e+00)
14 ; R600-NEXT: MOV T0.X, literal.x,
15 ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
16 ; R600-NEXT: 5(7.006492e-45), 2(2.802597e-45)
23 ; R600-LABEL: build_vector4:
24 ; R600: ; %bb.0: ; %entry
25 ; R600-NEXT: ALU 8, @4, KC0[CB0:0-32], KC1[]
26 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
27 ; R600-NEXT: CF_END
28 ; R600-NEXT: PAD
29 ; R600-NEXT: ALU clause starting at 4:
30 ; R600-NEXT: MOV * T0.W, literal.x,
31 ; R600-NEXT: 8(1.121039e-44), 0(0.000000e+00)
32 ; R600-NEXT: MOV * T0.Z, literal.x,
33 ; R600-NEXT: 7(9.809089e-45), 0(0.000000e+00)
34 ; R600-NEXT: MOV * T0.Y, literal.x,
35 ; R600-NEXT: 6(8.407791e-45), 0(0.000000e+00)
36 ; R600-NEXT: MOV T0.X, literal.x,
37 ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
38 ; R600-NEXT: 5(7.006492e-45), 2(2.802597e-45)
45 ; R600-LABEL: build_vector_v2i16:
46 ; R600: ; %bb.0: ; %entry
47 ; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
48 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.X, T5.X, 1
49 ; R600-NEXT: CF_END
50 ; R600-NEXT: PAD
51 ; R600-NEXT: ALU clause starting at 4:
52 ; R600-NEXT: MOV T4.X, literal.x,
53 ; R600-NEXT: LSHR * T5.X, KC0[2].Y, literal.y,
54 ; R600-NEXT: 393221(5.510200e-40), 2(2.802597e-45)
61 ; R600-LABEL: build_vector_v2i16_trunc:
62 ; R600: ; %bb.0:
63 ; R600-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]
64 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.X, T5.X, 1
65 ; R600-NEXT: CF_END
66 ; R600-NEXT: PAD
67 ; R600-NEXT: ALU clause starting at 4:
68 ; R600-NEXT: LSHR * T0.W, KC0[2].Z, literal.x,
69 ; R600-NEXT: 16(2.242078e-44), 0(0.000000e+00)
70 ; R600-NEXT: OR_INT T4.X, PV.W, literal.x,
71 ; R600-NEXT: LSHR * T5.X, KC0[2].Y, literal.y,
72 ; R600-NEXT: 327680(4.591775e-40), 2(2.802597e-45)
82 ; R600-LABEL: build_v2i32_from_v4i16_shuffle:
83 ; R600: ; %bb.0: ; %entry
84 ; R600-NEXT: ALU 0, @10, KC0[], KC1[]
85 ; R600-NEXT: TEX 1 @6
86 ; R600-NEXT: ALU 4, @11, KC0[CB0:0-32], KC1[]
87 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
88 ; R600-NEXT: CF_END
89 ; R600-NEXT: PAD
90 ; R600-NEXT: Fetch clause starting at 6:
91 ; R600-NEXT: VTX_READ_16 T1.X, T0.X, 48, #3
92 ; R600-NEXT: VTX_READ_16 T0.X, T0.X, 44, #3
93 ; R600-NEXT: ALU clause starting at 10:
94 ; R600-NEXT: MOV * T0.X, 0.0,
95 ; R600-NEXT: ALU clause starting at 11:
96 ; R600-NEXT: LSHL * T0.Y, T1.X, literal.x,
97 ; R600-NEXT: 16(2.242078e-44), 0(0.000000e+00)
98 ; R600-NEXT: LSHL T0.X, T0.X, literal.x,
99 ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
100 ; R600-NEXT: 16(2.242078e-44), 2(2.802597e-45)